diff options
| author | Clyne Sullivan <tullivan99@gmail.com> | 2019-02-28 17:04:22 -0500 |
|---|---|---|
| committer | Clyne Sullivan <tullivan99@gmail.com> | 2019-02-28 17:04:22 -0500 |
| commit | d6869d1ec4bd24cd2c3eafa534f0849b25ec5607 (patch) | |
| tree | 79e54ed27b39c31864895535d11399708d5a45c0 /arduino/cores/nRF5/nordic | |
| parent | 614ee97bf3a2270c413527a7f35c54cbecd9e601 (diff) | |
added basic code
Diffstat (limited to 'arduino/cores/nRF5/nordic')
150 files changed, 106864 insertions, 0 deletions
diff --git a/arduino/cores/nRF5/nordic/nrfx/CHANGELOG.md b/arduino/cores/nRF5/nordic/nrfx/CHANGELOG.md new file mode 100755 index 0000000..2889528 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/CHANGELOG.md @@ -0,0 +1,111 @@ +# Changelog +All notable changes to this project are documented in this file. + +## [1.3.1] - 2018-09-28 +### Fixed +- Corrected the type of nrfx_usbd_ep_status_get() return value. +- Corrected calls to undefined macros in NFCT and USBD drivers. + +## [1.3.0] - 2018-09-21 +### Added +- Added HAL and driver for NFCT. +- Added driver for USBD. +- Added function for setting the burst mode in the SAADC HAL. +- Added the NRFX_ARRAY_SIZE macro. + +### Changed +- Moved the implementation of nrfx_power_clock_irq_handler() to nrfx_power.c, removed nrfx_power_clock.c. + +### Fixed +- Replaced ARRAY_SIZE macro calls with NRFX_ARRAY_SIZE ones. + +## [1.2.0] - 2018-09-06 +### Added +- Added function for checking if a specific channel is enabled in the GPIOTE HAL. +- Added support for using the QDEC driver without LED. +- Added functions for modifying only the event endpoint or only the task endpoint in the PPI HAL. +- Added function for reading the pin pull configuration in the GPIO HAL. + +### Changed +- Corrected ISOSPLIT enumerator names in the USBD HAL. + +### Fixed +- Fixed a double buffering bug that occurred in the UARTE driver after the RX abort. +- Fixed the TXRX transfers in the TWIM driver. They can now be started after transfers that are not ended with the stop condition. + +## [1.1.0] - 2018-06-15 +### Added +- Implemented workaround for nRF52832 and nRF52840 anomaly 194 in the I2S driver. +- Implemented workaround for nRF52840 anomaly 195 in the SPIM driver. +- Added HALs for CCM, ECB, and RADIO. +- Extended HALs for GPIO, PPI, SAADC, and USBD. +- Added support for external LFCLK sources. + +### Changed +- Corrected handling of transfer lengths in the TWI driver. +- Updated MDK to version 8.17.0. + +### Fixed +- Fixed logging in the PPI driver. +- Fixed SPIM interrupt definition for nRF52810. +- Fixed Slave Select configuration in the SPIM driver. +- Corrected default settings for NRF_SPIM3. +- Fixed a typo in the UARTE TXDRDY event definition. +- Corrected the TIMEOUT event clearing in the WDT interrupt handler. + +## [1.0.0] - 2018-03-21 +### Added +- Added the NRFX_WAIT_FOR macro to improve the time-out functionality in QSPI and SAADC drivers. +- Added glue layer macros for checking and modifying the pending status of interrupts. +- Added new enumeration values for interrupts and events in the UARTE HAL. +- Implemented workarounds for nRF52 anomalies 192 and 201 in the CLOCK driver. +- Implemented workaround for nRF52840 anomaly 122 in the QSPI driver. +- Implemented workaround for nRF52840 anomaly 198 in the SPIM driver. + +### Changed +- Updated MDK to 8.16.0. +- Extended input pin configuration in the GPIOTE driver. +- Unified the way of checking if a required event handler was provided. Now, all drivers do it with assertions. +- Changed the RNG bias correction configuration option to be enabled by default. +- Refactored the ADC driver and HAL. +- Corrected assertions in the TIMER driver to make it usable in debug version with PPI. +- Improved buffer handling in the I2S driver. The API of the driver has been slightly modified. +- Enhanced SPIS driver API: added the "p_context" parameter, allowed NULL pointers for zero-length buffers. + +### Fixed +- Fixed result value casting in the TEMP HAL. +- Fixed types of conversion result and buffer size in the ADC HAL and driver. +- Fixed time-out in the SAADC driver in abort function. + +## [0.8.0] - 2017-12-20 +### Added +- Added XIP support in the QSPI driver. +- Implemented Errata 132 in the CLOCK driver. +- Added function for checking if a TIMER instance is enabled. +- Added extended SPIM support. + +### Changed +- Updated MDK to 8.15.0. Introduced Segger Embedded Studio startup files. +- Updated drivers: COMP, PWM, QDEC, SAADC, SPIS, TIMER, TWI, TWIS. +- Changed the type used for transfer lengths to 'size_t' in drivers: SPI, SPIM, SPIS, TWI, TWIM, TWIS, UART, UARTE. Introduced checking of EasyDMA transfers limits. +- Updated HALs: COMP, NVMC, UART, UARTE, USBD. +- Updated template files and documentation of configuration options. + +### Fixed +- Fixed TWI and TWIM drivers so that they now support GPIOs from all ports. +- Fixed definitions related to compare channels in the TIMER HAL. + +### Removed +- Removed the possibility of passing NULL instead of configuration to get default settings during drivers initialization. +- Removed support for UART1 and PRS box #5. + +## [0.7.0] - 2017-10-20 +### Added +- This CHANGELOG.md file. +- README.md file with simple description and explanations. +- HAL for: ADC, CLOCK, COMP, ECB, EGU, GPIO, GPIOTE, I2S, LPCOMP, NVMC, PDM, POWER, PPI, PWM, QDEC, QSPI, RNG, RTC, SAADC, SPI, SPIM, SPIS, ARM(R) SysTick, TEMP, TIMER, TWI, TWIM, TWIS, UART, UARTE, USBD, WDT. +- Drivers for: ADC, CLOCK, COMP, GPIOTE, I2S, LPCOMP, PDM, POWER, PWM, QDEC, QSPI, RNG, RTC, SAADC, SPI, SPIM, SPIS, ARM(R) SysTick, TIMER, TWI, TWIM, TWIS, UART, UARTE, WDT. +- Allocators for: PPI, SWI/EGU. +- MDK in version 8.14.0. +- Offline documentation for every added driver and simple integration description. +- Template integration files. diff --git a/arduino/cores/nRF5/nordic/nrfx/LICENSE b/arduino/cores/nRF5/nordic/nrfx/LICENSE new file mode 100755 index 0000000..67c8788 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/LICENSE @@ -0,0 +1,29 @@ +Copyright (c) 2017 - 2018, Nordic Semiconductor ASA +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + diff --git a/arduino/cores/nRF5/nordic/nrfx/README.md b/arduino/cores/nRF5/nordic/nrfx/README.md new file mode 100755 index 0000000..2bbfc75 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/README.md @@ -0,0 +1,37 @@ +# nrfx + +## Overview + +nrfx is an extract from the nRF5 SDK that contains solely the drivers for +peripherals present in Nordic SoCs, for convenience complemented with the MDK +package containing required structures and bitfields definitions, startup +files etc. + +## Supported SoCs + +* nRF51 Series +* nRF52810 +* nRF52832 +* nRF52840 + +## Directories + +``` + . + ├── doc # Project documentation files + ├── drivers # nrfx drivers files + │ └── include # nrfx drivers headers + │ └── src # nrfx drivers sources + ├── hal # Hardware Access Layer files + ├── mdk # Nordic MDK files + ├── soc # Nordic SoC related files + └── templates # Templates of nrfx integration files +``` + +## Generating documentation + +nrfx documentation is availabe in the `doc\html` folder of the release package. + +You can also generate documentation yourself from the source code. To do it, install doxygen +and run one of the scripts: `generate_html_doc.bat` or `generate_html_doc.sh`. Generated +documentation will be stored in the `doc\html` directory. Use `index.html` to open it. diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrf_bitmask.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrf_bitmask.h new file mode 100755 index 0000000..229f88b --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrf_bitmask.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_BITMASK_H +#define NRF_BITMASK_H + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_bitmask Bitmask module + * @{ + * @ingroup nrfx + * @brief Bitmask managing module. + */ + +#define BITMASK_BYTE_GET(abs_bit) ((abs_bit)/8) +#define BITMASK_RELBIT_GET(abs_bit) ((abs_bit) & 0x00000007) + +/** + * Function for checking if bit in the multi-byte bit mask is set. + * + * @param bit Bit index. + * @param p_mask A pointer to mask with bit fields. + * + * @return 0 if bit is not set, positive value otherwise. + */ +__STATIC_INLINE uint32_t nrf_bitmask_bit_is_set(uint32_t bit, void const * p_mask) +{ + uint8_t const * p_mask8 = (uint8_t const *)p_mask; + uint32_t byte_idx = BITMASK_BYTE_GET(bit); + bit = BITMASK_RELBIT_GET(bit); + return (1 << bit) & p_mask8[byte_idx]; +} + +/** + * Function for setting a bit in the multi-byte bit mask. + * + * @param bit Bit index. + * @param p_mask A pointer to mask with bit fields. + */ +__STATIC_INLINE void nrf_bitmask_bit_set(uint32_t bit, void * p_mask) +{ + uint8_t * p_mask8 = (uint8_t *)p_mask; + uint32_t byte_idx = BITMASK_BYTE_GET(bit); + bit = BITMASK_RELBIT_GET(bit); + p_mask8[byte_idx] |= (1 << bit); +} + +/** + * Function for clearing a bit in the multi-byte bit mask. + * + * @param bit Bit index. + * @param p_mask A pointer to mask with bit fields. + */ +__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask) +{ + uint8_t * p_mask8 = (uint8_t *)p_mask; + uint32_t byte_idx = BITMASK_BYTE_GET(bit); + bit = BITMASK_RELBIT_GET(bit); + p_mask8[byte_idx] &= ~(1 << bit); +} + +/** + * Function for performing bitwise OR operation on two multi-byte bit masks. + * + * @param p_mask1 A pointer to the first bit mask. + * @param p_mask2 A pointer to the second bit mask. + * @param p_out_mask A pointer to the output bit mask. + * @param length Length of output mask in bytes. + */ +__STATIC_INLINE void nrf_bitmask_masks_or(void const * p_mask1, + void const * p_mask2, + void * p_out_mask, + uint32_t length) +{ + uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1; + uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2; + uint8_t * p_mask8_out = (uint8_t *)p_out_mask; + uint32_t i; + for (i = 0; i < length; i++) + { + p_mask8_out[i] = p_mask8_1[i] | p_mask8_2[i]; + } +} + +/** + * Function for performing bitwise AND operation on two multi-byte bit masks. + * + * @param p_mask1 A pointer to the first bit mask. + * @param p_mask2 A pointer to the second bit mask. + * @param p_out_mask A pointer to the output bit mask. + * @param length Length of output mask in bytes. + */ +__STATIC_INLINE void nrf_bitmask_masks_and(void const * p_mask1, + void const * p_mask2, + void * p_out_mask, + uint32_t length) +{ + uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1; + uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2; + uint8_t * p_mask8_out = (uint8_t *)p_out_mask; + uint32_t i; + for (i = 0; i < length; i++) + { + p_mask8_out[i] = p_mask8_1[i] & p_mask8_2[i]; + } +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_BITMASK_H diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_adc.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_adc.h new file mode 100755 index 0000000..a2361fd --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_adc.h @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_ADC_H__ +#define NRFX_ADC_H__ + +#include <nrfx.h> +#include <hal/nrf_adc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_adc ADC driver + * @{ + * @ingroup nrf_adc + * @brief Analog-to-Digital Converter (ADC) peripheral driver. + */ + +/** + * @brief Driver event types. + */ +typedef enum +{ + NRFX_ADC_EVT_DONE, ///< Event generated when the buffer is filled with samples. + NRFX_ADC_EVT_SAMPLE, ///< Event generated when the requested channel is sampled. +} nrfx_adc_evt_type_t; + +/** + * @brief Analog-to-digital converter driver DONE event. + */ +typedef struct +{ + nrf_adc_value_t * p_buffer; ///< Pointer to the buffer with converted samples. + uint16_t size; ///< Number of samples in the buffer. +} nrfx_adc_done_evt_t; + +/** + * @brief Analog-to-digital converter driver SAMPLE event. + */ +typedef struct +{ + nrf_adc_value_t sample; ///< Converted sample. +} nrfx_adc_sample_evt_t; + +/** + * @brief Analog-to-digital converter driver event. + */ +typedef struct +{ + nrfx_adc_evt_type_t type; ///< Event type. + union + { + nrfx_adc_done_evt_t done; ///< Data for DONE event. + nrfx_adc_sample_evt_t sample; ///< Data for SAMPLE event. + } data; +} nrfx_adc_evt_t; + +/**@brief Macro for initializing the ADC channel with the default configuration. */ +#define NRFX_ADC_DEFAULT_CHANNEL(analog_input) \ + { \ + NULL, \ + { \ + .resolution = NRF_ADC_CONFIG_RES_10BIT, \ + .scaling = NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE, \ + .reference = NRF_ADC_CONFIG_REF_VBG, \ + .input = (analog_input), \ + .extref = NRF_ADC_CONFIG_EXTREFSEL_NONE \ + } \ + } + +// Forward declaration of the nrfx_adc_channel_t type. +typedef struct nrfx_adc_channel_s nrfx_adc_channel_t; + +/** + * @brief ADC channel. + * + * This structure is defined by the user and used by the driver. Therefore, it should + * not be defined on the stack as a local variable. + */ +struct nrfx_adc_channel_s +{ + nrfx_adc_channel_t * p_next; ///< Pointer to the next enabled channel (for internal use). + nrf_adc_config_t config; ///< ADC configuration for the current channel. +}; + +/** + * @brief ADC configuration. + */ +typedef struct +{ + uint8_t interrupt_priority; ///< Priority of ADC interrupt. +} nrfx_adc_config_t; + +/** @brief ADC default configuration. */ +#define NRFX_ADC_DEFAULT_CONFIG \ +{ \ + .interrupt_priority = NRFX_ADC_CONFIG_IRQ_PRIORITY \ +} + +/** + * @brief User event handler prototype. + * + * This function is called when the requested number of samples has been processed. + * + * @param p_event Event. + */ +typedef void (*nrfx_adc_event_handler_t)(nrfx_adc_evt_t const * p_event); + +/** + * @brief Function for initializing the ADC. + * + * If a valid event handler is provided, the driver is initialized in non-blocking mode. + * If event_handler is NULL, the driver works in blocking mode. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized. + */ +nrfx_err_t nrfx_adc_init(nrfx_adc_config_t const * p_config, + nrfx_adc_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the ADC. + * + * This function stops all ongoing conversions and disables all channels. + */ +void nrfx_adc_uninit(void); + +/** + * @brief Function for enabling an ADC channel. + * + * This function configures and enables the channel. When @ref nrfx_adc_buffer_convert is + * called, all channels that have been enabled with this function are sampled. + * + * This function can be called only when there is no conversion in progress + * (the ADC is not busy). + * + * @note The channel instance variable @p p_channel is used by the driver as an item + * in a list. Therefore, it cannot be an automatic variable that is located on the stack. + */ +void nrfx_adc_channel_enable(nrfx_adc_channel_t * const p_channel); + +/** + * @brief Function for disabling an ADC channel. + * + * This function can be called only when there is no conversion in progress + * (the ADC is not busy). + */ +void nrfx_adc_channel_disable(nrfx_adc_channel_t * const p_channel); + +/** + * @brief Function for disabling all ADC channels. + * + * This function can be called only when there is no conversion in progress + * (the ADC is not busy). + */ +void nrfx_adc_all_channels_disable(void); + +/** + * @brief Function for starting ADC sampling. + * + * This function triggers single ADC sampling. If more than one channel is enabled, the driver + * emulates scanning and all channels are sampled in the order they were enabled. + */ +void nrfx_adc_sample(void); + +/** + * @brief Function for executing a single ADC conversion. + * + * This function selects the desired input and starts a single conversion. If a valid pointer + * is provided for the result, the function blocks until the conversion is completed. Otherwise, the + * function returns when the conversion is started, and the result is provided in an event (driver + * must be initialized in non-blocking mode, otherwise an assertion will fail). The function will + * fail if ADC is busy. The channel does not need to be enabled to perform a single conversion. + * + * @param[in] p_channel Channel. + * @param[out] p_value Pointer to the location where the result should be placed. Unless NULL is + * provided, the function is blocking. + * + * @retval NRFX_SUCCESS If conversion was successful. + * @retval NRFX_ERROR_BUSY If the ADC driver is busy. + */ +nrfx_err_t nrfx_adc_sample_convert(nrfx_adc_channel_t const * const p_channel, + nrf_adc_value_t * p_value); + +/** + * @brief Function for converting data to the buffer. + * + * If the driver is initialized in non-blocking mode, this function returns when the first + * conversion is set up. When the buffer is filled, the application is notified by the event + * handler. If the driver is initialized in blocking mode, the function returns when the buffer is + * filled. + * + * Conversion is done on all enabled channels, but it is not triggered by this + * function. This function will prepare the ADC for sampling and then + * wait for the SAMPLE task. Sampling can be triggered manually by the @ref + * nrfx_adc_sample function or by PPI using the @ref NRF_ADC_TASK_START task. + * + * @note If more than one channel is enabled, the function emulates scanning, and + * a single START task will trigger conversion on all enabled channels. For example: + * If 3 channels are enabled and the user requests 6 samples, the completion event + * handler will be called after 2 START tasks. + * + * @note The application must adjust the sampling frequency. The maximum frequency + * depends on the sampling timer and the maximum latency of the ADC interrupt. If + * an interrupt is not handled before the next sampling is triggered, the sample + * will be lost. + * + * @param[in] buffer Result buffer. + * @param[in] size Buffer size in samples. + * + * @retval NRFX_SUCCESS If conversion was successful. + * @retval NRFX_ERROR_BUSY If the driver is busy. + */ +nrfx_err_t nrfx_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size); + +/** + * @brief Function for retrieving the ADC state. + * + * @retval true If the ADC is busy. + * @retval false If the ADC is ready. + */ +bool nrfx_adc_is_busy(void); + +/** + * @brief Function for getting the address of the ADC START task. + * + * This function is used to get the address of the START task, which can be used to trigger ADC + * conversion. + * + * @return Start task address. + */ +__STATIC_INLINE uint32_t nrfx_adc_start_task_get(void); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrfx_adc_start_task_get(void) +{ + return nrf_adc_task_address_get(NRF_ADC_TASK_START); +} + +#endif + + +void nrfx_adc_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_ADC_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_clock.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_clock.h new file mode 100755 index 0000000..151d70f --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_clock.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_CLOCK_H__ +#define NRFX_CLOCK_H__ + +#include <nrfx.h> +#include <hal/nrf_clock.h> +#include <nrfx_power_clock.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_clock CLOCK driver + * @{ + * @ingroup nrf_clock + * @brief CLOCK peripheral driver. + */ + +/** + * @brief Clock events. + */ +typedef enum +{ + NRFX_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started. + NRFX_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started. + NRFX_CLOCK_EVT_CTTO, ///< Calibration timeout. + NRFX_CLOCK_EVT_CAL_DONE ///< Calibration has been done. +} nrfx_clock_evt_type_t; + +/** + * @brief Clock event handler. + * + * @param[in] event Event. + */ +typedef void (*nrfx_clock_event_handler_t)(nrfx_clock_evt_type_t event); + +/** + * @brief Function for initializing internal structures in the nrfx_clock module. + * + * After initialization, the module is in power off state (clocks are not started). + * + * @param[in] event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_ALREADY_INITIALIZED If the driver was already initialized. + */ +nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler); + +/** + * @brief Function for enabling interrupts in the clock module. + */ +void nrfx_clock_enable(void); + +/** + * @brief Function for disabling interrupts in the clock module. + */ +void nrfx_clock_disable(void); + +/** + * @brief Function for uninitializing the clock module. + */ +void nrfx_clock_uninit(void); + +/** + * @brief Function for starting the LFCLK. + */ +void nrfx_clock_lfclk_start(void); + +/** + * @brief Function for stoping the LFCLK. + */ +void nrfx_clock_lfclk_stop(void); + +/** + * @brief Function for checking the LFCLK state. + * + * @retval true If the LFCLK is running. + * @retval false If the LFCLK is not running. + */ +__STATIC_INLINE bool nrfx_clock_lfclk_is_running(void); + +/** + * @brief Function for starting the high-accuracy source HFCLK. + */ +void nrfx_clock_hfclk_start(void); + +/** + * @brief Function for stoping external high-accuracy source HFCLK. + */ +void nrfx_clock_hfclk_stop(void); + +/** + * @brief Function for checking the HFCLK state. + * + * @retval true If the HFCLK is running (XTAL source). + * @retval false If the HFCLK is not running. + */ +__STATIC_INLINE bool nrfx_clock_hfclk_is_running(void); + +/** + * @brief Function for starting calibration of internal LFCLK. + * + * This function starts the calibration process. The process cannot be aborted. LFCLK and HFCLK + * must be running before this function is called. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_INVALID_STATE If the low-frequency of high-frequency clock is off. + * @retval NRFX_ERROR_BUSY If calibration is in progress. + */ +nrfx_err_t nrfx_clock_calibration_start(void); + +/** + * @brief Function for checking if calibration is in progress. + * + * This function indicates that the system is in calibration phase. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If calibration is in progress. + */ +nrfx_err_t nrfx_clock_is_calibrating(void); + +/** + * @brief Function for starting calibration timer. + * @param interval Time after which the CTTO event and interrupt will be generated (in 0.25 s units). + */ +void nrfx_clock_calibration_timer_start(uint8_t interval); + +/** + * @brief Function for stoping calibration timer. + */ +void nrfx_clock_calibration_timer_stop(void); + +/**@brief Function for returning a requested task address for the clock driver module. + * + * @param[in] task One of the peripheral tasks. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task); + +/**@brief Function for returning a requested event address for the clock driver module. + * + * @param[in] event One of the peripheral events. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint32_t nrfx_clock_ppi_task_addr(nrf_clock_task_t task) +{ + return nrf_clock_task_address_get(task); +} + +__STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event) +{ + return nrf_clock_event_address_get(event); +} + +__STATIC_INLINE bool nrfx_clock_hfclk_is_running(void) +{ + return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY); +} + +__STATIC_INLINE bool nrfx_clock_lfclk_is_running(void) +{ + return nrf_clock_lf_is_running(); +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_clock_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_CLOCK_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_comp.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_comp.h new file mode 100755 index 0000000..f7a5c13 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_comp.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_COMP_H__ +#define NRFX_COMP_H__ + +#include <nrfx.h> +#include <hal/nrf_comp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_comp COMP driver + * @{ + * @ingroup nrf_comp + * @brief Comparator (COMP) peripheral driver. + */ + +/** + * @brief Macro to convert the threshold voltage to an integer value + * (needed by the COMP_TH register). + * + * @param[in] vol Voltage to be changed to COMP_TH register value. This value + * must not be smaller than reference voltage divided by 64. + * @param[in] ref Reference voltage. + */ +#define NRFX_VOLTAGE_THRESHOLD_TO_INT(vol, ref) \ + (uint8_t)(((vol) > ((ref) / 64)) ? (NRFX_ROUNDED_DIV((vol) * 64,(ref)) - 1) : 0) + +/** + * @brief COMP event handler function type. + * @param[in] event COMP event. + */ +typedef void (* nrfx_comp_event_handler_t)(nrf_comp_event_t event); + +/** @brief COMP shortcut masks. */ +typedef enum +{ + NRFX_COMP_SHORT_STOP_AFTER_CROSS_EVT = COMP_SHORTS_CROSS_STOP_Msk, /*!< Shortcut between the CROSS event and the STOP task. */ + NRFX_COMP_SHORT_STOP_AFTER_UP_EVT = COMP_SHORTS_UP_STOP_Msk, /*!< Shortcut between the UP event and the STOP task. */ + NRFX_COMP_SHORT_STOP_AFTER_DOWN_EVT = COMP_SHORTS_DOWN_STOP_Msk /*!< Shortcut between the DOWN event and the STOP task. */ +} nrfx_comp_short_mask_t; + +/** @brief COMP events masks. */ +typedef enum +{ + NRFX_COMP_EVT_EN_CROSS_MASK = COMP_INTENSET_CROSS_Msk, /*!< CROSS event (generated after VIN+ == VIN-). */ + NRFX_COMP_EVT_EN_UP_MASK = COMP_INTENSET_UP_Msk, /*!< UP event (generated when VIN+ crosses VIN- while increasing). */ + NRFX_COMP_EVT_EN_DOWN_MASK = COMP_INTENSET_DOWN_Msk, /*!< DOWN event (generated when VIN+ crosses VIN- while decreasing). */ + NRFX_COMP_EVT_EN_READY_MASK = COMP_INTENSET_READY_Msk /*!< READY event (generated when the module is ready). */ +} nrfx_comp_evt_en_mask_t; + +/** @brief COMP configuration. */ +typedef struct +{ + nrf_comp_ref_t reference; /**< Reference selection. */ + nrf_comp_ext_ref_t ext_ref; /**< External analog reference selection. */ + nrf_comp_main_mode_t main_mode; /**< Main operation mode. */ + nrf_comp_th_t threshold; /**< Structure holding THDOWN and THUP values needed by the COMP_TH register. */ + nrf_comp_sp_mode_t speed_mode; /**< Speed and power mode. */ + nrf_comp_hyst_t hyst; /**< Comparator hysteresis.*/ +#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__) + nrf_isource_t isource; /**< Current source selected on analog input. */ +#endif + nrf_comp_input_t input; /**< Input to be monitored. */ + uint8_t interrupt_priority; /**< Interrupt priority. */ +} nrfx_comp_config_t; + +/** @brief COMP threshold default configuration. */ +#define NRFX_COMP_CONFIG_TH \ +{ \ + .th_down = NRFX_VOLTAGE_THRESHOLD_TO_INT(0.5, 1.8), \ + .th_up = NRFX_VOLTAGE_THRESHOLD_TO_INT(1.5, 1.8) \ +} + +/** @brief COMP driver default configuration including the COMP HAL configuration. */ +#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__) +#define NRFX_COMP_DEFAULT_CONFIG(_input) \ +{ \ + .reference = (nrf_comp_ref_t)NRFX_COMP_CONFIG_REF, \ + .main_mode = (nrf_comp_main_mode_t)NRFX_COMP_CONFIG_MAIN_MODE, \ + .threshold = NRFX_COMP_CONFIG_TH, \ + .speed_mode = (nrf_comp_sp_mode_t)NRFX_COMP_CONFIG_SPEED_MODE, \ + .hyst = (nrf_comp_hyst_t)NRFX_COMP_CONFIG_HYST, \ + .isource = (nrf_isource_t)NRFX_COMP_CONFIG_ISOURCE, \ + .input = (nrf_comp_input_t)_input, \ + .interrupt_priority = NRFX_COMP_CONFIG_IRQ_PRIORITY \ +} +#else +#define NRFX_COMP_DEFAULT_CONFIG(_input) \ +{ \ + .reference = (nrf_comp_ref_t)NRFX_COMP_CONFIG_REF, \ + .main_mode = (nrf_comp_main_mode_t)NRFX_COMP_CONFIG_MAIN_MODE, \ + .threshold = NRFX_COMP_CONFIG_TH, \ + .speed_mode = (nrf_comp_sp_mode_t)NRFX_COMP_CONFIG_SPEED_MODE, \ + .hyst = (nrf_comp_hyst_t)NRFX_COMP_CONFIG_HYST, \ + .input = (nrf_comp_input_t)_input, \ + .interrupt_priority = NRFX_COMP_CONFIG_IRQ_PRIORITY \ +} +#endif + +/** + * @brief Function for initializing the COMP driver. + * + * This function initializes the COMP driver, but does not enable the peripheral or any interrupts. + * To start the driver, call the function @ref nrfx_comp_start() after initialization. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver has already been initialized. + * @retval NRFX_ERROR_BUSY If the LPCOMP peripheral is already in use. + * This is possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config, + nrfx_comp_event_handler_t event_handler); + + +/** + * @brief Function for uninitializing the COMP driver. + * + * This function uninitializes the COMP driver. The COMP peripheral and + * its interrupts are disabled, and local variables are cleaned. After this call, you must + * initialize the driver again by calling nrfx_comp_init() if you want to use it. + * + * @sa nrfx_comp_stop() + */ +void nrfx_comp_uninit(void); + +/** + * @brief Function for setting the analog input. + * + * @param[in] psel COMP analog pin selection. + */ +void nrfx_comp_pin_select(nrf_comp_input_t psel); + +/** + * @brief Function for starting the COMP peripheral and interrupts. + * + * Before calling this function, the driver must be initialized. This function + * enables the COMP peripheral and its interrupts. + * + * @param[in] comp_evt_en_mask Mask of events to be enabled. This parameter should be built as + * 'or' of elements from @ref nrfx_comp_evt_en_mask_t. + * @param[in] comp_shorts_mask Mask of shorts to be enabled. This parameter should be built as + * 'or' of elements from @ref nrfx_comp_short_mask_t. + * + * @sa nrfx_comp_init() + * + */ +void nrfx_comp_start(uint32_t comp_evt_en_mask, uint32_t comp_shorts_mask); + +/**@brief Function for stopping the COMP peripheral. + * + * Before calling this function, the driver must be enabled. This function disables the COMP + * peripheral and its interrupts. + * + * @sa nrfx_comp_uninit() + * + */ +void nrfx_comp_stop(void); + +/** + * @brief Function for copying the current state of the comparator result to the RESULT register. + * + * @retval 0 If the input voltage is below the threshold (VIN+ < VIN-). + * @retval 1 If the input voltage is above the threshold (VIN+ > VIN-). + */ +uint32_t nrfx_comp_sample(void); + +/** + * @brief Function for getting the address of a COMP task. + * + * @param[in] task COMP task. + * + * @return Address of the given COMP task. + */ +__STATIC_INLINE uint32_t nrfx_comp_task_address_get(nrf_comp_task_t task) +{ + return (uint32_t)nrf_comp_task_address_get(task); +} + +/** + * @brief Function for getting the address of a COMP event. + * + * @param[in] event COMP event. + * + * @return Address of the given COMP event. + */ +__STATIC_INLINE uint32_t nrfx_comp_event_address_get(nrf_comp_event_t event) +{ + return (uint32_t)nrf_comp_event_address_get(event); +} + + +void nrfx_comp_irq_handler(void); + + +/** @} **/ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_COMP_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_gpiote.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_gpiote.h new file mode 100755 index 0000000..c0b1886 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_gpiote.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_GPIOTE_H__ +#define NRFX_GPIOTE_H__ + +#include <nrfx.h> +#include <hal/nrf_gpiote.h> +#include <hal/nrf_gpio.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_gpiote GPIOTE driver + * @{ + * @ingroup nrf_gpiote + * @brief GPIOTE peripheral driver. + */ + +/**@brief Input pin configuration. */ +typedef struct +{ + nrf_gpiote_polarity_t sense; /**< Transition that triggers interrupt. */ + nrf_gpio_pin_pull_t pull; /**< Pulling mode. */ + bool is_watcher : 1; /**< True when the input pin is tracking an output pin. */ + bool hi_accuracy : 1; /**< True when high accuracy (IN_EVENT) is used. */ + bool skip_gpio_setup : 1; /**< Do not change GPIO configuration */ +} nrfx_gpiote_in_config_t; + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition. + * @details Set hi_accu to true to use IN_EVENT. */ +#define NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_LOTOHI, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition. + * @details Set hi_accu to true to use IN_EVENT. */ +#define NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_HITOLO, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin. + * @details Set hi_accu to true to use IN_EVENT.*/ +#define NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_TOGGLE, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition. + * @details Set hi_accu to true to use IN_EVENT. + * @note This macro prepares configuration that skips GPIO setup. */ +#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_LOTOHI(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_LOTOHI, \ + .skip_gpio_setup = true, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition. + * @details Set hi_accu to true to use IN_EVENT. + * @note This macro prepares configuration that skips GPIO setup. */ +#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_HITOLO(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_HITOLO, \ + .skip_gpio_setup = true, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin. + * @details Set hi_accu to true to use IN_EVENT. + * @note This macro prepares configuration that skips GPIO setup. */ +#define NRFX_GPIOTE_RAW_CONFIG_IN_SENSE_TOGGLE(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_TOGGLE, \ + .skip_gpio_setup = true, \ + } + + +/**@brief Output pin configuration. */ +typedef struct +{ + nrf_gpiote_polarity_t action; /**< Configuration of the pin task. */ + nrf_gpiote_outinit_t init_state; /**< Initial state of the output pin. */ + bool task_pin; /**< True if the pin is controlled by a GPIOTE task. */ +} nrfx_gpiote_out_config_t; + +/**@brief Macro for configuring a pin to use as output. GPIOTE is not used for the pin. */ +#define NRFX_GPIOTE_CONFIG_OUT_SIMPLE(init_high) \ + { \ + .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = false, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from high to low. + * @details The task will clear the pin. Therefore, the pin is set initially. */ +#define NRFX_GPIOTE_CONFIG_OUT_TASK_LOW \ + { \ + .init_state = NRF_GPIOTE_INITIAL_VALUE_HIGH, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_HITOLO, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from low to high. + * @details The task will set the pin. Therefore, the pin is cleared initially. */ +#define NRFX_GPIOTE_CONFIG_OUT_TASK_HIGH \ + { \ + .init_state = NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_LOTOHI, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to toggle the pin state. + * @details The initial pin state must be provided. */ +#define NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(init_high) \ + { \ + .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_TOGGLE, \ + } + +/** @brief Pin. */ +typedef uint32_t nrfx_gpiote_pin_t; + +/** + * @brief Pin event handler prototype. + * + * @param pin Pin that triggered this event. + * @param action Action that lead to triggering this event. + */ +typedef void (*nrfx_gpiote_evt_handler_t)(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action); + +/** + * @brief Function for initializing the GPIOTE module. + * + * @details Only static configuration is supported to prevent the shared + * resource being customized by the initiator. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + */ +nrfx_err_t nrfx_gpiote_init(void); + +/** + * @brief Function for checking if the GPIOTE module is initialized. + * + * @details The GPIOTE module is a shared module. Therefore, you should check if + * the module is already initialized and skip initialization if it is. + * + * @retval true If the module is already initialized. + * @retval false If the module is not initialized. + */ +bool nrfx_gpiote_is_init(void); + +/** + * @brief Function for uninitializing the GPIOTE module. + */ +void nrfx_gpiote_uninit(void); + +/** + * @brief Function for initializing a GPIOTE output pin. + * @details The output pin can be controlled by the CPU or by PPI. The initial + * configuration specifies which mode is used. If PPI mode is used, the driver + * attempts to allocate one of the available GPIOTE channels. If no channel is + * available, an error is returned. + * + * @param[in] pin Pin. + * @param[in] p_config Initial configuration. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used. + * @retval NRFX_ERROR_NO_MEM If no GPIOTE channel is available. + */ +nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_out_config_t const * p_config); + +/** + * @brief Function for uninitializing a GPIOTE output pin. + * @details The driver frees the GPIOTE channel if the output pin was using one. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for setting a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for clearing a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for toggling a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for enabling a GPIOTE output pin task. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for disabling a GPIOTE output pin task. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of OUT task. + */ +uint32_t nrfx_gpiote_out_task_addr_get(nrfx_gpiote_pin_t pin); + +#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of SET task. + */ +uint32_t nrfx_gpiote_set_task_addr_get(nrfx_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of CLR task. + */ +uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for initializing a GPIOTE input pin. + * @details The input pin can act in two ways: + * - lower accuracy but low power (high frequency clock not needed) + * - higher accuracy (high frequency clock required) + * + * The initial configuration specifies which mode is used. + * If high-accuracy mode is used, the driver attempts to allocate one + * of the available GPIOTE channels. If no channel is + * available, an error is returned. + * In low accuracy mode SENSE feature is used. In this case only one active pin + * can be detected at a time. It can be worked around by setting all of the used + * low accuracy pins to toggle mode. + * For more information about SENSE functionality, refer to Product Specification. + * + * @param[in] pin Pin. + * @param[in] p_config Initial configuration. + * @param[in] evt_handler User function to be called when the configured transition occurs. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used. + * @retval NRFX_ERROR_NO_MEM If no GPIOTE channel is available. + */ +nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin, + nrfx_gpiote_in_config_t const * p_config, + nrfx_gpiote_evt_handler_t evt_handler); + +/** + * @brief Function for uninitializing a GPIOTE input pin. + * @details The driver frees the GPIOTE channel if the input pin was using one. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for enabling sensing of a GPIOTE input pin. + * + * @details If the input pin is configured as high-accuracy pin, the function + * enables an IN_EVENT. Otherwise, the function enables the GPIO sense mechanism. + * Note that a PORT event is shared between multiple pins, therefore the + * interrupt is always enabled. + * + * @param[in] pin Pin. + * @param[in] int_enable True to enable the interrupt. Always valid for a high-accuracy pin. + */ +void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable); + +/** + * @brief Function for disabling a GPIOTE input pin. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for checking if a GPIOTE input pin is set. + * + * @param[in] pin Pin. + * + * @retval true If the input pin is set. + * @retval false If the input pin is not set. + */ +bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for getting the address of a GPIOTE input pin event. + * @details If the pin is configured to use low-accuracy mode, the address of the PORT event is returned. + * + * @param[in] pin Pin. + */ +uint32_t nrfx_gpiote_in_event_addr_get(nrfx_gpiote_pin_t pin); + +/** + * @brief Function for forcing a specific state on the pin configured as task. + * + * @param[in] pin Pin. + * @param[in] state Pin state. + */ +void nrfx_gpiote_out_task_force(nrfx_gpiote_pin_t pin, uint8_t state); + +/** + * @brief Function for triggering the task OUT manually. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_out_task_trigger(nrfx_gpiote_pin_t pin); + +#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for triggering the task SET manually. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for triggering the task CLR manually. + * + * @param[in] pin Pin. + */ +void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) + + +void nrfx_gpiote_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GPIOTE_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_i2s.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_i2s.h new file mode 100755 index 0000000..ea4e4d0 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_i2s.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_I2S_H__ +#define NRFX_I2S_H__ + +#include <nrfx.h> +#include <hal/nrf_i2s.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_i2s I2S driver + * @{ + * @ingroup nrf_i2s + * @brief Inter-IC Sound (I2S) peripheral driver. + */ + + +/** + * @brief This value can be provided instead of a pin number for the signals + * SDOUT, SDIN, and MCK to specify that a given signal is not used + * and therefore does not need to be connected to a pin. + */ +#define NRFX_I2S_PIN_NOT_USED 0xFF + +/** @brief I2S driver configuration structure. */ +typedef struct +{ + uint8_t sck_pin; ///< SCK pin number. + uint8_t lrck_pin; ///< LRCK pin number. + uint8_t mck_pin; ///< MCK pin number. + /**< Optional. Use @ref NRFX_I2S_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t sdout_pin; ///< SDOUT pin number. + /**< Optional. Use @ref NRFX_I2S_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t sdin_pin; ///< SDIN pin number. + /**< Optional. Use @ref NRFX_I2S_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t irq_priority; ///< Interrupt priority. + + nrf_i2s_mode_t mode; ///< Mode of operation. + nrf_i2s_format_t format; ///< Frame format. + nrf_i2s_align_t alignment; ///< Alignment of sample within a frame. + nrf_i2s_swidth_t sample_width; ///< Sample width. + nrf_i2s_channels_t channels; ///< Enabled channels. + nrf_i2s_mck_t mck_setup; ///< Master clock setup. + nrf_i2s_ratio_t ratio; ///< MCK/LRCK ratio. +} nrfx_i2s_config_t; + +/** @brief I2S driver buffers structure. */ +typedef struct +{ + uint32_t * p_rx_buffer; + uint32_t const * p_tx_buffer; +} nrfx_i2s_buffers_t; + +/** + * @brief I2S driver default configuration. + */ +#define NRFX_I2S_DEFAULT_CONFIG \ +{ \ + .sck_pin = NRFX_I2S_CONFIG_SCK_PIN, \ + .lrck_pin = NRFX_I2S_CONFIG_LRCK_PIN, \ + .mck_pin = NRFX_I2S_CONFIG_MCK_PIN, \ + .sdout_pin = NRFX_I2S_CONFIG_SDOUT_PIN, \ + .sdin_pin = NRFX_I2S_CONFIG_SDIN_PIN, \ + .irq_priority = NRFX_I2S_CONFIG_IRQ_PRIORITY, \ + .mode = (nrf_i2s_mode_t)NRFX_I2S_CONFIG_MASTER, \ + .format = (nrf_i2s_format_t)NRFX_I2S_CONFIG_FORMAT, \ + .alignment = (nrf_i2s_align_t)NRFX_I2S_CONFIG_ALIGN, \ + .sample_width = (nrf_i2s_swidth_t)NRFX_I2S_CONFIG_SWIDTH, \ + .channels = (nrf_i2s_channels_t)NRFX_I2S_CONFIG_CHANNELS, \ + .mck_setup = (nrf_i2s_mck_t)NRFX_I2S_CONFIG_MCK_SETUP, \ + .ratio = (nrf_i2s_ratio_t)NRFX_I2S_CONFIG_RATIO, \ +} + + +#define NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED (1UL << 0) + /**< The application should provide buffers that are to be used in the next + * part of the transfer. A call to @ref nrfx_i2s_next_buffers_set should + * be done before the currently used buffers are completely processed + * (i.e. the time remaining for supplying the next buffers depends on + * the used size of the buffers). */ + +/** + * @brief I2S driver data handler type. + * + * A data handling function of this type must be specified during initialization + * of the driver. The driver will call this function when it finishes using + * buffers passed to it by the application, and when it needs to be provided + * with buffers for the next part of the transfer. + * + * @note The @c p_released pointer passed to this function is temporary and + * will be invalid after the function returns, hence it cannot be stored + * and used later. If needed, the pointed content (i.e. buffers pointers) + * should be copied instead. + * + * @param[in] p_released Pointer to a structure with pointers to buffers + * passed previously to the driver that will no longer + * be access by it (they can be now safely released or + * used for another purpose, in particular for a next + * part of the transfer). + * This pointer will be NULL if the application did not + * supply the buffers for the next part of the transfer + * (via a call to @ref nrfx_i2s_next_buffers_set) since + * the previous time the data handler signaled such need. + * This means that data corruption occurred (the previous + * buffers are used for the second time) and no buffers + * can be released at the moment. + * Both pointers in this structure are NULL when the + * handler is called for the first time after a transfer + * is started, because no data has been transferred yet + * at this point. In all successive calls the pointers + * specify what has been sent (TX) and what has been + * received (RX) in the part of transfer that has just + * been completed (provided that a given direction is + * enabled, see @ref nrfx_i2s_start). + * @param[in] status Bit field describing the current status of the transfer. + * It can be 0 or a combination of the following flags: + * - @ref NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED + */ +typedef void (* nrfx_i2s_data_handler_t)(nrfx_i2s_buffers_t const * p_released, + uint32_t status); + + +/** + * @brief Function for initializing the I2S driver. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] handler Data handler provided by the user. Must not be NULL. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + * @retval NRFX_ERROR_INVALID_PARAM If the requested combination of configuration + * options is not allowed by the I2S peripheral. + */ +nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config, + nrfx_i2s_data_handler_t handler); + +/** @brief Function for uninitializing the I2S driver. */ +void nrfx_i2s_uninit(void); + +/** + * @brief Function for starting the continuous I2S transfer. + * + * The I2S data transfer can be performed in one of three modes: RX (reception) + * only, TX (transmission) only, or in both directions simultaneously. + * The mode is selected by specifying a proper buffer for a given direction + * in the call to this function or by passing NULL instead if this direction + * should be disabled. + * + * The length of the buffer (which is a common value for RX and TX if both + * directions are enabled) is specified in 32-bit words. One 32-bit memory + * word can either contain four 8-bit samples, two 16-bit samples, or one + * right-aligned 24-bit sample sign-extended to a 32-bit value. + * For a detailed memory mapping for different supported configurations, + * see the @linkProductSpecification52. + * + * @note Peripherals using EasyDMA (including I2S) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_initial_buffers Pointer to a structure specifying the buffers + * to be used in the initial part of the transfer + * (buffers for all consecutive parts are provided + * through the data handler). + * @param[in] buffer_size Size of the buffers (in 32-bit words). + * Must not be 0. + * @param[in] flags Transfer options (0 for default settings). + * Currently, no additional flags are available. + * + * @retval NRFX_SUCCESS If the operation was successful. + * @retval NRFX_ERROR_INVALID_STATE If a transfer was already started or + * the driver has not been initialized. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed + * in the Data RAM region. + */ +nrfx_err_t nrfx_i2s_start(nrfx_i2s_buffers_t const * p_initial_buffers, + uint16_t buffer_size, + uint8_t flags); + +/** + * @brief Function for supplying the buffers to be used in the next part of + * the transfer. + * + * The application should call this function when the data handler receives + * @ref NRFX_I2S_STATUS_NEXT_BUFFERS_NEEDED in the @c status parameter. + * The call can be done immediately from the data handler function or later, + * but it has to be done before the I2S peripheral finishes processing the + * buffers supplied previously. Otherwise, data corruption will occur. + * + * @sa nrfx_i2s_data_handler_t + * + * @retval NRFX_SUCCESS If the operation was successful. + * @retval NRFX_ERROR_INVALID_STATE If the buffers were already supplied or + * the peripheral is currently being stopped. + */ +nrfx_err_t nrfx_i2s_next_buffers_set(nrfx_i2s_buffers_t const * p_buffers); + +/** @brief Function for stopping the I2S transfer. */ +void nrfx_i2s_stop(void); + +/** @} */ + + +void nrfx_i2s_irq_handler(void); + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_I2S_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_lpcomp.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_lpcomp.h new file mode 100755 index 0000000..fada3ae --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_lpcomp.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_LPCOMP_H__ +#define NRFX_LPCOMP_H__ + +#include <nrfx.h> +#include <hal/nrf_lpcomp.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_lpcomp LPCOMP driver + * @{ + * @ingroup nrf_lpcomp + * @brief Low Power Comparator (LPCOMP) peripheral driver. + */ + +/** + * @brief LPCOMP event handler function type. + * @param[in] event LPCOMP event. + */ +typedef void (* nrfx_lpcomp_event_handler_t)(nrf_lpcomp_event_t event); + +/** @brief LPCOMP configuration. */ +typedef struct +{ + nrf_lpcomp_config_t hal; /**< LPCOMP HAL configuration. */ + nrf_lpcomp_input_t input; /**< Input to be monitored. */ + uint8_t interrupt_priority; /**< LPCOMP interrupt priority. */ +} nrfx_lpcomp_config_t; + +/** @brief LPCOMP driver default configuration including the LPCOMP HAL configuration. */ +#ifdef NRF52_SERIES +#define NRFX_LPCOMP_DEFAULT_CONFIG \ + { \ + .hal = { (nrf_lpcomp_ref_t)NRFX_LPCOMP_CONFIG_REFERENCE , \ + (nrf_lpcomp_detect_t)NRFX_LPCOMP_CONFIG_DETECTION, \ + (nrf_lpcomp_hysteresis_t)NRFX_LPCOMP_CONFIG_HYST }, \ + .input = (nrf_lpcomp_input_t)NRFX_LPCOMP_CONFIG_INPUT, \ + .interrupt_priority = NRFX_LPCOMP_CONFIG_IRQ_PRIORITY \ + } +#else +#define NRFX_LPCOMP_DEFAULT_CONFIG \ + { \ + .hal = { (nrf_lpcomp_ref_t)NRFX_LPCOMP_CONFIG_REFERENCE , \ + (nrf_lpcomp_detect_t)NRFX_LPCOMP_CONFIG_DETECTION }, \ + .input = (nrf_lpcomp_input_t)NRFX_LPCOMP_CONFIG_INPUT, \ + .interrupt_priority = NRFX_LPCOMP_CONFIG_IRQ_PRIORITY \ + } +#endif + +/** + * @brief Function for initializing the LPCOMP driver. + * + * This function initializes the LPCOMP driver, but does not enable the peripheral or any interrupts. + * To start the driver, call the function nrfx_lpcomp_enable() after initialization. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver has already been initialized. + * @retval NRFX_ERROR_BUSY If the COMP peripheral is already in use. + * This is possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_lpcomp_init(nrfx_lpcomp_config_t const * p_config, + nrfx_lpcomp_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the LCOMP driver. + * + * This function uninitializes the LPCOMP driver. The LPCOMP peripheral and + * its interrupts are disabled, and local variables are cleaned. After this call, you must + * initialize the driver again by calling nrfx_lpcomp_init() if you want to use it. + * + * @sa nrfx_lpcomp_disable() + * @sa nrfx_lpcomp_init() + */ +void nrfx_lpcomp_uninit(void); + +/**@brief Function for enabling the LPCOMP peripheral and interrupts. + * + * Before calling this function, the driver must be initialized. This function + * enables the LPCOMP peripheral and its interrupts. + * + * @sa nrfx_lpcomp_disable() + */ +void nrfx_lpcomp_enable(void); + +/**@brief Function for disabling the LPCOMP peripheral. + * + * Before calling this function, the driver must be initialized. This function disables the LPCOMP + * peripheral and its interrupts. + * + * @sa nrfx_lpcomp_enable() + */ +void nrfx_lpcomp_disable(void); + + +void nrfx_lpcomp_irq_handler(void); + +/** @} **/ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LPCOMP_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_nfct.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_nfct.h new file mode 100755 index 0000000..ceb5a34 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_nfct.h @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_NFCT_H__ +#define NRFX_NFCT_H__ + +#include <nrfx.h> +#include <hal/nrf_nfct.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_nfct NFCT driver + * @{ + * @ingroup nrf_nfct + * @brief Near Field Communication Tag (NFCT) peripheral driver. + */ + +#define NRFX_NFCT_NFCID1_SINGLE_SIZE 4u ///< Length of single-size NFCID1. +#define NRFX_NFCT_NFCID1_DOUBLE_SIZE 7u ///< Length of double-size NFCID1. +#define NRFX_NFCT_NFCID1_TRIPLE_SIZE 10u ///< Length of triple-size NFCID1. + +#define NRFX_NFCT_NFCID1_DEFAULT_LEN NRFX_NFCT_NFCID1_DOUBLE_SIZE ///< Default length of NFC ID. */ + +/** + * @brief NFCT hardware states. + */ +typedef enum +{ + NRFX_NFCT_STATE_DISABLED = NRF_NFCT_TASK_DISABLE, ///< NFC Tag is disabled (no sensing of an external NFC field). + NRFX_NFCT_STATE_SENSING = NRF_NFCT_TASK_SENSE, ///< NFC Tag is sensing whether there is an external NFC field. + NRFX_NFCT_STATE_ACTIVATED = NRF_NFCT_TASK_ACTIVATE, ///< NFC Tag is powered-up (see @ref nrfx_nfct_active_state_t for possible substates). +} nrfx_nfct_state_t; + +/** + * @brief NFC tag states, when NFCT hardware is activated. + * + * @details These states are substates of the @ref NRFX_NFCT_STATE_ACTIVATED state. + */ +typedef enum +{ + NRFX_NFCT_ACTIVE_STATE_IDLE = NRF_NFCT_TASK_GOIDLE, ///< NFC Tag is activated and idle (not selected by a reader). + NRFX_NFCT_ACTIVE_STATE_SLEEP = NRF_NFCT_TASK_GOSLEEP, ///< NFC Tag is sleeping. + NRFX_NFCT_ACTIVE_STATE_DEFAULT, ///< NFC Tag is either sleeping or idle, depending on the previous state before being selected by a poller. +} nrfx_nfct_active_state_t; + +/** + * @brief NFCT driver event types, passed to the upper-layer callback function + * provided during the initialization. + */ +typedef enum +{ + NRFX_NFCT_EVT_FIELD_DETECTED = NRF_NFCT_INT_FIELDDETECTED_MASK, ///< External NFC field is detected. + NRFX_NFCT_EVT_FIELD_LOST = NRF_NFCT_INT_FIELDLOST_MASK, ///< External NFC Field is lost. + NRFX_NFCT_EVT_SELECTED = NRF_NFCT_INT_SELECTED_MASK, ///< Tag was selected by the poller. + NRFX_NFCT_EVT_RX_FRAMESTART = NRF_NFCT_INT_RXFRAMESTART_MASK, ///< Data frame reception started. + NRFX_NFCT_EVT_RX_FRAMEEND = NRF_NFCT_INT_RXFRAMEEND_MASK, ///< Data frame is received. + NRFX_NFCT_EVT_TX_FRAMESTART = NRF_NFCT_INT_TXFRAMESTART_MASK, ///< Data frame transmission started. + NRFX_NFCT_EVT_TX_FRAMEEND = NRF_NFCT_INT_TXFRAMEEND_MASK, ///< Data frame is transmitted. + NRFX_NFCT_EVT_ERROR = NRF_NFCT_INT_ERROR_MASK, ///< Error occurred in an NFC communication. +} nrfx_nfct_evt_id_t; + +/** + * @brief NFCT timing-related error types. + */ +typedef enum +{ + NRFX_NFCT_ERROR_FRAMEDELAYTIMEOUT, ///< No response frame was transmitted to the poller in the transmit window. + NRFX_NFCT_ERROR_NUM, ///< Total number of possible errors. +} nrfx_nfct_error_t; + +/** + * @brief NFCT driver parameter types. + */ +typedef enum +{ + NRFX_NFCT_PARAM_ID_FDT, ///< NFC-A Frame Delay Time parameter. + NRFX_NFCT_PARAM_ID_SEL_RES, ///< Value of the 'Protocol' field in the NFC-A SEL_RES frame. + NRFX_NFCT_PARAM_ID_NFCID1, ///< NFC-A NFCID1 setting (NFC tag identifier). +} nrfx_nfct_param_id_t; + +/** + * @brief NFCID1 descriptor. + */ +typedef struct +{ + uint8_t const * p_id; ///< NFCID1 data. + uint8_t id_size; ///< NFCID1 size. +} nrfx_nfct_nfcid1_t; + +/** + * @brief NFCT driver parameter descriptor. + */ +typedef struct +{ + nrfx_nfct_param_id_t id; ///< Type of parameter. + union + { + uint32_t fdt; ///< NFC-A Frame Delay Time. Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_FDT. + uint8_t sel_res_protocol; ///< NFC-A value of the 'Protocol' field in the SEL_RES frame. Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_SEL_RES. + nrfx_nfct_nfcid1_t nfcid1; ///< NFC-A NFCID1 value (tag identifier). Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_NFCID1. + } data; +} nrfx_nfct_param_t; + +/** + * @brief NFCT driver RX/TX buffer descriptor. + */ +typedef struct +{ + uint32_t data_size; ///< RX/TX buffer size. + uint8_t const * p_data; ///< RX/TX buffer. +} nrfx_nfct_data_desc_t; + +/** + * @brief Structure used to describe the @ref NRFX_NFCT_EVT_RX_FRAMEEND event type. + */ +typedef struct +{ + uint32_t rx_status; ///< RX error status. + nrfx_nfct_data_desc_t rx_data; ///< RX buffer. +} nrfx_nfct_evt_rx_frameend_t; + +/** + * @brief Structure used to describe the @ref NRFX_NFCT_EVT_TX_FRAMESTART event type. + */ +typedef struct +{ + nrfx_nfct_data_desc_t tx_data; ///< TX buffer. +} nrfx_nfct_evt_tx_framestart_t; + +/** + * @brief Structure used to describe the @ref NRFX_NFCT_EVT_ERROR event type. + */ +typedef struct +{ + nrfx_nfct_error_t reason; ///< Reason for error. +} nrfx_nfct_evt_error_t; + +/** + * @brief NFCT driver event. + */ +typedef struct +{ + nrfx_nfct_evt_id_t evt_id; ///< Type of event. + union + { + nrfx_nfct_evt_rx_frameend_t rx_frameend; ///< End of the RX frame data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_RX_FRAMEEND. + nrfx_nfct_evt_tx_framestart_t tx_framestart; ///< Start of the TX frame data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_TX_FRAMESTART. + nrfx_nfct_evt_error_t error; ///< Error data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_ERROR. + } params; +} nrfx_nfct_evt_t; + +/** + * @brief Callback descriptor to pass events from the NFCT driver to the upper layer. + * + * @param[in] p_event Pointer to the event descriptor. + */ +typedef void (*nrfx_nfct_handler_t)(nrfx_nfct_evt_t const * p_event); + +/** + * @brief NFCT driver configuration structure. + */ +typedef struct +{ + uint32_t rxtx_int_mask; ///< Mask for enabling RX/TX events. Indicate which events must be forwarded to the upper layer by using @ref nrfx_nfct_evt_id_t. By default, no events are enabled. */ + nrfx_nfct_handler_t cb; ///< Callback. +} nrfx_nfct_config_t; + +/** + * @brief Function for initializing the NFCT driver. + * + * @param[in] p_config Pointer to the NFCT driver configuration structure. + * + * @retval NRFX_SUCCESS If the NFCT driver was initialized successfully. + * @retval NRFX_ERROR_INVALID_STATE If the NFCT driver is already initialized. + */ +nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config); + +/** + * @brief Function for uninitializing the NFCT driver. + * + * After uninitialization, the instance is in disabled state. + */ +void nrfx_nfct_uninit(void); + +/** + * @brief Function for starting the NFC subsystem. + * + * After this function completes, NFC readers are able to detect the tag. + */ +void nrfx_nfct_enable(void); + +/** + * @brief Function for disabling the NFCT driver. + * + * After this function returns, NFC readers are no longer able to connect + * to the tag. + */ +void nrfx_nfct_disable(void); + +/** + * @brief Function for checking whether the external NFC field is present in the range of the tag. + * + * @retval true If the NFC field is present. + * @retval false If no NFC field is present. + */ +bool nrfx_nfct_field_check(void); + +/** + * @brief Function for preparing the NFCT driver for receiving an NFC frame. + * + * @param[in] p_rx_data Pointer to the RX buffer. + */ +void nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_rx_data); + +/** + * @brief Function for transmitting an NFC frame. + * + * @param[in] p_tx_data Pointer to the TX buffer. + * @param[in] delay_mode Delay mode of the NFCT frame timer. + * + * @retval NRFX_SUCCESS If the operation was successful. + * @retval NRFX_ERROR_INVALID_LENGTH If the TX buffer size is invalid. + */ +nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data, + nrf_nfct_frame_delay_mode_t delay_mode); + +/** + * @brief Function for moving the NFCT to a new state. + * + * @note The HFCLK must be running before activating the NFCT with + * @ref NRFX_NFCT_STATE_ACTIVATED. + * + * @param[in] state The required state. + */ +void nrfx_nfct_state_force(nrfx_nfct_state_t state); + +/** + * @brief Function for moving the NFCT to a new initial substate within @ref NRFX_NFCT_STATE_ACTIVATED. + * + * @param[in] sub_state The required substate. + */ +void nrfx_nfct_init_substate_force(nrfx_nfct_active_state_t sub_state); + +/** + * @brief Function for setting the NFC communication parameter. + * + * @note Parameter validation for length and acceptable values. + * + * @param[in] p_param Pointer to parameter descriptor. + * + * @retval NRFX_SUCCESS If the operation was successful. + * @retval NRFX_ERROR_INVALID_PARAM If the parameter data is invalid. + */ +nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param); + +/** + * @brief Function for getting default bytes for NFCID1. + * + * @param[in,out] p_nfcid1_buff In: empty buffer for data; + * Out: buffer with the NFCID1 default data. These values + * can be used to fill the Type 2 Tag Internal Bytes. + * @param[in] nfcid1_buff_len Length of the NFCID1 buffer. + * + * @retval NRFX_SUCCESS If the operation was successful. + * @retval NRFX_ERROR_INVALID_LENGTH If length of the NFCID buffer is different than + * @ref NRFX_NFCT_NFCID1_SINGLE_SIZE, + * @ref NRFX_NFCT_NFCID1_DOUBLE_SIZE, or + * @ref NRFX_NFCT_NFCID1_TRIPLE_SIZE. + */ +nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff, + uint32_t nfcid1_buff_len); + +/** + * @brief Function for enabling the automatic collision resolution. + * + * @details As defined by the NFC Forum Digital Protocol Technical Specification (and ISO 14443-3), + * the automatic collision resolution is implemented in the NFCT hardware. + * This function allows enabling and disabling this feature. + */ +void nrfx_nfct_autocolres_enable(void); + +/** + * @brief Function for disabling the automatic collision resolution. + * + * @details See also details in @ref nrfx_nfct_autocolres_enable. + */ +void nrfx_nfct_autocolres_disable(void); + + +void nrfx_nfct_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + + +/** + * @defgroup nrfx_nfct_fixes NFCT driver fixes and workarounds + * @{ + * @ingroup nrf_nfct + * @brief Fixes for hardware-related anomalies. + * + * If you are using the nRF52832 chip, the workarounds for the following anomalies are applied: + * - 79. NFCT: A false EVENTS_FIELDDETECTED event occurs after the field is lost. + * - 116. NFCT does not release HFCLK when switching from ACTIVATED to SENSE mode. + * To implement the first workaround, an instance of NRF_TIMER is used. After the NFC field is detected, + * the timing module periodically polls its state to determine when the field is turned off. + * To implement the second workaround, power reset is used to release the clock acquired by NFCT + * after the field is turned off. Note that the NFCT register configuration is restored to defaults. + * + * If you are using the nRF52840 chip, rev. Engineering A, the workarounds for the following anomalies + * are applied: + * - 98. NFCT: The NFCT is not able to communicate with the peer. + * - 116. NFCT does not release HFCLK when switching from ACTIVATED to SENSE mode. + * - 144. NFCT: Not optimal NFC performance + * + * If you are using the nRF52840 chip, rev. 1, or rev. Engineering B or C, the workarounds for the following + * anomalies are applied: + * - 190. NFCT: Event FIELDDETECTED can be generated too early. + * To implement this workaround, an instance of NRF_TIMER is used. After the NFC field is detected, + * the timing module measures the necessary waiting period after which NFCT can be activated. + * This debouncing technique is used to filter possible field instabilities. + * + * The application of the implemented workarounds for the nRF52840 chip is determined at runtime and depends + * on the chip variant. + * + * The current code contains a patch for the anomaly 25 (NFCT: Reset value of + * SENSRES register is incorrect), so that the module now works on Windows Phone. + * @} + */ + +#endif // NRFX_NFCT_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_pdm.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_pdm.h new file mode 100755 index 0000000..49d5dbf --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_pdm.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_PDM_H__ +#define NRFX_PDM_H__ + +#include <nrfx.h> +#include <hal/nrf_pdm.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_pdm PDM driver + * @{ + * @ingroup nrf_pdm + * @brief Pulse Density Modulation (PDM) peripheral driver. + */ + + +#define NRFX_PDM_MAX_BUFFER_SIZE 32767 + + +/** + * @brief PDM error type. + */ +typedef enum +{ + NRFX_PDM_NO_ERROR = 0, + NRFX_PDM_ERROR_OVERFLOW = 1 +} nrfx_pdm_error_t; + +/** + * @brief PDM event structure. + */ +typedef struct +{ + bool buffer_requested; ///< Buffer request flag. + int16_t * buffer_released; ///< Pointer to the released buffer. Can be NULL. + nrfx_pdm_error_t error; ///< Error type. +} nrfx_pdm_evt_t; + +/** + * @brief PDM interface driver configuration structure. + */ +typedef struct +{ + nrf_pdm_mode_t mode; ///< Interface operation mode. + nrf_pdm_edge_t edge; ///< Sampling mode. + uint8_t pin_clk; ///< CLK pin. + uint8_t pin_din; ///< DIN pin. + nrf_pdm_freq_t clock_freq; ///< Clock frequency. + nrf_pdm_gain_t gain_l; ///< Left channel gain. + nrf_pdm_gain_t gain_r; ///< Right channel gain. + uint8_t interrupt_priority; ///< Interrupt priority. +} nrfx_pdm_config_t; + +/** + * @brief Macro for setting @ref nrfx_pdm_config_t to default settings + * in single ended mode. + * + * @param _pin_clk CLK output pin. + * @param _pin_din DIN input pin. + */ +#define NRFX_PDM_DEFAULT_CONFIG(_pin_clk, _pin_din) \ +{ \ + .mode = (nrf_pdm_mode_t)NRFX_PDM_CONFIG_MODE, \ + .edge = (nrf_pdm_edge_t)NRFX_PDM_CONFIG_EDGE, \ + .pin_clk = _pin_clk, \ + .pin_din = _pin_din, \ + .clock_freq = (nrf_pdm_freq_t)NRFX_PDM_CONFIG_CLOCK_FREQ, \ + .gain_l = NRF_PDM_GAIN_DEFAULT, \ + .gain_r = NRF_PDM_GAIN_DEFAULT, \ + .interrupt_priority = NRFX_PDM_CONFIG_IRQ_PRIORITY \ +} + +/** + * @brief Handler for PDM interface ready events. + * + * This event handler is called on a buffer request, an error or when a buffer + * is full and ready to be processed. + * + * @param[in] p_evt Pointer to the PDM event structure. + */ +typedef void (*nrfx_pdm_event_handler_t)(nrfx_pdm_evt_t const * const p_evt); + + +/** + * @brief Function for initializing the PDM interface. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. Cannot be NULL. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized. + * @retval NRFX_ERROR_INVALID_PARAM If invalid configuration was specified. + */ +nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config, + nrfx_pdm_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the PDM interface. + * + * This function stops PDM sampling, if it is in progress. + */ +void nrfx_pdm_uninit(void); + +/** + * @brief Function for getting the address of a PDM interface task. + * + * @param[in] task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_pdm_task_address_get(nrf_pdm_task_t task) +{ + return nrf_pdm_task_address_get(task); +} + +/** + * @brief Function for getting the state of the PDM interface. + * + * @retval true If the PDM interface is enabled. + * @retval false If the PDM interface is disabled. + */ +__STATIC_INLINE bool nrfx_pdm_enable_check(void) +{ + return nrf_pdm_enable_check(); +} + +/** + * @brief Function for starting PDM sampling. + * + * @retval NRFX_SUCCESS If sampling was started successfully or was already in progress. + * @retval NRFX_ERROR_BUSY If a previous start/stop operation is in progress. + */ +nrfx_err_t nrfx_pdm_start(void); + +/** + * @brief Function for stopping PDM sampling. + * + * When this function is called, the PDM interface is stopped after finishing + * the current frame. + * The event handler function might be called once more after calling this function. + * + * @retval NRFX_SUCCESS If sampling was stopped successfully or was already stopped before. + * @retval NRFX_ERROR_BUSY If a previous start/stop operation is in progress. + */ +nrfx_err_t nrfx_pdm_stop(void); + +/** + * @brief Function for supplying the sample buffer. + * + * Call this function after every buffer request event. + * + * @param[in] buffer Pointer to the receive buffer. Cannot be NULL. + * @param[in] buffer_length Length of the receive buffer in 16-bit words. + * + * @retval NRFX_SUCCESS If the buffer was applied successfully. + * @retval NRFX_ERROR_BUSY If the buffer was already supplied or the peripheral is currently being stopped. + * @retval NRFX_ERROR_INVALID_STATE If the driver was not initialized. + * @retval NRFX_ERROR_INVALID_PARAM If invalid parameters were provided. + */ +nrfx_err_t nrfx_pdm_buffer_set(int16_t * buffer, uint16_t buffer_length); + + +void nrfx_pdm_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_PDM_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_power.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_power.h new file mode 100755 index 0000000..a587630 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_power.h @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_POWER_H__ +#define NRFX_POWER_H__ + +#include <nrfx.h> +#include <hal/nrf_power.h> +#include <nrfx_power_clock.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_power POWER driver + * @{ + * @ingroup nrf_power + * @brief POWER peripheral driver. + */ + +/** + * @brief Power mode possible configurations + */ +typedef enum +{ + NRFX_POWER_MODE_CONSTLAT, /**< Constant latency mode */ + NRFX_POWER_MODE_LOWPWR /**< Low power mode */ +}nrfx_power_mode_t; + +#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) +/** + * @brief Events from power system + */ +typedef enum +{ + NRFX_POWER_SLEEP_EVT_ENTER, /**< CPU entered WFI/WFE sleep + * + * Keep in mind that if this interrupt is enabled, + * it means that CPU was waken up just after WFI by this interrupt. + */ + NRFX_POWER_SLEEP_EVT_EXIT /**< CPU exited WFI/WFE sleep */ +}nrfx_power_sleep_evt_t; +#endif /* NRF_POWER_HAS_SLEEPEVT */ + +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) +/** + * @brief Events from USB power system + */ +typedef enum +{ + NRFX_POWER_USB_EVT_DETECTED, /**< USB power detected on the connector (plugged in). */ + NRFX_POWER_USB_EVT_REMOVED, /**< USB power removed from the connector. */ + NRFX_POWER_USB_EVT_READY /**< USB power regulator ready. */ +}nrfx_power_usb_evt_t; + +/** + * @brief USB power state + * + * The single enumerator that holds all data about current state of USB + * related POWER. + * + * Organized this way that higher power state has higher numeric value + */ +typedef enum +{ + NRFX_POWER_USB_STATE_DISCONNECTED, /**< No power on USB lines detected */ + NRFX_POWER_USB_STATE_CONNECTED, /**< The USB power is detected, but USB power regulator is not ready */ + NRFX_POWER_USB_STATE_READY /**< From the power point of view USB is ready for working */ +}nrfx_power_usb_state_t; +#endif /* NRF_POWER_HAS_USBREG */ + +/** + * @name Callback types + * + * Defined types of callback functions + * @{ + */ +/** + * @brief Event handler for power failure warning + */ +typedef void (*nrfx_power_pofwarn_event_handler_t)(void); + +#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) +/** + * @brief Event handler for entering/exiting sleep + * + * @param event Event type + */ +typedef void (*nrfx_power_sleep_event_handler_t)(nrfx_power_sleep_evt_t event); +#endif + +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) +/** + * @brief Event handler for USB related power events + * + * @param event Event type + */ +typedef void (*nrfx_power_usb_event_handler_t)(nrfx_power_usb_evt_t event); +#endif +/** @} */ + +/** + * @brief General power configuration + * + * Parameters required to initialize power driver. + */ +typedef struct +{ + /** + * @brief Enable main DCDC regulator + * + * This bit only informs the driver that elements for DCDC regulator + * are installed and regulator can be used. + * The regulator would be enabled or disabled automatically + * by the hardware, basing on current power requirement. + */ + bool dcdcen:1; + +#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__) + /** + * @brief Enable HV DCDC regulator + * + * This bit only informs the driver that elements for DCDC regulator + * are installed and regulator can be used. + * The regulator would be enabled or disabled automatically + * by the hardware, basing on current power requirement. + */ + bool dcdcenhv: 1; +#endif +}nrfx_power_config_t; + +/** + * @brief The configuration for power failure comparator + * + * Configuration used to enable and configure power failure comparator + */ +typedef struct +{ + nrfx_power_pofwarn_event_handler_t handler; //!< Event handler + nrf_power_pof_thr_t thr; //!< Threshold for power failure detection +#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__) + nrf_power_pof_thrvddh_t thrvddh; //!< Threshold for power failure detection on VDDH pin +#endif +}nrfx_power_pofwarn_config_t; + +#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) +/** + * @brief The configuration of sleep event processing + * + * Configuration used to enable and configure sleep event handling + */ +typedef struct +{ + nrfx_power_sleep_event_handler_t handler; //!< Event handler + bool en_enter:1; //!< Enable event on sleep entering + bool en_exit :1; //!< Enable event on sleep exiting +}nrfx_power_sleepevt_config_t; +#endif + +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) +/** + * @brief The configuration of USB related power events + * + * Configuration used to enable and configure USB power event handling + */ +typedef struct +{ + nrfx_power_usb_event_handler_t handler; //!< Event processing +}nrfx_power_usbevt_config_t; +#endif /* NRF_POWER_HAS_USBREG */ + +/** + * @brief Function for getting the handler of the power failure comparator. + * @return Handler of the power failure comparator. + */ +nrfx_power_pofwarn_event_handler_t nrfx_power_pof_handler_get(void); + +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for getting the handler of the USB power. + * @return Handler of the USB power. + */ +nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void); +#endif + +/** + * @brief Initialize power module driver + * + * Enabled power module driver would process all the interrupts from power system. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * + * @retval NRFX_SUCCESS Successfully initialized. + * @retval NRFX_ERROR_ALREADY_INITIALIZED Module was already initialized. + */ +nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config); + +/** + * @brief Unintialize power module driver + * + * Disables all the interrupt handling in the module. + * + * @sa nrfx_power_init + */ +void nrfx_power_uninit(void); + +/** + * @brief Initialize power failure comparator + * + * Configures the power failure comparator. This function does not setup and enable it. + * Those steps can be done with functions @ref nrfx_power_pof_enable and @ref nrfx_power_pof_disable + * or with Softdevice API (when Softdevice is using). + * + * @param[in] p_config Configuration with values and event handler. + * If event handler is set to NULL, interrupt would be disabled. + */ +void nrfx_power_pof_init(nrfx_power_pofwarn_config_t const * p_config); + +/** + * @brief Enable power failure comparator + * Sets and enables interrupt of the power failure comparator. This functions cannot be using + * when Softdevice is enabled. If event handler set in init function is set to NULL, interrupt + * would be disabled. + * + * @param[in] p_config Configuration with values and event handler. + */ +void nrfx_power_pof_enable(nrfx_power_pofwarn_config_t const * p_config); + +/** + * @brief Disable the power failure comparator + * + * Disables the power failure comparator interrupt. + */ +void nrfx_power_pof_disable(void); + +/** + * @brief Clear the power failure comparator settings + * + * Clears the settings of the power failure comparator. + */ +void nrfx_power_pof_uninit(void); + +#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) +/** + * @brief Initialize sleep entering and exiting events processing + * + * Configures and setups the sleep event processing. + * + * @param[in] p_config Configuration with values and event handler. + * + * @sa nrfx_power_sleepevt_uninit + * + */ +void nrfx_power_sleepevt_init(nrfx_power_sleepevt_config_t const * p_config); + +/** + * @brief Enable sleep entering and exiting events processing + * + * @param[in] p_config Configuration with values and event handler. + */ +void nrfx_power_sleepevt_enable(nrfx_power_sleepevt_config_t const * p_config); + +/** + * @brief Disable sleep entering and exiting events processing + */ +void nrfx_power_sleepevt_disable(void); + +/** + * @brief Uninitialize sleep entering and exiting events processing + * + * @sa nrfx_power_sleepevt_init + */ +void nrfx_power_sleepevt_uninit(void); +#endif /* NRF_POWER_HAS_SLEEPEVT */ + +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) +/** + * @brief Initialize USB power event processing + * + * Configures and setups the USB power event processing. + * + * @param[in] p_config Configuration with values and event handler. + * + * @sa nrfx_power_usbevt_uninit + */ +void nrfx_power_usbevt_init(nrfx_power_usbevt_config_t const * p_config); + +/** + * @brief Enable USB power event processing + */ +void nrfx_power_usbevt_enable(void); + +/** + * @brief Disable USB power event processing + */ +void nrfx_power_usbevt_disable(void); + +/** + * @brief Uninitalize USB power event processing + * + * @sa nrfx_power_usbevt_init + */ +void nrfx_power_usbevt_uninit(void); + +/** + * @brief Get the status of USB power + * + * @return Current USB power status + */ +__STATIC_INLINE nrfx_power_usb_state_t nrfx_power_usbstatus_get(void); + +#endif /* NRF_POWER_HAS_USBREG */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +#if NRF_POWER_HAS_USBREG +__STATIC_INLINE nrfx_power_usb_state_t nrfx_power_usbstatus_get(void) +{ + uint32_t status = nrf_power_usbregstatus_get(); + if(0 == (status & NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK)) + { + return NRFX_POWER_USB_STATE_DISCONNECTED; + } + if(0 == (status & NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK)) + { + return NRFX_POWER_USB_STATE_CONNECTED; + } + return NRFX_POWER_USB_STATE_READY; +} +#endif /* NRF_POWER_HAS_USBREG */ + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + + +void nrfx_power_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRFX_POWER_H__ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_power_clock.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_power_clock.h new file mode 100755 index 0000000..3615f89 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_power_clock.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_POWER_CLOCK_H__ +#define NRFX_POWER_CLOCK_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + + +__STATIC_INLINE void nrfx_power_clock_irq_init(void); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrfx_power_clock_irq_init(void) +{ + uint8_t priority; +#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED) + #if NRFX_POWER_CONFIG_IRQ_PRIORITY != NRFX_CLOCK_CONFIG_IRQ_PRIORITY + #error "IRQ priority for POWER and CLOCK have to be the same. Check <nrfx_config.h>." + #endif + priority = NRFX_POWER_CONFIG_IRQ_PRIORITY; +#elif NRFX_CHECK(NRFX_POWER_ENABLED) + priority = NRFX_POWER_CONFIG_IRQ_PRIORITY; +#elif NRFX_CHECK(NRFX_CLOCK_ENABLED) + priority = NRFX_CLOCK_CONFIG_IRQ_PRIORITY; +#endif + + if (!NRFX_IRQ_IS_ENABLED(POWER_CLOCK_IRQn)) + { + NRFX_IRQ_PRIORITY_SET(POWER_CLOCK_IRQn, priority); + NRFX_IRQ_ENABLE(POWER_CLOCK_IRQn); + } +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED) +void nrfx_power_clock_irq_handler(void); +#elif NRFX_CHECK(NRFX_POWER_ENABLED) +#define nrfx_power_irq_handler nrfx_power_clock_irq_handler +#elif NRFX_CHECK(NRFX_CLOCK_ENABLED) +#define nrfx_clock_irq_handler nrfx_power_clock_irq_handler +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_POWER_CLOCK_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_ppi.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_ppi.h new file mode 100755 index 0000000..193148e --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_ppi.h @@ -0,0 +1,318 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_PPI_H__ +#define NRFX_PPI_H__ + +#include <nrfx.h> +#include <hal/nrf_ppi.h> + +/** + * @defgroup nrfx_ppi PPI allocator + * @{ + * @ingroup nrf_ppi + * @brief Programmable Peripheral Interconnect (PPI) allocator. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef NRFX_PPI_CHANNELS_USED +#define NRFX_PPI_CHANNELS_USED 0 +#endif + +#ifndef NRFX_PPI_GROUPS_USED +#define NRFX_PPI_GROUPS_USED 0 +#endif + +#if PPI_CH_NUM > 16 +#define NRFX_PPI_ALL_APP_CHANNELS_MASK ((uint32_t)0xFFFFFFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< All PPI channels available to the application. */ +#define NRFX_PPI_PROG_APP_CHANNELS_MASK ((uint32_t)0x000FFFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< Programmable PPI channels available to the application. */ +#else +#define NRFX_PPI_ALL_APP_CHANNELS_MASK ((uint32_t)0xFFF0FFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< All PPI channels available to the application. */ +#define NRFX_PPI_PROG_APP_CHANNELS_MASK ((uint32_t)0x0000FFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< Programmable PPI channels available to the application. */ +#endif + +#define NRFX_PPI_ALL_APP_GROUPS_MASK (((1uL << PPI_GROUP_NUM) - 1) & ~(NRFX_PPI_GROUPS_USED)) /**< All PPI groups available to the application. */ + +/** + * @brief Function for uninitializing the PPI module. + * + * This function disables all channels and clears the channel groups. + */ +void nrfx_ppi_free_all(void); + +/** + * @brief Function for allocating a PPI channel. + * @details This function allocates the first unused PPI channel. + * + * @param[out] p_channel Pointer to the PPI channel that has been allocated. + * + * @retval NRFX_SUCCESS If the channel was successfully allocated. + * @retval NRFX_ERROR_NO_MEM If there is no available channel to be used. + */ +nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel); + +/** + * @brief Function for freeing a PPI channel. + * @details This function also disables the chosen channel. + * + * @param[in] channel PPI channel to be freed. + * + * @retval NRFX_SUCCESS If the channel was successfully freed. + * @retval NRFX_ERROR_INVALID_PARAM If the channel is not user-configurable. + */ +nrfx_err_t nrfx_ppi_channel_free(nrf_ppi_channel_t channel); + +/** + * @brief Function for assigning task and event endpoints to the PPI channel. + * + * @param[in] channel PPI channel to be assigned endpoints. + * @param[in] eep Event endpoint address. + * @param[in] tep Task endpoint address. + * + * @retval NRFX_SUCCESS If the channel was successfully assigned. + * @retval NRFX_ERROR_INVALID_STATE If the channel is not allocated for the user. + * @retval NRFX_ERROR_INVALID_PARAM If the channel is not user-configurable. + */ +nrfx_err_t nrfx_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep); + +/** + * @brief Function for assigning or clearing fork endpoint to the PPI channel. + * + * @param[in] channel PPI channel to be assigned endpoints. + * @param[in] fork_tep Fork task endpoint address or 0 to clear. + * + * @retval NRFX_SUCCESS If the channel was successfully assigned. + * @retval NRFX_ERROR_INVALID_STATE If the channel is not allocated for the user. + * @retval NRFX_ERROR_INVALID_PARAM If the channel is not user-configurable. + * @retval NRFX_ERROR_NOT_SUPPORTED If function is not supported. + */ +nrfx_err_t nrfx_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep); + +/** + * @brief Function for enabling a PPI channel. + * + * @param[in] channel PPI channel to be enabled. + * + * @retval NRFX_SUCCESS If the channel was successfully enabled. + * @retval NRFX_ERROR_INVALID_STATE If the user-configurable channel is not allocated. + * @retval NRFX_ERROR_INVALID_PARAM If the channel cannot be enabled by the user. + */ +nrfx_err_t nrfx_ppi_channel_enable(nrf_ppi_channel_t channel); + +/** + * @brief Function for disabling a PPI channel. + * + * @param[in] channel PPI channel to be disabled. + * + * @retval NRFX_SUCCESS If the channel was successfully disabled. + * @retval NRFX_ERROR_INVALID_STATE If the user-configurable channel is not allocated. + * @retval NRFX_ERROR_INVALID_PARAM If the channel cannot be disabled by the user. + */ +nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel); + +/** + * @brief Function for allocating a PPI channel group. + * @details This function allocates the first unused PPI group. + * + * @param[out] p_group Pointer to the PPI channel group that has been allocated. + * + * @retval NRFX_SUCCESS If the channel group was successfully allocated. + * @retval NRFX_ERROR_NO_MEM If there is no available channel group to be used. + */ +nrfx_err_t nrfx_ppi_group_alloc(nrf_ppi_channel_group_t * p_group); + +/** + * @brief Function for freeing a PPI channel group. + * @details This function also disables the chosen group. + * + * @param[in] group PPI channel group to be freed. + * + * @retval NRFX_SUCCESS If the channel group was successfully freed. + * @retval NRFX_ERROR_INVALID_PARAM If the channel group is not user-configurable. + */ +nrfx_err_t nrfx_ppi_group_free(nrf_ppi_channel_group_t group); + +/** + * @brief Compute a channel mask for NRF_PPI registers. + * + * @param[in] channel Channel number to transform to a mask. + * + * @retval Channel mask. + */ +__STATIC_INLINE uint32_t nrfx_ppi_channel_to_mask(nrf_ppi_channel_t channel) +{ + return (1uL << (uint32_t) channel); +} + +/** + * @brief Function for including multiple PPI channels in a channel group. + * + * @param[in] channel_mask PPI channels to be added. + * @param[in] group Channel group in which to include the channels. + * + * @retval NRFX_SUCCESS If the channels was successfully included. + * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channels are not an + * application channels. + * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. + */ +nrfx_err_t nrfx_ppi_channels_include_in_group(uint32_t channel_mask, + nrf_ppi_channel_group_t group); + +/** + * @brief Function for including a PPI channel in a channel group. + * + * @param[in] channel PPI channel to be added. + * @param[in] group Channel group in which to include the channel. + * + * @retval NRFX_SUCCESS If the channel was successfully included. + * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channel is not an + * application channel. + * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. + */ +__STATIC_INLINE nrfx_err_t nrfx_ppi_channel_include_in_group(nrf_ppi_channel_t channel, + nrf_ppi_channel_group_t group) +{ + return nrfx_ppi_channels_include_in_group(nrfx_ppi_channel_to_mask(channel), group); +} + +/** + * @brief Function for removing multiple PPI channels from a channel group. + * + * @param[in] channel_mask PPI channels to be removed. + * @param[in] group Channel group from which to remove the channels. + * + * @retval NRFX_SUCCESS If the channel was successfully removed. + * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channels are not an + * application channels. + * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. + */ +nrfx_err_t nrfx_ppi_channels_remove_from_group(uint32_t channel_mask, + nrf_ppi_channel_group_t group); + +/** + * @brief Function for removing a PPI channel from a channel group. + * + * @param[in] channel PPI channel to be removed. + * @param[in] group Channel group from which to remove the channel. + * + * @retval NRFX_SUCCESS If the channel was successfully removed. + * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group or channel is not an + * application channel. + * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. + */ +__STATIC_INLINE nrfx_err_t nrfx_ppi_channel_remove_from_group(nrf_ppi_channel_t channel, + nrf_ppi_channel_group_t group) +{ + return nrfx_ppi_channels_remove_from_group(nrfx_ppi_channel_to_mask(channel), group); +} + +/** + * @brief Function for clearing a PPI channel group. + * + * @param[in] group Channel group to be cleared. + * + * @retval NRFX_SUCCESS If the group was successfully cleared. + * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group. + * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. + */ +__STATIC_INLINE nrfx_err_t nrfx_ppi_group_clear(nrf_ppi_channel_group_t group) +{ + return nrfx_ppi_channels_remove_from_group(NRFX_PPI_ALL_APP_CHANNELS_MASK, group); +} + +/** + * @brief Function for enabling a PPI channel group. + * + * @param[in] group Channel group to be enabled. + * + * @retval NRFX_SUCCESS If the group was successfully enabled. + * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group. + * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. + */ +nrfx_err_t nrfx_ppi_group_enable(nrf_ppi_channel_group_t group); + +/** + * @brief Function for disabling a PPI channel group. + * + * @param[in] group Channel group to be disabled. + * + * @retval NRFX_SUCCESS If the group was successfully disabled. + * @retval NRFX_ERROR_INVALID_PARAM If group is not an application group. + * @retval NRFX_ERROR_INVALID_STATE If group is not an allocated group. + */ +nrfx_err_t nrfx_ppi_group_disable(nrf_ppi_channel_group_t group); + +/** + * @brief Function for getting the address of a PPI task. + * + * @param[in] task Task. + * + * @retval Task address. + */ +__STATIC_INLINE uint32_t nrfx_ppi_task_addr_get(nrf_ppi_task_t task) +{ + return (uint32_t) nrf_ppi_task_address_get(task); +} + +/** + * @brief Function for getting the address of a PPI group enable task. + * + * @param[in] group PPI channel group + * + * @retval Task address. + */ +__STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_enable_get(nrf_ppi_channel_group_t group) +{ + return (uint32_t) nrf_ppi_task_group_enable_address_get(group); +} + +/** + * @brief Function for getting the address of a PPI group enable task. + * + * @param[in] group PPI channel group + * + * @retval Task address. + */ +__STATIC_INLINE uint32_t nrfx_ppi_task_addr_group_disable_get(nrf_ppi_channel_group_t group) +{ + return (uint32_t) nrf_ppi_task_group_disable_address_get(group); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_PPI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_pwm.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_pwm.h new file mode 100755 index 0000000..6e72486 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_pwm.h @@ -0,0 +1,488 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_PWM_H__ +#define NRFX_PWM_H__ + +#include <nrfx.h> +#include <hal/nrf_pwm.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_pwm PWM driver + * @{ + * @ingroup nrf_pwm + * @brief Pulse Width Modulation (PWM) peripheral driver. + */ + +/** + * @brief PWM driver instance data structure. + */ +typedef struct +{ + NRF_PWM_Type * p_registers; ///< Pointer to the structure with PWM peripheral instance registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_pwm_t; + +/** + * @brief Macro for creating a PWM driver instance. + */ +#define NRFX_PWM_INSTANCE(id) \ +{ \ + .p_registers = NRFX_CONCAT_2(NRF_PWM, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_PWM, id, _INST_IDX), \ +} + +enum { +#if NRFX_CHECK(NRFX_PWM0_ENABLED) + NRFX_PWM0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_PWM1_ENABLED) + NRFX_PWM1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_PWM2_ENABLED) + NRFX_PWM2_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_PWM3_ENABLED) + NRFX_PWM3_INST_IDX, +#endif + NRFX_PWM_ENABLED_COUNT +}; + +/** + * @brief This value can be provided instead of a pin number for any channel + * to specify that its output is not used and therefore does not need + * to be connected to a pin. + */ +#define NRFX_PWM_PIN_NOT_USED 0xFF + +/** + * @brief This value can be added to a pin number to inverse its polarity + * (set idle state = 1). + */ +#define NRFX_PWM_PIN_INVERTED 0x80 + +/** + * @brief PWM driver configuration structure. + */ +typedef struct +{ + uint8_t output_pins[NRF_PWM_CHANNEL_COUNT]; ///< Pin numbers for individual output channels (optional). + /**< Use @ref NRFX_PWM_PIN_NOT_USED + * if a given output channel is not needed. */ + uint8_t irq_priority; ///< Interrupt priority. + nrf_pwm_clk_t base_clock; ///< Base clock frequency. + nrf_pwm_mode_t count_mode; ///< Operating mode of the pulse generator counter. + uint16_t top_value; ///< Value up to which the pulse generator counter counts. + nrf_pwm_dec_load_t load_mode; ///< Mode of loading sequence data from RAM. + nrf_pwm_dec_step_t step_mode; ///< Mode of advancing the active sequence. +} nrfx_pwm_config_t; + +/** + * @brief PWM driver default configuration. + */ +#define NRFX_PWM_DEFAULT_CONFIG \ +{ \ + .output_pins = { NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN, \ + NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN, \ + NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN, \ + NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN }, \ + .irq_priority = NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .base_clock = (nrf_pwm_clk_t)NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK, \ + .count_mode = (nrf_pwm_mode_t)NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE, \ + .top_value = NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE, \ + .load_mode = (nrf_pwm_dec_load_t)NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE, \ + .step_mode = (nrf_pwm_dec_step_t)NRFX_PWM_DEFAULT_CONFIG_STEP_MODE, \ +} + + +/** + * @brief PWM flags providing additional playback options. + */ +typedef enum +{ + NRFX_PWM_FLAG_STOP = 0x01, /**< When the requested playback is finished, + the peripheral should be stopped. + @note The STOP task is triggered when + the last value of the final sequence is + loaded from RAM, and the peripheral stops + at the end of the current PWM period. + For sequences with configured repeating + of duty cycle values, this might result in + less than the requested number of repeats + of the last value. */ + NRFX_PWM_FLAG_LOOP = 0x02, /**< When the requested playback is finished, + it should be started from the beginning. + This flag is ignored if used together + with @ref NRFX_PWM_FLAG_STOP. + @note The playback restart is done via a + shortcut configured in the PWM peripheral. + This shortcut triggers the proper starting + task when the final value of previous + playback is read from RAM and applied to + the pulse generator counter. + When this mechanism is used together with + the @ref NRF_PWM_STEP_TRIGGERED mode, + the playback restart will occur right + after switching to the final value (this + final value will be played only once). */ + NRFX_PWM_FLAG_SIGNAL_END_SEQ0 = 0x04, /**< The event handler should be + called when the last value + from sequence 0 is loaded. */ + NRFX_PWM_FLAG_SIGNAL_END_SEQ1 = 0x08, /**< The event handler should be + called when the last value + from sequence 1 is loaded. */ + NRFX_PWM_FLAG_NO_EVT_FINISHED = 0x10, /**< The playback finished event + (enabled by default) should be + suppressed. */ + NRFX_PWM_FLAG_START_VIA_TASK = 0x80, /**< The playback should not be + started directly by the called + function. Instead, the function + should only prepare it and + return the address of the task + to be triggered to start the + playback. */ +} nrfx_pwm_flag_t; + + +/** + * @brief PWM driver event type. + */ +typedef enum +{ + NRFX_PWM_EVT_FINISHED, ///< Sequence playback finished. + NRFX_PWM_EVT_END_SEQ0, /**< End of sequence 0 reached. Its data can be + safely modified now. */ + NRFX_PWM_EVT_END_SEQ1, /**< End of sequence 1 reached. Its data can be + safely modified now. */ + NRFX_PWM_EVT_STOPPED, ///< The PWM peripheral has been stopped. +} nrfx_pwm_evt_type_t; + +/** + * @brief PWM driver event handler type. + */ +typedef void (* nrfx_pwm_handler_t)(nrfx_pwm_evt_type_t event_type); + + +/** + * @brief Function for initializing the PWM driver. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * + * @param[in] handler Event handler provided by the user. If NULL is passed + * instead, event notifications are not done and PWM + * interrupts are disabled. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + */ +nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * const p_instance, + nrfx_pwm_config_t const * p_config, + nrfx_pwm_handler_t handler); + +/** + * @brief Function for uninitializing the PWM driver. + * + * If any sequence playback is in progress, it is stopped immediately. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_pwm_uninit(nrfx_pwm_t const * const p_instance); + +/** + * @brief Function for starting a single sequence playback. + * + * To take advantage of the looping mechanism in the PWM peripheral, both + * sequences must be used (single sequence can be played back only once by + * the peripheral). Therefore, the provided sequence is internally set and + * played back as both sequence 0 and sequence 1. Consequently, if end of + * sequence notifications are required, events for both sequences should be + * used (that means that both the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ0 flag + * and the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ1 flag should be specified and + * the @ref NRFX_PWM_EVT_END_SEQ0 event and the @ref NRFX_PWM_EVT_END_SEQ1 + * event should be handled in the same way). + * + * Use the @ref NRFX_PWM_FLAG_START_VIA_TASK flag if you want the playback + * to be only prepared by this function, and you want to start it later by + * triggering a task (using PPI for instance). The function will then return + * the address of the task to be triggered. + * + * @note The array containing the duty cycle values for the specified sequence + * must be in RAM and cannot be allocated on stack. + * For detailed information, see @ref nrf_pwm_sequence_t. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_sequence Sequence to be played back. + * @param[in] playback_count Number of playbacks to be performed (must not be 0). + * @param[in] flags Additional options. Pass any combination of + * @ref nrfx_pwm_flag_t "playback flags", or 0 + * for default settings. + * + * @return Address of the task to be triggered to start the playback if the @ref + * NRFX_PWM_FLAG_START_VIA_TASK flag was used, 0 otherwise. + */ +uint32_t nrfx_pwm_simple_playback(nrfx_pwm_t const * const p_instance, + nrf_pwm_sequence_t const * p_sequence, + uint16_t playback_count, + uint32_t flags); + +/** + * @brief Function for starting a two-sequence playback. + * + * Use the @ref NRFX_PWM_FLAG_START_VIA_TASK flag if you want the playback + * to be only prepared by this function, and you want to start it later by + * triggering a task (using PPI for instance). The function will then return + * the address of the task to be triggered. + * + * @note The array containing the duty cycle values for the specified sequence + * must be in RAM and cannot be allocated on stack. + * For detailed information, see @ref nrf_pwm_sequence_t. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_sequence_0 First sequence to be played back. + * @param[in] p_sequence_1 Second sequence to be played back. + * @param[in] playback_count Number of playbacks to be performed (must not be 0). + * @param[in] flags Additional options. Pass any combination of + * @ref nrfx_pwm_flag_t "playback flags", or 0 + * for default settings. + * + * @return Address of the task to be triggered to start the playback if the @ref + * NRFX_PWM_FLAG_START_VIA_TASK flag was used, 0 otherwise. + */ +uint32_t nrfx_pwm_complex_playback(nrfx_pwm_t const * const p_instance, + nrf_pwm_sequence_t const * p_sequence_0, + nrf_pwm_sequence_t const * p_sequence_1, + uint16_t playback_count, + uint32_t flags); + +/** + * @brief Function for advancing the active sequence. + * + * This function only applies to @ref NRF_PWM_STEP_TRIGGERED mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance); + +/** + * @brief Function for stopping the sequence playback. + * + * The playback is stopped at the end of the current PWM period. + * This means that if the active sequence is configured to repeat each duty + * cycle value for a certain number of PWM periods, the last played value + * might appear on the output less times than requested. + * + * @note This function can be instructed to wait until the playback is stopped + * (by setting @p wait_until_stopped to true). Note that, depending on + * the length of the PMW period, this might take a significant amount of + * time. Alternatively, the @ref nrfx_pwm_is_stopped function can be + * used to poll the status, or the @ref NRFX_PWM_EVT_STOPPED event can + * be used to get the notification when the playback is stopped, provided + * the event handler is defined. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] wait_until_stopped If true, the function will not return until + * the playback is stopped. + * + * @retval true If the PWM peripheral is stopped. + * @retval false If the PWM peripheral is not stopped. + */ +bool nrfx_pwm_stop(nrfx_pwm_t const * const p_instance, + bool wait_until_stopped); + +/** + * @brief Function for checking the status of the PWM peripheral. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If the PWM peripheral is stopped. + * @retval false If the PWM peripheral is not stopped. + */ +bool nrfx_pwm_is_stopped(nrfx_pwm_t const * const p_instance); + +/** + * @brief Function for updating the sequence data during playback. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] p_sequence Pointer to the new sequence definition. + */ +__STATIC_INLINE void nrfx_pwm_sequence_update( + nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + nrf_pwm_sequence_t const * p_sequence); + +/** + * @brief Function for updating the pointer to the duty cycle values + * in the specified sequence during playback. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] values New pointer to the duty cycle values. + */ +__STATIC_INLINE void nrfx_pwm_sequence_values_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + nrf_pwm_values_t values); + +/** + * @brief Function for updating the number of duty cycle values + * in the specified sequence during playback. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] length New number of the duty cycle values. + */ +__STATIC_INLINE void nrfx_pwm_sequence_length_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + uint16_t length); + +/** + * @brief Function for updating the number of repeats for duty cycle values + * in specified sequence during playback. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] repeats New number of repeats. + */ +__STATIC_INLINE void nrfx_pwm_sequence_repeats_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + uint32_t repeats); + +/** + * @brief Function for updating the additional delay after the specified + * sequence during playback. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] end_delay New end delay value (in PWM periods). + */ +__STATIC_INLINE void nrfx_pwm_sequence_end_delay_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + uint32_t end_delay); + +/** + * @brief Function for returning the address of a specified PWM task that can + * be used in PPI module. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] task Requested task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_pwm_task_address_get(nrfx_pwm_t const * const p_instance, + nrf_pwm_task_t task); + +/**@brief Function for returning the address of a specified PWM event that can + * be used in PPI module. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event Requested event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_instance, + nrf_pwm_event_t event); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance) +{ + nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_NEXTSTEP); +} + +__STATIC_INLINE void nrfx_pwm_sequence_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + nrf_pwm_sequence_t const * p_sequence) +{ + nrf_pwm_sequence_set(p_instance->p_registers, seq_id, p_sequence); +} + +__STATIC_INLINE void nrfx_pwm_sequence_values_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + nrf_pwm_values_t values) +{ + nrf_pwm_seq_ptr_set(p_instance->p_registers, seq_id, values.p_raw); +} + +__STATIC_INLINE void nrfx_pwm_sequence_length_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + uint16_t length) +{ + nrf_pwm_seq_cnt_set(p_instance->p_registers, seq_id, length); +} + +__STATIC_INLINE void nrfx_pwm_sequence_repeats_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + uint32_t repeats) +{ + nrf_pwm_seq_refresh_set(p_instance->p_registers, seq_id, repeats); +} + +__STATIC_INLINE void nrfx_pwm_sequence_end_delay_update(nrfx_pwm_t const * const p_instance, + uint8_t seq_id, + uint32_t end_delay) +{ + nrf_pwm_seq_end_delay_set(p_instance->p_registers, seq_id, end_delay); +} + +__STATIC_INLINE uint32_t nrfx_pwm_task_address_get(nrfx_pwm_t const * const p_instance, + nrf_pwm_task_t task) +{ + return nrf_pwm_task_address_get(p_instance->p_registers, task); +} + +__STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_instance, + nrf_pwm_event_t event) +{ + return nrf_pwm_event_address_get(p_instance->p_registers, event); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_pwm_0_irq_handler(void); +void nrfx_pwm_1_irq_handler(void); +void nrfx_pwm_2_irq_handler(void); +void nrfx_pwm_3_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_PWM_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_qdec.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_qdec.h new file mode 100755 index 0000000..c8b3f64 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_qdec.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_QDEC_H__ +#define NRFX_QDEC_H__ + +#include <nrfx.h> +#include <hal/nrf_qdec.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_qdec QDEC driver + * @{ + * @ingroup nrf_qdec + * @brief Quadrature Decoder (QDEC) peripheral driver. + */ + +/**@brief QDEC configuration structure.*/ +typedef struct +{ + nrf_qdec_reportper_t reportper; /**< Report period in samples. */ + nrf_qdec_sampleper_t sampleper; /**< Sampling period in microseconds. */ + uint32_t psela; /**< Pin number for A input. */ + uint32_t pselb; /**< Pin number for B input. */ + uint32_t pselled; /**< Pin number for LED output. */ + uint32_t ledpre; /**< Time (in microseconds) how long LED is switched on before sampling. */ + nrf_qdec_ledpol_t ledpol; /**< Active LED polarity. */ + bool dbfen; /**< State of debouncing filter. */ + bool sample_inten; /**< Enabling sample ready interrupt. */ + uint8_t interrupt_priority; /**< QDEC interrupt priority. */ +} nrfx_qdec_config_t; + +/**@brief QDEC default configuration. */ +#define NRFX_QDEC_DEFAULT_CONFIG \ + { \ + .reportper = (nrf_qdec_reportper_t)NRFX_QDEC_CONFIG_REPORTPER, \ + .sampleper = (nrf_qdec_sampleper_t)NRFX_QDEC_CONFIG_SAMPLEPER, \ + .psela = NRFX_QDEC_CONFIG_PIO_A, \ + .pselb = NRFX_QDEC_CONFIG_PIO_B, \ + .pselled = NRFX_QDEC_CONFIG_PIO_LED, \ + .ledpre = NRFX_QDEC_CONFIG_LEDPRE, \ + .ledpol = (nrf_qdec_ledpol_t)NRFX_QDEC_CONFIG_LEDPOL, \ + .interrupt_priority = NRFX_QDEC_CONFIG_IRQ_PRIORITY, \ + .dbfen = NRFX_QDEC_CONFIG_DBFEN, \ + .sample_inten = NRFX_QDEC_CONFIG_SAMPLE_INTEN \ + } + +/**@brief QDEC sample event data.*/ +typedef struct +{ + int8_t value; /**< Sample value. */ +} nrfx_qdec_sample_data_evt_t; + +/**@brief QDEC report event data.*/ +typedef struct +{ + int16_t acc; /**< Accumulated transitions. */ + uint16_t accdbl; /**< Accumulated double transitions. */ +} nrfx_qdec_report_data_evt_t; + +/**@brief QDEC event handler structure. */ +typedef struct +{ + nrf_qdec_event_t type; + union + { + nrfx_qdec_sample_data_evt_t sample; /**< Sample event data. */ + nrfx_qdec_report_data_evt_t report; /**< Report event data. */ + } data; +} nrfx_qdec_event_t; + +/**@brief QDEC event handler. + * @param[in] event QDEC event structure. + */ +typedef void (*nrfx_qdec_event_handler_t)(nrfx_qdec_event_t event); + +/**@brief Function for initializing QDEC. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If QDEC was already initialized. + */ +nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config, + nrfx_qdec_event_handler_t event_handler); + +/**@brief Function for uninitializing QDEC. + * @note Function asserts if module is uninitialized. + */ +void nrfx_qdec_uninit(void); + +/**@brief Function for enabling QDEC. + * @note Function asserts if module is uninitialized or enabled. + */ +void nrfx_qdec_enable(void); + +/**@brief Function for disabling QDEC. + * @note Function asserts if module is uninitialized or disabled. + */ +void nrfx_qdec_disable(void); + +/**@brief Function for reading accumulated transitions QDEC. + * @note Function asserts if module is not enabled. + * @note Accumulators are cleared after reading. + * + * @param[out] p_acc Pointer to store accumulated transitions. + * @param[out] p_accdbl Pointer to store accumulated double transitions. + */ +void nrfx_qdec_accumulators_read(int16_t * p_acc, int16_t * p_accdbl); + +/** + * @brief Function for returning the address of a specific QDEC task. + * + * @param task QDEC task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_qdec_task_address_get(nrf_qdec_task_t task) +{ + return (uint32_t)nrf_qdec_task_address_get(task); +} + +/** + * @brief Function for returning the address of a specific QDEC event. + * + * @param event QDEC event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_qdec_event_address_get(nrf_qdec_event_t event) +{ + return (uint32_t)nrf_qdec_event_address_get(event); +} + + +void nrfx_qdec_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_QDEC_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_qspi.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_qspi.h new file mode 100755 index 0000000..8e2de16 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_qspi.h @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_QSPI_H__ +#define NRFX_QSPI_H__ + +#include <nrfx.h> +#include <hal/nrf_qspi.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_qspi QSPI driver + * @{ + * @ingroup nrf_qspi + * @brief Quad Serial Peripheral Interface (QSPI) peripheral driver. + */ + +/** + * @brief QSPI driver instance configuration structure. + */ +typedef struct +{ + uint32_t xip_offset; /**< Address offset into the external memory for Execute in Place operation. */ + nrf_qspi_pins_t pins; /**< Pins configuration structure. */ + nrf_qspi_prot_conf_t prot_if; /**< Protocol layer interface configuration structure. */ + nrf_qspi_phy_conf_t phy_if; /**< Physical layer interface configuration structure. */ + uint8_t irq_priority; /**< Interrupt priority. */ +} nrfx_qspi_config_t; + +/** + * @brief QSPI instance default configuration. + */ +#define NRFX_QSPI_DEFAULT_CONFIG \ +{ \ + .xip_offset = NRFX_QSPI_CONFIG_XIP_OFFSET, \ + .pins = { \ + .sck_pin = NRFX_QSPI_PIN_SCK, \ + .csn_pin = NRFX_QSPI_PIN_CSN, \ + .io0_pin = NRFX_QSPI_PIN_IO0, \ + .io1_pin = NRFX_QSPI_PIN_IO1, \ + .io2_pin = NRFX_QSPI_PIN_IO2, \ + .io3_pin = NRFX_QSPI_PIN_IO3, \ + }, \ + .irq_priority = (uint8_t)NRFX_QSPI_CONFIG_IRQ_PRIORITY, \ + .prot_if = { \ + .readoc = (nrf_qspi_readoc_t)NRFX_QSPI_CONFIG_READOC, \ + .writeoc = (nrf_qspi_writeoc_t)NRFX_QSPI_CONFIG_WRITEOC, \ + .addrmode = (nrf_qspi_addrmode_t)NRFX_QSPI_CONFIG_ADDRMODE, \ + .dpmconfig = false, \ + }, \ + .phy_if = { \ + .sck_freq = (nrf_qspi_frequency_t)NRFX_QSPI_CONFIG_FREQUENCY, \ + .sck_delay = (uint8_t)NRFX_QSPI_CONFIG_SCK_DELAY, \ + .spi_mode = (nrf_qspi_spi_mode_t)NRFX_QSPI_CONFIG_MODE, \ + .dpmen = false \ + }, \ +} + +/** + * @brief QSPI custom instruction helper with default configuration. + */ +#define NRFX_QSPI_DEFAULT_CINSTR(opc, len) \ +{ \ + .opcode = (opc), \ + .length = (len), \ + .io2_level = false, \ + .io3_level = false, \ + .wipwait = false, \ + .wren = false \ +} + +/** + * @brief QSPI master driver event types, passed to the handler routine provided + * during initialization. + */ +typedef enum +{ + NRFX_QSPI_EVENT_DONE, /**< Transfer done. */ +} nrfx_qspi_evt_t; + +/** + * @brief QSPI driver event handler type. + */ +typedef void (*nrfx_qspi_handler_t)(nrfx_qspi_evt_t event, void * p_context); + +/** + * @brief Function for initializing the QSPI driver instance. + * + * This function configures the peripheral and its interrupts and activates it. During the + * activation process, the internal clocks are started and the QSPI peripheral tries to read + * the status byte to read the busy bit. Reading the status byte is done in a simple poll and wait + * mechanism. + * If the busy bit is 1, this indicates issues with the external memory device. As a result, + * @ref nrfx_qspi_init returns NRFX_ERROR_TIMEOUT. + * + * In case of issues: + * - Check the connection. + * - Make sure that the memory device does not perform other operations like erasing or writing. + * - Check if there is a short circuit. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] handler Event handler provided by the user. If NULL, transfers + * will be performed in blocking mode. + * @param[in] p_context Pointer to context. Use in interrupt handler. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_TIMEOUT If the peripheral cannot connect with external memory. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + * @retval NRFX_ERROR_INVALID_PARAM If the pin configuration was incorrect. + */ +nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, + nrfx_qspi_handler_t handler, + void * p_context); + +/** + * @brief Function for uninitializing the QSPI driver instance. + */ +void nrfx_qspi_uninit(void); + +/** + * @brief Function for reading data from QSPI memory. + * + * Write, read, and erase operations check memory device busy state before starting the operation. + * If the memory is busy, the resulting action depends on the mode in which the read operation is used: + * - blocking mode (without handler) - a delay occurs until the last operation still runs and + * until operation data is still being read. + * - interrupt mode (with handler) - event emission occurs after the last operation + * and reading of data are finished. + * + * @param[out] p_rx_buffer Pointer to the receive buffer. + * @param[in] rx_buffer_length Size of the data to read. + * @param[in] src_address Address in memory to read from. + * + * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation + * was commissioned (handler mode). + * @retval NRFX_ERROR_BUSY If the driver currently handles another operation. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region. + */ +nrfx_err_t nrfx_qspi_read(void * p_rx_buffer, + size_t rx_buffer_length, + uint32_t src_address); + +/** + * @brief Function for writing data to QSPI memory. + * + * Write, read, and erase operations check memory device busy state before starting the operation. + * If the memory is busy, the resulting action depends on the mode in which the write operation is used: + * - blocking mode (without handler) - a delay occurs until the last operation still runs and + * until operation data is still being sent. + * - interrupt mode (with handler) - event emission occurs after the last operation + * and sending of operation data are finished. + * To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check + * after executing the write function. + * Remember that an incoming event signalizes only that data was sent to the memory device and the periheral + * before the write operation checked if memory was busy. + * + * @param[in] p_tx_buffer Pointer to the writing buffer. + * @param[in] tx_buffer_length Size of the data to write. + * @param[in] dst_address Address in memory to write to. + * + * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation + * was commissioned (handler mode). + * @retval NRFX_ERROR_BUSY If the driver currently handles other operation. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region. + */ +nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer, + size_t tx_buffer_length, + uint32_t dst_address); + +/** + * @brief Function for starting erasing of one memory block - 4KB, 64KB, or the whole chip. + * + * Write, read, and erase operations check memory device busy state before starting the operation. + * If the memory is busy, the resulting action depends on the mode in which the erase operation is used: + * - blocking mode (without handler) - a delay occurs until the last operation still runs and + * until operation data is still being sent. + * - interrupt mode (with handler) - event emission occurs after the last operation + * and sending of operation data are finished. + * To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check + * after executing the erase function. + * Remember that an incoming event signalizes only that data was sent to the memory device and the periheral + * before the erase operation checked if memory was busy. + * + * @param[in] length Size of data to erase. See @ref nrf_qspi_erase_len_t. + * @param[in] start_address Memory address to start erasing. If chip erase is performed, address + * field is ommited. + * + * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation + * was commissioned (handler mode). + * @retval NRFX_ERROR_BUSY If the driver currently handles another operation. + */ +nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length, + uint32_t start_address); + +/** + * @brief Function for starting an erase operation of the whole chip. + * + * @retval NRFX_SUCCESS If the operation was successful (blocking mode) or operation + * was commissioned (handler mode). + * @retval NRFX_ERROR_BUSY If the driver currently handles another operation. + */ +nrfx_err_t nrfx_qspi_chip_erase(void); + +/** + * @brief Function for getting the current driver status and status byte of memory device with + * testing WIP (write in progress) bit. + * + * @retval NRFX_SUCCESS If the driver and memory are ready to handle a new operation. + * @retval NRFX_ERROR_BUSY If the driver or memory currently handle another operation. + */ +nrfx_err_t nrfx_qspi_mem_busy_check(void); + +/** + * @brief Function for sending operation code, sending data, and receiving data from the memory device. + * + * Use this function to transfer configuration data to memory and to receive data from memory. + * Pointers can be addresses from flash memory. + * This function is a synchronous function and should be used only if necessary. + * + * @param[in] p_config Pointer to the structure with opcode and transfer configuration. + * @param[in] p_tx_buffer Pointer to the array with data to send. Can be NULL if only opcode is transmitted. + * @param[out] p_rx_buffer Pointer to the array for data to receive. Can be NULL if there is nothing to receive. + * + * @retval NRFX_SUCCESS If the operation was successful. + * @retval NRFX_ERROR_TIMEOUT If the external memory is busy or there are connection issues. + * @retval NRFX_ERROR_BUSY If the driver currently handles other operation. + */ +nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, + void const * p_tx_buffer, + void * p_rx_buffer); +/** + * @brief Function for sending operation code and data to the memory device with simpler configuration. + * + * Use this function to transfer configuration data to memory and to receive data from memory. + * This function is a synchronous function and should be used only if necessary. + * + * @param[in] opcode Operation code. Sending first. + * @param[in] length Length of the data to send and opcode. See @ref nrf_qspi_cinstr_len_t. + * @param[in] p_tx_buffer Pointer to input data array. + * + * @retval NRFX_SUCCESS If the operation was successful. + * @retval NRFX_ERROR_BUSY If the driver currently handles another operation. + */ +nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode, + nrf_qspi_cinstr_len_t length, + void const * p_tx_buffer); + + +void nrfx_qspi_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_QSPI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_rng.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_rng.h new file mode 100755 index 0000000..2188b10 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_rng.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NRFX_RNG_H__ +#define NRFX_RNG_H__ + +#include <nrfx.h> +#include <hal/nrf_rng.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_rng RNG driver + * @{ + * @ingroup nrf_rng + * @brief Random Number Generator (RNG) peripheral driver. + */ + +/** + * @brief Struct for RNG configuration. + */ +typedef struct +{ + bool error_correction : 1; /**< Error correction flag. */ + uint8_t interrupt_priority; /**< interrupt priority */ +} nrfx_rng_config_t; + +/** + * @brief RNG default configuration. + * Basic usage: + * @code + * nrfx_rng_config_t config = NRFX_RNG_DEFAULT_CONFIG; + * if (nrfx_rng_init(&config, handler) + * { ... + * @endcode + */ +#define NRFX_RNG_DEFAULT_CONFIG \ + { \ + .error_correction = NRFX_RNG_CONFIG_ERROR_CORRECTION, \ + .interrupt_priority = NRFX_RNG_CONFIG_IRQ_PRIORITY, \ + } + +/** + * @brief RNG driver event handler type. + */ +typedef void (* nrfx_rng_evt_handler_t)(uint8_t rng_data); + +/** + * @brief Function for initializing the nrfx_rng module. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] handler Event handler provided by the user. Must not be NULL. + * + * @retval NRFX_SUCCESS Driver was successfully initialized. + * @retval NRFX_ERROR_ALREADY_INITIALIZED Driver was already initialized. + */ +nrfx_err_t nrfx_rng_init(nrfx_rng_config_t const * p_config, nrfx_rng_evt_handler_t handler); + +/** + * @brief Function for starting the random value generation. + * + * Function enables interrupts in perihperal and start them. + */ +void nrfx_rng_start(void); + +/** + * @brief Function for stoping the random value generation. + * + * Function disables interrupts in perihperal and stop generation of new random values. + */ +void nrfx_rng_stop(void); + +/** + * @brief Function for uninitializing the nrfx_rng module. + */ +void nrfx_rng_uninit(void); + + +void nrfx_rng_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_RNG_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_rtc.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_rtc.h new file mode 100755 index 0000000..1cc9eed --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_rtc.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_RTC_H__ +#define NRFX_RTC_H__ + +#include <nrfx.h> +#include <hal/nrf_rtc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_rtc RTC driver + * @{ + * @ingroup nrf_rtc + * @brief Real Timer Counter (RTC) peripheral driver. + */ + +/**@brief Macro to convert microseconds into ticks. */ +#define NRFX_RTC_US_TO_TICKS(us,freq) (((us) * (freq)) / 1000000U) + +/**@brief RTC driver interrupt types. */ +typedef enum +{ + NRFX_RTC_INT_COMPARE0 = 0, /**< Interrupt from COMPARE0 event. */ + NRFX_RTC_INT_COMPARE1 = 1, /**< Interrupt from COMPARE1 event. */ + NRFX_RTC_INT_COMPARE2 = 2, /**< Interrupt from COMPARE2 event. */ + NRFX_RTC_INT_COMPARE3 = 3, /**< Interrupt from COMPARE3 event. */ + NRFX_RTC_INT_TICK = 4, /**< Interrupt from TICK event. */ + NRFX_RTC_INT_OVERFLOW = 5 /**< Interrupt from OVERFLOW event. */ +} nrfx_rtc_int_type_t; + +/**@brief RTC driver instance structure. */ +typedef struct +{ + NRF_RTC_Type * p_reg; /**< Pointer to instance register set. */ + IRQn_Type irq; /**< Instance IRQ ID. */ + uint8_t instance_id; /**< Instance index. */ + uint8_t cc_channel_count; /**< Number of capture/compare channels. */ +} nrfx_rtc_t; + +/**@brief Macro for creating RTC driver instance.*/ +#define NRFX_RTC_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_RTC, id), \ + .irq = NRFX_CONCAT_3(RTC, id, _IRQn), \ + .instance_id = NRFX_CONCAT_3(NRFX_RTC, id, _INST_IDX), \ + .cc_channel_count = NRF_RTC_CC_CHANNEL_COUNT(id), \ +} + +enum { +#if NRFX_CHECK(NRFX_RTC0_ENABLED) + NRFX_RTC0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_RTC1_ENABLED) + NRFX_RTC1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_RTC2_ENABLED) + NRFX_RTC2_INST_IDX, +#endif + NRFX_RTC_ENABLED_COUNT +}; + +/**@brief RTC driver instance configuration structure. */ +typedef struct +{ + uint16_t prescaler; /**< Prescaler. */ + uint8_t interrupt_priority; /**< Interrupt priority. */ + uint8_t tick_latency; /**< Maximum length of interrupt handler in ticks (max 7.7 ms). */ + bool reliable; /**< Reliable mode flag. */ +} nrfx_rtc_config_t; + +/**@brief RTC instance default configuration. */ +#define NRFX_RTC_DEFAULT_CONFIG \ +{ \ + .prescaler = RTC_FREQ_TO_PRESCALER(NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), \ + .interrupt_priority = NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .reliable = NRFX_RTC_DEFAULT_CONFIG_RELIABLE, \ + .tick_latency = NRFX_RTC_US_TO_TICKS(NRFX_RTC_MAXIMUM_LATENCY_US, \ + NRFX_RTC_DEFAULT_CONFIG_FREQUENCY), \ +} + +/**@brief RTC driver instance handler type. */ +typedef void (*nrfx_rtc_handler_t)(nrfx_rtc_int_type_t int_type); + +/**@brief Function for initializing the RTC driver instance. + * + * After initialization, the instance is in power off state. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS If successfully initialized. + * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. + */ +nrfx_err_t nrfx_rtc_init(nrfx_rtc_t const * const p_instance, + nrfx_rtc_config_t const * p_config, + nrfx_rtc_handler_t handler); + +/**@brief Function for uninitializing the RTC driver instance. + * + * After uninitialization, the instance is in idle state. The hardware should return to the state + * before initialization. The function asserts if the instance is in idle state. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_rtc_uninit(nrfx_rtc_t const * const p_instance); + +/**@brief Function for enabling the RTC driver instance. + * + * @note Function asserts if instance is enabled. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_rtc_enable(nrfx_rtc_t const * const p_instance); + +/**@brief Function for disabling the RTC driver instance. + * + * @note Function asserts if instance is disabled. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_rtc_disable(nrfx_rtc_t const * const p_instance); + +/**@brief Function for setting a compare channel. + * + * The function asserts if the instance is not initialized or if the channel parameter is + * wrong. The function powers on the instance if the instance was in power off state. + * + * The driver is not entering a critical section when configuring RTC, which means that it can be + * preempted for a certain amount of time. When the driver was preempted and the value to be set + * is short in time, there is a risk that the driver sets a compare value that is + * behind. If RTCn_CONFIG_RELIABLE is 1 for the given instance, the Reliable mode handles that case. + * However, to detect if the requested value is behind, this mode makes the following assumptions: + * - The maximum preemption time in ticks (8 - bit value) is known and is less than 7.7 ms + * (for prescaler = 0, RTC frequency 32 kHz). + * - The requested absolute compare value is not bigger than (0x00FFFFFF) - tick_latency. It is + * the user's responsibility to ensure that. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel One of the instance's channels. + * @param[in] val Absolute value to be set in the compare register. + * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_TIMEOUT If the compare was not set because the request value is behind the current counter + * value. This error can only be reported if RTCn_CONFIG_RELIABLE = 1. + */ +nrfx_err_t nrfx_rtc_cc_set(nrfx_rtc_t const * const p_instance, + uint32_t channel, + uint32_t val, + bool enable_irq); + +/**@brief Function for disabling a channel. + * + * This function disables channel events and channel interrupts. The function asserts if the instance is not + * initialized or if the channel parameter is wrong. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel One of the instance's channels. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_TIMEOUT If an interrupt was pending on the requested channel. + */ +nrfx_err_t nrfx_rtc_cc_disable(nrfx_rtc_t const * const p_instance, uint32_t channel); + +/**@brief Function for enabling tick. + * + * This function enables the tick event and optionally the interrupt. The function asserts if the instance is not + * powered on. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. + */ +void nrfx_rtc_tick_enable(nrfx_rtc_t const * const p_instance, bool enable_irq); + +/**@brief Function for disabling tick. + * + * This function disables the tick event and interrupt. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_rtc_tick_disable(nrfx_rtc_t const * const p_instance); + +/**@brief Function for enabling overflow. + * + * This function enables the overflow event and optionally the interrupt. The function asserts if the instance is + * not powered on. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] enable_irq True to enable the interrupt. False to disable the interrupt. + */ +void nrfx_rtc_overflow_enable(nrfx_rtc_t const * const p_instance, bool enable_irq); + +/**@brief Function for disabling overflow. + * + * This function disables the overflow event and interrupt. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_rtc_overflow_disable(nrfx_rtc_t const * const p_instance); + +/**@brief Function for getting the maximum relative ticks value that can be set in the compare channel. + * + * When a stack (for example SoftDevice) is used and it occupies high priority interrupts, + * the application code can be interrupted at any moment for a certain period of time. + * If Reliable mode is enabled, the provided maximum latency is taken into account + * and the return value is smaller than the RTC counter resolution. + * If Reliable mode is disabled, the return value equals the counter resolution. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval ticks Maximum ticks value. + */ +uint32_t nrfx_rtc_max_ticks_get(nrfx_rtc_t const * const p_instance); + +/**@brief Function for disabling all instance interrupts. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_mask Pointer to the location where the mask is filled. + */ +__STATIC_INLINE void nrfx_rtc_int_disable(nrfx_rtc_t const * const p_instance, + uint32_t * p_mask); + +/**@brief Function for enabling instance interrupts. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] mask Mask of interrupts to enable. + */ +__STATIC_INLINE void nrfx_rtc_int_enable(nrfx_rtc_t const * const p_instance, uint32_t mask); + +/**@brief Function for retrieving the current counter value. + * + * This function asserts if the instance is not powered on or if p_val is NULL. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval value Counter value. + */ +__STATIC_INLINE uint32_t nrfx_rtc_counter_get(nrfx_rtc_t const * const p_instance); + +/**@brief Function for clearing the counter value. + * + * This function asserts if the instance is not powered on. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +__STATIC_INLINE void nrfx_rtc_counter_clear(nrfx_rtc_t const * const p_instance); + +/**@brief Function for returning a requested task address for the RTC driver instance. + * + * This function asserts if the output pointer is NULL. The task address can be used by the PPI module. + * + * @param[in] p_instance Pointer to the instance. + * @param[in] task One of the peripheral tasks. + * + * @retval Address of task register. + */ +__STATIC_INLINE uint32_t nrfx_rtc_task_address_get(nrfx_rtc_t const * const p_instance, + nrf_rtc_task_t task); + +/**@brief Function for returning a requested event address for the RTC driver instance. + * + * This function asserts if the output pointer is NULL. The event address can be used by the PPI module. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event One of the peripheral events. + * + * @retval Address of event register. + */ +__STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * const p_instance, + nrf_rtc_event_t event); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrfx_rtc_int_disable(nrfx_rtc_t const * const p_instance, + uint32_t * p_mask) +{ + *p_mask = nrf_rtc_int_get(p_instance->p_reg); + nrf_rtc_int_disable(p_instance->p_reg, NRF_RTC_INT_TICK_MASK | + NRF_RTC_INT_OVERFLOW_MASK | + NRF_RTC_INT_COMPARE0_MASK | + NRF_RTC_INT_COMPARE1_MASK | + NRF_RTC_INT_COMPARE2_MASK | + NRF_RTC_INT_COMPARE3_MASK); +} + +__STATIC_INLINE void nrfx_rtc_int_enable(nrfx_rtc_t const * const p_instance, uint32_t mask) +{ + nrf_rtc_int_enable(p_instance->p_reg, mask); +} + +__STATIC_INLINE uint32_t nrfx_rtc_counter_get(nrfx_rtc_t const * const p_instance) +{ + return nrf_rtc_counter_get(p_instance->p_reg); +} + +__STATIC_INLINE void nrfx_rtc_counter_clear(nrfx_rtc_t const * const p_instance) +{ + nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_CLEAR); +} + +__STATIC_INLINE uint32_t nrfx_rtc_task_address_get(nrfx_rtc_t const * const p_instance, + nrf_rtc_task_t task) +{ + return nrf_rtc_task_address_get(p_instance->p_reg, task); +} + +__STATIC_INLINE uint32_t nrfx_rtc_event_address_get(nrfx_rtc_t const * const p_instance, + nrf_rtc_event_t event) +{ + return nrf_rtc_event_address_get(p_instance->p_reg, event); +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_rtc_0_irq_handler(void); +void nrfx_rtc_1_irq_handler(void); +void nrfx_rtc_2_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_RTC_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_saadc.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_saadc.h new file mode 100755 index 0000000..db56875 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_saadc.h @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_SAADC_H__ +#define NRFX_SAADC_H__ + +#include <nrfx.h> +#include <hal/nrf_saadc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_saadc SAADC driver + * @{ + * @ingroup nrf_saadc + * @brief Successive Approximation Analog-to-Digital Converter (SAADC) peripheral driver. + */ + +/** + * @brief Value that should be set as high limit to disable limit detection. + */ +#define NRFX_SAADC_LIMITH_DISABLED (2047) +/** + * @brief Value that should be set as low limit to disable limit detection. + */ +#define NRFX_SAADC_LIMITL_DISABLED (-2048) + +/** + * @brief Macro for setting @ref nrfx_saadc_config_t to default settings. + */ +#define NRFX_SAADC_DEFAULT_CONFIG \ +{ \ + .resolution = (nrf_saadc_resolution_t)NRFX_SAADC_CONFIG_RESOLUTION, \ + .oversample = (nrf_saadc_oversample_t)NRFX_SAADC_CONFIG_OVERSAMPLE, \ + .interrupt_priority = NRFX_SAADC_CONFIG_IRQ_PRIORITY, \ + .low_power_mode = NRFX_SAADC_CONFIG_LP_MODE \ +} + +/** + * @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings + * in single ended mode. + * + * @param PIN_P Analog input. + */ +#define NRFX_SAADC_DEFAULT_CHANNEL_CONFIG_SE(PIN_P) \ +{ \ + .resistor_p = NRF_SAADC_RESISTOR_DISABLED, \ + .resistor_n = NRF_SAADC_RESISTOR_DISABLED, \ + .gain = NRF_SAADC_GAIN1_6, \ + .reference = NRF_SAADC_REFERENCE_INTERNAL, \ + .acq_time = NRF_SAADC_ACQTIME_10US, \ + .mode = NRF_SAADC_MODE_SINGLE_ENDED, \ + .burst = NRF_SAADC_BURST_DISABLED, \ + .pin_p = (nrf_saadc_input_t)(PIN_P), \ + .pin_n = NRF_SAADC_INPUT_DISABLED \ +} + +/** + * @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings + * in differential mode. + * + * @param PIN_P Positive analog input. + * @param PIN_N Negative analog input. + */ +#define NRFX_SAADC_DEFAULT_CHANNEL_CONFIG_DIFFERENTIAL(PIN_P, PIN_N) \ +{ \ + .resistor_p = NRF_SAADC_RESISTOR_DISABLED, \ + .resistor_n = NRF_SAADC_RESISTOR_DISABLED, \ + .gain = NRF_SAADC_GAIN1_6, \ + .reference = NRF_SAADC_REFERENCE_INTERNAL, \ + .acq_time = NRF_SAADC_ACQTIME_10US, \ + .mode = NRF_SAADC_MODE_DIFFERENTIAL, \ + .pin_p = (nrf_saadc_input_t)(PIN_P), \ + .pin_n = (nrf_saadc_input_t)(PIN_N) \ +} + +/** + * @brief Analog-to-digital converter driver configuration structure. + */ +typedef struct +{ + nrf_saadc_resolution_t resolution; ///< Resolution configuration. + nrf_saadc_oversample_t oversample; ///< Oversampling configuration. + uint8_t interrupt_priority; ///< Interrupt priority. + bool low_power_mode; ///< Indicates if low power mode is active. +} nrfx_saadc_config_t; + +/** + * @brief Driver event types. + */ +typedef enum +{ + NRFX_SAADC_EVT_DONE, ///< Event generated when the buffer is filled with samples. + NRFX_SAADC_EVT_LIMIT, ///< Event generated after one of the limits is reached. + NRFX_SAADC_EVT_CALIBRATEDONE ///< Event generated when the calibration is complete. +} nrfx_saadc_evt_type_t; + +/** + * @brief Analog-to-digital converter driver done event data. + */ +typedef struct +{ + nrf_saadc_value_t * p_buffer; ///< Pointer to buffer with converted samples. + uint16_t size; ///< Number of samples in the buffer. +} nrfx_saadc_done_evt_t; + +/** + * @brief Analog-to-digital converter driver limit event data. + */ +typedef struct +{ + uint8_t channel; ///< Channel on which the limit was detected. + nrf_saadc_limit_t limit_type; ///< Type of limit detected. +} nrfx_saadc_limit_evt_t; + +/** + * @brief Analog-to-digital converter driver event structure. + */ +typedef struct +{ + nrfx_saadc_evt_type_t type; ///< Event type. + union + { + nrfx_saadc_done_evt_t done; ///< Data for @ref NRFX_SAADC_EVT_DONE event. + nrfx_saadc_limit_evt_t limit; ///< Data for @ref NRFX_SAADC_EVT_LIMIT event. + } data; +} nrfx_saadc_evt_t; + +/** + * @brief ADC event handler. + * + * @param[in] p_event Pointer to an ADC event. The event structure is allocated on + * the stack, so it is valid only within the context of + * the event handler. + */ +typedef void (* nrfx_saadc_event_handler_t)(nrfx_saadc_evt_t const * p_event); + +/** + * @brief Function for initializing the SAADC. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized. + */ +nrfx_err_t nrfx_saadc_init(nrfx_saadc_config_t const * p_config, + nrfx_saadc_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the SAADC. + * + * This function stops all ongoing conversions and disables all channels. + */ +void nrfx_saadc_uninit(void); + + +/** + * @brief Function for getting the address of a SAMPLE SAADC task. + * + * @return Task address. + */ +uint32_t nrfx_saadc_sample_task_get(void); + +/** + * @brief Function for initializing an SAADC channel. + * + * This function configures and enables the channel. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the ADC was not initialized. + * @retval NRFX_ERROR_NO_MEM If the specified channel was already allocated. + */ +nrfx_err_t nrfx_saadc_channel_init(uint8_t channel, + nrf_saadc_channel_config_t const * const p_config); + + +/** + * @brief Function for uninitializing an SAADC channel. + * + * @retval NRFX_SUCCESS If uninitialization was successful. + * @retval NRFX_ERROR_BUSY If the ADC is busy. + */ +nrfx_err_t nrfx_saadc_channel_uninit(uint8_t channel); + +/** + * @brief Function for starting SAADC sampling. + * + * @retval NRFX_SUCCESS If ADC sampling was triggered. + * @retval NRFX_ERROR_INVALID_STATE If ADC is in idle state. + */ +nrfx_err_t nrfx_saadc_sample(void); + +/** + * @brief Blocking function for executing a single ADC conversion. + * + * This function selects the desired input, starts a single conversion, + * waits for it to finish, and returns the result. + * + * The function will fail if ADC is busy. + * + * @param[in] channel Channel. + * @param[out] p_value Pointer to the location where the result should be placed. + * + * @retval NRFX_SUCCESS If conversion was successful. + * @retval NRFX_ERROR_BUSY If the ADC driver is busy. + */ +nrfx_err_t nrfx_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value); + +/** + * @brief Function for issuing conversion of data to the buffer. + * + * This function is non-blocking. The application is notified about filling the buffer by the event + * handler. Conversion will be done on all enabled channels. If the ADC is in idle state, the + * function will set up Easy DMA for the conversion. The ADC will be ready for sampling and wait for + * the SAMPLE task. It can be triggered manually by the @ref nrfx_saadc_sample function or by PPI + * using the @ref NRF_SAADC_TASK_SAMPLE task. If one buffer is already set and the conversion is + * ongoing, calling this function will result in queuing the given buffer. The driver will start + * filling the issued buffer when the first one is completed. If the function is called again before + * the first buffer is filled or calibration is in progress, it will return with error. + * + * @param[in] buffer Result buffer. + * @param[in] size Buffer size in words. + * + * @retval NRFX_SUCCESS If conversion was successful. + * @retval NRFX_ERROR_BUSY If the driver already has two buffers set or calibration is in progress. + */ +nrfx_err_t nrfx_saadc_buffer_convert(nrf_saadc_value_t * buffer, uint16_t size); + +/** + * @brief Function for triggering the ADC offset calibration. + * + * This function is non-blocking. The application is notified about completion by the event handler. + * Calibration will also trigger DONE and RESULTDONE events. + * + * The function will fail if ADC is busy or calibration is already in progress. + * + * @retval NRFX_SUCCESS If calibration was started successfully. + * @retval NRFX_ERROR_BUSY If the ADC driver is busy. + */ +nrfx_err_t nrfx_saadc_calibrate_offset(void); + +/** + * @brief Function for retrieving the SAADC state. + * + * @retval true If the ADC is busy. + * @retval false If the ADC is ready. + */ +bool nrfx_saadc_is_busy(void); + +/** + * @brief Function for aborting ongoing and buffered conversions. + * @note @ref NRFX_SAADC_EVT_DONE event will be generated if there is a conversion in progress. + * Event will contain number of words in the sample buffer. + */ +void nrfx_saadc_abort(void); + +/** + * @brief Function for setting the SAADC channel limits. + * When limits are enabled and the result exceeds the defined bounds, the limit handler + * function is called. + * + * @param[in] channel SAADC channel number. + * @param[in] limit_low Lower limit (valid values from @ref NRFX_SAADC_LIMITL_DISABLED to + * @ref NRFX_SAADC_LIMITH_DISABLED). Conversion results below this value will + * trigger the handler function. Set to @ref NRFX_SAADC_LIMITL_DISABLED + * to disable this limit. + * @param[in] limit_high Upper limit (valid values from @ref NRFX_SAADC_LIMITL_DISABLED to + * @ref NRFX_SAADC_LIMITH_DISABLED). Conversion results above this value will + * trigger the handler function. Set to @ref NRFX_SAADC_LIMITH_DISABLED + * to disable this limit. + */ +void nrfx_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high); + + +void nrfx_saadc_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_SAADC_H__ + diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spi.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spi.h new file mode 100755 index 0000000..929a267 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spi.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_SPI_H__ +#define NRFX_SPI_H__ + +#include <nrfx.h> +#include <hal/nrf_spi.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_spi SPI driver + * @{ + * @ingroup nrf_spi + * @brief SPI peripheral driver. + */ + +/** + * @brief SPI master driver instance data structure. + */ +typedef struct +{ + NRF_SPI_Type * p_reg; ///< Pointer to a structure with SPI registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_spi_t; + +enum { +#if NRFX_CHECK(NRFX_SPI0_ENABLED) + NRFX_SPI0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPI1_ENABLED) + NRFX_SPI1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPI2_ENABLED) + NRFX_SPI2_INST_IDX, +#endif + NRFX_SPI_ENABLED_COUNT +}; + +/** + * @brief Macro for creating an SPI master driver instance. + */ +#define NRFX_SPI_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_SPI, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPI, id, _INST_IDX), \ +} + +/** + * @brief This value can be provided instead of a pin number for signals MOSI, + * MISO, and Slave Select to specify that the given signal is not used and + * therefore does not need to be connected to a pin. + */ +#define NRFX_SPI_PIN_NOT_USED 0xFF + +/** + * @brief SPI master driver instance configuration structure. + */ +typedef struct +{ + uint8_t sck_pin; ///< SCK pin number. + uint8_t mosi_pin; ///< MOSI pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t miso_pin; ///< MISO pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t ss_pin; ///< Slave Select pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. The driver + * supports only active low for this signal. + * If the signal should be active high, + * it must be controlled externally. */ + uint8_t irq_priority; ///< Interrupt priority. + uint8_t orc; ///< Over-run character. + /**< This character is used when all bytes from the TX buffer are sent, + but the transfer continues due to RX. */ + nrf_spi_frequency_t frequency; ///< SPI frequency. + nrf_spi_mode_t mode; ///< SPI mode. + nrf_spi_bit_order_t bit_order; ///< SPI bit order. +} nrfx_spi_config_t; + +/** + * @brief SPI master instance default configuration. + */ +#define NRFX_SPI_DEFAULT_CONFIG \ +{ \ + .sck_pin = NRFX_SPI_PIN_NOT_USED, \ + .mosi_pin = NRFX_SPI_PIN_NOT_USED, \ + .miso_pin = NRFX_SPI_PIN_NOT_USED, \ + .ss_pin = NRFX_SPI_PIN_NOT_USED, \ + .irq_priority = NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .orc = 0xFF, \ + .frequency = NRF_SPI_FREQ_4M, \ + .mode = NRF_SPI_MODE_0, \ + .bit_order = NRF_SPI_BIT_ORDER_MSB_FIRST, \ +} + +/** + * @brief Single transfer descriptor structure. + */ +typedef struct +{ + uint8_t const * p_tx_buffer; ///< Pointer to TX buffer. + size_t tx_length; ///< TX buffer length. + uint8_t * p_rx_buffer; ///< Pointer to RX buffer. + size_t rx_length; ///< RX buffer length. +} nrfx_spi_xfer_desc_t; + +/** + * @brief Macro for setting up single transfer descriptor. + * + * This macro is for internal use only. + */ +#define NRFX_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \ + { \ + .p_tx_buffer = (uint8_t const *)(p_tx), \ + .tx_length = (tx_len), \ + .p_rx_buffer = (p_rx), \ + .rx_length = (rx_len), \ + } + +/** + * @brief Macro for setting duplex TX RX transfer. + */ +#define NRFX_SPI_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \ + NRFX_SPI_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length) + +/** + * @brief Macro for setting TX transfer. + */ +#define NRFX_SPI_XFER_TX(p_buf, length) \ + NRFX_SPI_SINGLE_XFER(p_buf, length, NULL, 0) + +/** + * @brief Macro for setting RX transfer. + */ +#define NRFX_SPI_XFER_RX(p_buf, length) \ + NRFX_SPI_SINGLE_XFER(NULL, 0, p_buf, length) + +/** + * @brief SPI master driver event types, passed to the handler routine provided + * during initialization. + */ +typedef enum +{ + NRFX_SPI_EVENT_DONE, ///< Transfer done. +} nrfx_spi_evt_type_t; + +typedef struct +{ + nrfx_spi_evt_type_t type; ///< Event type. + nrfx_spi_xfer_desc_t xfer_desc; ///< Transfer details. +} nrfx_spi_evt_t; + +/** + * @brief SPI master driver event handler type. + */ +typedef void (* nrfx_spi_evt_handler_t)(nrfx_spi_evt_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the SPI master driver instance. + * + * This function configures and enables the specified peripheral. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * + * @param handler Event handler provided by the user. If NULL, transfers + * will be performed in blocking mode. + * @param p_context Context passed to event handler. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance, + nrfx_spi_config_t const * p_config, + nrfx_spi_evt_handler_t handler, + void * p_context); + +/** + * @brief Function for uninitializing the SPI master driver instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spi_uninit(nrfx_spi_t const * const p_instance); + +/** + * @brief Function for starting the SPI data transfer. + * + * If an event handler was provided in the @ref nrfx_spi_init call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, which means that this function + * returns when the transfer is finished. + * + * @param p_instance Pointer to the driver instance structure. + * @param p_xfer_desc Pointer to the transfer descriptor. + * @param flags Transfer options (0 for default settings). + * Currently, no additional flags are available. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + */ +nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * const p_instance, + nrfx_spi_xfer_desc_t const * p_xfer_desc, + uint32_t flags); + +/** + * @brief Function for aborting ongoing transfer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spi_abort(nrfx_spi_t const * p_instance); + + +void nrfx_spi_0_irq_handler(void); +void nrfx_spi_1_irq_handler(void); +void nrfx_spi_2_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_SPI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spim.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spim.h new file mode 100755 index 0000000..cc94991 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spim.h @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_SPIM_H__ +#define NRFX_SPIM_H__ + +#include <nrfx.h> +#include <hal/nrf_spim.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_spim SPIM driver + * @{ + * @ingroup nrf_spim + * @brief SPIM peripheral driver. + */ + +/** + * @brief SPIM master driver instance data structure. + */ +typedef struct +{ + NRF_SPIM_Type * p_reg; ///< Pointer to a structure with SPIM registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_spim_t; + +enum { +#if NRFX_CHECK(NRFX_SPIM0_ENABLED) + NRFX_SPIM0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPIM1_ENABLED) + NRFX_SPIM1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPIM2_ENABLED) + NRFX_SPIM2_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPIM3_ENABLED) + NRFX_SPIM3_INST_IDX, +#endif + NRFX_SPIM_ENABLED_COUNT +}; + +/** + * @brief Macro for creating an SPIM master driver instance. + */ +#define NRFX_SPIM_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_SPIM, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPIM, id, _INST_IDX), \ +} + +/** + * @brief This value can be provided instead of a pin number for signals MOSI, + * MISO, and Slave Select to specify that the given signal is not used and + * therefore does not need to be connected to a pin. + */ +#define NRFX_SPIM_PIN_NOT_USED 0xFF + +/** + * @brief SPIM master driver instance configuration structure. + */ +typedef struct +{ + uint8_t sck_pin; ///< SCK pin number. + uint8_t mosi_pin; ///< MOSI pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t miso_pin; ///< MISO pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t ss_pin; ///< Slave Select pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. */ + bool ss_active_high; ///< Polarity of the Slave Select pin during transmission. + uint8_t irq_priority; ///< Interrupt priority. + uint8_t orc; ///< Over-run character. + /**< This character is used when all bytes from the TX buffer are sent, + but the transfer continues due to RX. */ + nrf_spim_frequency_t frequency; ///< SPI frequency. + nrf_spim_mode_t mode; ///< SPI mode. + nrf_spim_bit_order_t bit_order; ///< SPI bit order. +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) + uint8_t dcx_pin; ///< D/CX pin number (optional). + uint8_t rx_delay; ///< Sample delay for input serial data on MISO. + /**< The value specifies the delay, in number of 64 MHz clock cycles + * (15.625 ns), from the the sampling edge of SCK (leading edge for + * CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until + * the input serial data is sampled.*/ + bool use_hw_ss; ///< Indication to use software or hardware controlled Slave Select pin. + uint8_t ss_duration; ///< Slave Select duration before and after transmission. + /**< Minimum duration between the edge of CSN and the edge of SCK and minimum + * duration of CSN must stay inactive between transactions. + * The value is specified in number of 64 MHz clock cycles (15.625 ns). + * Supported only for hardware controlled Slave Select.*/ +#endif +} nrfx_spim_config_t; + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) +/** + * @brief SPIM master instance extended default configuration. + */ + #define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \ + .dcx_pin = NRFX_SPIM_PIN_NOT_USED, \ + .rx_delay = 0x02, \ + .ss_duration = 0x02, \ + .use_hw_ss = false, +#else + #define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG +#endif + +/** + * @brief SPIM master instance default configuration. + */ +#define NRFX_SPIM_DEFAULT_CONFIG \ +{ \ + .sck_pin = NRFX_SPIM_PIN_NOT_USED, \ + .mosi_pin = NRFX_SPIM_PIN_NOT_USED, \ + .miso_pin = NRFX_SPIM_PIN_NOT_USED, \ + .ss_pin = NRFX_SPIM_PIN_NOT_USED, \ + .ss_active_high = false, \ + .irq_priority = NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .orc = 0xFF, \ + .frequency = NRF_SPIM_FREQ_4M, \ + .mode = NRF_SPIM_MODE_0, \ + .bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST, \ + NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \ +} + +#define NRFX_SPIM_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */ +#define NRFX_SPIM_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */ +#define NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ +#define NRFX_SPIM_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */ +#define NRFX_SPIM_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */ + +/** + * @brief Single transfer descriptor structure. + */ +typedef struct +{ + uint8_t const * p_tx_buffer; ///< Pointer to TX buffer. + size_t tx_length; ///< TX buffer length. + uint8_t * p_rx_buffer; ///< Pointer to RX buffer. + size_t rx_length; ///< RX buffer length. +} nrfx_spim_xfer_desc_t; + +/** + * @brief Macro for setting up single transfer descriptor. + * + * This macro is for internal use only. + */ +#define NRFX_SPIM_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len) \ + { \ + .p_tx_buffer = (uint8_t const *)(p_tx), \ + .tx_length = (tx_len), \ + .p_rx_buffer = (p_rx), \ + .rx_length = (rx_len), \ + } + +/** + * @brief Macro for setting duplex TX RX transfer. + */ +#define NRFX_SPIM_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length) \ + NRFX_SPIM_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length) + +/** + * @brief Macro for setting TX transfer. + */ +#define NRFX_SPIM_XFER_TX(p_buf, length) \ + NRFX_SPIM_SINGLE_XFER(p_buf, length, NULL, 0) + +/** + * @brief Macro for setting RX transfer. + */ +#define NRFX_SPIM_XFER_RX(p_buf, length) \ + NRFX_SPIM_SINGLE_XFER(NULL, 0, p_buf, length) + +/** + * @brief SPIM master driver event types, passed to the handler routine provided + * during initialization. + */ +typedef enum +{ + NRFX_SPIM_EVENT_DONE, ///< Transfer done. +} nrfx_spim_evt_type_t; + +typedef struct +{ + nrfx_spim_evt_type_t type; ///< Event type. + nrfx_spim_xfer_desc_t xfer_desc; ///< Transfer details. +} nrfx_spim_evt_t; + +/** + * @brief SPIM master driver event handler type. + */ +typedef void (* nrfx_spim_evt_handler_t)(nrfx_spim_evt_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the SPI master driver instance. + * + * This function configures and enables the specified peripheral. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * + * @param handler Event handler provided by the user. If NULL, transfers + * will be performed in blocking mode. + * @param p_context Context passed to event handler. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + * @retval NRFX_ERROR_NOT_SUPPORTED If requested configuration is not supported + * by the SPIM instance. + */ +nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance, + nrfx_spim_config_t const * p_config, + nrfx_spim_evt_handler_t handler, + void * p_context); + +/** + * @brief Function for uninitializing the SPI master driver instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spim_uninit(nrfx_spim_t const * const p_instance); + +/** + * @brief Function for starting the SPI data transfer. + * + * Additional options are provided using the @c flags parameter: + * + * - @ref NRFX_SPIM_FLAG_TX_POSTINC and @ref NRFX_SPIM_FLAG_RX_POSTINC<span></span>: + * Post-incrementation of buffer addresses. Supported only by SPIM. + * - @ref NRFX_SPIM_FLAG_HOLD_XFER<span></span>: Driver is not starting the transfer. Use this + * flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use + * @ref nrfx_spim_start_task_get to get the address of the start task. + * - @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER<span></span>: No user event handler after transfer + * completion. This also means no interrupt at the end of the transfer. Supported only by SPIM. + * If @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into + * busy state, so you must ensure that the next transfers are set up when SPIM is not active. + * @ref nrfx_spim_end_event_get function can be used to detect end of transfer. Option can be used + * together with @ref NRFX_SPIM_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers + * without interruptions. + * - @ref NRFX_SPIM_FLAG_REPEATED_XFER<span></span>: Prepare for repeated transfers. You can set + * up a number of transfers that will be triggered externally (for example by PPI). An example is + * a TXRX transfer with the options @ref NRFX_SPIM_FLAG_RX_POSTINC, + * @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER, and @ref NRFX_SPIM_FLAG_REPEATED_XFER. After the + * transfer is set up, a set of transfers can be triggered by PPI that will read, for example, + * the same register of an external component and put it into a RAM buffer without any interrupts. + * @ref nrfx_spim_end_event_get can be used to get the address of the END event, which can be + * used to count the number of transfers. If @ref NRFX_SPIM_FLAG_REPEATED_XFER is used, + * the driver does not set the instance into busy state, so you must ensure that the next + * transfers are set up when SPIM is not active. Supported only by SPIM. + * + * @note Peripherals using EasyDMA (including SPIM) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param p_instance Pointer to the driver instance structure. + * @param p_xfer_desc Pointer to the transfer descriptor. + * @param flags Transfer options (0 for default settings). + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data + * RAM region. + */ +nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance, + nrfx_spim_xfer_desc_t const * p_xfer_desc, + uint32_t flags); + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for starting the SPI data transfer with DCX control. + * + * See @ref nrfx_spim_xfer for description of additional options of transfer + * provided by the @c flags parameter. + * + * @note Peripherals that use EasyDMA (including SPIM) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param p_instance Pointer to the driver instance structure. + * @param p_xfer_desc Pointer to the transfer descriptor. + * @param flags Transfer options (0 for default settings). + * @param cmd_length Length of the command bytes preceding the data + * bytes. The DCX line will be low during transmission + * of command bytes and high during transmission of data bytes. + * Maximum value available for dividing the transmitted bytes + * into command bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1. + * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the + * @c cmd_length parameter causes all transmitted bytes + * to be marked as command bytes. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data + * RAM region. + */ +nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance, + nrfx_spim_xfer_desc_t const * p_xfer_desc, + uint32_t flags, + uint8_t cmd_length); +#endif + +/** + * @brief Function for returning the address of a SPIM start task. + * + * This function should be used if @ref nrfx_spim_xfer was called with the flag @ref NRFX_SPIM_FLAG_HOLD_XFER. + * In that case, the transfer is not started by the driver, but it must be started externally by PPI. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Start task address. + */ +uint32_t nrfx_spim_start_task_get(nrfx_spim_t const * p_instance); + +/** + * @brief Function for returning the address of a END SPIM event. + * + * The END event can be used to detect the end of a transfer + * if the @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER option is used. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return END event address. + */ +uint32_t nrfx_spim_end_event_get(nrfx_spim_t const * p_instance); + +/** + * @brief Function for aborting ongoing transfer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spim_abort(nrfx_spim_t const * p_instance); + + +void nrfx_spim_0_irq_handler(void); +void nrfx_spim_1_irq_handler(void); +void nrfx_spim_2_irq_handler(void); +void nrfx_spim_3_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_SPIM_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spis.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spis.h new file mode 100755 index 0000000..6783674 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_spis.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_SPIS_H__ +#define NRFX_SPIS_H__ + +#include <nrfx.h> +#include <hal/nrf_spis.h> +#include <hal/nrf_gpio.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_spis SPI slave driver + * @{ + * @ingroup nrf_spis + * @brief SPI Slave peripheral driver. + */ + +/** @brief SPI slave driver instance data structure. */ +typedef struct +{ + NRF_SPIS_Type * p_reg; //!< Pointer to a structure with SPIS registers. + uint8_t drv_inst_idx; //!< Driver instance index. +} nrfx_spis_t; + +enum { +#if NRFX_CHECK(NRFX_SPIS0_ENABLED) + NRFX_SPIS0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPIS1_ENABLED) + NRFX_SPIS1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_SPIS2_ENABLED) + NRFX_SPIS2_INST_IDX, +#endif + NRFX_SPIS_ENABLED_COUNT +}; + +/** @brief Macro for creating an SPI slave driver instance. */ +#define NRFX_SPIS_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_SPIS, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_SPIS, id, _INST_IDX), \ +} + +/** + * @brief This value can be provided instead of a pin number for the signals MOSI + * and MISO to specify that the given signal is not used and therefore + * does not need to be connected to a pin. + */ +#define NRFX_SPIS_PIN_NOT_USED 0xFF + +/** @brief Default pull-up configuration of the SPI CS. */ +#define NRFX_SPIS_DEFAULT_CSN_PULLUP NRF_GPIO_PIN_NOPULL +/** @brief Default drive configuration of the SPI MISO. */ +#define NRFX_SPIS_DEFAULT_MISO_DRIVE NRF_GPIO_PIN_S0S1 + +/** @brief SPI slave driver event types. */ +typedef enum +{ + NRFX_SPIS_BUFFERS_SET_DONE, //!< Memory buffer set event. Memory buffers have been set successfully to the SPI slave device, and SPI transaction can be done. + NRFX_SPIS_XFER_DONE, //!< SPI transaction event. SPI transaction has been completed. + NRFX_SPIS_EVT_TYPE_MAX //!< Enumeration upper bound. +} nrfx_spis_evt_type_t; + +/** @brief SPI slave driver event structure. */ +typedef struct +{ + nrfx_spis_evt_type_t evt_type; //!< Type of the event. + size_t rx_amount; //!< Number of bytes received in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events. + size_t tx_amount; //!< Number of bytes transmitted in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events. +} nrfx_spis_evt_t; + +/** @brief SPI slave instance default configuration. */ +#define NRFX_SPIS_DEFAULT_CONFIG \ +{ \ + .sck_pin = NRFX_SPIS_PIN_NOT_USED, \ + .mosi_pin = NRFX_SPIS_PIN_NOT_USED, \ + .miso_pin = NRFX_SPIS_PIN_NOT_USED, \ + .csn_pin = NRFX_SPIS_PIN_NOT_USED, \ + .mode = NRF_SPIS_MODE_0, \ + .bit_order = NRF_SPIS_BIT_ORDER_MSB_FIRST, \ + .csn_pullup = NRFX_SPIS_DEFAULT_CSN_PULLUP, \ + .miso_drive = NRFX_SPIS_DEFAULT_MISO_DRIVE, \ + .def = NRFX_SPIS_DEFAULT_DEF, \ + .orc = NRFX_SPIS_DEFAULT_ORC, \ + .irq_priority = NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY, \ +} + +/** @brief SPI peripheral device configuration data. */ +typedef struct +{ + uint32_t miso_pin; //!< SPI MISO pin (optional). + /**< Set @ref NRFX_SPIS_PIN_NOT_USED + * if this signal is not needed. */ + uint32_t mosi_pin; //!< SPI MOSI pin (optional). + /**< Set @ref NRFX_SPIS_PIN_NOT_USED + * if this signal is not needed. */ + uint32_t sck_pin; //!< SPI SCK pin. + uint32_t csn_pin; //!< SPI CSN pin. + nrf_spis_mode_t mode; //!< SPI mode. + nrf_spis_bit_order_t bit_order; //!< SPI transaction bit order. + nrf_gpio_pin_pull_t csn_pullup; //!< CSN pin pull-up configuration. + nrf_gpio_pin_drive_t miso_drive; //!< MISO pin drive configuration. + uint8_t def; //!< Character clocked out in case of an ignored transaction. + uint8_t orc; //!< Character clocked out after an over-read of the transmit buffer. + uint8_t irq_priority; //!< Interrupt priority. +} nrfx_spis_config_t; + + +/** + * @brief SPI slave driver event handler type. + * + * @param[in] p_event Pointer to the event structure. The structure is + * allocated on the stack so it is valid only until + * the event handler returns. + * @param[in] p_context Context set on initialization. + */ +typedef void (*nrfx_spis_event_handler_t)(nrfx_spis_evt_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the SPI slave driver instance. + * + * @note When the nRF52 Anomaly 109 workaround for SPIS is enabled, this function + * initializes the GPIOTE driver as well, and uses one of GPIOTE channels + * to detect falling edges on CSN pin. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Function to be called by the SPI slave driver upon event. + * Must not be NULL. + * @param[in] p_context Context passed to the event handler. + * + * @retval NRFX_SUCCESS If the initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. + * @retval NRFX_ERROR_INVALID_PARAM If an invalid parameter is supplied. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + * @retval NRFX_ERROR_INTERNAL GPIOTE channel for detecting falling edges + * on CSN pin cannot be initialized. Possible + * only when using nRF52 Anomaly 109 workaround. + */ +nrfx_err_t nrfx_spis_init(nrfx_spis_t const * const p_instance, + nrfx_spis_config_t const * p_config, + nrfx_spis_event_handler_t event_handler, + void * p_context); + +/** + * @brief Function for uninitializing the SPI slave driver instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_spis_uninit(nrfx_spis_t const * const p_instance); + +/** + * @brief Function for preparing the SPI slave instance for a single SPI transaction. + * + * This function prepares the SPI slave device to be ready for a single SPI transaction. It configures + * the SPI slave device to use the memory supplied with the function call in SPI transactions. + * + * When either the memory buffer configuration or the SPI transaction has been + * completed, the event callback function will be called with the appropriate event + * @ref nrfx_spis_evt_type_t. Note that the callback function can be called before returning from + * this function, because it is called from the SPI slave interrupt context. + * + * @note This function can be called from the callback function context. + * + * @note Client applications must call this function after every @ref NRFX_SPIS_XFER_DONE event if + * the SPI slave driver should be prepared for a possible new SPI transaction. + * + * @note Peripherals using EasyDMA (including SPIS) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_tx_buffer Pointer to the TX buffer. Can be NULL when the buffer length is zero. + * @param[in] p_rx_buffer Pointer to the RX buffer. Can be NULL when the buffer length is zero. + * @param[in] tx_buffer_length Length of the TX buffer in bytes. + * @param[in] rx_buffer_length Length of the RX buffer in bytes. + * + * @retval NRFX_SUCCESS If the operation was successful. + * @retval NRFX_ERROR_INVALID_STATE If the operation failed because the SPI slave device is in an incorrect state. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data + * RAM region. + * @retval NRFX_ERROR_INVALID_LENGTH If provided lengths exceed the EasyDMA limits for the peripheral. + * @retval NRFX_ERROR_INTERNAL If the operation failed because of an internal error. + */ +nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance, + uint8_t const * p_tx_buffer, + size_t tx_buffer_length, + uint8_t * p_rx_buffer, + size_t rx_buffer_length); + + +void nrfx_spis_0_irq_handler(void); +void nrfx_spis_1_irq_handler(void); +void nrfx_spis_2_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_SPIS_H__ + diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_swi.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_swi.h new file mode 100755 index 0000000..37583e2 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_swi.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_SWI_H__ +#define NRFX_SWI_H__ + +#include <nrfx.h> + +#if NRFX_CHECK(NRFX_EGU_ENABLED) +#include <hal/nrf_egu.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_swi SWI driver + * @{ + * @ingroup nrf_swi_egu + * + * @brief Driver for managing software interrupts (SWI). + */ + +/** @brief SWI instance. */ +typedef uint8_t nrfx_swi_t; + +/** + * @brief SWI user flags. + * + * User flags are set during the SWI trigger and passed to the callback function as an argument. + */ +typedef uint16_t nrfx_swi_flags_t; + +/** @brief Unallocated instance value. */ +#define NRFX_SWI_UNALLOCATED ((nrfx_swi_t)0xFFuL) + +/** @brief Default SWI priority. */ +#define NRFX_SWI_DEFAULT_PRIORITY APP_IRQ_PRIORITY_LOWEST + +/** + * @brief SWI handler function. + * + * @param swi SWI instance. + * @param flags User flags. + */ +typedef void (*nrfx_swi_handler_t)(nrfx_swi_t swi, nrfx_swi_flags_t flags); + + +/** + * @brief Function for allocating the first unused SWI instance and setting a handler. + * + * @param[out] p_swi Points to a place where the allocated SWI instance + * number is to be stored. + * @param[in] event_handler Event handler function. + * If NULL, no interrupt will be enabled. + * It can be NULL only if the EGU driver is enabled. + * For classic SWI, it must be a valid handler pointer. + * @param[in] irq_priority Interrupt priority. + * + * @retval NRFX_SUCCESS If the SWI was successfully allocated. + * @retval NRFX_ERROR_NO_MEM If there is no available SWI to be used. + */ +nrfx_err_t nrfx_swi_alloc(nrfx_swi_t * p_swi, + nrfx_swi_handler_t event_handler, + uint32_t irq_priority); + +/** + * @brief Function for freeing a previously allocated SWI. + * + * @param[in,out] p_swi SWI instance to free. The value is changed to + * @ref NRFX_SWI_UNALLOCATED on success. + */ +void nrfx_swi_free(nrfx_swi_t * p_swi); + +/** @brief Function for freeing all allocated SWIs. */ +void nrfx_swi_all_free(void); + +/** + * @brief Function for triggering the SWI. + * + * @param[in] swi SWI to trigger. + * @param[in] flag_number Number of user flag to trigger. + */ +void nrfx_swi_trigger(nrfx_swi_t swi, + uint8_t flag_number); + +/** + * @brief Function for checking if the specified SWI is currently allocated. + * + * @param[in] swi SWI instance. + * + * @retval true If the SWI instance is allocated. + * @retval false Otherwise. + */ +bool nrfx_swi_is_allocated(nrfx_swi_t swi); + +#if NRFX_CHECK(NRFX_EGU_ENABLED) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for returning the base address of the EGU peripheral + * associated with the specified SWI instance. + * + * @param[in] swi SWI instance. + * + * @returns EGU base address or NULL if the specified SWI instance number + * is too high. + */ +__STATIC_INLINE NRF_EGU_Type * nrfx_swi_egu_instance_get(nrfx_swi_t swi) +{ +#if (EGU_COUNT < SWI_COUNT) + if (swi >= EGU_COUNT) + { + return NULL; + } +#endif + uint32_t offset = ((uint32_t)swi) * (NRF_EGU1_BASE - NRF_EGU0_BASE); + return (NRF_EGU_Type *)(NRF_EGU0_BASE + offset); +} + +/** + * @brief Function for returning the EGU trigger task address. + * + * @param[in] swi SWI instance. + * @param[in] channel Number of the EGU channel. + * + * @returns Address of EGU trigger task. + */ +__STATIC_INLINE uint32_t nrfx_swi_task_trigger_address_get(nrfx_swi_t swi, + uint8_t channel) +{ + NRFX_ASSERT(nrfx_swi_is_allocated(swi)); + + NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi); +#if (EGU_COUNT < SWI_COUNT) + if (p_egu == NULL) + { + return 0; + } +#endif + + return (uint32_t)nrf_egu_task_trigger_address_get(p_egu, channel); +} + +/** + * @brief Function for returning the EGU triggered event address. + * + * @param[in] swi SWI instance. + * @param[in] channel Number of the EGU channel. + * + * @returns Address of EGU triggered event. + */ +__STATIC_INLINE uint32_t nrfx_swi_event_triggered_address_get(nrfx_swi_t swi, + uint8_t channel) +{ + NRFX_ASSERT(nrfx_swi_is_allocated(swi)); + + NRF_EGU_Type * p_egu = nrfx_swi_egu_instance_get(swi); +#if (EGU_COUNT < SWI_COUNT) + if (p_egu == NULL) + { + return 0; + } +#endif + + return (uint32_t)nrf_egu_event_triggered_address_get(p_egu, channel); +} + +#endif // NRFX_CHECK(NRFX_EGU_ENABLED) || defined(__NRFX_DOXYGEN__) + + +void nrfx_swi_0_irq_handler(void); +void nrfx_swi_1_irq_handler(void); +void nrfx_swi_2_irq_handler(void); +void nrfx_swi_3_irq_handler(void); +void nrfx_swi_4_irq_handler(void); +void nrfx_swi_5_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_SWI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_systick.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_systick.h new file mode 100755 index 0000000..9e9678c --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_systick.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_SYSTICK_H__ +#define NRFX_SYSTICK_H__ + +#include <nrfx.h> +#include <hal/nrf_systick.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_systick ARM(R) SysTick driver + * @{ + * @ingroup nrf_systick + * + * @brief ARM(R) SysTick driver. + * + * This driver configures ARM(R) SysTick as a free-running timer. + * This timer is used to generate delays and pool for timeouts. + * Only relatively short timeouts are supported. + * The SysTick works on 64MHz and is 24-bits wide. + * It means that it overflows around 4 times per second and around 250 ms + * would be the highest supported time in the library. + * But it would be really hard to detect if overflow was generated without + * using interrupts. For safety we would limit the maximum delay range by half. + */ + +/** + * @brief The value type that holds the SysTick state + * + * This variable is used to count the requested timeout. + * @sa nrfx_systick_get + */ +typedef struct { + uint32_t time; //!< Registered time value +} nrfx_systick_state_t; + +/** + * @brief Configure and start the timer + * + * Function configures SysTick as a free-running timer without interrupt. + */ +void nrfx_systick_init(void); + +/** + * @brief Get current SysTick state + * + * Function gets current state of the SysTick timer. + * It can be used to check time-out by @ref nrfx_systick_test. + * + * @param[out] p_state The pointer to the state variable to be filled + */ +void nrfx_systick_get(nrfx_systick_state_t * p_state); + +/** + * @brief Test if specified time is up in relation to remembered state + * + * @param[in] p_state Remembered state set by @ref nrfx_systick_get + * @param[in] us Required time-out. + * + * @retval true If current time is higher than specified state plus given time-out. + * @retval false If current time is lower than specified state plus given time-out + */ +bool nrfx_systick_test(nrfx_systick_state_t const * p_state, uint32_t us); + +/** + * @brief Blocking delay in CPU ticks + * + * @param[in] ticks Number of CPU ticks to delay. + */ +void nrfx_systick_delay_ticks(uint32_t ticks); + +/** + * @brief Blocking delay in us + * + * @param[in] us Number of microseconds to delay. + */ +void nrfx_systick_delay_us(uint32_t us); + +/** + * @brief Blocking delay in ms + * + * This delay function removes the limits of the highest possible delay value. + * + * @param[in] ms Number of milliseconds to delay. + */ +void nrfx_systick_delay_ms(uint32_t ms); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRFX_SYSTICK_H__ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_timer.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_timer.h new file mode 100755 index 0000000..b6c648a --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_timer.h @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_TIMER_H__ +#define NRFX_TIMER_H__ + +#include <nrfx.h> +#include <hal/nrf_timer.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_timer Timer driver + * @{ + * @ingroup nrf_timer + * @brief TIMER peripheral driver. + */ + +/** + * @brief Timer driver instance data structure. + */ +typedef struct +{ + NRF_TIMER_Type * p_reg; ///< Pointer to the structure with TIMER peripheral instance registers. + uint8_t instance_id; ///< Driver instance index. + uint8_t cc_channel_count; ///< Number of capture/compare channels. +} nrfx_timer_t; + +/** + * @brief Macro for creating a timer driver instance. + */ +#define NRFX_TIMER_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_TIMER, id), \ + .instance_id = NRFX_CONCAT_3(NRFX_TIMER, id, _INST_IDX), \ + .cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id), \ +} + +enum { +#if NRFX_CHECK(NRFX_TIMER0_ENABLED) + NRFX_TIMER0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TIMER1_ENABLED) + NRFX_TIMER1_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TIMER2_ENABLED) + NRFX_TIMER2_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TIMER3_ENABLED) + NRFX_TIMER3_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TIMER4_ENABLED) + NRFX_TIMER4_INST_IDX, +#endif + NRFX_TIMER_ENABLED_COUNT +}; + +/** + * @brief Timer driver instance configuration structure. + */ +typedef struct +{ + nrf_timer_frequency_t frequency; ///< Frequency. + nrf_timer_mode_t mode; ///< Mode of operation. + nrf_timer_bit_width_t bit_width; ///< Bit width. + uint8_t interrupt_priority; ///< Interrupt priority. + void * p_context; ///< Context passed to interrupt handler. +} nrfx_timer_config_t; + +/** + * @brief Timer driver instance default configuration. + */ +#define NRFX_TIMER_DEFAULT_CONFIG \ +{ \ + .frequency = (nrf_timer_frequency_t)NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY,\ + .mode = (nrf_timer_mode_t)NRFX_TIMER_DEFAULT_CONFIG_MODE, \ + .bit_width = (nrf_timer_bit_width_t)NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH,\ + .interrupt_priority = NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .p_context = NULL \ +} + +/** + * @brief Timer driver event handler type. + * + * @param[in] event_type Timer event. + * @param[in] p_context General purpose parameter set during initialization of + * the timer. This parameter can be used to pass + * additional information to the handler function, for + * example, the timer ID. + */ +typedef void (* nrfx_timer_event_handler_t)(nrf_timer_event_t event_type, + void * p_context); + +/** + * @brief Function for initializing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] timer_event_handler Event handler provided by the user. + * Must not be NULL. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the instance is already initialized. + */ +nrfx_err_t nrfx_timer_init(nrfx_timer_t const * const p_instance, + nrfx_timer_config_t const * p_config, + nrfx_timer_event_handler_t timer_event_handler); + +/** + * @brief Function for uninitializing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_uninit(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for turning on the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_enable(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for turning off the timer. + * + * Note that the timer will allow to enter the lowest possible SYSTEM_ON state + * only after this function is called. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_disable(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for checking the timer state. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return True if timer is enabled, false otherwise. + */ +bool nrfx_timer_is_enabled(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for pausing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_pause(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for resuming the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_resume(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for clearing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_clear(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for incrementing the timer. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_timer_increment(nrfx_timer_t const * const p_instance); + +/** + * @brief Function for returning the address of a specific timer task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] timer_task Timer task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_timer_task_address_get(nrfx_timer_t const * const p_instance, + nrf_timer_task_t timer_task); + +/** + * @brief Function for returning the address of a specific timer capture task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel Capture channel number. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_timer_capture_task_address_get(nrfx_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for returning the address of a specific timer event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] timer_event Timer event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_timer_event_address_get(nrfx_timer_t const * const p_instance, + nrf_timer_event_t timer_event); + +/** + * @brief Function for returning the address of a specific timer compare event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel Compare channel number. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_timer_compare_event_address_get(nrfx_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for capturing the timer value. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] cc_channel Capture channel number. + * + * @return Captured value. + */ +uint32_t nrfx_timer_capture(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for returning the capture value from a specific channel. + * + * Use this function to read channel values when PPI is used for capturing. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] cc_channel Capture channel number. + * + * @return Captured value. + */ +__STATIC_INLINE uint32_t nrfx_timer_capture_get(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for setting the timer channel in compare mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] cc_channel Compare channel number. + * @param[in] cc_value Compare value. + * @param[in] enable_int Enable or disable the interrupt for the compare channel. + */ +void nrfx_timer_compare(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + bool enable_int); + +/** + * @brief Function for setting the timer channel in extended compare mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] cc_channel Compare channel number. + * @param[in] cc_value Compare value. + * @param[in] timer_short_mask Shortcut between the compare event on the channel + * and the timer task (STOP or CLEAR). + * @param[in] enable_int Enable or disable the interrupt for the compare + * channel. + */ +void nrfx_timer_extended_compare(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value, + nrf_timer_short_mask_t timer_short_mask, + bool enable_int); + +/** + * @brief Function for converting time in microseconds to timer ticks. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] time_us Time in microseconds. + * + * @return Number of ticks. + */ +__STATIC_INLINE uint32_t nrfx_timer_us_to_ticks(nrfx_timer_t const * const p_instance, + uint32_t time_us); + +/** + * @brief Function for converting time in milliseconds to timer ticks. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] time_ms Time in milliseconds. + * + * @return Number of ticks. + */ +__STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * const p_instance, + uint32_t time_ms); + +/** + * @brief Function for enabling timer compare interrupt. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel Compare channel. + */ +void nrfx_timer_compare_int_enable(nrfx_timer_t const * const p_instance, + uint32_t channel); + +/** + * @brief Function for disabling timer compare interrupt. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] channel Compare channel. + */ +void nrfx_timer_compare_int_disable(nrfx_timer_t const * const p_instance, + uint32_t channel); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrfx_timer_task_address_get(nrfx_timer_t const * const p_instance, + nrf_timer_task_t timer_task) +{ + return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, timer_task); +} + +__STATIC_INLINE uint32_t nrfx_timer_capture_task_address_get(nrfx_timer_t const * const p_instance, + uint32_t channel) +{ + NRFX_ASSERT(channel < p_instance->cc_channel_count); + return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, + nrf_timer_capture_task_get(channel)); +} + +__STATIC_INLINE uint32_t nrfx_timer_event_address_get(nrfx_timer_t const * const p_instance, + nrf_timer_event_t timer_event) +{ + return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, timer_event); +} + +__STATIC_INLINE uint32_t nrfx_timer_compare_event_address_get(nrfx_timer_t const * const p_instance, + uint32_t channel) +{ + NRFX_ASSERT(channel < p_instance->cc_channel_count); + return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, + nrf_timer_compare_event_get(channel)); +} + +__STATIC_INLINE uint32_t nrfx_timer_capture_get(nrfx_timer_t const * const p_instance, + nrf_timer_cc_channel_t cc_channel) +{ + return nrf_timer_cc_read(p_instance->p_reg, cc_channel); +} + +__STATIC_INLINE uint32_t nrfx_timer_us_to_ticks(nrfx_timer_t const * const p_instance, + uint32_t timer_us) +{ + return nrf_timer_us_to_ticks(timer_us, nrf_timer_frequency_get(p_instance->p_reg)); +} + +__STATIC_INLINE uint32_t nrfx_timer_ms_to_ticks(nrfx_timer_t const * const p_instance, + uint32_t timer_ms) +{ + return nrf_timer_ms_to_ticks(timer_ms, nrf_timer_frequency_get(p_instance->p_reg)); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_timer_0_irq_handler(void); +void nrfx_timer_1_irq_handler(void); +void nrfx_timer_2_irq_handler(void); +void nrfx_timer_3_irq_handler(void); +void nrfx_timer_4_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_TIMER_H__ + diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twi.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twi.h new file mode 100755 index 0000000..f7e2dff --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twi.h @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_TWI_H__ +#define NRFX_TWI_H__ + +#include <nrfx.h> +#include <hal/nrf_twi.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_twi TWI driver + * @{ + * @ingroup nrf_twi + * @brief TWI peripheral driver. + */ + +/** + * @brief Structure for the TWI master driver instance. + */ +typedef struct +{ + NRF_TWI_Type * p_twi; ///< Pointer to a structure with TWI registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_twi_t; + +/** + * @brief Macro for creating a TWI master driver instance. + */ +#define NRFX_TWI_INSTANCE(id) \ +{ \ + .p_twi = NRFX_CONCAT_2(NRF_TWI, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_TWI, id, _INST_IDX), \ +} + +enum { +#if NRFX_CHECK(NRFX_TWI0_ENABLED) + NRFX_TWI0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TWI1_ENABLED) + NRFX_TWI1_INST_IDX, +#endif + NRFX_TWI_ENABLED_COUNT +}; + +/** + * @brief Structure for the TWI master driver instance configuration. + */ +typedef struct +{ + uint32_t scl; ///< SCL pin number. + uint32_t sda; ///< SDA pin number. + nrf_twi_frequency_t frequency; ///< TWI frequency. + uint8_t interrupt_priority; ///< Interrupt priority. + bool hold_bus_uninit; ///< Hold pull up state on gpio pins after uninit. +} nrfx_twi_config_t; + +/** + * @brief TWI master driver instance default configuration. + */ +#define NRFX_TWI_DEFAULT_CONFIG \ +{ \ + .frequency = (nrf_twi_frequency_t)NRFX_TWI_DEFAULT_CONFIG_FREQUENCY, \ + .scl = 31, \ + .sda = 31, \ + .interrupt_priority = NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .hold_bus_uninit = NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT, \ +} + +#define NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ +#define NRFX_TWI_FLAG_TX_NO_STOP (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */ + +/** + * @brief TWI master driver event types. + */ +typedef enum +{ + NRFX_TWI_EVT_DONE, ///< Transfer completed event. + NRFX_TWI_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address. + NRFX_TWI_EVT_DATA_NACK ///< Error event: NACK received after sending a data byte. +} nrfx_twi_evt_type_t; + +/** + * @brief TWI master driver transfer types. + */ +typedef enum +{ + NRFX_TWI_XFER_TX, ///< TX transfer. + NRFX_TWI_XFER_RX, ///< RX transfer. + NRFX_TWI_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start. + NRFX_TWI_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start. +} nrfx_twi_xfer_type_t; + +/** + * @brief Structure for a TWI transfer descriptor. + */ +typedef struct +{ + nrfx_twi_xfer_type_t type; ///< Type of transfer. + uint8_t address; ///< Slave address. + size_t primary_length; ///< Number of bytes transferred. + size_t secondary_length; ///< Number of bytes transferred. + uint8_t * p_primary_buf; ///< Pointer to transferred data. + uint8_t * p_secondary_buf; ///< Pointer to transferred data. +} nrfx_twi_xfer_desc_t; + + +/**@brief Macro for setting the TX transfer descriptor. */ +#define NRFX_TWI_XFER_DESC_TX(addr, p_data, length) \ + { \ + .type = NRFX_TWI_XFER_TX, \ + .address = addr, \ + .primary_length = length, \ + .p_primary_buf = p_data, \ + } + +/**@brief Macro for setting the RX transfer descriptor. */ +#define NRFX_TWI_XFER_DESC_RX(addr, p_data, length) \ + { \ + .type = NRFX_TWI_XFER_RX, \ + .address = addr, \ + .primary_length = length, \ + .p_primary_buf = p_data, \ + } + +/**@brief Macro for setting the TXRX transfer descriptor. */ +#define NRFX_TWI_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len) \ + { \ + .type = NRFX_TWI_XFER_TXRX, \ + .address = addr, \ + .primary_length = tx_len, \ + .secondary_length = rx_len, \ + .p_primary_buf = p_tx, \ + .p_secondary_buf = p_rx, \ + } + +/**@brief Macro for setting the TXTX transfer descriptor. */ +#define NRFX_TWI_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \ + { \ + .type = NRFX_TWI_XFER_TXTX, \ + .address = addr, \ + .primary_length = tx_len, \ + .secondary_length = tx_len2, \ + .p_primary_buf = p_tx, \ + .p_secondary_buf = p_tx2, \ + } + +/** + * @brief Structure for a TWI event. + */ +typedef struct +{ + nrfx_twi_evt_type_t type; ///< Event type. + nrfx_twi_xfer_desc_t xfer_desc; ///< Transfer details. +} nrfx_twi_evt_t; + +/** + * @brief TWI event handler prototype. + */ +typedef void (* nrfx_twi_evt_handler_t)(nrfx_twi_evt_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the TWI driver instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled. + * @param[in] p_context Context passed to event handler. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is in invalid state. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_twi_init(nrfx_twi_t const * p_instance, + nrfx_twi_config_t const * p_config, + nrfx_twi_evt_handler_t event_handler, + void * p_context); + +/** + * @brief Function for uninitializing the TWI instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_twi_uninit(nrfx_twi_t const * p_instance); + +/** + * @brief Function for enabling the TWI instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_twi_enable(nrfx_twi_t const * p_instance); + +/** + * @brief Function for disabling the TWI instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_twi_disable(nrfx_twi_t const * p_instance); + +/** + * @brief Function for sending data to a TWI slave. + * + * The transmission will be stopped when an error occurs. If a transfer is ongoing, + * the function returns the error code @ref NRFX_ERROR_BUSY. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] address Address of a specific slave device (only 7 LSB). + * @param[in] p_data Pointer to a transmit buffer. + * @param[in] length Number of bytes to send. + * @param[in] no_stop If set, the stop condition is not generated on the bus + * after the transfer has completed successfully (allowing + * for a repeated start in the next transfer). + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. + * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. + * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. + */ +nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance, + uint8_t address, + uint8_t const * p_data, + size_t length, + bool no_stop); + +/** + * @brief Function for reading data from a TWI slave. + * + * The transmission will be stopped when an error occurs. If a transfer is ongoing, + * the function returns the error code @ref NRFX_ERROR_BUSY. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] address Address of a specific slave device (only 7 LSB). + * @param[in] p_data Pointer to a receive buffer. + * @param[in] length Number of bytes to be received. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. + * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN If the unread data was replaced by new data + * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. + * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. + */ +nrfx_err_t nrfx_twi_rx(nrfx_twi_t const * p_instance, + uint8_t address, + uint8_t * p_data, + size_t length); + +/** + * @brief Function for preparing a TWI transfer. + * + * The following transfer types can be configured (@ref nrfx_twi_xfer_desc_t::type): + * - @ref NRFX_TWI_XFER_TXRX<span></span>: Write operation followed by a read operation (without STOP condition in between). + * - @ref NRFX_TWI_XFER_TXTX<span></span>: Write operation followed by a write operation (without STOP condition in between). + * - @ref NRFX_TWI_XFER_TX<span></span>: Write operation (with or without STOP condition). + * - @ref NRFX_TWI_XFER_RX<span></span>: Read operation (with STOP condition). + * + * @note TXRX and TXTX transfers are supported only in non-blocking mode. + * + * Additional options are provided using the flags parameter: + * - @ref NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER<span></span>: No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer. + * - @ref NRFX_TWI_FLAG_TX_NO_STOP<span></span>: No stop condition after TX transfer. + * + * @note + * Some flag combinations are invalid: + * - @ref NRFX_TWI_FLAG_TX_NO_STOP with @ref nrfx_twi_xfer_desc_t::type different than @ref NRFX_TWI_XFER_TX + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_xfer_desc Pointer to the transfer descriptor. + * @param[in] flags Transfer options (0 for default settings). + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. + * @retval NRFX_ERROR_DRV_TWI_ERR_OVERRUN If the unread data was replaced by new data (TXRX and RX) + * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address. + * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte. + */ +nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const * p_instance, + nrfx_twi_xfer_desc_t const * p_xfer_desc, + uint32_t flags); + +/** + * @brief Function for checking the TWI driver state. + * + * @param[in] p_instance TWI instance. + * + * @retval true If the TWI driver is currently busy performing a transfer. + * @retval false If the TWI driver is ready for a new transfer. + */ +bool nrfx_twi_is_busy(nrfx_twi_t const * p_instance); + +/** + * @brief Function for getting the transferred data count. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Data count. + */ +size_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance); + +/** + * @brief Function for returning the address of a STOPPED TWI event. + * + * A STOPPED event can be used to detect the end of a transfer if the @ref NRFX_TWI_FLAG_NO_XFER_EVT_HANDLER + * option is used. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return STOPPED event address. + */ +uint32_t nrfx_twi_stopped_event_get(nrfx_twi_t const * p_instance); + +void nrfx_twi_0_irq_handler(void); +void nrfx_twi_1_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_TWI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twim.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twim.h new file mode 100755 index 0000000..93dd090 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twim.h @@ -0,0 +1,399 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_TWIM_H__ +#define NRFX_TWIM_H__ + +#include <nrfx.h> +#include <hal/nrf_twim.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_twim TWIM driver + * @{ + * @ingroup nrf_twim + * @brief TWIM peripheral driver. + */ + +/** + * @brief Structure for the TWI master driver instance. + */ +typedef struct +{ + NRF_TWIM_Type * p_twim; ///< Pointer to a structure with TWIM registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_twim_t; + +/** + * @brief Macro for creating a TWI master driver instance. + */ +#define NRFX_TWIM_INSTANCE(id) \ +{ \ + .p_twim = NRFX_CONCAT_2(NRF_TWIM, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_TWIM, id, _INST_IDX), \ +} + +enum { +#if NRFX_CHECK(NRFX_TWIM0_ENABLED) + NRFX_TWIM0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TWIM1_ENABLED) + NRFX_TWIM1_INST_IDX, +#endif + NRFX_TWIM_ENABLED_COUNT +}; + +/** + * @brief Structure for the TWI master driver instance configuration. + */ +typedef struct +{ + uint32_t scl; ///< SCL pin number. + uint32_t sda; ///< SDA pin number. + nrf_twim_frequency_t frequency; ///< TWIM frequency. + uint8_t interrupt_priority; ///< Interrupt priority. + bool hold_bus_uninit; ///< Hold pull up state on gpio pins after uninit. +} nrfx_twim_config_t; + +/** + * @brief TWI master driver instance default configuration. + */ +#define NRFX_TWIM_DEFAULT_CONFIG \ +{ \ + .frequency = (nrf_twim_frequency_t)NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY, \ + .scl = 31, \ + .sda = 31, \ + .interrupt_priority = NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY, \ + .hold_bus_uninit = NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT, \ +} + +#define NRFX_TWIM_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */ +#define NRFX_TWIM_FLAG_RX_POSTINC (1UL << 1) /**< RX buffer address incremented after transfer. */ +#define NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */ +#define NRFX_TWIM_FLAG_HOLD_XFER (1UL << 3) /**< Set up the transfer but do not start it. */ +#define NRFX_TWIM_FLAG_REPEATED_XFER (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */ +#define NRFX_TWIM_FLAG_TX_NO_STOP (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */ + +/** + * @brief TWI master driver event types. + */ +typedef enum +{ + NRFX_TWIM_EVT_DONE, ///< Transfer completed event. + NRFX_TWIM_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address. + NRFX_TWIM_EVT_DATA_NACK ///< Error event: NACK received after sending a data byte. +} nrfx_twim_evt_type_t; + +/** + * @brief TWI master driver transfer types. + */ +typedef enum +{ + NRFX_TWIM_XFER_TX, ///< TX transfer. + NRFX_TWIM_XFER_RX, ///< RX transfer. + NRFX_TWIM_XFER_TXRX, ///< TX transfer followed by RX transfer with repeated start. + NRFX_TWIM_XFER_TXTX ///< TX transfer followed by TX transfer with repeated start. +} nrfx_twim_xfer_type_t; + +/** + * @brief Structure for a TWI transfer descriptor. + */ +typedef struct +{ + nrfx_twim_xfer_type_t type; ///< Type of transfer. + uint8_t address; ///< Slave address. + size_t primary_length; ///< Number of bytes transferred. + size_t secondary_length; ///< Number of bytes transferred. + uint8_t * p_primary_buf; ///< Pointer to transferred data. + uint8_t * p_secondary_buf; ///< Pointer to transferred data. +} nrfx_twim_xfer_desc_t; + + +/**@brief Macro for setting the TX transfer descriptor. */ +#define NRFX_TWIM_XFER_DESC_TX(addr, p_data, length) \ + { \ + .type = NRFX_TWIM_XFER_TX, \ + .address = addr, \ + .primary_length = length, \ + .p_primary_buf = p_data, \ + } + +/**@brief Macro for setting the RX transfer descriptor. */ +#define NRFX_TWIM_XFER_DESC_RX(addr, p_data, length) \ + { \ + .type = NRFX_TWIM_XFER_RX, \ + .address = addr, \ + .primary_length = length, \ + .p_primary_buf = p_data, \ + } + +/**@brief Macro for setting the TXRX transfer descriptor. */ +#define NRFX_TWIM_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len) \ + { \ + .type = NRFX_TWIM_XFER_TXRX, \ + .address = addr, \ + .primary_length = tx_len, \ + .secondary_length = rx_len, \ + .p_primary_buf = p_tx, \ + .p_secondary_buf = p_rx, \ + } + +/**@brief Macro for setting the TXTX transfer descriptor. */ +#define NRFX_TWIM_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \ + { \ + .type = NRFX_TWIM_XFER_TXTX, \ + .address = addr, \ + .primary_length = tx_len, \ + .secondary_length = tx_len2, \ + .p_primary_buf = p_tx, \ + .p_secondary_buf = p_tx2, \ + } + +/** + * @brief Structure for a TWI event. + */ +typedef struct +{ + nrfx_twim_evt_type_t type; ///< Event type. + nrfx_twim_xfer_desc_t xfer_desc; ///< Transfer details. +} nrfx_twim_evt_t; + +/** + * @brief TWI event handler prototype. + */ +typedef void (* nrfx_twim_evt_handler_t)(nrfx_twim_evt_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the TWI driver instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled. + * @param[in] p_context Context passed to event handler. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is in invalid state. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance, + nrfx_twim_config_t const * p_config, + nrfx_twim_evt_handler_t event_handler, + void * p_context); + +/** + * @brief Function for uninitializing the TWI instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_twim_uninit(nrfx_twim_t const * p_instance); + +/** + * @brief Function for enabling the TWI instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_twim_enable(nrfx_twim_t const * p_instance); + +/** + * @brief Function for disabling the TWI instance. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_twim_disable(nrfx_twim_t const * p_instance); + +/** + * @brief Function for sending data to a TWI slave. + * + * The transmission will be stopped when an error occurs. If a transfer is ongoing, + * the function returns the error code @ref NRFX_ERROR_BUSY. + * + * @note Peripherals using EasyDMA (including TWIM) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] address Address of a specific slave device (only 7 LSB). + * @param[in] p_data Pointer to a transmit buffer. + * @param[in] length Number of bytes to send. Maximum possible length is + * dependent on the used SoC (see the MAXCNT register + * description in the Product Specification). The driver + * checks it with assertion. + * @param[in] no_stop If set, the stop condition is not generated on the bus + * after the transfer has completed successfully (allowing + * for a repeated start in the next transfer). + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffer is not placed in the Data RAM region. + * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. + * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. + */ +nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance, + uint8_t address, + uint8_t const * p_data, + size_t length, + bool no_stop); + +/** + * @brief Function for reading data from a TWI slave. + * + * The transmission will be stopped when an error occurs. If a transfer is ongoing, + * the function returns the error code @ref NRFX_ERROR_BUSY. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] address Address of a specific slave device (only 7 LSB). + * @param[in] p_data Pointer to a receive buffer. + * @param[in] length Number of bytes to be received. Maximum possible length + * is dependent on the used SoC (see the MAXCNT register + * description in the Product Specification). The driver + * checks it with assertion. + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. + * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address in polling mode. + * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte in polling mode. + */ +nrfx_err_t nrfx_twim_rx(nrfx_twim_t const * p_instance, + uint8_t address, + uint8_t * p_data, + size_t length); + +/** + * @brief Function for preparing a TWI transfer. + * + * The following transfer types can be configured (@ref nrfx_twim_xfer_desc_t::type): + * - @ref NRFX_TWIM_XFER_TXRX<span></span>: Write operation followed by a read operation (without STOP condition in between). + * - @ref NRFX_TWIM_XFER_TXTX<span></span>: Write operation followed by a write operation (without STOP condition in between). + * - @ref NRFX_TWIM_XFER_TX<span></span>: Write operation (with or without STOP condition). + * - @ref NRFX_TWIM_XFER_RX<span></span>: Read operation (with STOP condition). + * + * @note TXRX and TXTX transfers are supported only in non-blocking mode. + * + * Additional options are provided using the flags parameter: + * - @ref NRFX_TWIM_FLAG_TX_POSTINC and @ref NRFX_TWIM_FLAG_RX_POSTINC<span></span>: Post-incrementation of buffer addresses. Supported only by TWIM. + * - @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER<span></span>: No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer. + * - @ref NRFX_TWIM_FLAG_HOLD_XFER<span></span>: Driver is not starting the transfer. Use this flag if the transfer is triggered externally by PPI. Supported only by TWIM. + * Use @ref nrfx_twim_start_task_get to get the address of the start task. + * - @ref NRFX_TWIM_FLAG_REPEATED_XFER<span></span>: Prepare for repeated transfers. You can set up a number of transfers that will be triggered externally (for example by PPI). + * An example is a TXRX transfer with the options @ref NRFX_TWIM_FLAG_RX_POSTINC, @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER, and @ref NRFX_TWIM_FLAG_REPEATED_XFER. + * After the transfer is set up, a set of transfers can be triggered by PPI that will read, for example, the same register of an + * external component and put it into a RAM buffer without any interrupts. @ref nrfx_twim_stopped_event_get can be used to get the + * address of the STOPPED event, which can be used to count the number of transfers. If @ref NRFX_TWIM_FLAG_REPEATED_XFER is used, + * the driver does not set the driver instance into busy state, so you must ensure that the next transfers are set up + * when TWIM is not active. Supported only by TWIM. + * - @ref NRFX_TWIM_FLAG_TX_NO_STOP<span></span>: No stop condition after TX transfer. + * + * @note + * Some flag combinations are invalid: + * - @ref NRFX_TWIM_FLAG_TX_NO_STOP with @ref nrfx_twim_xfer_desc_t::type different than @ref NRFX_TWIM_XFER_TX + * - @ref NRFX_TWIM_FLAG_REPEATED_XFER with @ref nrfx_twim_xfer_desc_t::type set to @ref NRFX_TWIM_XFER_TXTX + * + * If @ref nrfx_twim_xfer_desc_t::type is set to @ref NRFX_TWIM_XFER_TX and the @ref NRFX_TWIM_FLAG_TX_NO_STOP and @ref NRFX_TWIM_FLAG_REPEATED_XFER + * flags are set, two tasks must be used to trigger a transfer: TASKS_RESUME followed by TASKS_STARTTX. If no stop condition is generated, + * TWIM is in SUSPENDED state. Therefore, it must be resumed before the transfer can be started. + * + * @note Peripherals using EasyDMA (including TWIM) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_xfer_desc Pointer to the transfer descriptor. + * @param[in] flags Transfer options (0 for default settings). + * + * @retval NRFX_SUCCESS If the procedure was successful. + * @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer. + * @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported. + * @retval NRFX_ERROR_INTERNAL If an error was detected by hardware. + * @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data RAM region. + * @retval NRFX_ERROR_DRV_TWI_ERR_ANACK If NACK received after sending the address. + * @retval NRFX_ERROR_DRV_TWI_ERR_DNACK If NACK received after sending a data byte. + */ +nrfx_err_t nrfx_twim_xfer(nrfx_twim_t const * p_instance, + nrfx_twim_xfer_desc_t const * p_xfer_desc, + uint32_t flags); + +/** + * @brief Function for checking the TWI driver state. + * + * @param[in] p_instance TWI instance. + * + * @retval true If the TWI driver is currently busy performing a transfer. + * @retval false If the TWI driver is ready for a new transfer. + */ +bool nrfx_twim_is_busy(nrfx_twim_t const * p_instance); + + +/** + * @brief Function for returning the address of a TWIM start task. + * + * This function should be used if @ref nrfx_twim_xfer was called with the flag @ref NRFX_TWIM_FLAG_HOLD_XFER. + * In that case, the transfer is not started by the driver, but it must be started externally by PPI. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] xfer_type Transfer type used in the last call of the @ref nrfx_twim_xfer function. + * + * @return Start task address (TX or RX) depending on the value of xfer_type. + */ +uint32_t nrfx_twim_start_task_get(nrfx_twim_t const * p_instance, nrfx_twim_xfer_type_t xfer_type); + +/** + * @brief Function for returning the address of a STOPPED TWIM event. + * + * A STOPPED event can be used to detect the end of a transfer if the @ref NRFX_TWIM_FLAG_NO_XFER_EVT_HANDLER + * option is used. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return STOPPED event address. + */ +uint32_t nrfx_twim_stopped_event_get(nrfx_twim_t const * p_instance); + + +void nrfx_twim_0_irq_handler(void); +void nrfx_twim_1_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_TWIM_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twis.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twis.h new file mode 100755 index 0000000..049a37c --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_twis.h @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_TWIS_H__ +#define NRFX_TWIS_H__ + +#include <nrfx.h> +#include <hal/nrf_twis.h> +#include <hal/nrf_gpio.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_twis TWIS driver + * @{ + * @ingroup nrf_twis + * @brief Two Wire Slave interface (TWIS) peripheral driver. + */ + +/** + * @brief TWIS driver instance data structure. + */ +typedef struct +{ + NRF_TWIS_Type * p_reg; ///< Pointer to a structure with TWIS registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_twis_t; + +enum { +#if NRFX_CHECK(NRFX_TWIS0_ENABLED) + NRFX_TWIS0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_TWIS1_ENABLED) + NRFX_TWIS1_INST_IDX, +#endif + NRFX_TWIS_ENABLED_COUNT +}; + +/** + * @brief Macro for creating a TWIS driver instance. + */ +#define NRFX_TWIS_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_TWIS, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_TWIS, id, _INST_IDX), \ +} + +/** + * @brief Event callback function event definitions. + */ +typedef enum +{ + NRFX_TWIS_EVT_READ_REQ, ///< Read request detected. + /**< If there is no buffer prepared, buf_req flag in the even will be set. + Call then @ref nrfx_twis_tx_prepare to give parameters for buffer. + */ + NRFX_TWIS_EVT_READ_DONE, ///< Read request has finished - free any data. + NRFX_TWIS_EVT_READ_ERROR, ///< Read request finished with error. + NRFX_TWIS_EVT_WRITE_REQ, ///< Write request detected. + /**< If there is no buffer prepared, buf_req flag in the even will be set. + Call then @ref nrfx_twis_rx_prepare to give parameters for buffer. + */ + NRFX_TWIS_EVT_WRITE_DONE, ///< Write request has finished - process data. + NRFX_TWIS_EVT_WRITE_ERROR, ///< Write request finished with error. + NRFX_TWIS_EVT_GENERAL_ERROR ///< Error that happens not inside WRITE or READ transaction. +} nrfx_twis_evt_type_t; + +/** + * @brief Possible error sources. + * + * This is flag enum - values from this enum can be connected using logical or operator. + * @note + * We could use directly @ref nrf_twis_error_t. Error type enum is redefined here because + * of possible future extension (eg. supporting timeouts and synchronous mode). + */ +typedef enum +{ + NRFX_TWIS_ERROR_OVERFLOW = NRF_TWIS_ERROR_OVERFLOW, /**< RX buffer overflow detected, and prevented. */ + NRFX_TWIS_ERROR_DATA_NACK = NRF_TWIS_ERROR_DATA_NACK, /**< NACK sent after receiving a data byte. */ + NRFX_TWIS_ERROR_OVERREAD = NRF_TWIS_ERROR_OVERREAD, /**< TX buffer over-read detected, and prevented. */ + NRFX_TWIS_ERROR_UNEXPECTED_EVENT = 1 << 8 /**< Unexpected event detected by state machine. */ +} nrfx_twis_error_t; + +/** + * @brief TWIS driver event structure. + */ +typedef struct +{ + nrfx_twis_evt_type_t type; ///< Event type. + union + { + bool buf_req; ///< Flag for @ref NRFX_TWIS_EVT_READ_REQ and @ref NRFX_TWIS_EVT_WRITE_REQ. + /**< Information if transmission buffer requires to be prepared. */ + uint32_t tx_amount; ///< Data for @ref NRFX_TWIS_EVT_READ_DONE. + uint32_t rx_amount; ///< Data for @ref NRFX_TWIS_EVT_WRITE_DONE. + uint32_t error; ///< Data for @ref NRFX_TWIS_EVT_GENERAL_ERROR. + } data; +} nrfx_twis_evt_t; + +/** + * @brief TWI slave event callback function type. + * + * @param[in] p_event Event information structure. + */ +typedef void (*nrfx_twis_event_handler_t)(nrfx_twis_evt_t const * p_event); + +/** + * @brief Structure for TWIS configuration. + */ +typedef struct +{ + uint32_t addr[2]; //!< Set addresses that this slave should respond. Set 0 to disable. + uint32_t scl; //!< SCL pin number. + uint32_t sda; //!< SDA pin number. + nrf_gpio_pin_pull_t scl_pull; //!< SCL pin pull. + nrf_gpio_pin_pull_t sda_pull; //!< SDA pin pull. + uint8_t interrupt_priority; //!< The priority of interrupt for the module to set. +} nrfx_twis_config_t; + +/** + * @brief Generate default configuration for TWIS driver instance. + */ +#define NRFX_TWIS_DEFAULT_CONFIG \ +{ \ + .addr = { NRFX_TWIS_DEFAULT_CONFIG_ADDR0, \ + NRFX_TWIS_DEFAULT_CONFIG_ADDR1 }, \ + .scl = 31, \ + .scl_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL, \ + .sda = 31, \ + .sda_pull = (nrf_gpio_pin_pull_t)NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL, \ + .interrupt_priority = NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY \ +} + +/** + * @brief Function for initializing the TWIS driver instance. + * + * Function initializes and enables TWIS driver. + * @attention After driver initialization enable it by @ref nrfx_twis_enable. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @attention @em p_instance has to be global object. + * It would be used by interrupts so make it sure that object + * would not be destroyed when function is leaving. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if NRFX_PRS_ENABLED + * is set to a value other than zero. + */ +nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, + nrfx_twis_config_t const * p_config, + nrfx_twis_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the TWIS driver instance. + * + * Function initializes the peripheral and resets all registers to default values. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @note + * It is safe to call nrfx_twis_uninit even before initialization. + * Actually @ref nrfx_twis_init function calls this function to + * make sure that TWIS state is known. + * @note + * If TWIS driver was in uninitialized state before calling this function, + * selected pins would not be reset to default configuration. + */ +void nrfx_twis_uninit(nrfx_twis_t const * p_instance); + +/** + * @brief Enable TWIS instance. + * + * This function enables TWIS instance. + * Function defined if there is needs for dynamically enabling and disabling the peripheral. + * Use @ref nrfx_twis_enable and @ref nrfx_twis_disable functions. + * They do not change any configuration registers. + * + * @param p_instance Pointer to the driver instance structure. + */ +void nrfx_twis_enable(nrfx_twis_t const * p_instance); + +/** + * @brief Disable TWIS instance. + * + * Disabling TWIS instance gives possibility to turn off the TWIS while + * holding configuration done by @ref nrfx_twis_init. + * + * @param p_instance Pointer to the driver instance structure. + */ +void nrfx_twis_disable(nrfx_twis_t const * p_instance); + +/** + * @brief Get and clear last error flags. + * + * Function gets information about errors. + * This is also the only possibility to exit from error substate of the internal state machine. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @return Error flags defined in @ref nrfx_twis_error_t. + * @attention + * This function clears error state and flags. + */ +uint32_t nrfx_twis_error_get_and_clear(nrfx_twis_t const * p_instance); + + +/** + * @brief Prepare data for sending. + * + * This function should be used in response for @ref NRFX_TWIS_EVT_READ_REQ event. + * + * @note Peripherals using EasyDMA (including TWIS) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_buf Transmission buffer. + * @attention Transmission buffer has to be placed in RAM. + * @param size Maximum number of bytes that master may read from buffer given. + * + * @retval NRFX_SUCCESS Preparation finished properly. + * @retval NRFX_ERROR_INVALID_ADDR Given @em p_buf is not placed inside the RAM. + * @retval NRFX_ERROR_INVALID_LENGTH Wrong value in @em size parameter. + * @retval NRFX_ERROR_INVALID_STATE Module not initialized or not enabled. + */ +nrfx_err_t nrfx_twis_tx_prepare(nrfx_twis_t const * p_instance, + void const * p_buf, + size_t size); + +/** + * @brief Get number of transmitted bytes. + * + * Function returns number of bytes sent. + * This function may be called after @ref NRFX_TWIS_EVT_READ_DONE or @ref NRFX_TWIS_EVT_READ_ERROR events. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Number of bytes sent. + */ +__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance); + +/** + * @brief Prepare data for receiving + * + * This function should be used in response for @ref NRFX_TWIS_EVT_WRITE_REQ event. + * + * @note Peripherals using EasyDMA (including TWIS) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_buf Buffer that would be filled with received data. + * @attention Receiving buffer has to be placed in RAM. + * @param size Size of the buffer (maximum amount of data to receive). + * + * @retval NRFX_SUCCESS Preparation finished properly. + * @retval NRFX_ERROR_INVALID_ADDR Given @em p_buf is not placed inside the RAM. + * @retval NRFX_ERROR_INVALID_LENGTH Wrong value in @em size parameter. + * @retval NRFX_ERROR_INVALID_STATE Module not initialized or not enabled. + */ +nrfx_err_t nrfx_twis_rx_prepare(nrfx_twis_t const * p_instance, + void * p_buf, + size_t size); + +/** + * @brief Get number of received bytes. + * + * Function returns number of bytes received. + * This function may be called after @ref NRFX_TWIS_EVT_WRITE_DONE or @ref NRFX_TWIS_EVT_WRITE_ERROR events. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @return Number of bytes received. + */ +__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance); + +/** + * @brief Function checks if driver is busy right now. + * + * Actual driver substate is tested. + * If driver is in any other state than IDLE or ERROR this function returns true. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true Driver is in state other than ERROR or IDLE. + * @retval false There is no transmission pending. + */ +bool nrfx_twis_is_busy(nrfx_twis_t const * p_instance); + +/** + * @brief Function checks if driver is waiting for tx buffer. + * + * If this function returns true, it means that driver is stalled expecting + * of the @ref nrfx_twis_tx_prepare function call. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true Driver waits for @ref nrfx_twis_tx_prepare. + * @retval false Driver is not in the state where it waits for preparing tx buffer. + */ +bool nrfx_twis_is_waiting_tx_buff(nrfx_twis_t const * p_instance); + +/** + * @brief Function checks if driver is waiting for rx buffer. + * + * If this function returns true, it means that driver is staled expecting + * of the @ref nrfx_twis_rx_prepare function call. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true Driver waits for @ref nrfx_twis_rx_prepare. + * @retval false Driver is not in the state where it waits for preparing rx buffer. + */ +bool nrfx_twis_is_waiting_rx_buff(nrfx_twis_t const * p_instance); + +/** + * @brief Check if driver is sending data. + * + * If this function returns true, it means that there is ongoing output transmission. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true There is ongoing output transmission. + * @retval false Driver is in other state. + */ +bool nrfx_twis_is_pending_tx(nrfx_twis_t const * p_instance); + +/** + * @brief Check if driver is receiving data. + * + * If this function returns true, it means that there is ongoing input transmission. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true There is ongoing input transmission. + * @retval false Driver is in other state. + */ +bool nrfx_twis_is_pending_rx(nrfx_twis_t const * p_instance); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE size_t nrfx_twis_tx_amount(nrfx_twis_t const * p_instance) +{ + return nrf_twis_tx_amount_get(p_instance->p_reg); +} + +__STATIC_INLINE size_t nrfx_twis_rx_amount(nrfx_twis_t const * p_instance) +{ + return nrf_twis_rx_amount_get(p_instance->p_reg); +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_twis_0_irq_handler(void); +void nrfx_twis_1_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_TWIS_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_uart.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_uart.h new file mode 100755 index 0000000..53bd7a4 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_uart.h @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_UART_H__ +#define NRFX_UART_H__ + +#include <nrfx.h> +#include <hal/nrf_uart.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_uart UART driver + * @{ + * @ingroup nrf_uart + * @brief UART peripheral driver. + */ + +/** + * @brief UART driver instance data structure. + */ +typedef struct +{ + NRF_UART_Type * p_reg; ///< Pointer to a structure with UART registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_uart_t; + +enum { +#if NRFX_CHECK(NRFX_UART0_ENABLED) + NRFX_UART0_INST_IDX, +#endif + NRFX_UART_ENABLED_COUNT +}; + +/** + * @brief Macro for creating a UART driver instance. + */ +#define NRFX_UART_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_UART, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_UART, id, _INST_IDX), \ +} + +/** + * @brief Types of UART driver events. + */ +typedef enum +{ + NRFX_UART_EVT_TX_DONE, ///< Requested TX transfer completed. + NRFX_UART_EVT_RX_DONE, ///< Requested RX transfer completed. + NRFX_UART_EVT_ERROR, ///< Error reported by UART peripheral. +} nrfx_uart_evt_type_t; + +/** + * @brief Structure for UART configuration. + */ +typedef struct +{ + uint32_t pseltxd; ///< TXD pin number. + uint32_t pselrxd; ///< RXD pin number. + uint32_t pselcts; ///< CTS pin number. + uint32_t pselrts; ///< RTS pin number. + void * p_context; ///< Context passed to interrupt handler. + nrf_uart_hwfc_t hwfc; ///< Flow control configuration. + nrf_uart_parity_t parity; ///< Parity configuration. + nrf_uart_baudrate_t baudrate; ///< Baudrate. + uint8_t interrupt_priority; ///< Interrupt priority. +} nrfx_uart_config_t; + +/** + * @brief UART default configuration. + */ +#define NRFX_UART_DEFAULT_CONFIG \ +{ \ + .pseltxd = NRF_UART_PSEL_DISCONNECTED, \ + .pselrxd = NRF_UART_PSEL_DISCONNECTED, \ + .pselcts = NRF_UART_PSEL_DISCONNECTED, \ + .pselrts = NRF_UART_PSEL_DISCONNECTED, \ + .p_context = NULL, \ + .hwfc = (nrf_uart_hwfc_t)NRFX_UART_DEFAULT_CONFIG_HWFC, \ + .parity = (nrf_uart_parity_t)NRFX_UART_DEFAULT_CONFIG_PARITY, \ + .baudrate = (nrf_uart_baudrate_t)NRFX_UART_DEFAULT_CONFIG_BAUDRATE, \ + .interrupt_priority = NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY, \ +} + +/** + * @brief Structure for UART transfer completion event. + */ +typedef struct +{ + uint8_t * p_data; ///< Pointer to memory used for transfer. + uint32_t bytes; ///< Number of bytes transfered. +} nrfx_uart_xfer_evt_t; + +/** + * @brief Structure for UART error event. + */ +typedef struct +{ + nrfx_uart_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transferred. + uint32_t error_mask; ///< Mask of error flags that generated the event. +} nrfx_uart_error_evt_t; + +/** + * @brief Structure for UART event. + */ +typedef struct +{ + nrfx_uart_evt_type_t type; ///< Event type. + union + { + nrfx_uart_xfer_evt_t rxtx; ///< Data provided for transfer completion events. + nrfx_uart_error_evt_t error; ///< Data provided for error event. + } data; +} nrfx_uart_event_t; + +/** + * @brief UART interrupt event handler. + * + * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available + * only within the context of the event handler. + * @param[in] p_context Context passed to interrupt handler, set on initialization. + */ +typedef void (*nrfx_uart_event_handler_t)(nrfx_uart_event_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the UART driver. + * + * This function configures and enables UART. After this function GPIO pins are controlled by UART. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. If not provided driver works in + * blocking mode. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_uart_init(nrfx_uart_t const * p_instance, + nrfx_uart_config_t const * p_config, + nrfx_uart_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the UART driver. + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_uninit(nrfx_uart_t const * p_instance); + +/** + * @brief Function for getting the address of a specific UART task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_uart_task_address_get(nrfx_uart_t const * p_instance, + nrf_uart_task_t task); + +/** + * @brief Function for getting the address of a specific UART event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event Event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_instance, + nrf_uart_event_t event); + +/** + * @brief Function for sending data over UART. + * + * If an event handler was provided in nrfx_uart_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt + * so there is no context switching inside the function. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to send. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If driver is already transferring. + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only). + */ +nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance, + uint8_t const * p_data, + size_t length); + +/** + * @brief Function for checking if UART is currently transmitting. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If UART is transmitting. + * @retval false If UART is not transmitting. + */ +bool nrfx_uart_tx_in_progress(nrfx_uart_t const * p_instance); + +/** + * @brief Function for aborting any ongoing transmission. + * @note @ref NRFX_UART_EVT_TX_DONE event will be generated in non-blocking mode. + * It will contain number of bytes sent until abort was called. The event + * handler will be called from the function context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_tx_abort(nrfx_uart_t const * p_instance); + +/** + * @brief Function for receiving data over UART. + * + * If an event handler was provided in the nrfx_uart_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt so + * there is no context switching inside the function. + * The receive buffer pointer is double buffered in non-blocking mode. The secondary + * buffer can be set immediately after starting the transfer and will be filled + * when the primary buffer is full. The double buffering feature allows + * receiving data continuously. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to receive. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If the driver is already receiving + * (and the secondary buffer has already been set + * in non-blocking mode). + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only, also see @ref nrfx_uart_rx_disable). + * @retval NRFX_ERROR_INTERNAL If UART peripheral reported an error. + */ +nrfx_err_t nrfx_uart_rx(nrfx_uart_t const * p_instance, + uint8_t * p_data, + size_t length); + + + +/** + * @brief Function for testing the receiver state in blocking mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If the receiver has at least one byte of data to get. + * @retval false If the receiver is empty. + */ +bool nrfx_uart_rx_ready(nrfx_uart_t const * p_instance); + +/** + * @brief Function for enabling the receiver. + * + * UART has a 6-byte-long RX FIFO and it is used to store incoming data. If a user does not call the + * UART receive function before the FIFO is filled, an overrun error will appear. The receiver must be + * explicitly closed by the user @sa nrfx_uart_rx_disable. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_rx_enable(nrfx_uart_t const * p_instance); + +/** + * @brief Function for disabling the receiver. + * + * This function must be called to close the receiver after it has been explicitly enabled by + * @sa nrfx_uart_rx_enable. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_rx_disable(nrfx_uart_t const * p_instance); + +/** + * @brief Function for aborting any ongoing reception. + * @note @ref NRFX_UART_EVT_TX_DONE event will be generated in non-blocking mode. + * It will contain number of bytes received until abort was called. The event + * handler will be called from the UART interrupt context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uart_rx_abort(nrfx_uart_t const * p_instance); + +/** + * @brief Function for reading error source mask. Mask contains values from @ref nrf_uart_error_mask_t. + * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is + * generated. Function clears error sources after reading. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval Mask of reported errors. + */ +uint32_t nrfx_uart_errorsrc_get(nrfx_uart_t const * p_instance); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint32_t nrfx_uart_task_address_get(nrfx_uart_t const * p_instance, + nrf_uart_task_t task) +{ + return nrf_uart_task_address_get(p_instance->p_reg, task); +} + +__STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_instance, + nrf_uart_event_t event) +{ + return nrf_uart_event_address_get(p_instance->p_reg, event); +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_uart_0_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_UART_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_uarte.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_uarte.h new file mode 100755 index 0000000..00ba08a --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_uarte.h @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_UARTE_H__ +#define NRFX_UARTE_H__ + +#include <nrfx.h> +#include <hal/nrf_uarte.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_uarte UARTE driver + * @{ + * @ingroup nrf_uarte + * @brief UARTE peripheral driver. + */ + +/** + * @brief Structure for the UARTE driver instance. + */ +typedef struct +{ + NRF_UARTE_Type * p_reg; ///< Pointer to a structure with UARTE registers. + uint8_t drv_inst_idx; ///< Driver instance index. +} nrfx_uarte_t; + +enum { +#if NRFX_CHECK(NRFX_UARTE0_ENABLED) + NRFX_UARTE0_INST_IDX, +#endif +#if NRFX_CHECK(NRFX_UARTE1_ENABLED) + NRFX_UARTE1_INST_IDX, +#endif + NRFX_UARTE_ENABLED_COUNT +}; + +/** + * @brief Macro for creating a UARTE driver instance. + */ +#define NRFX_UARTE_INSTANCE(id) \ +{ \ + .p_reg = NRFX_CONCAT_2(NRF_UARTE, id), \ + .drv_inst_idx = NRFX_CONCAT_3(NRFX_UARTE, id, _INST_IDX), \ +} + +/** + * @brief Types of UARTE driver events. + */ +typedef enum +{ + NRFX_UARTE_EVT_TX_DONE, ///< Requested TX transfer completed. + NRFX_UARTE_EVT_RX_DONE, ///< Requested RX transfer completed. + NRFX_UARTE_EVT_ERROR, ///< Error reported by UART peripheral. +} nrfx_uarte_evt_type_t; + +/** + * @brief Structure for UARTE configuration. + */ +typedef struct +{ + uint32_t pseltxd; ///< TXD pin number. + uint32_t pselrxd; ///< RXD pin number. + uint32_t pselcts; ///< CTS pin number. + uint32_t pselrts; ///< RTS pin number. + void * p_context; ///< Context passed to interrupt handler. + nrf_uarte_hwfc_t hwfc; ///< Flow control configuration. + nrf_uarte_parity_t parity; ///< Parity configuration. + nrf_uarte_baudrate_t baudrate; ///< Baudrate. + uint8_t interrupt_priority; ///< Interrupt priority. +} nrfx_uarte_config_t; + +/** + * @brief UARTE default configuration. + */ +#define NRFX_UARTE_DEFAULT_CONFIG \ +{ \ + .pseltxd = NRF_UARTE_PSEL_DISCONNECTED, \ + .pselrxd = NRF_UARTE_PSEL_DISCONNECTED, \ + .pselcts = NRF_UARTE_PSEL_DISCONNECTED, \ + .pselrts = NRF_UARTE_PSEL_DISCONNECTED, \ + .p_context = NULL, \ + .hwfc = (nrf_uarte_hwfc_t)NRFX_UARTE_DEFAULT_CONFIG_HWFC, \ + .parity = (nrf_uarte_parity_t)NRFX_UARTE_DEFAULT_CONFIG_PARITY, \ + .baudrate = (nrf_uarte_baudrate_t)NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE, \ + .interrupt_priority = NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY, \ +} + +/** + * @brief Structure for UARTE transfer completion event. + */ +typedef struct +{ + uint8_t * p_data; ///< Pointer to memory used for transfer. + uint8_t bytes; ///< Number of bytes transfered. +} nrfx_uarte_xfer_evt_t; + +/** + * @brief Structure for UARTE error event. + */ +typedef struct +{ + nrfx_uarte_xfer_evt_t rxtx; ///< Transfer details includes number of bytes transferred. + uint32_t error_mask; ///< Mask of error flags that generated the event. +} nrfx_uarte_error_evt_t; + +/** + * @brief Structure for UARTE event. + */ +typedef struct +{ + nrfx_uarte_evt_type_t type; ///< Event type. + union + { + nrfx_uarte_xfer_evt_t rxtx; ///< Data provided for transfer completion events. + nrfx_uarte_error_evt_t error; ///< Data provided for error event. + } data; +} nrfx_uarte_event_t; + +/** + * @brief UARTE interrupt event handler. + * + * @param[in] p_event Pointer to event structure. Event is allocated on the stack so it is available + * only within the context of the event handler. + * @param[in] p_context Context passed to interrupt handler, set on initialization. + */ +typedef void (*nrfx_uarte_event_handler_t)(nrfx_uarte_event_t const * p_event, + void * p_context); + +/** + * @brief Function for initializing the UARTE driver. + * + * This function configures and enables UARTE. After this function GPIO pins are controlled by UARTE. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] event_handler Event handler provided by the user. If not provided driver works in + * blocking mode. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_INVALID_STATE If driver is already initialized. + * @retval NRFX_ERROR_BUSY If some other peripheral with the same + * instance ID is already in use. This is + * possible only if @ref nrfx_prs module + * is enabled. + */ +nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance, + nrfx_uarte_config_t const * p_config, + nrfx_uarte_event_handler_t event_handler); + +/** + * @brief Function for uninitializing the UARTE driver. + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for getting the address of a specific UARTE task. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrfx_uarte_task_address_get(nrfx_uarte_t const * p_instance, + nrf_uarte_task_t task); + +/** + * @brief Function for getting the address of a specific UARTE event. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] event Event. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_instance, + nrf_uarte_event_t event); + +/** + * @brief Function for sending data over UARTE. + * + * If an event handler was provided in nrfx_uarte_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt + * so there is no context switching inside the function. + * + * @note Peripherals using EasyDMA (including UARTE) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to send. Maximum possible length is + * dependent on the used SoC (see the MAXCNT register + * description in the Product Specification). The driver + * checks it with assertion. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If driver is already transferring. + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only). + * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer. + */ +nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance, + uint8_t const * p_data, + size_t length); + +/** + * @brief Function for checking if UARTE is currently transmitting. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If UARTE is transmitting. + * @retval false If UARTE is not transmitting. + */ +bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for aborting any ongoing transmission. + * @note @ref NRFX_UARTE_EVT_TX_DONE event will be generated in non-blocking mode. + * It will contain number of bytes sent until abort was called. The event + * handler will be called from UARTE interrupt context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for receiving data over UARTE. + * + * If an event handler was provided in the nrfx_uarte_init() call, this function + * returns immediately and the handler is called when the transfer is done. + * Otherwise, the transfer is performed in blocking mode, i.e. this function + * returns when the transfer is finished. Blocking mode is not using interrupt so + * there is no context switching inside the function. + * The receive buffer pointer is double buffered in non-blocking mode. The secondary + * buffer can be set immediately after starting the transfer and will be filled + * when the primary buffer is full. The double buffering feature allows + * receiving data continuously. + * + * @note Peripherals using EasyDMA (including UARTE) require the transfer buffers + * to be placed in the Data RAM region. If this condition is not met, + * this function will fail with the error code NRFX_ERROR_INVALID_ADDR. + * + * @param[in] p_instance Pointer to the driver instance structure. + * @param[in] p_data Pointer to data. + * @param[in] length Number of bytes to receive. Maximum possible length is + * dependent on the used SoC (see the MAXCNT register + * description in the Product Specification). The driver + * checks it with assertion. + * + * @retval NRFX_SUCCESS If initialization was successful. + * @retval NRFX_ERROR_BUSY If the driver is already receiving + * (and the secondary buffer has already been set + * in non-blocking mode). + * @retval NRFX_ERROR_FORBIDDEN If the transfer was aborted from a different context + * (blocking mode only). + * @retval NRFX_ERROR_INTERNAL If UARTE peripheral reported an error. + * @retval NRFX_ERROR_INVALID_ADDR If p_data does not point to RAM buffer. + */ +nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance, + uint8_t * p_data, + size_t length); + + + +/** + * @brief Function for testing the receiver state in blocking mode. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval true If the receiver has at least one byte of data to get. + * @retval false If the receiver is empty. + */ +bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for aborting any ongoing reception. + * @note @ref NRFX_UARTE_EVT_RX_DONE event will be generated in non-blocking mode. + * It will contain number of bytes received until abort was called. The event + * handler will be called from UARTE interrupt context. + * + * @param[in] p_instance Pointer to the driver instance structure. + */ +void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance); + +/** + * @brief Function for reading error source mask. Mask contains values from @ref nrf_uarte_error_mask_t. + * @note Function should be used in blocking mode only. In case of non-blocking mode, an error event is + * generated. Function clears error sources after reading. + * + * @param[in] p_instance Pointer to the driver instance structure. + * + * @retval Mask of reported errors. + */ +uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint32_t nrfx_uarte_task_address_get(nrfx_uarte_t const * p_instance, + nrf_uarte_task_t task) +{ + return nrf_uarte_task_address_get(p_instance->p_reg, task); +} + +__STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_instance, + nrf_uarte_event_t event) +{ + return nrf_uarte_event_address_get(p_instance->p_reg, event); +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +void nrfx_uarte_0_irq_handler(void); +void nrfx_uarte_1_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_UARTE_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_wdt.h b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_wdt.h new file mode 100755 index 0000000..ff00ff5 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/include/nrfx_wdt.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_WDT_H__ +#define NRFX_WDT_H__ + +#include <nrfx.h> +#include <hal/nrf_wdt.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_wdt WDT driver + * @{ + * @ingroup nrf_wdt + * @brief Watchdog Timer (WDT) peripheral driver. + */ + +/**@brief Struct for WDT initialization. */ +typedef struct +{ + nrf_wdt_behaviour_t behaviour; /**< WDT behaviour when CPU in sleep/halt mode. */ + uint32_t reload_value; /**< WDT reload value in ms. */ + uint8_t interrupt_priority; /**< WDT interrupt priority */ +} nrfx_wdt_config_t; + +/**@brief WDT event handler function type. */ +typedef void (*nrfx_wdt_event_handler_t)(void); + +/**@brief WDT channel id type. */ +typedef nrf_wdt_rr_register_t nrfx_wdt_channel_id; + +#define NRFX_WDT_DEAFULT_CONFIG \ + { \ + .behaviour = (nrf_wdt_behaviour_t)NRFX_WDT_CONFIG_BEHAVIOUR, \ + .reload_value = NRFX_WDT_CONFIG_RELOAD_VALUE, \ + .interrupt_priority = NRFX_WDT_CONFIG_IRQ_PRIORITY, \ + } +/** + * @brief This function initializes watchdog. + * + * @param[in] p_config Pointer to the structure with initial configuration. + * @param[in] wdt_event_handler Event handler provided by the user. + * Must not be NULL. + * + * @return NRFX_SUCCESS on success, otherwise an error code. + */ +nrfx_err_t nrfx_wdt_init(nrfx_wdt_config_t const * p_config, + nrfx_wdt_event_handler_t wdt_event_handler); + +/** + * @brief This function allocate watchdog channel. + * + * @note This function can not be called after nrfx_wdt_start(void). + * + * @param[out] p_channel_id ID of granted channel. + * + * @return NRFX_SUCCESS on success, otherwise an error code. + */ +nrfx_err_t nrfx_wdt_channel_alloc(nrfx_wdt_channel_id * p_channel_id); + +/** + * @brief This function starts watchdog. + * + * @note After calling this function the watchdog is started, so the user needs to feed all allocated + * watchdog channels to avoid reset. At least one watchdog channel has to be allocated. + */ +void nrfx_wdt_enable(void); + +/** + * @brief This function feeds the watchdog. + * + * @details Function feeds all allocated watchdog channels. + */ +void nrfx_wdt_feed(void); + +/** + * @brief This function feeds the invidual watchdog channel. + * + * @param[in] channel_id ID of watchdog channel. + */ +void nrfx_wdt_channel_feed(nrfx_wdt_channel_id channel_id); + +/**@brief Function for returning a requested task address for the wdt driver module. + * + * @param[in] task One of the peripheral tasks. + * + * @retval Task address. + */ +__STATIC_INLINE uint32_t nrfx_wdt_ppi_task_addr(nrf_wdt_task_t task) +{ + return nrf_wdt_task_address_get(task); +} + +/**@brief Function for returning a requested event address for the wdt driver module. + * + * @param[in] event One of the peripheral events. + * + * @retval Event address + */ +__STATIC_INLINE uint32_t nrfx_wdt_ppi_event_addr(nrf_wdt_event_t event) +{ + return nrf_wdt_event_address_get(event); +} + + +void nrfx_wdt_irq_handler(void); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/nrfx_common.h b/arduino/cores/nRF5/nordic/nrfx/drivers/nrfx_common.h new file mode 100755 index 0000000..537f1ef --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/nrfx_common.h @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_COMMON_H__ +#define NRFX_COMMON_H__ + +#include <stdint.h> +#include <stddef.h> +#include <stdbool.h> + +#include <nrf.h> +#include <nrf_peripherals.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_common Common module + * @{ + * @ingroup nrfx + * @brief Common module. + */ + +/** + * @brief Macro for checking if the specified identifier is defined and it has + * a non-zero value. + * + * Normally, preprocessors treat all undefined identifiers as having the value + * zero. However, some tools, like static code analyzers, may issue a warning + * when such identifier is evaluated. This macro gives the possibility to suppress + * such warnings only in places where this macro is used for evaluation, not in + * the whole analyzed code. + */ +#define NRFX_CHECK(module_enabled) (module_enabled) + +/** + * @brief Macro for concatenating two tokens in macro expansion. + * + * @note This macro is expanded in two steps so that tokens given as macros + * themselves are fully expanded before they are merged. + * + * @param p1 First token. + * @param p2 Second token. + * + * @return The two tokens merged into one, unless they cannot together form + * a valid token (in such case, the preprocessor issues a warning and + * does not perform the concatenation). + * + * @sa NRFX_CONCAT_3 + */ +#define NRFX_CONCAT_2(p1, p2) NRFX_CONCAT_2_(p1, p2) +/** + * @brief Internal macro used by @ref NRFX_CONCAT_2 to perform the expansion + * in two steps. + */ +#define NRFX_CONCAT_2_(p1, p2) p1 ## p2 + +/** + * @brief Macro for concatenating three tokens in macro expansion. + * + * @note This macro is expanded in two steps so that tokens given as macros + * themselves are fully expanded before they are merged. + * + * @param p1 First token. + * @param p2 Second token. + * @param p3 Third token. + * + * @return The three tokens merged into one, unless they cannot together form + * a valid token (in such case, the preprocessor issues a warning and + * does not perform the concatenation). + * + * @sa NRFX_CONCAT_2 + */ +#define NRFX_CONCAT_3(p1, p2, p3) NRFX_CONCAT_3_(p1, p2, p3) +/** + * @brief Internal macro used by @ref NRFX_CONCAT_3 to perform the expansion + * in two steps. + */ +#define NRFX_CONCAT_3_(p1, p2, p3) p1 ## p2 ## p3 + +/**@brief Macro for performing rounded integer division (as opposed to + * truncating the result). + * + * @param a Numerator. + * @param b Denominator. + * + * @return Rounded (integer) result of dividing @c a by @c b. + */ +#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) + +/**@brief Macro for performing integer division, making sure the result is rounded up. + * + * @details A typical use case for this macro is to compute the number of objects + * with size @c b required to hold @c a number of bytes. + * + * @param a Numerator. + * @param b Denominator. + * + * @return Integer result of dividing @c a by @c b, rounded up. + */ +#define NRFX_CEIL_DIV(a, b) ((((a) - 1) / (b)) + 1) + +/** + * @brief Macro for getting the number of elements in an array. + * + * @param array Name of the array. + * + * @return Array element count. + */ +#define NRFX_ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0])) + +/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed + * the limit of the specified peripheral. + * + * @param peripheral Peripheral to check the lengths against. + * @param length1 First length to be checked. + * @param length2 Second length to be checked (pass 0 if not needed). + * + * @return + */ +#define NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, length1, length2) \ + (((length1) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE))) && \ + ((length2) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE)))) + +/**@brief Macro for waiting until condition is met. + * + * @param[in] condition Condition to meet. + * @param[in] attempts Maximum number of condition checks. Must not be 0. + * @param[in] delay_us Delay between consecutive checks, in microseconds. + * @param[out] result Boolean variable to store the result of the wait process. + * Set to true if the condition is met or false otherwise. + */ +#define NRFX_WAIT_FOR(condition, attempts, delay_us, result) \ +do { \ + result = false; \ + uint32_t remaining_attempts = (attempts); \ + do { \ + if (condition) \ + { \ + result = true; \ + break; \ + } \ + NRFX_DELAY_US(delay_us); \ + } while (--remaining_attempts); \ +} while(0) + +/** + * @brief Macro for getting the interrupt number assigned to a specific + * peripheral. + * + * In Nordic SoCs the IRQ number assigned to a peripheral is equal to the ID + * of this peripheral, and there is a direct relationship between this ID and + * the peripheral base address, i.e. the address of a fixed block of 0x1000 + * bytes of address space assigned to this peripheral. + * See the chapter "Peripheral interface" (sections "Peripheral ID" and + * "Interrupts") in the product specification of a given SoC. + * + * @param[in] base_addr Peripheral base address or pointer. + * + * @return Interrupt number associated with the specified peripheral. + */ +#define NRFX_IRQ_NUMBER_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12) + +/** + * @brief IRQ handler type. + */ +typedef void (* nrfx_irq_handler_t)(void); + +/** + * @brief Driver state. + */ +typedef enum +{ + NRFX_DRV_STATE_UNINITIALIZED, ///< Uninitialized. + NRFX_DRV_STATE_INITIALIZED, ///< Initialized but powered off. + NRFX_DRV_STATE_POWERED_ON, ///< Initialized and powered on. +} nrfx_drv_state_t; + + +/** + * @brief Function for checking if an object is placed in the Data RAM region. + * + * Several peripherals (the ones using EasyDMA) require the transfer buffers + * to be placed in the Data RAM region. This function can be used to check if + * this condition is met. + * + * @param[in] p_object Pointer to an object whose location is to be checked. + * + * @retval true If the pointed object is located in the Data RAM region. + * @retval false Otherwise. + */ +__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object); + +/** + * @brief Function for getting the interrupt number for a specific peripheral. + * + * @param[in] p_reg Peripheral base pointer. + * + * @return Interrupt number associated with the pointed peripheral. + */ +__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg); + +/** + * @brief Function for converting an INTEN register bit position to the + * corresponding event identifier. + * + * The event identifier is the offset between the event register address and + * the peripheral base address, and is equal (thus, can be directly cast) to + * the corresponding value of the enumerated type from HAL (nrf_*_event_t). + + * @param bit INTEN register bit position. + * + * @return Event identifier. + * + * @sa nrfx_event_to_bitpos + */ +__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit); + +/** + * @brief Function for converting an event identifier to the corresponding + * INTEN register bit position. + * + * The event identifier is the offset between the event register address and + * the peripheral base address, and is equal (thus, can be directly cast) to + * the corresponding value of the enumerated type from HAL (nrf_*_event_t). + * + * @param event Event identifier. + * + * @return INTEN register bit position. + * + * @sa nrfx_bitpos_to_event + */ +__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE bool nrfx_is_in_ram(void const * p_object) +{ + return ((((uint32_t)p_object) & 0xE0000000u) == 0x20000000u); +} + +__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg) +{ + return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg); +} + +__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit) +{ + static const uint32_t event_reg_offset = 0x100u; + return event_reg_offset + (bit * sizeof(uint32_t)); +} + +__STATIC_INLINE uint32_t nrfx_event_to_bitpos(uint32_t event) +{ + static const uint32_t event_reg_offset = 0x100u; + return (event - event_reg_offset) / sizeof(uint32_t); +} + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_COMMON_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/nrfx_errors.h b/arduino/cores/nRF5/nordic/nrfx/drivers/nrfx_errors.h new file mode 100755 index 0000000..31062ce --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/nrfx_errors.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_ERRORS_H__ +#define NRFX_ERRORS_H__ + +#if !NRFX_CHECK(NRFX_CUSTOM_ERROR_CODES) + +/** + * @defgroup nrfx_error_codes Global Error Codes + * @{ + * @ingroup nrfx + * + * @brief Global error codes definitions. + */ + +#define NRFX_ERROR_BASE_NUM 0x0BAD0000 +#define NRFX_ERROR_DRIVERS_BASE_NUM (NRFX_ERROR_BASE_NUM + 0x10000) + +/** @brief Enumerated type for error codes. */ +typedef enum { + NRFX_SUCCESS = (NRFX_ERROR_BASE_NUM + 0), ///< Operation performed successfully. + NRFX_ERROR_INTERNAL = (NRFX_ERROR_BASE_NUM + 1), ///< Internal error. + NRFX_ERROR_NO_MEM = (NRFX_ERROR_BASE_NUM + 2), ///< No memory for operation. + NRFX_ERROR_NOT_SUPPORTED = (NRFX_ERROR_BASE_NUM + 3), ///< Not supported. + NRFX_ERROR_INVALID_PARAM = (NRFX_ERROR_BASE_NUM + 4), ///< Invalid parameter. + NRFX_ERROR_INVALID_STATE = (NRFX_ERROR_BASE_NUM + 5), ///< Invalid state, operation disallowed in this state. + NRFX_ERROR_INVALID_LENGTH = (NRFX_ERROR_BASE_NUM + 6), ///< Invalid length. + NRFX_ERROR_TIMEOUT = (NRFX_ERROR_BASE_NUM + 7), ///< Operation timed out. + NRFX_ERROR_FORBIDDEN = (NRFX_ERROR_BASE_NUM + 8), ///< Operation is forbidden. + NRFX_ERROR_NULL = (NRFX_ERROR_BASE_NUM + 9), ///< Null pointer. + NRFX_ERROR_INVALID_ADDR = (NRFX_ERROR_BASE_NUM + 10), ///< Bad memory address. + NRFX_ERROR_BUSY = (NRFX_ERROR_BASE_NUM + 11), ///< Busy. + NRFX_ERROR_ALREADY_INITIALIZED = (NRFX_ERROR_BASE_NUM + 12), ///< Module already initialized. + + NRFX_ERROR_DRV_TWI_ERR_OVERRUN = (NRFX_ERROR_DRIVERS_BASE_NUM + 0), ///< TWI error: Overrun. + NRFX_ERROR_DRV_TWI_ERR_ANACK = (NRFX_ERROR_DRIVERS_BASE_NUM + 1), ///< TWI error: Address not acknowledged. + NRFX_ERROR_DRV_TWI_ERR_DNACK = (NRFX_ERROR_DRIVERS_BASE_NUM + 2) ///< TWI error: Data not acknowledged. +} nrfx_err_t; + +/** @} */ + +#endif // !NRFX_CHECK(NRFX_CUSTOM_ERROR_CODES) + +#endif // NRFX_ERRORS_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/src/nrfx_power.c b/arduino/cores/nRF5/nordic/nrfx/drivers/src/nrfx_power.c new file mode 100755 index 0000000..194ce60 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/src/nrfx_power.c @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <nrfx.h> + +#if NRFX_CHECK(NRFX_POWER_ENABLED) + +#include <nrfx_power.h> + +#if NRFX_CHECK(NRFX_CLOCK_ENABLED) +extern bool nrfx_clock_irq_enabled; +extern void nrfx_clock_irq_handler(void); +#endif + +/** + * @internal + * @defgroup nrfx_power_internals POWER driver internals + * @ingroup nrfx_power + * + * Internal variables, auxiliary macros and functions of POWER driver. + * @{ + */ + +/** + * This variable is used to check whether common POWER_CLOCK common interrupt + * should be disabled or not if @ref nrfx_clock tries to disable the interrupt. + */ + +bool nrfx_power_irq_enabled; + +/** + * @brief The initialization flag + */ + +#define m_initialized nrfx_power_irq_enabled + +/** + * @brief The handler of power fail comparator warning event + */ +static nrfx_power_pofwarn_event_handler_t m_pofwarn_handler; + +#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) +/** + * @brief The handler of sleep event handler + */ +static nrfx_power_sleep_event_handler_t m_sleepevt_handler; +#endif + +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) +/** + * @brief The handler of USB power events + */ +static nrfx_power_usb_event_handler_t m_usbevt_handler; +#endif + +/** @} */ + +nrfx_power_pofwarn_event_handler_t nrfx_power_pof_handler_get(void) +{ + return m_pofwarn_handler; +} + +#if NRF_POWER_HAS_USBREG +nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void) +{ + return m_usbevt_handler; +} +#endif + +nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config) +{ + NRFX_ASSERT(p_config); + if (m_initialized) + { + return NRFX_ERROR_ALREADY_INITIALIZED; + } + +#if NRF_POWER_HAS_VDDH + nrf_power_dcdcen_vddh_set(p_config->dcdcenhv); +#endif + nrf_power_dcdcen_set(p_config->dcdcen); + + nrfx_power_clock_irq_init(); + + m_initialized = true; + return NRFX_SUCCESS; +} + + +void nrfx_power_uninit(void) +{ + NRFX_ASSERT(m_initialized); + +#if NRFX_CHECK(NRFX_CLOCK_ENABLED) + if (!nrfx_clock_irq_enabled) +#endif + { + NRFX_IRQ_DISABLE(POWER_CLOCK_IRQn); + } + + nrfx_power_pof_uninit(); +#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) + nrfx_power_sleepevt_uninit(); +#endif +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) + nrfx_power_usbevt_uninit(); +#endif + m_initialized = false; +} + +void nrfx_power_pof_init(nrfx_power_pofwarn_config_t const * p_config) +{ + NRFX_ASSERT(p_config != NULL); + + nrfx_power_pof_uninit(); + + if (p_config->handler != NULL) + { + m_pofwarn_handler = p_config->handler; + } +} + +void nrfx_power_pof_enable(nrfx_power_pofwarn_config_t const * p_config) +{ + nrf_power_pofcon_set(true, p_config->thr); +#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__) + nrf_power_pofcon_vddh_set(p_config->thrvddh); +#endif + if (m_pofwarn_handler != NULL) + { + nrf_power_int_enable(NRF_POWER_INT_POFWARN_MASK); + } +} + +void nrfx_power_pof_disable(void) +{ + nrf_power_int_disable(NRF_POWER_INT_POFWARN_MASK); +} + +void nrfx_power_pof_uninit(void) +{ + m_pofwarn_handler = NULL; +} + +#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) +void nrfx_power_sleepevt_init(nrfx_power_sleepevt_config_t const * p_config) +{ + NRFX_ASSERT(p_config != NULL); + + nrfx_power_sleepevt_uninit(); + if (p_config->handler != NULL) + { + m_sleepevt_handler = p_config->handler; + } +} + +void nrfx_power_sleepevt_enable(nrfx_power_sleepevt_config_t const * p_config) +{ + uint32_t enmask = 0; + if (p_config->en_enter) + { + enmask |= NRF_POWER_INT_SLEEPENTER_MASK; + nrf_power_event_clear(NRF_POWER_EVENT_SLEEPENTER); + } + if (p_config->en_exit) + { + enmask |= NRF_POWER_INT_SLEEPEXIT_MASK; + nrf_power_event_clear(NRF_POWER_EVENT_SLEEPEXIT); + } + nrf_power_int_enable(enmask); +} + +void nrfx_power_sleepevt_disable(void) +{ + nrf_power_int_disable( + NRF_POWER_INT_SLEEPENTER_MASK | + NRF_POWER_INT_SLEEPEXIT_MASK); +} + +void nrfx_power_sleepevt_uninit(void) +{ + m_sleepevt_handler = NULL; +} +#endif /* NRF_POWER_HAS_SLEEPEVT */ + +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) +void nrfx_power_usbevt_init(nrfx_power_usbevt_config_t const * p_config) +{ + nrfx_power_usbevt_uninit(); + if (p_config->handler != NULL) + { + m_usbevt_handler = p_config->handler; + } +} + +void nrfx_power_usbevt_enable(void) +{ + nrf_power_int_enable( + NRF_POWER_INT_USBDETECTED_MASK | + NRF_POWER_INT_USBREMOVED_MASK | + NRF_POWER_INT_USBPWRRDY_MASK); +} + +void nrfx_power_usbevt_disable(void) +{ + nrf_power_int_disable( + NRF_POWER_INT_USBDETECTED_MASK | + NRF_POWER_INT_USBREMOVED_MASK | + NRF_POWER_INT_USBPWRRDY_MASK); +} + +void nrfx_power_usbevt_uninit(void) +{ + m_usbevt_handler = NULL; +} +#endif /* NRF_POWER_HAS_USBREG */ + + +void nrfx_power_irq_handler(void) +{ + uint32_t enabled = nrf_power_int_enable_get(); + if ((0 != (enabled & NRF_POWER_INT_POFWARN_MASK)) && + nrf_power_event_get_and_clear(NRF_POWER_EVENT_POFWARN)) + { + /* Cannot be null if event is enabled */ + NRFX_ASSERT(m_pofwarn_handler != NULL); + m_pofwarn_handler(); + } +#if NRF_POWER_HAS_SLEEPEVT || defined(__NRFX_DOXYGEN__) + if ((0 != (enabled & NRF_POWER_INT_SLEEPENTER_MASK)) && + nrf_power_event_get_and_clear(NRF_POWER_EVENT_SLEEPENTER)) + { + /* Cannot be null if event is enabled */ + NRFX_ASSERT(m_sleepevt_handler != NULL); + m_sleepevt_handler(NRFX_POWER_SLEEP_EVT_ENTER); + } + if ((0 != (enabled & NRF_POWER_INT_SLEEPEXIT_MASK)) && + nrf_power_event_get_and_clear(NRF_POWER_EVENT_SLEEPEXIT)) + { + /* Cannot be null if event is enabled */ + NRFX_ASSERT(m_sleepevt_handler != NULL); + m_sleepevt_handler(NRFX_POWER_SLEEP_EVT_EXIT); + } +#endif +#if NRF_POWER_HAS_USBREG || defined(__NRFX_DOXYGEN__) + if ((0 != (enabled & NRF_POWER_INT_USBDETECTED_MASK)) && + nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBDETECTED)) + { + /* Cannot be null if event is enabled */ + NRFX_ASSERT(m_usbevt_handler != NULL); + m_usbevt_handler(NRFX_POWER_USB_EVT_DETECTED); + } + if ((0 != (enabled & NRF_POWER_INT_USBREMOVED_MASK)) && + nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBREMOVED)) + { + /* Cannot be null if event is enabled */ + NRFX_ASSERT(m_usbevt_handler != NULL); + m_usbevt_handler(NRFX_POWER_USB_EVT_REMOVED); + } + if ((0 != (enabled & NRF_POWER_INT_USBPWRRDY_MASK)) && + nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBPWRRDY)) + { + /* Cannot be null if event is enabled */ + NRFX_ASSERT(m_usbevt_handler != NULL); + m_usbevt_handler(NRFX_POWER_USB_EVT_READY); + } +#endif +} + +#if NRFX_CHECK(NRFX_CLOCK_ENABLED) +/* + * If both POWER and CLOCK drivers are used, a common IRQ handler function must + * be used that calls the handlers in these two drivers. This is because these + * two peripherals share one interrupt. + * This function is located here, not in a separate nrfx_power_clock.c file, + * so that it does not end up as the only symbol in a separate object when + * a library with nrfx is created. In such case, forcing a linker to use this + * function instead of another one defined as weak will require additional + * actions, and might be even impossible. + */ +void nrfx_power_clock_irq_handler(void) +{ + nrfx_power_irq_handler(); + nrfx_clock_irq_handler(); +} +#endif + +#endif // NRFX_CHECK(NRFX_POWER_ENABLED) diff --git a/arduino/cores/nRF5/nordic/nrfx/drivers/src/nrfx_qspi.c b/arduino/cores/nRF5/nordic/nrfx/drivers/src/nrfx_qspi.c new file mode 100755 index 0000000..8eae4d7 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/drivers/src/nrfx_qspi.c @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <nrfx.h> + +#if NRFX_CHECK(NRFX_QSPI_ENABLED) + +#include <nrfx_qspi.h> + + +/** + * @brief Command byte used to read status register. + * + */ +#define QSPI_STD_CMD_RDSR 0x05 + +/** + * @brief Byte used to mask status register and retrieve the write-in-progess bit. + * + */ +#define QSPI_MEM_STATUSREG_WIP_Pos 0x01 + +/** + * @brief Default time used in timeout function. + */ +#define QSPI_DEF_WAIT_TIME_US 10 + +/** + * @brief Default number of tries in timeout function. + */ +#define QSPI_DEF_WAIT_ATTEMPTS 100 + +/** + * @brief Control block - driver instance local data. + */ +typedef struct +{ + nrfx_qspi_handler_t handler; /**< Handler. */ + nrfx_drv_state_t state; /**< Driver state. */ + volatile bool interrupt_driven; /**< Information if the current operation is performed and is interrupt-driven. */ + void * p_context; /**< Driver context used in interrupt. */ +} qspi_control_block_t; + +static qspi_control_block_t m_cb; + +static nrfx_err_t qspi_task_perform(nrf_qspi_task_t task) +{ + // Wait for peripheral + if (m_cb.interrupt_driven) + { + return NRFX_ERROR_BUSY; + } + + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + + if (m_cb.handler) + { + m_cb.interrupt_driven = true; + nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + } + + nrf_qspi_task_trigger(NRF_QSPI, task); + + if (m_cb.handler == NULL) + { + while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) + {}; + } + return NRFX_SUCCESS; +} + +static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config) +{ + // Check if the user set meaningful values to struct fields. If not, return false. + if ((p_config->sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->io1_pin == NRF_QSPI_PIN_NOT_CONNECTED)) + { + return false; + } + + nrf_qspi_pins_set(NRF_QSPI, p_config); + + return true; +} + +nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, + nrfx_qspi_handler_t handler, + void * p_context) +{ + NRFX_ASSERT(p_config); + if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) + { + return NRFX_ERROR_INVALID_STATE; + } + + if (!qspi_pins_configure(&p_config->pins)) + { + return NRFX_ERROR_INVALID_PARAM; + } + + nrf_qspi_xip_offset_set(NRF_QSPI, p_config->xip_offset); + nrf_qspi_ifconfig0_set(NRF_QSPI, &p_config->prot_if); + nrf_qspi_ifconfig1_set(NRF_QSPI, &p_config->phy_if); + + m_cb.interrupt_driven = false; + m_cb.handler = handler; + m_cb.p_context = p_context; + + /* QSPI interrupt is disabled because the device should be enabled in polling mode (wait for activate + task event ready)*/ + nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + + if (handler) + { + NRFX_IRQ_PRIORITY_SET(QSPI_IRQn, p_config->irq_priority); + NRFX_IRQ_ENABLE(QSPI_IRQn); + } + + m_cb.state = NRFX_DRV_STATE_INITIALIZED; + + nrf_qspi_enable(NRF_QSPI); + + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ACTIVATE); + + // Waiting for the peripheral to activate + bool result; + NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY), + QSPI_DEF_WAIT_ATTEMPTS, + QSPI_DEF_WAIT_TIME_US, + result); + + if (!result) + { + return NRFX_ERROR_TIMEOUT; + } + + return NRFX_SUCCESS; +} + +nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, + void const * p_tx_buffer, + void * p_rx_buffer) +{ + NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + + if (m_cb.interrupt_driven) + { + return NRFX_ERROR_BUSY; + } + + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + /* In some cases, only opcode should be sent. To prevent execution, set function code is + * surrounded by an if. + */ + if (p_tx_buffer) + { + nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer); + } + nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + + nrf_qspi_cinstr_transfer_start(NRF_QSPI, p_config); + + bool result; + NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY), + QSPI_DEF_WAIT_ATTEMPTS, + QSPI_DEF_WAIT_TIME_US, + result); + + if (!result) + { + // This timeout should never occur when WIPWAIT is not active, since in this + // case the QSPI peripheral should send the command immediately, without any + // waiting for previous write to complete. + NRFX_ASSERT(p_config->wipwait); + + return NRFX_ERROR_TIMEOUT; + } + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + + if (p_rx_buffer) + { + nrf_qspi_cinstrdata_get(NRF_QSPI, p_config->length, p_rx_buffer); + } + + return NRFX_SUCCESS; +} + +nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode, + nrf_qspi_cinstr_len_t length, + void const * p_tx_buffer) +{ + nrf_qspi_cinstr_conf_t config = NRFX_QSPI_DEFAULT_CINSTR(opcode, length); + return nrfx_qspi_cinstr_xfer(&config, p_tx_buffer, NULL); +} + +nrfx_err_t nrfx_qspi_mem_busy_check(void) +{ + nrfx_err_t ret_code; + uint8_t status_value = 0; + + nrf_qspi_cinstr_conf_t const config = + NRFX_QSPI_DEFAULT_CINSTR(QSPI_STD_CMD_RDSR, + NRF_QSPI_CINSTR_LEN_2B); + ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value); + + if (ret_code != NRFX_SUCCESS) + { + return ret_code; + } + + if ((status_value & QSPI_MEM_STATUSREG_WIP_Pos) != 0x00) + { + return NRFX_ERROR_BUSY; + } + + return NRFX_SUCCESS; +} + +void nrfx_qspi_uninit(void) +{ + NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + + nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + + nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_DEACTIVATE); + + // Workaround for nRF52840 anomaly 122: Current consumption is too high. + *(volatile uint32_t *)0x40029054ul = 1ul; + + nrf_qspi_disable(NRF_QSPI); + + NRFX_IRQ_DISABLE(QSPI_IRQn); + + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + + m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; +} + +nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer, + size_t tx_buffer_length, + uint32_t dst_address) +{ + NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(p_tx_buffer != NULL); + + if (!nrfx_is_in_ram(p_tx_buffer)) + { + return NRFX_ERROR_INVALID_ADDR; + } + + nrf_qspi_write_buffer_set(NRF_QSPI, p_tx_buffer, tx_buffer_length, dst_address); + return qspi_task_perform(NRF_QSPI_TASK_WRITESTART); + +} + +nrfx_err_t nrfx_qspi_read(void * p_rx_buffer, + size_t rx_buffer_length, + uint32_t src_address) +{ + NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(p_rx_buffer != NULL); + + if (!nrfx_is_in_ram(p_rx_buffer)) + { + return NRFX_ERROR_INVALID_ADDR; + } + + nrf_qspi_read_buffer_set(NRF_QSPI, p_rx_buffer, rx_buffer_length, src_address); + return qspi_task_perform(NRF_QSPI_TASK_READSTART); +} + +nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length, + uint32_t start_address) +{ + NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + nrf_qspi_erase_ptr_set(NRF_QSPI, start_address, length); + return qspi_task_perform(NRF_QSPI_TASK_ERASESTART); +} + +nrfx_err_t nrfx_qspi_chip_erase(void) +{ + return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0); +} + +void nrfx_qspi_irq_handler(void) +{ + // Catch Event ready interrupts + if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) + { + m_cb.interrupt_driven = false; + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + m_cb.handler(NRFX_QSPI_EVENT_DONE, m_cb.p_context); + } +} + +#endif // NRFX_CHECK(NRFX_QSPI_ENABLED) diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_adc.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_adc.h new file mode 100755 index 0000000..97a8cdb --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_adc.h @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_ADC_H_ +#define NRF_ADC_H_ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_adc_hal ADC HAL + * @{ + * @ingroup nrf_adc + * @brief Hardware access layer for managing the Analog-to-Digital Converter (ADC) + * peripheral. + */ + +/** @brief ADC interrupts. */ +typedef enum +{ + NRF_ADC_INT_END_MASK = ADC_INTENSET_END_Msk, /**< ADC interrupt on END event. */ +} nrf_adc_int_mask_t; + +/** @brief Resolution of the analog-to-digital converter. */ +typedef enum +{ + NRF_ADC_CONFIG_RES_8BIT = ADC_CONFIG_RES_8bit, /**< 8-bit resolution. */ + NRF_ADC_CONFIG_RES_9BIT = ADC_CONFIG_RES_9bit, /**< 9-bit resolution. */ + NRF_ADC_CONFIG_RES_10BIT = ADC_CONFIG_RES_10bit, /**< 10-bit resolution. */ +} nrf_adc_config_resolution_t; + + +/** @brief Scaling factor of the analog-to-digital conversion. */ +typedef enum +{ + NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE = ADC_CONFIG_INPSEL_AnalogInputNoPrescaling, /**< Full scale input. */ + NRF_ADC_CONFIG_SCALING_INPUT_TWO_THIRDS = ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling, /**< 2/3 scale input. */ + NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD = ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling, /**< 1/3 scale input. */ + NRF_ADC_CONFIG_SCALING_SUPPLY_TWO_THIRDS = ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling, /**< 2/3 of supply. */ + NRF_ADC_CONFIG_SCALING_SUPPLY_ONE_THIRD = ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling /**< 1/3 of supply. */ +} nrf_adc_config_scaling_t; + + +/** + * @brief External reference selection of the analog-to-digital converter. + */ +typedef enum +{ + NRF_ADC_CONFIG_EXTREFSEL_NONE = ADC_CONFIG_EXTREFSEL_None, /**< Analog reference inputs disabled. */ + NRF_ADC_CONFIG_EXTREFSEL_AREF0 = ADC_CONFIG_EXTREFSEL_AnalogReference0, /**< AREF0 as analog reference. */ + NRF_ADC_CONFIG_EXTREFSEL_AREF1 = ADC_CONFIG_EXTREFSEL_AnalogReference1 /**< AREF1 as analog reference. */ +} nrf_adc_config_extref_t; + +/** + * @brief Reference selection of the analog-to-digital converter. + */ +typedef enum +{ + NRF_ADC_CONFIG_REF_VBG = ADC_CONFIG_REFSEL_VBG, /**< 1.2 V reference. */ + NRF_ADC_CONFIG_REF_SUPPLY_ONE_HALF = ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling, /**< 1/2 of power supply. */ + NRF_ADC_CONFIG_REF_SUPPLY_ONE_THIRD = ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling, /**< 1/3 of power supply. */ + NRF_ADC_CONFIG_REF_EXT = ADC_CONFIG_REFSEL_External /**< External reference. See @ref nrf_adc_config_extref_t for further configuration.*/ +} nrf_adc_config_reference_t; + +/** @brief Input selection of the analog-to-digital converter. */ +typedef enum +{ + NRF_ADC_CONFIG_INPUT_DISABLED = ADC_CONFIG_PSEL_Disabled, /**< No input selected. */ + NRF_ADC_CONFIG_INPUT_0 = ADC_CONFIG_PSEL_AnalogInput0, /**< Input 0. */ + NRF_ADC_CONFIG_INPUT_1 = ADC_CONFIG_PSEL_AnalogInput1, /**< Input 1. */ + NRF_ADC_CONFIG_INPUT_2 = ADC_CONFIG_PSEL_AnalogInput2, /**< Input 2. */ + NRF_ADC_CONFIG_INPUT_3 = ADC_CONFIG_PSEL_AnalogInput3, /**< Input 3. */ + NRF_ADC_CONFIG_INPUT_4 = ADC_CONFIG_PSEL_AnalogInput4, /**< Input 4. */ + NRF_ADC_CONFIG_INPUT_5 = ADC_CONFIG_PSEL_AnalogInput5, /**< Input 5. */ + NRF_ADC_CONFIG_INPUT_6 = ADC_CONFIG_PSEL_AnalogInput6, /**< Input 6. */ + NRF_ADC_CONFIG_INPUT_7 = ADC_CONFIG_PSEL_AnalogInput7, /**< Input 7. */ +} nrf_adc_config_input_t; + +/** @brief Analog-to-digital converter tasks. */ +typedef enum +{ + /*lint -save -e30*/ + NRF_ADC_TASK_START = offsetof(NRF_ADC_Type, TASKS_START), /**< ADC start sampling task. */ + NRF_ADC_TASK_STOP = offsetof(NRF_ADC_Type, TASKS_STOP) /**< ADC stop sampling task. */ + /*lint -restore*/ +} nrf_adc_task_t; + +/** @brief Analog-to-digital converter events. */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + /*lint -save -e30*/ + NRF_ADC_EVENT_END = offsetof(NRF_ADC_Type, EVENTS_END) /**< End of a conversion event. */ + /*lint -restore*/ +} nrf_adc_event_t; + +/**@brief Analog-to-digital converter configuration. */ +typedef struct +{ + nrf_adc_config_resolution_t resolution; /**< ADC resolution. */ + nrf_adc_config_scaling_t scaling; /**< ADC scaling factor. */ + nrf_adc_config_reference_t reference; /**< ADC reference. */ + nrf_adc_config_input_t input; /**< ADC input selection. */ + nrf_adc_config_extref_t extref; /**< ADC external reference selection. */ +} nrf_adc_config_t; + +/**@brief Analog-to-digital value type. */ +typedef uint16_t nrf_adc_value_t; + +/** + * @brief Function for activating a specific ADC task. + * + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task); + +/** + * @brief Function for getting the address of an ADC task register. + * + * @param[in] task ADC task. + * + * @return Address of the specified ADC task. + */ +__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t task); + +/** + * @brief Function for checking the state of an ADC event. + * + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event); + +/** + * @brief Function for clearing an ADC event. + * + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event); + +/** + * @brief Function for getting the address of a specific ADC event register. + * + * @param[in] adc_event ADC event. + * + * @return Address of the specified ADC event. + */ +__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event); + +/** + * @brief Function for enabling the specified interrupts. + * + * @param[in] int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask); + +/** + * @brief Function for disabling the specified interrupts. + * + * @param[in] int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask); + +/** + * @brief Function for retrieving the state of the specified ADC interrupts. + * + * @param[in] int_mask Interrupts to check. + * + * @retval true If all specified interrupts are enabled. + * @retval false If at least one of the given interrupts is not enabled. + */ +__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t int_mask); + +/** + * @brief Function for checking whether the ADC is busy. + * + * This function checks whether the ADC converter is busy with a conversion. + * + * @retval true If the ADC is busy. + * @retval false If the ADC is not busy. + */ +__STATIC_INLINE bool nrf_adc_busy_check(void); + +/** + * @brief Function for enabling the ADC. + * + */ +__STATIC_INLINE void nrf_adc_enable(void); + +/** + * @brief Function for disabling the ADC. + * + */ +__STATIC_INLINE void nrf_adc_disable(void); + +/** + * @brief Function for checking if the ADC is enabled. + * + * @retval true If the ADC is enabled. + * @retval false If the ADC is not enabled. + */ +__STATIC_INLINE bool nrf_adc_enable_check(void); + +/** + * @brief Function for retrieving the ADC conversion result. + * + * This function retrieves and returns the last analog-to-digital conversion result. + * + * @return Last conversion result. + */ +__STATIC_INLINE nrf_adc_value_t nrf_adc_result_get(void); + +/** + * @brief Function for initializing the ADC. + * + * This function writes data to ADC's CONFIG register. After the configuration, + * the ADC is in DISABLE state and must be enabled before using it. + * + * @param[in] p_config Configuration parameters. + */ +__STATIC_INLINE void nrf_adc_init(nrf_adc_config_t const * p_config); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task) +{ + return (uint32_t)((uint8_t *)NRF_ADC + (uint32_t)adc_task); +} + +__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event); +} + +__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event)) = 0x0UL; +} + +__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event) +{ + return (uint32_t)((uint8_t *)NRF_ADC + (uint32_t)adc_event); +} + +__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask) +{ + NRF_ADC->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask) +{ + NRF_ADC->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t int_mask) +{ + return (bool)(NRF_ADC->INTENSET & int_mask); +} + +__STATIC_INLINE bool nrf_adc_busy_check(void) +{ + return ((NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) == (ADC_BUSY_BUSY_Busy << ADC_BUSY_BUSY_Pos)); +} + +__STATIC_INLINE void nrf_adc_enable(void) +{ + NRF_ADC->ENABLE = (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_adc_disable(void) +{ + NRF_ADC->ENABLE = (ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE bool nrf_adc_enable_check(void) +{ + return (NRF_ADC->ENABLE == (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos)); +} + +__STATIC_INLINE nrf_adc_value_t nrf_adc_result_get(void) +{ + return (nrf_adc_value_t)NRF_ADC->RESULT; +} + +__STATIC_INLINE void nrf_adc_init(nrf_adc_config_t const * p_config) +{ + NRF_ADC->CONFIG = + ((p_config->resolution << ADC_CONFIG_RES_Pos) & ADC_CONFIG_RES_Msk) + |((p_config->scaling << ADC_CONFIG_INPSEL_Pos) & ADC_CONFIG_INPSEL_Msk) + |((p_config->reference << ADC_CONFIG_REFSEL_Pos) & ADC_CONFIG_REFSEL_Msk) + |((p_config->input << ADC_CONFIG_PSEL_Pos) & ADC_CONFIG_PSEL_Msk) + |((p_config->extref << ADC_CONFIG_EXTREFSEL_Pos) & ADC_CONFIG_EXTREFSEL_Msk); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_ADC_H_ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ccm.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ccm.h new file mode 100755 index 0000000..7546cb5 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ccm.h @@ -0,0 +1,497 @@ +/* + * Copyright (c) 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_CCM_H__ +#define NRF_CCM_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_ccm_hal AES CCM HAL + * @{ + * @ingroup nrf_ccm + * @brief Hardware access layer for managing the AES CCM peripheral. + */ + +/** + * @brief CCM tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_CCM_TASK_KSGEN = offsetof(NRF_CCM_Type, TASKS_KSGEN), ///< Start generation of key-stream. + NRF_CCM_TASK_CRYPT = offsetof(NRF_CCM_Type, TASKS_CRYPT), ///< Start encryption/decryption. + NRF_CCM_TASK_STOP = offsetof(NRF_CCM_Type, TASKS_STOP), ///< Stop encryption/decryption. +#if defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) || defined(__NRFX_DOXYGEN__) + NRF_CCM_TASK_RATEOVERRIDE = offsetof(NRF_CCM_Type, TASKS_RATEOVERRIDE), ///< Override DATARATE setting in MODE register. +#endif + /*lint -restore*/ +} nrf_ccm_task_t; + +/** + * @brief CCM events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_CCM_EVENT_ENDKSGEN = offsetof(NRF_CCM_Type, EVENTS_ENDKSGEN), ///< Keystream generation complete. + NRF_CCM_EVENT_ENDCRYPT = offsetof(NRF_CCM_Type, EVENTS_ENDCRYPT), ///< Encrypt/decrypt complete. + NRF_CCM_EVENT_ERROR = offsetof(NRF_CCM_Type, EVENTS_ERROR), ///< CCM error event. + /*lint -restore*/ +} nrf_ccm_event_t; + +/** + * @brief CCM interrupts. + */ +typedef enum +{ + NRF_CCM_INT_ENDKSGEN_MASK = CCM_INTENSET_ENDKSGEN_Msk, ///< Interrupt on ENDKSGEN event. + NRF_CCM_INT_ENDCRYPT_MASK = CCM_INTENSET_ENDCRYPT_Msk, ///< Interrupt on ENDCRYPT event. + NRF_CCM_INT_ERROR_MASK = CCM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. +} nrf_ccm_int_mask_t; + +/** + * @brief CCM modes of operation. + */ +typedef enum +{ + NRF_CCM_MODE_ENCRYPTION = CCM_MODE_MODE_Encryption, ///< Encryption mode. + NRF_CCM_MODE_DECRYPTION = CCM_MODE_MODE_Decryption, ///< Decryption mode. +} nrf_ccm_mode_t; + +#if defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__) +/** + * @brief CCM data rates. + */ +typedef enum +{ + NRF_CCM_DATARATE_1M = CCM_MODE_DATARATE_1Mbit, ///< 1 Mbps. + NRF_CCM_DATARATE_2M = CCM_MODE_DATARATE_2Mbit, ///< 2 Mbps. +#if defined(CCM_MODE_DATARATE_125Kbps) || defined(__NRFX_DOXYGEN__) + NRF_CCM_DATARATE_125K = CCM_MODE_DATARATE_125Kbps, ///< 125 Kbps. +#endif +#if defined(CCM_MODE_DATARATE_500Kbps) || defined(__NRFX_DOXYGEN__) + NRF_CCM_DATARATE_500K = CCM_MODE_DATARATE_500Kbps, ///< 500 Kbps. +#endif +} nrf_ccm_datarate_t; +#endif // defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__) + +#if defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__) +/** + * @brief CCM packet length options. + */ +typedef enum +{ + NRF_CCM_LENGTH_DEFAULT = CCM_MODE_LENGTH_Default, ///< Default length. + NRF_CCM_LENGTH_EXTENDED = CCM_MODE_LENGTH_Extended, ///< Extended length. +} nrf_ccm_length_t; +#endif // defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__) + +/** + * @brief CCM configuration. + */ +typedef struct { + nrf_ccm_mode_t mode; +#if defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__) + nrf_ccm_datarate_t datarate; +#endif +#if defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__) + nrf_ccm_length_t length; +#endif +} nrf_ccm_config_t; + +/** + * @brief Function for activating a specific CCM task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_ccm_task_trigger(NRF_CCM_Type * p_reg, + nrf_ccm_task_t task); + +/** + * @brief Function for getting the address of a specific CCM task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_ccm_task_address_get(NRF_CCM_Type const * p_reg, + nrf_ccm_task_t task); + +/** + * @brief Function for clearing a specific CCM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_ccm_event_clear(NRF_CCM_Type * p_reg, + nrf_ccm_event_t event); + +/** + * @brief Function for checking the state of a specific CCM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg, + nrf_ccm_event_t event); + +/** + * @brief Function for getting the address of a specific CCM event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg, + nrf_ccm_event_t event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] ccm_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_ccm_int_enable_check(NRF_CCM_Type const * p_reg, + nrf_ccm_int_mask_t ccm_int); + +/** + * @brief Function for enabling the CCM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_ccm_enable(NRF_CCM_Type * p_reg); + +/** + * @brief Function for disabling the CCM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_ccm_disable(NRF_CCM_Type * p_reg); + +/** + * @brief Function for setting the CCM peripheral configuration. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_config Pointer to the structure with configuration to be set. + */ +__STATIC_INLINE void nrf_ccm_configure(NRF_CCM_Type * p_reg, + nrf_ccm_config_t const * p_config); + +#if defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the length of key-stream generated + * when the packet length is configured as extended. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] size Maximum length of the key-stream. + */ +__STATIC_INLINE void nrf_ccm_maxpacketsize_set(NRF_CCM_Type * p_reg, + uint8_t size); +#endif // defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for getting the MIC check result. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @retval true If the MIC check passed. + * @retval false If the MIC check failed. + */ +__STATIC_INLINE bool nrf_ccm_micstatus_get(NRF_CCM_Type const * p_reg); + +/** + * @brief Function for setting the pointer to the data structure + * holding the AES key and the CCM NONCE vector. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_data Pointer to the data structure. + */ +__STATIC_INLINE void nrf_ccm_cnfptr_set(NRF_CCM_Type * p_reg, + uint32_t const * p_data); + +/** + * @brief Function for getting the pointer to the data structure + * holding the AES key and the CCM NONCE vector. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Pointer to the data structure. + */ +__STATIC_INLINE uint32_t * nrf_ccm_cnfptr_get(NRF_CCM_Type const * p_reg); + +/** + * @brief Function for setting the input data pointer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_data Input data pointer. + */ +__STATIC_INLINE void nrf_ccm_inptr_set(NRF_CCM_Type * p_reg, + uint32_t const * p_data); + +/** + * @brief Function for getting the input data pointer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Input data pointer. + */ +__STATIC_INLINE uint32_t * nrf_ccm_inptr_get(NRF_CCM_Type const * p_reg); + +/** + * @brief Function for setting the output data pointer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_data Output data pointer. + */ +__STATIC_INLINE void nrf_ccm_outptr_set(NRF_CCM_Type * p_reg, + uint32_t const * p_data); + +/** + * @brief Function for getting the output data pointer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Output data pointer. + */ +__STATIC_INLINE uint32_t * nrf_ccm_outptr_get(NRF_CCM_Type const * p_reg); + +/** + * @brief Function for setting the pointer to the scratch area used for + * temporary storage. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_area Pointer to the scratch area. + */ +__STATIC_INLINE void nrf_ccm_scratchptr_set(NRF_CCM_Type * p_reg, + uint32_t const * p_area); + +/** + * @brief Function for getting the pointer to the scratch area. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Pointer to the scratch area. + */ +__STATIC_INLINE uint32_t * nrf_ccm_stratchptr_get(NRF_CCM_Type const * p_reg); + +#if defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting the data rate override value. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] datarate Override value to be applied when the RATEOVERRIDE task + * is triggered. + */ +__STATIC_INLINE void nrf_ccm_datarate_override_set(NRF_CCM_Type * p_reg, + nrf_ccm_datarate_t datarate); +#endif // defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) || defined(__NRFX_DOXYGEN__) + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_ccm_task_trigger(NRF_CCM_Type * p_reg, + nrf_ccm_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_ccm_task_address_get(NRF_CCM_Type const * p_reg, + nrf_ccm_task_t task) +{ + return ((uint32_t)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_ccm_event_clear(NRF_CCM_Type * p_reg, + nrf_ccm_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg, + nrf_ccm_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg, + nrf_ccm_event_t event) +{ + return ((uint32_t)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask) +{ + p_reg->INTENSET = mask; +} + +__STATIC_INLINE void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask) +{ + p_reg->INTENCLR = mask; +} + +__STATIC_INLINE bool nrf_ccm_int_enable_check(NRF_CCM_Type const * p_reg, + nrf_ccm_int_mask_t ccm_int) +{ + return (bool)(p_reg->INTENSET & ccm_int); +} + +__STATIC_INLINE void nrf_ccm_enable(NRF_CCM_Type * p_reg) +{ + p_reg->ENABLE = (CCM_ENABLE_ENABLE_Enabled << CCM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_ccm_disable(NRF_CCM_Type * p_reg) +{ + p_reg->ENABLE = (CCM_ENABLE_ENABLE_Disabled << CCM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_ccm_configure(NRF_CCM_Type * p_reg, + nrf_ccm_config_t const * p_config) +{ + p_reg->MODE = (((uint32_t)p_config->mode << CCM_MODE_MODE_Pos) | +#if defined(CCM_MODE_DATARATE_Pos) + ((uint32_t)p_config->datarate << CCM_MODE_DATARATE_Pos) | +#endif +#if defined(CCM_MODE_LENGTH_Pos) + ((uint32_t)p_config->length << CCM_MODE_LENGTH_Pos) | +#endif + 0); +} + +#if defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) +__STATIC_INLINE void nrf_ccm_maxpacketsize_set(NRF_CCM_Type * p_reg, + uint8_t size) +{ + NRFX_ASSERT((size >= 0x1B) && (size <= 0xFB)); + + p_reg->MAXPACKETSIZE = size; +} +#endif // defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) + +__STATIC_INLINE bool nrf_ccm_micstatus_get(NRF_CCM_Type const * p_reg) +{ + return (bool)(p_reg->MICSTATUS); +} + +__STATIC_INLINE void nrf_ccm_cnfptr_set(NRF_CCM_Type * p_reg, + uint32_t const * p_data) +{ + p_reg->CNFPTR = (uint32_t)p_data; +} + +__STATIC_INLINE uint32_t * nrf_ccm_cnfptr_get(NRF_CCM_Type const * p_reg) +{ + return (uint32_t *)(p_reg->CNFPTR); +} + +__STATIC_INLINE void nrf_ccm_inptr_set(NRF_CCM_Type * p_reg, + uint32_t const * p_data) +{ + p_reg->INPTR = (uint32_t)p_data; +} + +__STATIC_INLINE uint32_t * nrf_ccm_inptr_get(NRF_CCM_Type const * p_reg) +{ + return (uint32_t *)(p_reg->INPTR); +} + +__STATIC_INLINE void nrf_ccm_outptr_set(NRF_CCM_Type * p_reg, + uint32_t const * p_data) +{ + p_reg->OUTPTR = (uint32_t)p_data; +} + +__STATIC_INLINE uint32_t * nrf_ccm_outptr_get(NRF_CCM_Type const * p_reg) +{ + return (uint32_t *)(p_reg->OUTPTR); +} + +__STATIC_INLINE void nrf_ccm_scratchptr_set(NRF_CCM_Type * p_reg, + uint32_t const * p_area) +{ + p_reg->SCRATCHPTR = (uint32_t)p_area; +} + +__STATIC_INLINE uint32_t * nrf_ccm_stratchptr_get(NRF_CCM_Type const * p_reg) +{ + return (uint32_t *)(p_reg->SCRATCHPTR); +} + +#if defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) +__STATIC_INLINE void nrf_ccm_datarate_override_set(NRF_CCM_Type * p_reg, + nrf_ccm_datarate_t datarate) +{ + p_reg->RATEOVERRIDE = ((uint32_t)datarate << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos); +} +#endif + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_CCM_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_clock.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_clock.h new file mode 100755 index 0000000..33455e8 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_clock.h @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_CLOCK_H__ +#define NRF_CLOCK_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_clock_hal Clock HAL + * @{ + * @ingroup nrf_clock + * @brief Hardware access layer for managing the CLOCK peripheral. + * + * This code can be used to managing low-frequency clock (LFCLK) and the high-frequency clock + * (HFCLK) settings. + */ + +#define NRF_CLOCK_TASK_TRIGGER (1UL) +#define NRF_CLOCK_EVENT_CLEAR (0UL) + +#if defined(NRF52810_XXAA) || \ + defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ + defined(NRF52840_XXAA) +// Enable support for external LFCLK sources. Read more in the Product Specification. +#define NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES +#endif + +/** + * @brief Low-frequency clock sources. + * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers. + */ +typedef enum +{ + NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */ + NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */ + NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth, /**< Internal 32 kHz synthesizer from HFCLK system clock. */ +#if defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__) + /** + * External 32 kHz low swing signal. Used only with the LFCLKSRC register. + * For the others @ref NRF_CLOCK_LFCLK_Xtal is returned for this setting. + */ + NRF_CLOCK_LFCLK_Xtal_Low_Swing = (CLOCK_LFCLKSRC_SRC_Xtal | + (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)), + /** + * External 32 kHz full swing signal. Used only with the LFCLKSRC register. + * For the others @ref NRF_CLOCK_LFCLK_Xtal is returned for this setting. + */ + NRF_CLOCK_LFCLK_Xtal_Full_Swing = (CLOCK_LFCLKSRC_SRC_Xtal | + (CLOCK_LFCLKSRC_BYPASS_Enabled << CLOCK_LFCLKSRC_BYPASS_Pos) | + (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)), +#endif // defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__) +} nrf_clock_lfclk_t; + +/** + * @brief High-frequency clock sources. + */ +typedef enum +{ + NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */ + NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */ +} nrf_clock_hfclk_t; + +/** + * @brief Trigger status of task LFCLKSTART/HFCLKSTART. + * @details Used by LFCLKRUN and HFCLKRUN registers. + */ +typedef enum +{ + NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */ + NRF_CLOCK_START_TASK_TRIGGERED = CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */ +} nrf_clock_start_task_status_t; + +/** + * @brief Interrupts. + */ +typedef enum +{ + NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */ + NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */ + NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */ + NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk /**< Interrupt on CTTO event. */ +} nrf_clock_int_mask_t; + +/** + * @brief Tasks. + * + * @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running. + * The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/ + NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source.*/ + NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/ + NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source.*/ + NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator.*/ + NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer.*/ + NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer.*/ +} nrf_clock_task_t; /*lint -restore */ + +/** + * @brief Events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/ + NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/ + NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed.*/ + NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO) /**< Calibration timer time-out.*/ +} nrf_clock_event_t; /*lint -restore */ + +/** + * @brief Function for enabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask); + +/** + * @brief Function for disabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a specific interrupt. + * + * @param[in] int_mask Interrupt. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask); + +/** + * @brief Function for retrieving the address of a specific task. + * @details This function can be used by the PPI module. + * + * @param[in] task Task. + * + * @return Address of the requested task register. + */ +__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task); + +/** + * @brief Function for setting a specific task. + * + * @param[in] task Task. + */ +__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task); + +/** + * @brief Function for retrieving the address of a specific event. + * @details This function can be used by the PPI module. + * + * @param[in] event Event. + * + * @return Address of the requested event register. + */ +__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event); + +/** + * @brief Function for clearing a specific event. + * + * @param[in] event Event. + */ +__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event); + +/** + * @brief Function for retrieving the state of a specific event. + * + * @param[in] event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event); + +/** + * @brief Function for changing the low-frequency clock source. + * @details This function cannot be called when the low-frequency clock is running. + * + * @param[in] source New low-frequency clock source. + * + */ +__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source); + +/** + * @brief Function for retrieving the selected source for the low-frequency clock. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the selected source for the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the selected source for the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the selected source for the low-frequency clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void); + +/** + * @brief Function for retrieving the active source of the low-frequency clock. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the active source of the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the active source of the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the active source of the low-frequency clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void); + +/** + * @brief Function for retrieving the clock source for the LFCLK clock when the task LKCLKSTART is triggered. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is running and generating the LFCLK clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is running and generating the LFCLK clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is running and generating the LFCLK clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void); + +/** + * @brief Function for retrieving the state of the LFCLK clock. + * + * @retval false If the LFCLK clock is not running. + * @retval true If the LFCLK clock is running. + */ +__STATIC_INLINE bool nrf_clock_lf_is_running(void); + +/** + * @brief Function for retrieving the trigger status of the task LFCLKSTART. + * + * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task LFCLKSTART has not been triggered. + * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task LFCLKSTART has been triggered. + */ +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void); + +/** + * @brief Function for retrieving the active source of the high-frequency clock. + * + * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY If the internal 16 MHz RC oscillator is the active source of the high-frequency clock. + * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY If an external 16 MHz/32 MHz crystal oscillator is the active source of the high-frequency clock. + */ +__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void); + +/** + * @brief Function for retrieving the state of the HFCLK clock. + * + * @param[in] clk_src Clock source to be checked. + * + * @retval false If the HFCLK clock is not running. + * @retval true If the HFCLK clock is running. + */ +__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src); + +/** + * @brief Function for retrieving the trigger status of the task HFCLKSTART. + * + * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task HFCLKSTART has not been triggered. + * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task HFCLKSTART has been triggered. + */ +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void); + +/** + * @brief Function for changing the calibration timer interval. + * + * @param[in] interval New calibration timer interval in 0.25 s resolution (range: 0.25 seconds to 31.75 seconds). + */ +__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask) +{ + NRF_CLOCK->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask) +{ + NRF_CLOCK->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask) +{ + return (bool)(NRF_CLOCK->INTENCLR & int_mask); +} + +__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task) +{ + return ((uint32_t )NRF_CLOCK + task); +} + +__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER; +} + +__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event) +{ + return ((uint32_t)NRF_CLOCK + event); +} + +__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event) +{ + return (bool)*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)); +} + +__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source) +{ + NRF_CLOCK->LFCLKSRC = (uint32_t)(source); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void) +{ + return (nrf_clock_lfclk_t)(NRF_CLOCK->LFCLKSRC); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void) +{ + return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSTAT & + CLOCK_LFCLKSTAT_SRC_Msk) >> CLOCK_LFCLKSTAT_SRC_Pos); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void) +{ + return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRCCOPY & + CLOCK_LFCLKSRCCOPY_SRC_Msk) >> CLOCK_LFCLKSRCCOPY_SRC_Pos); +} + +__STATIC_INLINE bool nrf_clock_lf_is_running(void) +{ + return ((NRF_CLOCK->LFCLKSTAT & + CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos); +} + +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void) +{ + return (nrf_clock_start_task_status_t)((NRF_CLOCK->LFCLKRUN & + CLOCK_LFCLKRUN_STATUS_Msk) >> + CLOCK_LFCLKRUN_STATUS_Pos); +} + +__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void) +{ + return (nrf_clock_hfclk_t)((NRF_CLOCK->HFCLKSTAT & + CLOCK_HFCLKSTAT_SRC_Msk) >> CLOCK_HFCLKSTAT_SRC_Pos); +} + +__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src) +{ + return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) == + (CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos)); +} + +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void) +{ + return (nrf_clock_start_task_status_t)((NRF_CLOCK->HFCLKRUN & + CLOCK_HFCLKRUN_STATUS_Msk) >> + CLOCK_HFCLKRUN_STATUS_Pos); +} + +__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval) +{ + NRF_CLOCK->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_CLOCK_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_comp.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_comp.h new file mode 100755 index 0000000..7663491 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_comp.h @@ -0,0 +1,500 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_COMP_H_ +#define NRF_COMP_H_ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_comp_hal COMP HAL + * @{ + * @ingroup nrf_comp + * @brief Hardware access layer for managing the Comparator (COMP) peripheral. + */ + +/** + * @enum nrf_comp_input_t + * @brief COMP analog pin selection. + */ +typedef enum +{ + NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */ + NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */ + NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */ + NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */ + NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */ + NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */ + NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */ +#if defined (COMP_PSEL_PSEL_AnalogInput7) || defined (__NRFX_DOXYGEN__) + NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */ +#endif +#if defined (COMP_PSEL_PSEL_VddDiv2) || defined (__NRFX_DOXYGEN__) + NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */ +#endif +}nrf_comp_input_t; + +/** + * @enum nrf_comp_ref_t + * @brief COMP reference selection. + */ +typedef enum +{ + NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2, /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */ + NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8, /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */ + NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4, /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */ + NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD, /*!< VREF = VDD. */ + NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */ +}nrf_comp_ref_t; + +/** + * @enum nrf_comp_ext_ref_t + * @brief COMP external analog reference selection. + */ +typedef enum +{ + NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0, /*!< Use AIN0 as external analog reference. */ + NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 /*!< Use AIN1 as external analog reference. */ +}nrf_comp_ext_ref_t; + +/** + * @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP. + */ +typedef struct +{ + uint8_t th_down; /*!< THDOWN value. */ + uint8_t th_up; /*!< THUP value. */ +}nrf_comp_th_t; + +/** + * @enum nrf_comp_main_mode_t + * @brief COMP main operation mode. + */ +typedef enum +{ + NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE, /*!< Single ended mode. */ + NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff /*!< Differential mode. */ +}nrf_comp_main_mode_t; + +/** + * @enum nrf_comp_sp_mode_t + * @brief COMP speed and power mode. + */ +typedef enum +{ + NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low, /*!< Low power mode. */ + NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal, /*!< Normal mode. */ + NRF_COMP_SP_MODE_High = COMP_MODE_SP_High /*!< High speed mode. */ +}nrf_comp_sp_mode_t; + +/** + * @enum nrf_comp_hyst_t + * @brief COMP comparator hysteresis. + */ +typedef enum +{ + NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst, /*!< Comparator hysteresis disabled. */ + NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */ +}nrf_comp_hyst_t; + +#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__) +/** + * @brief COMP current source selection on analog input. + */ +typedef enum +{ + NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off, /*!< Current source disabled. */ + NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5, /*!< Current source enabled (+/- 2.5 uA). */ + NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */ + NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */ +}nrf_isource_t; +#endif + +/** + * @enum nrf_comp_task_t + * @brief COMP tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_COMP_TASK_START = offsetof(NRF_COMP_Type, TASKS_START), /*!< COMP start sampling task. */ + NRF_COMP_TASK_STOP = offsetof(NRF_COMP_Type, TASKS_STOP), /*!< COMP stop sampling task. */ + NRF_COMP_TASK_SAMPLE = offsetof(NRF_COMP_Type, TASKS_SAMPLE) /*!< Sample comparator value. */ + /*lint -restore*/ +}nrf_comp_task_t; + +/** + * @enum nrf_comp_event_t + * @brief COMP events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_COMP_EVENT_READY = offsetof(NRF_COMP_Type, EVENTS_READY), /*!< COMP is ready and output is valid. */ + NRF_COMP_EVENT_DOWN = offsetof(NRF_COMP_Type, EVENTS_DOWN), /*!< Input voltage crossed the threshold going down. */ + NRF_COMP_EVENT_UP = offsetof(NRF_COMP_Type, EVENTS_UP), /*!< Input voltage crossed the threshold going up. */ + NRF_COMP_EVENT_CROSS = offsetof(NRF_COMP_Type, EVENTS_CROSS) /*!< Input voltage crossed the threshold in any direction. */ + /*lint -restore*/ +}nrf_comp_event_t; + +/** + * @brief COMP reference configuration. + */ +typedef struct +{ + nrf_comp_ref_t reference; /*!< COMP reference selection. */ + nrf_comp_ext_ref_t external; /*!< COMP external analog reference selection. */ +}nrf_comp_ref_conf_t; + + +/** + * @brief Function for enabling the COMP peripheral. + */ +__STATIC_INLINE void nrf_comp_enable(void); + + +/** + * @brief Function for disabling the COMP peripheral. + */ + +__STATIC_INLINE void nrf_comp_disable(void); + +/** + * @brief Function for checking if the COMP peripheral is enabled. + * + * @retval true If the COMP peripheral is enabled. + * @retval false If the COMP peripheral is not enabled. + */ +__STATIC_INLINE bool nrf_comp_enable_check(void); + +/** + * @brief Function for setting the reference source. + * + * @param[in] reference COMP reference selection. + */ +__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference); + + +/** + * @brief Function for setting the external analog reference source. + * + * @param[in] ext_ref COMP external analog reference selection. + */ +__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref); + + +/** + * @brief Function for setting threshold voltages. + * + * @param[in] threshold COMP VDOWN and VUP thresholds. + */ +__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold); + + +/** + * @brief Function for setting the main mode. + * + * @param[in] main_mode COMP main operation mode. + */ +__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode); + + +/** + * @brief Function for setting the speed mode. + * + * @param[in] speed_mode COMP speed and power mode. + */ +__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode); + + +/** + * @brief Function for setting the hysteresis. + * + * @param[in] hyst COMP comparator hysteresis. + */ +__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst); + + +#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__) +/** + * @brief Function for setting the current source on the analog input. + * + * @param[in] isource COMP current source selection on analog input. + */ +__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource); +#endif + + +/** + * @brief Function for selecting the active input of the COMP. + * + * @param[in] input Input to be selected. + */ +__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input); + + +/** + * @brief Function for getting the last COMP compare result. + * + * @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-. + * + * @note If VIN+ == VIN-, the return value depends on the previous result. + */ +__STATIC_INLINE uint32_t nrf_comp_result_get(void); + + +/** + * @brief Function for enabling interrupts from COMP. + * + * @param[in] comp_int_mask Mask of interrupts to be enabled. + * + * @sa nrf_comp_int_enable_check() + */ +__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask); + +/** + * @brief Function for disabling interrupts from COMP. + * + * @param[in] comp_int_mask Mask of interrupts to be disabled. + * + * @sa nrf_comp_int_enable_check() + */ +__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask); + + +/** + * @brief Function for getting the enabled interrupts of COMP. + * + * @param[in] comp_int_mask Mask of interrupts to be checked. + * + * @retval true If any interrupts of the specified mask are enabled. + */ +__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask); + + + +/** + * @brief Function for getting the address of a specific COMP task register. + * + * @param[in] comp_task COMP task. + * + * @return Address of the specified COMP task. + */ +__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task); + + +/** + * @brief Function for getting the address of a specific COMP event register. + * + * @param[in] comp_event COMP event. + * + * @return Address of the specified COMP event. + */ +__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event); + + +/** + * @brief Function for setting COMP shorts. + * + * @param[in] comp_short_mask COMP shorts by mask. + * + */ +__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask); + + +/** + * @brief Function for clearing COMP shorts by mask. + * + * @param[in] comp_short_mask COMP shorts to be cleared. + * + */ +__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask); + + +/** + * @brief Function for setting a specific COMP task. + * + * @param[in] comp_task COMP task to be set. + * + */ +__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task); + + +/** + * @brief Function for clearing a specific COMP event. + * + * @param[in] comp_event COMP event to be cleared. + * + */ +__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event); + + +/** + * @brief Function for getting the state of a specific COMP event. + * + * @retval true If the specified COMP event is active. + * + */ +__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_comp_enable(void) +{ + NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Enabled << COMP_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_comp_disable(void) +{ + NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE bool nrf_comp_enable_check(void) +{ + return ((NRF_COMP->ENABLE) & COMP_ENABLE_ENABLE_Enabled); +} + +__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference) +{ + NRF_COMP->REFSEL = (reference << COMP_REFSEL_REFSEL_Pos); +} + +__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref) +{ + NRF_COMP->EXTREFSEL = (ext_ref << COMP_EXTREFSEL_EXTREFSEL_Pos); +} + +__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold) +{ + NRF_COMP->TH = + ((threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) | + ((threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk); +} + +__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode) +{ + NRF_COMP->MODE |= (main_mode << COMP_MODE_MAIN_Pos); +} + +__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode) +{ + NRF_COMP->MODE |= (speed_mode << COMP_MODE_SP_Pos); +} + +__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst) +{ + NRF_COMP->HYST = (hyst << COMP_HYST_HYST_Pos) & COMP_HYST_HYST_Msk; +} + +#if defined (COMP_ISOURCE_ISOURCE_Msk) +__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource) +{ + NRF_COMP->ISOURCE = (isource << COMP_ISOURCE_ISOURCE_Pos) & COMP_ISOURCE_ISOURCE_Msk; +} +#endif + +__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input) +{ + NRF_COMP->PSEL = ((uint32_t)input << COMP_PSEL_PSEL_Pos); +} + +__STATIC_INLINE uint32_t nrf_comp_result_get(void) +{ + return (uint32_t)NRF_COMP->RESULT; +} + +__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask) +{ + NRF_COMP->INTENSET = comp_int_mask; +} + +__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask) +{ + NRF_COMP->INTENCLR = comp_int_mask; +} + +__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask) +{ + return (NRF_COMP->INTENSET & comp_int_mask); // when read this register will return the value of INTEN. +} + +__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task) +{ + return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_task); +} + +__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event) +{ + return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event); +} + +__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask) +{ + NRF_COMP->SHORTS |= comp_short_mask; +} + +__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask) +{ + NRF_COMP->SHORTS &= ~comp_short_mask; +} + +__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_task) ) = 1; +} + +__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)comp_event) ) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event) +{ + return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_event)); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_COMP_H_ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ecb.c b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ecb.c new file mode 100755 index 0000000..b83935e --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ecb.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +//lint -e438 + +#include <nrfx.h> +#include "nrf_ecb.h" +#include <string.h> + +static uint8_t ecb_data[48]; ///< ECB data structure for RNG peripheral to access. +static uint8_t* ecb_key; ///< Key: Starts at ecb_data +static uint8_t* ecb_cleartext; ///< Cleartext: Starts at ecb_data + 16 bytes. +static uint8_t* ecb_ciphertext; ///< Ciphertext: Starts at ecb_data + 32 bytes. + +bool nrf_ecb_init(void) +{ + ecb_key = ecb_data; + ecb_cleartext = ecb_data + 16; + ecb_ciphertext = ecb_data + 32; + + NRF_ECB->ECBDATAPTR = (uint32_t)ecb_data; + return true; +} + + +bool nrf_ecb_crypt(uint8_t * dest_buf, const uint8_t * src_buf) +{ + uint32_t counter = 0x1000000; + if (src_buf != ecb_cleartext) + { + memcpy(ecb_cleartext,src_buf,16); + } + NRF_ECB->EVENTS_ENDECB = 0; + NRF_ECB->TASKS_STARTECB = 1; + while (NRF_ECB->EVENTS_ENDECB == 0) + { + counter--; + if (counter == 0) + { + return false; + } + } + NRF_ECB->EVENTS_ENDECB = 0; + if (dest_buf != ecb_ciphertext) + { + memcpy(dest_buf,ecb_ciphertext,16); + } + return true; +} + +void nrf_ecb_set_key(const uint8_t * key) +{ + memcpy(ecb_key,key,16); +} + + diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ecb.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ecb.h new file mode 100755 index 0000000..25e7200 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ecb.h @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_ECB_H__ +#define NRF_ECB_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_ecb_drv AES ECB encryption driver + * @{ + * @ingroup nrf_ecb + * @brief Driver for the AES Electronic Code Book (ECB) peripheral. + * + * To encrypt data, the peripheral must first be powered on + * using @ref nrf_ecb_init. Next, the key must be set using @ref nrf_ecb_set_key. + */ + +/** + * @brief Function for initializing and powering on the ECB peripheral. + * + * This function allocates memory for the ECBDATAPTR. + * @retval true If initialization was successful. + * @retval false If powering on failed. + */ +bool nrf_ecb_init(void); + +/** + * @brief Function for encrypting 16-byte data using current key. + * + * This function avoids unnecessary copying of data if the parameters point to the + * correct locations in the ECB data structure. + * + * @param dst Result of encryption, 16 bytes will be written. + * @param src Source with 16-byte data to be encrypted. + * + * @retval true If the encryption operation completed. + * @retval false If the encryption operation did not complete. + */ +bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src); + +/** + * @brief Function for setting the key to be used for encryption. + * + * @param key Pointer to the key. 16 bytes will be read. + */ +void nrf_ecb_set_key(const uint8_t * key); + +/** @} */ + +/** + * @defgroup nrf_ecb_hal AES ECB encryption HAL + * @{ + * @ingroup nrf_ecb + * @brief Hardware access layer for managing the AES Electronic Codebook (ECB) peripheral. + */ + +/** + * @brief ECB tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_ECB_TASK_STARTECB = offsetof(NRF_ECB_Type, TASKS_STARTECB), /**< Task for starting ECB block encryption. */ + NRF_ECB_TASK_STOPECB = offsetof(NRF_ECB_Type, TASKS_STOPECB), /**< Task for stopping ECB block encryption. */ + /*lint -restore*/ +} nrf_ecb_task_t; + +/** + * @brief ECB events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_ECB_EVENT_ENDECB = offsetof(NRF_ECB_Type, EVENTS_ENDECB), /**< ECB block encrypt complete. */ + NRF_ECB_EVENT_ERRORECB = offsetof(NRF_ECB_Type, EVENTS_ERRORECB), /**< ECB block encrypt aborted because of a STOPECB task or due to an error. */ + /*lint -restore*/ +} nrf_ecb_event_t; + +/** + * @brief ECB interrupts. + */ +typedef enum +{ + NRF_ECB_INT_ENDECB_MASK = ECB_INTENSET_ENDECB_Msk, ///< Interrupt on ENDECB event. + NRF_ECB_INT_ERRORECB_MASK = ECB_INTENSET_ERRORECB_Msk, ///< Interrupt on ERRORECB event. +} nrf_ecb_int_mask_t; + + +/** + * @brief Function for activating a specific ECB task. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_ecb_task_trigger(NRF_ECB_Type * p_reg, nrf_ecb_task_t task); + +/** + * @brief Function for getting the address of a specific ECB task register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_ecb_task_address_get(NRF_ECB_Type const * p_reg, + nrf_ecb_task_t task); + +/** + * @brief Function for clearing a specific ECB event. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_ecb_event_clear(NRF_ECB_Type * p_reg, nrf_ecb_event_t event); + +/** + * @brief Function for checking the state of a specific ECB event. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_ecb_event_check(NRF_ECB_Type const * p_reg, nrf_ecb_event_t event); + +/** + * @brief Function for getting the address of a specific ECB event register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_ecb_event_address_get(NRF_ECB_Type const * p_reg, + nrf_ecb_event_t event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] ecb_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_ecb_int_enable_check(NRF_ECB_Type const * p_reg, + nrf_ecb_int_mask_t ecb_int); + +/** + * @brief Function for setting the pointer to the ECB data buffer. + * + * @note The buffer has to be placed in the Data RAM region. + * For description of the data structure in this buffer, see the Product Specification. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_buffer Pointer to the ECB data buffer. + */ +__STATIC_INLINE void nrf_ecb_data_pointer_set(NRF_ECB_Type * p_reg, void const * p_buffer); + +/** + * @brief Function for getting the pointer to the ECB data buffer. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * + * @return Pointer to the ECB data buffer. + */ +__STATIC_INLINE void * nrf_ecb_data_pointer_get(NRF_ECB_Type const * p_reg); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_ecb_task_trigger(NRF_ECB_Type * p_reg, nrf_ecb_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_ecb_task_address_get(NRF_ECB_Type const * p_reg, + nrf_ecb_task_t task) +{ + return ((uint32_t)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_ecb_event_clear(NRF_ECB_Type * p_reg, nrf_ecb_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_ecb_event_check(NRF_ECB_Type const * p_reg, nrf_ecb_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_ecb_event_address_get(NRF_ECB_Type const * p_reg, + nrf_ecb_event_t event) +{ + return ((uint32_t)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask) +{ + p_reg->INTENSET = mask; +} + +__STATIC_INLINE void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask) +{ + p_reg->INTENCLR = mask; +} + +__STATIC_INLINE bool nrf_ecb_int_enable_check(NRF_ECB_Type const * p_reg, + nrf_ecb_int_mask_t ecb_int) +{ + return (bool)(p_reg->INTENSET & ecb_int); +} + +__STATIC_INLINE void nrf_ecb_data_pointer_set(NRF_ECB_Type * p_reg, void const * p_buffer) +{ + p_reg->ECBDATAPTR = (uint32_t)p_buffer; +} + +__STATIC_INLINE void * nrf_ecb_data_pointer_get(NRF_ECB_Type const * p_reg) +{ + return (void *)(p_reg->ECBDATAPTR); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_ECB_H__ + diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_egu.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_egu.h new file mode 100755 index 0000000..5ff23ff --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_egu.h @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_EGU_H__ +#define NRF_EGU_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @defgroup nrf_egu_hal EGU HAL +* @{ +* @ingroup nrf_swi_egu +* @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral. +*/ + +/** + * @enum nrf_egu_task_t + * @brief EGU tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_EGU_TASK_TRIGGER0 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]), /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */ + NRF_EGU_TASK_TRIGGER1 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]), /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */ + NRF_EGU_TASK_TRIGGER2 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]), /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */ + NRF_EGU_TASK_TRIGGER3 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]), /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */ + NRF_EGU_TASK_TRIGGER4 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]), /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */ + NRF_EGU_TASK_TRIGGER5 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]), /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */ + NRF_EGU_TASK_TRIGGER6 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]), /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */ + NRF_EGU_TASK_TRIGGER7 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]), /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */ + NRF_EGU_TASK_TRIGGER8 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]), /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */ + NRF_EGU_TASK_TRIGGER9 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]), /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */ + NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */ + NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */ + NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */ + NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */ + NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */ + NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15]) /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */ + /*lint -restore*/ +} nrf_egu_task_t; + + +/** + * @enum nrf_egu_event_t + * @brief EGU events. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_EGU_EVENT_TRIGGERED0 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]), /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */ + NRF_EGU_EVENT_TRIGGERED1 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]), /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */ + NRF_EGU_EVENT_TRIGGERED2 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]), /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */ + NRF_EGU_EVENT_TRIGGERED3 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]), /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */ + NRF_EGU_EVENT_TRIGGERED4 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]), /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */ + NRF_EGU_EVENT_TRIGGERED5 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]), /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */ + NRF_EGU_EVENT_TRIGGERED6 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]), /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */ + NRF_EGU_EVENT_TRIGGERED7 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]), /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */ + NRF_EGU_EVENT_TRIGGERED8 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]), /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */ + NRF_EGU_EVENT_TRIGGERED9 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]), /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */ + NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */ + NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */ + NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */ + NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */ + NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */ + NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15]) /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */ + /*lint -restore*/ +} nrf_egu_event_t; + + +/** + * @enum nrf_egu_int_mask_t + * @brief EGU interrupts. + */ +typedef enum +{ + NRF_EGU_INT_TRIGGERED0 = EGU_INTENSET_TRIGGERED0_Msk, /**< Interrupt on EVENTS_TRIGGERED[0] event. */ + NRF_EGU_INT_TRIGGERED1 = EGU_INTENSET_TRIGGERED1_Msk, /**< Interrupt on EVENTS_TRIGGERED[1] event. */ + NRF_EGU_INT_TRIGGERED2 = EGU_INTENSET_TRIGGERED2_Msk, /**< Interrupt on EVENTS_TRIGGERED[2] event. */ + NRF_EGU_INT_TRIGGERED3 = EGU_INTENSET_TRIGGERED3_Msk, /**< Interrupt on EVENTS_TRIGGERED[3] event. */ + NRF_EGU_INT_TRIGGERED4 = EGU_INTENSET_TRIGGERED4_Msk, /**< Interrupt on EVENTS_TRIGGERED[4] event. */ + NRF_EGU_INT_TRIGGERED5 = EGU_INTENSET_TRIGGERED5_Msk, /**< Interrupt on EVENTS_TRIGGERED[5] event. */ + NRF_EGU_INT_TRIGGERED6 = EGU_INTENSET_TRIGGERED6_Msk, /**< Interrupt on EVENTS_TRIGGERED[6] event. */ + NRF_EGU_INT_TRIGGERED7 = EGU_INTENSET_TRIGGERED7_Msk, /**< Interrupt on EVENTS_TRIGGERED[7] event. */ + NRF_EGU_INT_TRIGGERED8 = EGU_INTENSET_TRIGGERED8_Msk, /**< Interrupt on EVENTS_TRIGGERED[8] event. */ + NRF_EGU_INT_TRIGGERED9 = EGU_INTENSET_TRIGGERED9_Msk, /**< Interrupt on EVENTS_TRIGGERED[9] event. */ + NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */ + NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */ + NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */ + NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */ + NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */ + NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */ + NRF_EGU_INT_ALL = 0xFFFFuL +} nrf_egu_int_mask_t; + +/**@brief Function for getting max channel number of given EGU. + * + * @param NRF_EGUx EGU instance. + * + * @returns number of available channels. + */ +__STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx); + +/** + * @brief Function for triggering a specific EGU task. + * + * @param NRF_EGUx EGU instance. + * @param egu_task EGU task. + */ +__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task); + +/** + * @brief Function for returning the address of a specific EGU task register. + * + * @param NRF_EGUx EGU instance. + * @param egu_task EGU task. + */ +__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx, + nrf_egu_task_t egu_task); + +/** + * @brief Function for returning the address of a specific EGU TRIGGER task register. + * + * @param NRF_EGUx EGU instance. + * @param channel Channel number. + */ +__STATIC_INLINE uint32_t * nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx, + uint8_t channel); + +/** + * @brief Function for returning the specific EGU TRIGGER task. + * + * @param NRF_EGUx EGU instance. + * @param channel Channel number. + */ +__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel); + +/** + * @brief Function for returning the state of a specific EGU event. + * + * @param NRF_EGUx EGU instance. + * @param egu_event EGU event to check. + */ +__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event); + +/** + * @brief Function for clearing a specific EGU event. + * + * @param NRF_EGUx EGU instance. + * @param egu_event EGU event to clear. + */ +__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event); + +/** + * @brief Function for returning the address of a specific EGU event register. + * + * @param NRF_EGUx EGU instance. + * @param egu_event EGU event. + */ +__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event); + +/** + * @brief Function for returning the address of a specific EGU TRIGGERED event register. + * + * @param NRF_EGUx EGU instance. + * @param channel Channel number. + */ +__STATIC_INLINE uint32_t * nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx, + uint8_t channel); + +/** + * @brief Function for returning the specific EGU TRIGGERED event. + * + * @param NRF_EGUx EGU instance. + * @param channel Channel number. + */ +__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx, + uint8_t channel); + +/** + * @brief Function for enabling one or more specific EGU interrupts. + * + * @param NRF_EGUx EGU instance. + * @param egu_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask); + +/** + * @brief Function for retrieving the state of one or more EGU interrupts. + * + * @param NRF_EGUx EGU instance. + * @param egu_int_mask Interrupts to check. + * + * @retval true If all of the specified interrupts are enabled. + * @retval false If at least one of the specified interrupts is disabled. + */ +__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask); + +/** + * @brief Function for disabling one or more specific EGU interrupts. + * + * @param NRF_EGUx EGU instance. + * @param egu_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask); + +/** + * @brief Function for retrieving one or more specific EGU interrupts. + * + * @param NRF_EGUx EGU instance. + * @param channel Channel number. + * + * @returns EGU interrupt mask. + */ +__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx) +{ + if (NRF_EGUx == NRF_EGU0){ + return EGU0_CH_NUM; + } + if (NRF_EGUx == NRF_EGU1){ + return EGU1_CH_NUM; + } +#if EGU_COUNT > 2 + if (NRF_EGUx == NRF_EGU2){ + return EGU2_CH_NUM; + } + if (NRF_EGUx == NRF_EGU3){ + return EGU3_CH_NUM; + } + if (NRF_EGUx == NRF_EGU4){ + return EGU4_CH_NUM; + } + if (NRF_EGUx == NRF_EGU5){ + return EGU5_CH_NUM; + } +#endif + return 0; +} + +__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task) +{ + NRFX_ASSERT(NRF_EGUx); + *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx, + nrf_egu_task_t egu_task) +{ + NRFX_ASSERT(NRF_EGUx); + return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task); +} + +__STATIC_INLINE uint32_t * nrf_egu_task_trigger_address_get(NRF_EGU_Type * NRF_EGUx, + uint8_t channel) +{ + NRFX_ASSERT(NRF_EGUx); + NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); + return (uint32_t*)&NRF_EGUx->TASKS_TRIGGER[channel]; +} + +__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel) +{ + NRFX_ASSERT(NRF_EGUx); + NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); + return (nrf_egu_task_t)((uint32_t) NRF_EGU_TASK_TRIGGER0 + (channel * sizeof(uint32_t))); +} + +__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event) +{ + NRFX_ASSERT(NRF_EGUx); + return (bool)*(volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event); +} + +__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event) +{ + NRFX_ASSERT(NRF_EGUx); + *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx, + nrf_egu_event_t egu_event) +{ + NRFX_ASSERT(NRF_EGUx); + return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event); +} + +__STATIC_INLINE uint32_t * nrf_egu_event_triggered_address_get(NRF_EGU_Type * NRF_EGUx, + uint8_t channel) +{ + NRFX_ASSERT(NRF_EGUx); + NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); + return (uint32_t*)&NRF_EGUx->EVENTS_TRIGGERED[channel]; +} + +__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx, + uint8_t channel) +{ + NRFX_ASSERT(NRF_EGUx); + NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); + return (nrf_egu_event_t)((uint32_t) NRF_EGU_EVENT_TRIGGERED0 + (channel * sizeof(uint32_t))); +} + +__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) +{ + NRFX_ASSERT(NRF_EGUx); + NRF_EGUx->INTENSET = egu_int_mask; +} + +__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) +{ + NRFX_ASSERT(NRF_EGUx); + return (bool)(NRF_EGUx->INTENSET & egu_int_mask); +} + +__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask) +{ + NRFX_ASSERT(NRF_EGUx); + NRF_EGUx->INTENCLR = egu_int_mask; +} + +__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel) +{ + NRFX_ASSERT(NRF_EGUx); + NRFX_ASSERT(channel < nrf_egu_channel_count(NRF_EGUx)); + return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel)); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_gpio.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_gpio.h new file mode 100755 index 0000000..253bd7b --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_gpio.h @@ -0,0 +1,812 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_GPIO_H__ +#define NRF_GPIO_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_gpio_hal GPIO HAL + * @{ + * @ingroup nrf_gpio + * @brief Hardware access layer for managing the GPIO peripheral. + */ + +#if (GPIO_COUNT == 1) +#define NUMBER_OF_PINS (P0_PIN_NUM) +#define GPIO_REG_LIST {NRF_GPIO} +#elif (GPIO_COUNT == 2) +#define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM) +#define GPIO_REG_LIST {NRF_P0, NRF_P1} +#else +#error "Not supported." +#endif + + +/** + * @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions. + */ +#define NRF_GPIO_PIN_MAP(port, pin) (((port) << 5) | ((pin) & 0x1F)) + +/** + * @brief Pin direction definitions. + */ +typedef enum +{ + NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input. + NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output. +} nrf_gpio_pin_dir_t; + +/** + * @brief Connection of input buffer. + */ +typedef enum +{ + NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer. + NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer. +} nrf_gpio_pin_input_t; + +/** + * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration. + */ +typedef enum +{ + NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pull-up resistor disabled. + NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pull-down resistor enabled. + NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pull-up resistor enabled. +} nrf_gpio_pin_pull_t; + +/** + * @brief Enumerator used for selecting output drive mode. + */ +typedef enum +{ + NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'. + NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'. + NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'. + NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'. + NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'. + NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'. + NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'. + NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'. +} nrf_gpio_pin_drive_t; + +/** + * @brief Enumerator used for selecting the pin to sense high or low level on the pin input. + */ +typedef enum +{ + NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled. + NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level. + NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level. +} nrf_gpio_pin_sense_t; + +/** + * @brief Function for configuring the GPIO pin range as output pins with normal drive strength. + * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * + * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * + * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output. + * Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. + */ +__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); + +/** + * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details. + * This function can be used to configure pin range as simple input. + * + * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * + * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30). + * + * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). + * + * @note For configuring only one pin as input, use @ref nrf_gpio_cfg_input. + * Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. + */ +__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, + uint32_t pin_range_end, + nrf_gpio_pin_pull_t pull_config); + +/** + * @brief Pin configuration function. + * + * The main pin configuration function. + * This function allows to set any aspect in PIN_CNF register. + * @param pin_number Specifies the pin number. + * @param dir Pin direction. + * @param input Connect or disconnect the input buffer. + * @param pull Pull configuration. + * @param drive Drive configuration. + * @param sense Pin sensing mechanism. + */ +__STATIC_INLINE void nrf_gpio_cfg( + uint32_t pin_number, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense); + +/** + * @brief Function for configuring the given GPIO pin number as output, hiding inner details. + * This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). + * + * @param pin_number Specifies the pin number. + * + * @note Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output. + */ +__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as input, hiding inner details. + * This function can be used to configure a pin as simple input. + * + * @param pin_number Specifies the pin number. + * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high). + * + * @note Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable. + */ +__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); + +/** + * @brief Function for resetting pin configuration to its default state. + * + * @param pin_number Specifies the pin number. + */ +__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected. + * + * @param pin_number Specifies the pin number. + * + */ +__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); + +/** + * @brief Function for disconnecting input for the given GPIO. + * + * @param pin_number Specifies the pin number. + * + */ +__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); + +/** + * @brief Function for configuring the given GPIO pin number as input, hiding inner details. + * This function can be used to configure pin range as simple input. + * Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable. + * + * @param pin_number Specifies the pin number. + * @param pull_config State of the pin pull resistor (no pull, pulled down, or pulled high). + * @param sense_config Sense level of the pin (no sense, sense low, or sense high). + */ +__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, + nrf_gpio_pin_pull_t pull_config, + nrf_gpio_pin_sense_t sense_config); + +/** + * @brief Function for configuring sense level for the given GPIO. + * + * @param pin_number Specifies the pin number. + * @param sense_config Sense configuration. + * + */ +__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config); + +/** + * @brief Function for setting the direction for a GPIO pin. + * + * @param pin_number Specifies the pin number for which to set the direction. + * + * @param direction Specifies the direction. + */ +__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); + +/** + * @brief Function for setting a GPIO pin. + * + * Note that the pin must be configured as an output for this function to have any effect. + * + * @param pin_number Specifies the pin number to set. + */ +__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); + +/** + * @brief Function for clearing a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number to clear. + */ +__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); + +/** + * @brief Function for toggling a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number to toggle. + */ +__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); + +/** + * @brief Function for writing a value to a GPIO pin. + * + * Note that the pin must be configured as an output for this + * function to have any effect. + * + * @param pin_number Specifies the pin number to write. + * + * @param value Specifies the value to be written to the pin. + * @arg 0 Clears the pin. + * @arg >=1 Sets the pin. + */ +__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); + +/** + * @brief Function for reading the input level of a GPIO pin. + * + * Note that the pin must have input connected for the value + * returned from this function to be valid. + * + * @param pin_number Specifies the pin number to read. + * + * @return 0 if the pin input level is low. Positive value if the pin is high. + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); + +/** + * @brief Function for reading the output level of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @return 0 if the pin output level is low. Positive value if pin output is high. + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number); + +/** + * @brief Function for reading the sense configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @retval Sense configuration. + */ +__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); + +/** + * @brief Function for reading the direction configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @retval Direction configuration. + */ +__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number); + +/** + * @brief Function for reading the pull configuration of a GPIO pin. + * + * @param pin_number Specifies the pin number to read. + * + * @retval Pull configuration. + */ +__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number); + +/** + * @brief Function for setting output direction on selected pins on a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param out_mask Mask specifying the pins to set as output. + * + */ +__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask); + +/** + * @brief Function for setting input direction on selected pins on a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param in_mask Mask specifying the pins to set as input. + * + */ +__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask); + +/** + * @brief Function for writing the direction configuration of GPIO pins in a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param dir_mask Mask specifying the direction of pins. Bit set means that the given pin is configured as output. + * + */ +__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask); + +/** + * @brief Function for reading the direction configuration of a GPIO port. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @retval Pin configuration of the current direction settings. Bit set means that the given pin is configured as output. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for reading the input signals of GPIO pins on a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @retval Port input values. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for reading the output signals of GPIO pins of a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @retval Port output values. + */ +__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg); + +/** + * @brief Function for writing the GPIO pins output on a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param value Output port mask. + * + */ +__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value); + +/** + * @brief Function for setting high level on selected GPIO pins of a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param set_mask Mask with pins to set as logical high level. + * + */ +__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask); + +/** + * @brief Function for setting low level on selected GPIO pins of a given port. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param clr_mask Mask with pins to set as logical low level. + * + */ +__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask); + +/** + * @brief Function for reading pins state of multiple consecutive ports. + * + * @param start_port Index of the first port to read. + * @param length Number of ports to read. + * @param p_masks Pointer to output array where port states will be stored. + */ +__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks); + +#if defined(GPIO_DETECTMODE_DETECTMODE_LDETECT) || defined(__NRF_DOXYGEN__) +/** + * @brief Function for reading latch state of multiple consecutive ports. + * + * @param start_port Index of the first port to read. + * @param length Number of ports to read. + * @param p_masks Pointer to output array where latch states will be stored. + */ +__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, + uint32_t * p_masks); + +/** + * @brief Function for reading latch state of single pin. + * + * @param pin_number Pin number. + * @return 0 if latch is not set. Positive value otherwise. + * + */ +__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number); + +/** + * @brief Function for clearing latch state of a single pin. + * + * @param pin_number Pin number. + * + */ +__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number); +#endif + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +/** + * @brief Function for extracting port and relative pin number from absolute pin number. + * + * @param[inout] Pointer to absolute pin number which is overriden by relative to port pin number. + * + * @return Pointer to port register set. + * + */ +__STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) +{ + NRFX_ASSERT(*p_pin < NUMBER_OF_PINS); +#if (GPIO_COUNT == 1) + // The oldest definition case + return NRF_GPIO; +#else + if (*p_pin < P0_PIN_NUM) + { + return NRF_P0; + } + else + { + *p_pin = *p_pin & (P0_PIN_NUM - 1); + return NRF_P1; + } +#endif +} + + +__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + for (; pin_range_start <= pin_range_end; pin_range_start++) + { + nrf_gpio_cfg_output(pin_range_start); + } +} + + +__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, + uint32_t pin_range_end, + nrf_gpio_pin_pull_t pull_config) +{ + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + for (; pin_range_start <= pin_range_end; pin_range_start++) + { + nrf_gpio_cfg_input(pin_range_start, pull_config); + } +} + + +__STATIC_INLINE void nrf_gpio_cfg( + uint32_t pin_number, + nrf_gpio_pin_dir_t dir, + nrf_gpio_pin_input_t input, + nrf_gpio_pin_pull_t pull, + nrf_gpio_pin_drive_t drive, + nrf_gpio_pin_sense_t sense) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +} + + +__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + + reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); +} + + +__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; + + reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); +} + + +__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, + nrf_gpio_pin_pull_t pull_config, + nrf_gpio_pin_sense_t sense_config) +{ + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + pull_config, + NRF_GPIO_PIN_S0S1, + sense_config); +} + + +__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + /*lint -e{845} // A zero has been given as right argument to operator '|'" */ + reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk; + reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) +{ + if (direction == NRF_GPIO_PIN_DIR_INPUT) + { + nrf_gpio_cfg( + pin_number, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + } + else + { + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + reg->DIRSET = (1UL << pin_number); + } +} + + +__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + nrf_gpio_port_out_set(reg, 1UL << pin_number); +} + + +__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + nrf_gpio_port_out_clear(reg, 1UL << pin_number); +} + + +__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + uint32_t pins_state = reg->OUT; + + reg->OUTSET = (~pins_state & (1UL << pin_number)); + reg->OUTCLR = (pins_state & (1UL << pin_number)); +} + + +__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) +{ + if (value == 0) + { + nrf_gpio_pin_clear(pin_number); + } + else + { + nrf_gpio_pin_set(pin_number); + } +} + + +__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL); +} + + +__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL); +} + + +__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos); +} + + +__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos); +} + + +__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos); +} + + +__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask) +{ + p_reg->DIRSET = out_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask) +{ + p_reg->DIRCLR = in_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value) +{ + p_reg->DIR = value; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->DIR; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->IN; +} + + +__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg) +{ + return p_reg->OUT; +} + + +__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value) +{ + p_reg->OUT = value; +} + + +__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask) +{ + p_reg->OUTSET = set_mask; +} + + +__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask) +{ + p_reg->OUTCLR = clr_mask; +} + + +__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) +{ + NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; + + NRFX_ASSERT(start_port + length <= GPIO_COUNT); + uint32_t i; + + for (i = start_port; i < (start_port + length); i++) + { + *p_masks = nrf_gpio_port_in_read(gpio_regs[i]); + p_masks++; + } +} + + +#ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT +__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks) +{ + NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST; + uint32_t i; + + for (i = start_port; i < (start_port + length); i++) + { + *p_masks = gpio_regs[i]->LATCH; + p_masks++; + } +} + + +__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (reg->LATCH & (1 << pin_number)) ? 1 : 0; +} + + +__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + reg->LATCH = (1 << pin_number); +} + + +#endif +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_GPIO_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_gpiote.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_gpiote.h new file mode 100755 index 0000000..ab923af --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_gpiote.h @@ -0,0 +1,433 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_GPIOTE_H__ +#define NRF_GPIOTE_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @defgroup nrf_gpiote_hal GPIOTE HAL +* @{ +* @ingroup nrf_gpiote +* @brief Hardware access layer for managing the GPIOTE peripheral. +*/ + +#ifdef GPIOTE_CONFIG_PORT_Msk +#define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk) +#else +#define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk +#endif + + /** + * @enum nrf_gpiote_polarity_t + * @brief Polarity for the GPIOTE channel. + */ +typedef enum +{ + NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi, ///< Low to high. + NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo, ///< High to low. + NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle ///< Toggle. +} nrf_gpiote_polarity_t; + + + /** + * @enum nrf_gpiote_outinit_t + * @brief Initial output value for the GPIOTE channel. + */ +typedef enum +{ + NRF_GPIOTE_INITIAL_VALUE_LOW = GPIOTE_CONFIG_OUTINIT_Low, ///< Low to high. + NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High ///< High to low. +} nrf_gpiote_outinit_t; + +/** + * @brief Tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_GPIOTE_TASKS_OUT_0 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/ + NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/ + NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/ + NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/ +#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/ + NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/ + NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/ + NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/ +#endif +#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/ + NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/ + NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/ + NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/ + NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/ + NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/ + NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/ + NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/ +#endif +#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/ + NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/ + NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/ + NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/ + NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/ + NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/ + NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/ + NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/ +#endif + /*lint -restore*/ +} nrf_gpiote_tasks_t; + +/** + * @brief Events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_GPIOTE_EVENTS_IN_0 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/ + NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/ + NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/ + NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/ +#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/ + NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/ + NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/ + NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/ +#endif + NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/ + /*lint -restore*/ +} nrf_gpiote_events_t; + +/** + * @enum nrf_gpiote_int_t + * @brief GPIOTE interrupts. + */ +typedef enum +{ + NRF_GPIOTE_INT_IN0_MASK = GPIOTE_INTENSET_IN0_Msk, /**< GPIOTE interrupt from IN0. */ + NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */ + NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */ + NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */ +#if (GPIOTE_CH_NUM > 4) || defined(__NRFX_DOXYGEN__) + NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */ + NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */ + NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */ + NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */ +#endif + NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */ +} nrf_gpiote_int_t; + +#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\ + NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK) +#if (GPIOTE_CH_NUM > 4) +#undef NRF_GPIOTE_INT_IN_MASK +#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\ + NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\ + NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\ + NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK) +#endif + +/** + * @brief Function for activating a specific GPIOTE task. + * + * @param[in] task Task. + */ +__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task); + +/** + * @brief Function for getting the address of a specific GPIOTE task. + * + * @param[in] task Task. + * + * @returns Address. + */ +__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task); + +/** + * @brief Function for getting the state of a specific GPIOTE event. + * + * @param[in] event Event. + */ +__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event); + +/** + * @brief Function for clearing a specific GPIOTE event. + * + * @param[in] event Event. + */ +__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event); + +/** + * @brief Function for getting the address of a specific GPIOTE event. + * + * @param[in] event Event. + * + * @return Address + */ +__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event); + +/**@brief Function for enabling interrupts. + * + * @param[in] mask Interrupt mask to be enabled. + */ +__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask); + +/**@brief Function for disabling interrupts. + * + * @param[in] mask Interrupt mask to be disabled. + */ +__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask); + +/**@brief Function for checking if interrupts are enabled. + * + * @param[in] mask Mask of interrupt flags to check. + * + * @return Mask with enabled interrupts. + */ +__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask); + +/**@brief Function for enabling a GPIOTE event. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx); + +/**@brief Function for disabling a GPIOTE event. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx); + +/**@brief Function for configuring a GPIOTE event. + * + * @param[in] idx Task-Event index. + * @param[in] pin Pin associated with event. + * @param[in] polarity Transition that should generate an event. + */ +__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity); + +/**@brief Function for getting the pin associated with a GPIOTE event. + * + * @param[in] idx Task-Event index. + * + * @return Pin number. + */ +__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx); + +/**@brief Function for getting the polarity associated with a GPIOTE event. + * + * @param[in] idx Task-Event index. + * + * @return Polarity. + */ +__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx); + +/**@brief Function for enabling a GPIOTE task. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx); + +/**@brief Function for disabling a GPIOTE task. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx); + +/**@brief Function for configuring a GPIOTE task. + * @note Function is not configuring mode field so task is disabled after this function is called. + * + * @param[in] idx Task-Event index. + * @param[in] pin Pin associated with event. + * @param[in] polarity Transition that should generate an event. + * @param[in] init_val Initial value of the pin. + */ +__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity, + nrf_gpiote_outinit_t init_val); + +/**@brief Function for forcing a specific state on the pin connected to GPIOTE. + * + * @param[in] idx Task-Event index. + * @param[in] init_val Pin state. + */ +__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val); + +/**@brief Function for resetting a GPIOTE task event configuration to the default state. + * + * @param[in] idx Task-Event index. + */ +__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx); + +/**@brief Function for checking if particular Task-Event is enabled. + * + * @param[in] idx Task-Event index. + * + * @retval true If the Task-Event mode is set to Task or Event. + * @retval false If the Task-Event mode is set to Disabled. + */ +__STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task) +{ + *(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task) +{ + return ((uint32_t)NRF_GPIOTE + task); +} + +__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event) +{ + return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false; +} + +__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event) +{ + *(uint32_t *)nrf_gpiote_event_addr_get(event) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event)); + (void)dummy; +#endif +} + +__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event) +{ + return ((uint32_t)NRF_GPIOTE + event); +} + +__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask) +{ + NRF_GPIOTE->INTENSET = mask; +} + +__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask) +{ + NRF_GPIOTE->INTENCLR = mask; +} + +__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask) +{ + return (NRF_GPIOTE->INTENSET & mask); +} + +__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event; +} + +__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event; +} + +__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity) +{ + NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk); + NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | + ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk); +} + +__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx) +{ + return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos); +} + +__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx) +{ + return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos); +} + +__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx) +{ + uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task; +#ifdef NRF51 + /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens + on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the + correct state in GPIOTE but not in the OUT register. */ + /* Configure channel to not existing, not connected to the pin, and configure as a tasks that will set it to proper level */ + NRF_GPIOTE->CONFIG[idx] = final_config | (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk); + __NOP(); + __NOP(); + __NOP(); +#endif + NRF_GPIOTE->CONFIG[idx] = final_config; +} + +__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task; +} + +__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin, + nrf_gpiote_polarity_t polarity, + nrf_gpiote_outinit_t init_val) +{ + NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | + GPIOTE_CONFIG_POLARITY_Msk | + GPIOTE_CONFIG_OUTINIT_Msk); + + NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) | + ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) | + ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk); +} + +__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val) +{ + NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk) + | ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk); +} + +__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx) +{ + NRF_GPIOTE->CONFIG[idx] = 0; +} + +__STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx) +{ + return (NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_i2s.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_i2s.h new file mode 100755 index 0000000..91053a9 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_i2s.h @@ -0,0 +1,548 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_I2S_H__ +#define NRF_I2S_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_i2s_hal I2S HAL + * @{ + * @ingroup nrf_i2s + * @brief Hardware access layer for managing the Inter-IC Sound (I2S) peripheral. + */ + +/** + * @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set + * function call to specify that a given I2S signal (SDOUT, SDIN, or MCK) + * shall not be connected to a physical pin. + */ +#define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF + + +/** + * @brief I2S tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled. + NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator. + /*lint -restore*/ +} nrf_i2s_task_t; + +/** + * @brief I2S events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double-buffers. + NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double-buffers. + NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED) ///< I2S transfer stopped. + /*lint -restore*/ +} nrf_i2s_event_t; + +/** + * @brief I2S interrupts. + */ +typedef enum +{ + NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event. + NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event. + NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk ///< Interrupt on STOPPED event. +} nrf_i2s_int_mask_t; + +/** + * @brief I2S modes of operation. + */ +typedef enum +{ + NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode. + NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode. +} nrf_i2s_mode_t; + +/** + * @brief I2S master clock generator settings. + */ +typedef enum +{ + NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled. + // [conversion to 'int' needed to prevent compilers from complaining + // that the provided value (0x80000000UL) is out of range of "int"] + NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz. + NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz. + NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz. + NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz. + NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz. + NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz. + NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz. + NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz. + NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz. + NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz. + NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz. + NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz. + NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz. + NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz. + NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz. + NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz. +} nrf_i2s_mck_t; + +/** + * @brief I2S MCK/LRCK ratios. + */ +typedef enum +{ + NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32. + NRF_I2S_RATIO_48X = I2S_CONFIG_RATIO_RATIO_48X, ///< LRCK = MCK / 48. + NRF_I2S_RATIO_64X = I2S_CONFIG_RATIO_RATIO_64X, ///< LRCK = MCK / 64. + NRF_I2S_RATIO_96X = I2S_CONFIG_RATIO_RATIO_96X, ///< LRCK = MCK / 96. + NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128. + NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192. + NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256. + NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384. + NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512. +} nrf_i2s_ratio_t; + +/** + * @brief I2S sample widths. + */ +typedef enum +{ + NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit. + NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit. + NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit ///< 24 bit. +} nrf_i2s_swidth_t; + +/** + * @brief I2S alignments of sample within a frame. + */ +typedef enum +{ + NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned. + NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned. +} nrf_i2s_align_t; + +/** + * @brief I2S frame formats. + */ +typedef enum +{ + NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format. + NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left- or right-aligned) format. +} nrf_i2s_format_t; + +/** + * @brief I2S enabled channels. + */ +typedef enum +{ + NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo. + NRF_I2S_CHANNELS_LEFT = I2S_CONFIG_CHANNELS_CHANNELS_Left, ///< Left only. + NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only. +} nrf_i2s_channels_t; + + +/** + * @brief Function for activating a specific I2S task. + * + * @param[in] p_i2s I2S instance. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s, + nrf_i2s_task_t task); + +/** + * @brief Function for getting the address of a specific I2S task register. + * + * @param[in] p_i2s I2S instance. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s, + nrf_i2s_task_t task); + +/** + * @brief Function for clearing a specific I2S event. + * + * @param[in] p_i2s I2S instance. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s, + nrf_i2s_event_t event); + +/** + * @brief Function for checking the state of a specific I2S event. + * + * @param[in] p_i2s I2S instance. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s, + nrf_i2s_event_t event); + +/** + * @brief Function for getting the address of a specific I2S event register. + * + * @param[in] p_i2s I2S instance. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s, + nrf_i2s_event_t event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_i2s I2S instance. + * @param[in] mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_i2s I2S instance. + * @param[in] mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_i2s I2S instance. + * @param[in] i2s_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s, + nrf_i2s_int_mask_t i2s_int); + +/** + * @brief Function for enabling the I2S peripheral. + * + * @param[in] p_i2s I2S instance. + */ +__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s); + +/** + * @brief Function for disabling the I2S peripheral. + * + * @param[in] p_i2s I2S instance. + */ +__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s); + +/** + * @brief Function for configuring I2S pins. + * + * Usage of the SDOUT, SDIN, and MCK signals is optional. + * If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_i2s I2S instance. + * @param[in] sck_pin SCK pin number. + * @param[in] lrck_pin LRCK pin number. + * @param[in] mck_pin MCK pin number. + * @param[in] sdout_pin SDOUT pin number. + * @param[in] sdin_pin SDIN pin number. + */ +__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s, + uint32_t sck_pin, + uint32_t lrck_pin, + uint32_t mck_pin, + uint32_t sdout_pin, + uint32_t sdin_pin); + +/** + * @brief Function for setting the I2S peripheral configuration. + * + * @param[in] p_i2s I2S instance. + * @param[in] mode Mode of operation (master or slave). + * @param[in] format I2S frame format. + * @param[in] alignment Alignment of sample within a frame. + * @param[in] sample_width Sample width. + * @param[in] channels Enabled channels. + * @param[in] mck_setup Master clock generator setup. + * @param[in] ratio MCK/LRCK ratio. + * + * @retval true If the configuration has been set successfully. + * @retval false If the requested configuration is not allowed. + */ +__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s, + nrf_i2s_mode_t mode, + nrf_i2s_format_t format, + nrf_i2s_align_t alignment, + nrf_i2s_swidth_t sample_width, + nrf_i2s_channels_t channels, + nrf_i2s_mck_t mck_setup, + nrf_i2s_ratio_t ratio); + +/** + * @brief Function for setting up the I2S transfer. + * + * This function sets up the RX and TX buffers and enables reception and/or + * transmission accordingly. If the transfer in a given direction is not + * required, pass NULL instead of the pointer to the corresponding buffer. + * + * @param[in] p_i2s I2S instance. + * @param[in] size Size of the buffers (in 32-bit words). + * @param[in] p_rx_buffer Pointer to the receive buffer. + * Pass NULL to disable reception. + * @param[in] p_tx_buffer Pointer to the transmit buffer. + * Pass NULL to disable transmission. + */ +__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s, + uint16_t size, + uint32_t * p_rx_buffer, + uint32_t const * p_tx_buffer); + +/** + * @brief Function for setting the pointer to the receive buffer. + * + * @note The size of the buffer can be set only by calling + * @ref nrf_i2s_transfer_set. + * + * @param[in] p_i2s I2S instance. + * @param[in] p_buffer Pointer to the receive buffer. + */ +__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s, + uint32_t * p_buffer); + +/** + * @brief Function for getting the pointer to the receive buffer. + * + * @param[in] p_i2s I2S instance. + * + * @return Pointer to the receive buffer. + */ +__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s); + +/** + * @brief Function for setting the pointer to the transmit buffer. + * + * @note The size of the buffer can be set only by calling + * @ref nrf_i2s_transfer_set. + * + * @param[in] p_i2s I2S instance. + * @param[in] p_buffer Pointer to the transmit buffer. + */ +__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s, + uint32_t const * p_buffer); + +/** + * @brief Function for getting the pointer to the transmit buffer. + * + * @param[in] p_i2s I2S instance. + * + * @return Pointer to the transmit buffer. + */ +__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s, + nrf_i2s_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s, + nrf_i2s_task_t task) +{ + return ((uint32_t)p_i2s + (uint32_t)task); +} + +__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s, + nrf_i2s_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s, + nrf_i2s_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s, + nrf_i2s_event_t event) +{ + return ((uint32_t)p_i2s + (uint32_t)event); +} + +__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask) +{ + p_i2s->INTENSET = mask; +} + +__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask) +{ + p_i2s->INTENCLR = mask; +} + +__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s, + nrf_i2s_int_mask_t i2s_int) +{ + return (bool)(p_i2s->INTENSET & i2s_int); +} + +__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s) +{ + p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s) +{ + p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s, + uint32_t sck_pin, + uint32_t lrck_pin, + uint32_t mck_pin, + uint32_t sdout_pin, + uint32_t sdin_pin) +{ + p_i2s->PSEL.SCK = sck_pin; + p_i2s->PSEL.LRCK = lrck_pin; + p_i2s->PSEL.MCK = mck_pin; + p_i2s->PSEL.SDOUT = sdout_pin; + p_i2s->PSEL.SDIN = sdin_pin; +} + +__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s, + nrf_i2s_mode_t mode, + nrf_i2s_format_t format, + nrf_i2s_align_t alignment, + nrf_i2s_swidth_t sample_width, + nrf_i2s_channels_t channels, + nrf_i2s_mck_t mck_setup, + nrf_i2s_ratio_t ratio) +{ + if (mode == NRF_I2S_MODE_MASTER) + { + // The MCK/LRCK ratio shall be a multiple of 2 * sample width. + if (((sample_width == NRF_I2S_SWIDTH_16BIT) && + (ratio == NRF_I2S_RATIO_48X)) + || + ((sample_width == NRF_I2S_SWIDTH_24BIT) && + ((ratio == NRF_I2S_RATIO_32X) || + (ratio == NRF_I2S_RATIO_64X) || + (ratio == NRF_I2S_RATIO_128X) || + (ratio == NRF_I2S_RATIO_256X) || + (ratio == NRF_I2S_RATIO_512X)))) + { + return false; + } + } + + p_i2s->CONFIG.MODE = mode; + p_i2s->CONFIG.FORMAT = format; + p_i2s->CONFIG.ALIGN = alignment; + p_i2s->CONFIG.SWIDTH = sample_width; + p_i2s->CONFIG.CHANNELS = channels; + p_i2s->CONFIG.RATIO = ratio; + + if (mck_setup == NRF_I2S_MCK_DISABLED) + { + p_i2s->CONFIG.MCKEN = + (I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos); + } + else + { + p_i2s->CONFIG.MCKFREQ = mck_setup; + p_i2s->CONFIG.MCKEN = + (I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos); + } + + return true; +} + +__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s, + uint16_t size, + uint32_t * p_buffer_rx, + uint32_t const * p_buffer_tx) +{ + p_i2s->RXTXD.MAXCNT = size; + + nrf_i2s_rx_buffer_set(p_i2s, p_buffer_rx); + p_i2s->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0; + + nrf_i2s_tx_buffer_set(p_i2s, p_buffer_tx); + p_i2s->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0; +} + +__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s, + uint32_t * p_buffer) +{ + p_i2s->RXD.PTR = (uint32_t)p_buffer; +} + +__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s) +{ + return (uint32_t *)(p_i2s->RXD.PTR); +} + +__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s, + uint32_t const * p_buffer) +{ + p_i2s->TXD.PTR = (uint32_t)p_buffer; +} + +__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s) +{ + return (uint32_t *)(p_i2s->TXD.PTR); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_I2S_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_lpcomp.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_lpcomp.h new file mode 100755 index 0000000..d7347e6 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_lpcomp.h @@ -0,0 +1,403 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_LPCOMP_H_ +#define NRF_LPCOMP_H_ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_lpcomp_hal LPCOMP HAL + * @{ + * @ingroup nrf_lpcomp + * @brief Hardware access layer for managing the Low Power Comparator (LPCOMP) peripheral. + */ + +/** + * @enum nrf_lpcomp_ref_t + * @brief LPCOMP reference selection. + */ +typedef enum +{ +#if (LPCOMP_REFSEL_RESOLUTION == 8) || defined(__NRFX_DOXYGEN__) + NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling, /**< Use supply with a 1/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling, /**< Use supply with a 2/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling, /**< Use supply with a 3/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling, /**< Use supply with a 4/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling, /**< Use supply with a 5/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling, /**< Use supply with a 6/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, /**< Use supply with a 7/8 prescaler as reference. */ +#elif (LPCOMP_REFSEL_RESOLUTION == 16) || defined(__NRFX_DOXYGEN__) + NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref3_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref5_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref7_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref9_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref11_16Vdd, /**< Use supply with a 11/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref13_16Vdd, /**< Use supply with a 13/16 prescaler as reference. */ + NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref15_16Vdd, /**< Use supply with a 15/16 prescaler as reference. */ +#endif + NRF_LPCOMP_REF_EXT_REF0 = LPCOMP_REFSEL_REFSEL_ARef | + (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */ + NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef | + (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), /**< External reference 1. */ +} nrf_lpcomp_ref_t; + +/** + * @enum nrf_lpcomp_input_t + * @brief LPCOMP input selection. + */ +typedef enum +{ + NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */ + NRF_LPCOMP_INPUT_1 = LPCOMP_PSEL_PSEL_AnalogInput1, /**< Input 1. */ + NRF_LPCOMP_INPUT_2 = LPCOMP_PSEL_PSEL_AnalogInput2, /**< Input 2. */ + NRF_LPCOMP_INPUT_3 = LPCOMP_PSEL_PSEL_AnalogInput3, /**< Input 3. */ + NRF_LPCOMP_INPUT_4 = LPCOMP_PSEL_PSEL_AnalogInput4, /**< Input 4. */ + NRF_LPCOMP_INPUT_5 = LPCOMP_PSEL_PSEL_AnalogInput5, /**< Input 5. */ + NRF_LPCOMP_INPUT_6 = LPCOMP_PSEL_PSEL_AnalogInput6, /**< Input 6. */ + NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7 /**< Input 7. */ +} nrf_lpcomp_input_t; + +/** + * @enum nrf_lpcomp_detect_t + * @brief LPCOMP detection type selection. + */ +typedef enum +{ + NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */ + NRF_LPCOMP_DETECT_UP = LPCOMP_ANADETECT_ANADETECT_Up, /**< Generate ANADETEC on upwards crossing only. */ + NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down /**< Generate ANADETEC on downwards crossing only. */ +} nrf_lpcomp_detect_t; + +/** + * @enum nrf_lpcomp_task_t + * @brief LPCOMP tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_LPCOMP_TASK_START = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */ + NRF_LPCOMP_TASK_STOP = offsetof(NRF_LPCOMP_Type, TASKS_STOP), /**< LPCOMP stop sampling task. */ + NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */ +} nrf_lpcomp_task_t; /*lint -restore*/ + + +/** + * @enum nrf_lpcomp_event_t + * @brief LPCOMP events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */ + NRF_LPCOMP_EVENT_DOWN = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN), /**< Input voltage crossed the threshold going down. */ + NRF_LPCOMP_EVENT_UP = offsetof(NRF_LPCOMP_Type, EVENTS_UP), /**< Input voltage crossed the threshold going up. */ + NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS) /**< Input voltage crossed the threshold in any direction. */ +} nrf_lpcomp_event_t; /*lint -restore*/ + +/** + * @enum nrf_lpcomp_short_mask_t + * @brief LPCOMP shorts masks. + */ +typedef enum +{ + NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Short between CROSS event and STOP task. */ + NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Short between UP event and STOP task. */ + NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Short between DOWN event and STOP task. */ + NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Short between READY event and STOP task. */ + NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Short between READY event and SAMPLE task. */ +} nrf_lpcomp_short_mask_t; + +#ifdef LPCOMP_FEATURE_HYST_PRESENT +/** + * @enum nrf_lpcomp_hysteresis_t + * @brief LPCOMP hysteresis. + */ +typedef enum +{ + NRF_LPCOMP_HYST_NOHYST = LPCOMP_HYST_HYST_NoHyst, /**< Comparator hysteresis disabled. */ + NRF_LPCOMP_HYST_50mV = LPCOMP_HYST_HYST_Hyst50mV /**< Comparator hysteresis enabled (typ. 50 mV). */ +}nrf_lpcomp_hysteresis_t; +#endif // LPCOMP_FEATURE_HYST_PRESENT + +/** @brief LPCOMP configuration. */ +typedef struct +{ + nrf_lpcomp_ref_t reference; /**< LPCOMP reference. */ + nrf_lpcomp_detect_t detection; /**< LPCOMP detection type. */ +#ifdef LPCOMP_FEATURE_HYST_PRESENT + nrf_lpcomp_hysteresis_t hyst; /**< LPCOMP hysteresis. */ +#endif // LPCOMP_FEATURE_HYST_PRESENT +} nrf_lpcomp_config_t; + +/** Default LPCOMP configuration. */ +#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN } + +/** + * @brief Function for configuring LPCOMP. + * + * This function powers on LPCOMP and configures it. LPCOMP is in DISABLE state after configuration, + * so it must be enabled before using it. All shorts are inactive, events are cleared, and LPCOMP is stopped. + * + * @param[in] p_config Configuration. + */ +__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config) +{ + NRF_LPCOMP->TASKS_STOP = 1; + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->REFSEL = + (p_config->reference << LPCOMP_REFSEL_REFSEL_Pos) & LPCOMP_REFSEL_REFSEL_Msk; + + //If external source is choosen extract analog reference index. + if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef) + { + uint32_t extref = p_config->reference >> 16; + NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) & LPCOMP_EXTREFSEL_EXTREFSEL_Msk; + } + + NRF_LPCOMP->ANADETECT = + (p_config->detection << LPCOMP_ANADETECT_ANADETECT_Pos) & LPCOMP_ANADETECT_ANADETECT_Msk; +#ifdef LPCOMP_FEATURE_HYST_PRESENT + NRF_LPCOMP->HYST = ((p_config->hyst) << LPCOMP_HYST_HYST_Pos) & LPCOMP_HYST_HYST_Msk; +#endif //LPCOMP_FEATURE_HYST_PRESENT + NRF_LPCOMP->SHORTS = 0; + NRF_LPCOMP->INTENCLR = LPCOMP_INTENCLR_CROSS_Msk | LPCOMP_INTENCLR_UP_Msk | + LPCOMP_INTENCLR_DOWN_Msk | LPCOMP_INTENCLR_READY_Msk; +} + + +/** + * @brief Function for selecting the LPCOMP input. + * + * This function selects the active input of LPCOMP. + * + * @param[in] input Input to be selected. + */ +__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input) +{ + uint32_t lpcomp_enable_state = NRF_LPCOMP->ENABLE; + + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->PSEL = + ((uint32_t)input << LPCOMP_PSEL_PSEL_Pos) | (NRF_LPCOMP->PSEL & ~LPCOMP_PSEL_PSEL_Msk); + NRF_LPCOMP->ENABLE = lpcomp_enable_state; +} + + +/** + * @brief Function for enabling the Low Power Comparator. + * + * This function enables LPCOMP. + * + */ +__STATIC_INLINE void nrf_lpcomp_enable(void) +{ + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->EVENTS_READY = 0; + NRF_LPCOMP->EVENTS_DOWN = 0; + NRF_LPCOMP->EVENTS_UP = 0; + NRF_LPCOMP->EVENTS_CROSS = 0; +} + + +/** + * @brief Function for disabling the Low Power Comparator. + * + * This function disables LPCOMP. + * + */ +__STATIC_INLINE void nrf_lpcomp_disable(void) +{ + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; +} + + +/** + * @brief Function for getting the last LPCOMP compare result. + * + * @return The last compare result. If 0 then VIN+ < VIN-, if 1 then the opposite. + */ +__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void) +{ + return (uint32_t)NRF_LPCOMP->RESULT; +} + + +/** + * @brief Function for enabling interrupts from LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be enabled. + * + * @sa nrf_lpcomp_int_disable() + * @sa nrf_lpcomp_int_enable_check() + */ +__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask) +{ + NRF_LPCOMP->INTENSET = lpcomp_int_mask; +} + + +/** + * @brief Function for disabling interrupts from LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be disabled. + * + * @sa nrf_lpcomp_int_enable() + * @sa nrf_lpcomp_int_enable_check() + */ +__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask) +{ + NRF_LPCOMP->INTENCLR = lpcomp_int_mask; +} + + +/** + * @brief Function for getting the enabled interrupts of LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be checked. + * + * @retval true If any of interrupts of the specified mask are enabled. + * + * @sa nrf_lpcomp_int_enable() + * @sa nrf_lpcomp_int_disable() + */ +__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask) +{ + return (NRF_LPCOMP->INTENSET & lpcomp_int_mask); // when read this register will return the value of INTEN. +} + + +/** + * @brief Function for getting the address of a specific LPCOMP task register. + * + * @param[in] lpcomp_task LPCOMP task. + * + * @return The address of the specified LPCOMP task. + */ +__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task) +{ + return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_task); +} + + +/** + * @brief Function for getting the address of a specific LPCOMP event register. + * + * @param[in] lpcomp_event LPCOMP event. + * + * @return The address of the specified LPCOMP event. + */ +__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event) +{ + return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event); +} + + +/** + * @brief Function for setting LPCOMP shorts. + * + * @param[in] lpcomp_short_mask LPCOMP shorts by mask. + * + */ +__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask) +{ + NRF_LPCOMP->SHORTS |= lpcomp_short_mask; +} + + +/** + * @brief Function for clearing LPCOMP shorts by mask. + * + * @param[in] lpcomp_short_mask LPCOMP shorts to be cleared. + * + */ +__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask) +{ + NRF_LPCOMP->SHORTS &= ~lpcomp_short_mask; +} + + +/** + * @brief Function for setting a specific LPCOMP task. + * + * @param[in] lpcomp_task LPCOMP task to be set. + * + */ +__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_task) ) = 1; +} + + +/** + * @brief Function for clearing a specific LPCOMP event. + * + * @param[in] lpcomp_event LPCOMP event to be cleared. + * + */ +__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event) ) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event)); + (void)dummy; +#endif +} + + +/** + * @brief Function for getting the state of a specific LPCOMP event. + * + * @retval true If the specified LPCOMP event is active. + * + */ +__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event) +{ + return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event)); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_LPCOMP_H_ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_nvmc.c b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_nvmc.c new file mode 100755 index 0000000..be4bde4 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_nvmc.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +/** + *@file + *@brief NMVC driver implementation + */ + +#include <nrfx.h> +#include "nrf_nvmc.h" + +static inline void wait_for_flash_ready(void) +{ + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {;} +} + +void nrf_nvmc_page_erase(uint32_t address) +{ + // Enable erase. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een; + __ISB(); + __DSB(); + + // Erase the page + NRF_NVMC->ERASEPAGE = address; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + + +void nrf_nvmc_write_byte(uint32_t address, uint8_t value) +{ + uint32_t byte_shift = address & (uint32_t)0x03; + uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in. + uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3))); + value32 = value32 + ((uint32_t)value << (byte_shift << 3)); + + // Enable write. + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos); + __ISB(); + __DSB(); + + *(uint32_t*)address32 = value32; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos); + __ISB(); + __DSB(); +} + +void nrf_nvmc_write_word(uint32_t address, uint32_t value) +{ + // Enable write. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; + __ISB(); + __DSB(); + + *(uint32_t*)address = value; + wait_for_flash_ready(); + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes) +{ + uint32_t i; + for (i = 0; i < num_bytes; i++) + { + nrf_nvmc_write_byte(address + i,src[i]); + } +} + +void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words) +{ + uint32_t i; + + // Enable write. + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen; + __ISB(); + __DSB(); + + for (i = 0; i < num_words; i++) + { + ((uint32_t*)address)[i] = src[i]; + wait_for_flash_ready(); + } + + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren; + __ISB(); + __DSB(); +} + diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_nvmc.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_nvmc.h new file mode 100755 index 0000000..556672a --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_nvmc.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_NVMC_H__ +#define NRF_NVMC_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @defgroup nrf_nvmc_hal NVMC HAL + * @{ + * @ingroup nrf_nvmc + * @brief Hardware access layer for managing the Non-Volatile Memory Controller (NVMC) peripheral. + * + * This driver allows writing to the non-volatile memory (NVM) regions + * of the chip. In order to write to NVM the controller must be powered + * on and the relevant page must be erased. + * + */ + + +/** + * @brief Erase a page in flash. This is required before writing to any + * address in the page. + * + * @param address Start address of the page. + */ +void nrf_nvmc_page_erase(uint32_t address); + + +/** + * @brief Write a single byte to flash. + * + * The function reads the word containing the byte, and then + * rewrites the entire word. + * + * @param address Address to write to. + * @param value Value to write. + */ +void nrf_nvmc_write_byte(uint32_t address , uint8_t value); + + +/** + * @brief Write a 32-bit word to flash. + * @param address Address to write to. + * @param value Value to write. + */ +void nrf_nvmc_write_word(uint32_t address, uint32_t value); + + +/** + * @brief Write consecutive bytes to flash. + * + * @param address Address to write to. + * @param src Pointer to data to copy from. + * @param num_bytes Number of bytes in src to write. + */ +void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes); + + +/** + * @brief Write consecutive words to flash. + * + * @param address Address to write to. + * @param src Pointer to data to copy from. + * @param num_words Number of words in src to write. + */ +void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words); + + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_NVMC_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_pdm.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_pdm.h new file mode 100755 index 0000000..f9a37b9 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_pdm.h @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NRF_PDM_H_ +#define NRF_PDM_H_ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_pdm_hal PDM HAL + * @{ + * @ingroup nrf_pdm + * @brief Hardware access layer for managing the Pulse Density Modulation (PDM) peripheral. + */ + +#define NRF_PDM_GAIN_MINIMUM 0x00 +#define NRF_PDM_GAIN_DEFAULT 0x28 +#define NRF_PDM_GAIN_MAXIMUM 0x50 + +typedef uint8_t nrf_pdm_gain_t; + + +/** + * @brief PDM tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_PDM_TASK_START = offsetof(NRF_PDM_Type, TASKS_START), ///< Starts continuous PDM transfer. + NRF_PDM_TASK_STOP = offsetof(NRF_PDM_Type, TASKS_STOP) ///< Stops PDM transfer. +} nrf_pdm_task_t; + + +/** + * @brief PDM events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_PDM_EVENT_STARTED = offsetof(NRF_PDM_Type, EVENTS_STARTED), ///< PDM transfer has started. + NRF_PDM_EVENT_STOPPED = offsetof(NRF_PDM_Type, EVENTS_STOPPED), ///< PDM transfer has finished. + NRF_PDM_EVENT_END = offsetof(NRF_PDM_Type, EVENTS_END) ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM. +} nrf_pdm_event_t; + + +/** + * @brief PDM interrupt masks. + */ +typedef enum +{ + NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event. + NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event. + NRF_PDM_INT_END = PDM_INTENSET_END_Msk ///< Interrupt on EVENTS_END event. +} nrf_pdm_int_mask_t; + +/** + * @brief PDM clock frequency. + */ +typedef enum +{ + NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz. + NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz. + NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz. +} nrf_pdm_freq_t; + + +/** + * @brief PDM operation mode. + */ +typedef enum +{ + NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo, ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word. + NRF_PDM_MODE_MONO = PDM_MODE_OPERATION_Mono ///< Sample and store two successive Left samples (16 bit each) per RAM word. +} nrf_pdm_mode_t; + + +/** + * @brief PDM sampling mode. + */ +typedef enum +{ + NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling, ///< Left (or mono) is sampled on falling edge of PDM_CLK. + NRF_PDM_EDGE_LEFTRISING = PDM_MODE_EDGE_LeftRising ///< Left (or mono) is sampled on rising edge of PDM_CLK. +} nrf_pdm_edge_t; + + +/** + * @brief Function for triggering a PDM task. + * + * @param[in] pdm_task PDM task. + */ +__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_task)) = 0x1UL; +} + + +/** + * @brief Function for getting the address of a PDM task register. + * + * @param[in] pdm_task PDM task. + * + * @return Address of the specified PDM task. + */ +__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task) +{ + return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)pdm_task); +} + + +/** + * @brief Function for getting the state of a PDM event. + * + * @param[in] pdm_event PDM event. + * + * @return State of the specified PDM event. + */ +__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event); +} + + +/** + * @brief Function for clearing a PDM event. + * + * @param[in] pdm_event PDM event. + */ +__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)); + (void)dummy; +#endif +} + + +/** + * @brief Function for getting the address of a PDM event register. + * + * @param[in] pdm_event PDM event. + * + * @return Address of the specified PDM event. + */ +__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event) +{ + return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event); +} + + +/** + * @brief Function for enabling PDM interrupts. + * + * @param[in] pdm_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask) +{ + NRF_PDM->INTENSET = pdm_int_mask; +} + + +/** + * @brief Function for retrieving the state of PDM interrupts. + * + * @param[in] pdm_int_mask Interrupts to check. + * + * @retval true If all specified interrupts are enabled. + * @retval false If at least one of the given interrupts is not enabled. + */ +__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask) +{ + return (bool)(NRF_PDM->INTENSET & pdm_int_mask); +} + + +/** + * @brief Function for disabling interrupts. + * + * @param pdm_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask) +{ + NRF_PDM->INTENCLR = pdm_int_mask; +} + + +/** + * @brief Function for enabling the PDM peripheral. + * + * The PDM peripheral must be enabled before use. + */ +__STATIC_INLINE void nrf_pdm_enable(void) +{ + NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos); +} + + +/** + * @brief Function for disabling the PDM peripheral. + */ +__STATIC_INLINE void nrf_pdm_disable(void) +{ + NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Disabled << PDM_ENABLE_ENABLE_Pos); +} + + +/** + * @brief Function for checking if the PDM peripheral is enabled. + * + * @retval true If the PDM peripheral is enabled. + * @retval false If the PDM peripheral is not enabled. + */ +__STATIC_INLINE bool nrf_pdm_enable_check(void) +{ + return (NRF_PDM->ENABLE == (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos)); +} + + +/** + * @brief Function for setting the PDM operation mode. + * + * @param[in] pdm_mode PDM operation mode. + * @param[in] pdm_edge PDM sampling mode. + */ +__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge) +{ + NRF_PDM->MODE = ((pdm_mode << PDM_MODE_OPERATION_Pos) & PDM_MODE_OPERATION_Msk) + | ((pdm_edge << PDM_MODE_EDGE_Pos) & PDM_MODE_EDGE_Msk); +} + + +/** + * @brief Function for getting the PDM operation mode. + * + * @param[out] p_pdm_mode PDM operation mode. + * @param[out] p_pdm_edge PDM sampling mode. + */ +__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge) +{ + uint32_t mode = NRF_PDM->MODE; + *p_pdm_mode = (nrf_pdm_mode_t)((mode & PDM_MODE_OPERATION_Msk ) >> PDM_MODE_OPERATION_Pos); + *p_pdm_edge = (nrf_pdm_edge_t)((mode & PDM_MODE_EDGE_Msk ) >> PDM_MODE_EDGE_Pos); +} + + +/** + * @brief Function for setting the PDM clock frequency. + * + * @param[in] pdm_freq PDM clock frequency. + */ +__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq) +{ + NRF_PDM->PDMCLKCTRL = ((pdm_freq << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk); +} + + +/** + * @brief Function for getting the PDM clock frequency. + */ +__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void) +{ + return (nrf_pdm_freq_t) ((NRF_PDM->PDMCLKCTRL << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk); +} + + +/** + * @brief Function for setting up the PDM pins. + * + * @param[in] psel_clk CLK pin number. + * @param[in] psel_din DIN pin number. + */ +__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din) +{ + NRF_PDM->PSEL.CLK = psel_clk; + NRF_PDM->PSEL.DIN = psel_din; +} + +/** + * @brief Function for disconnecting the PDM pins. + */ +__STATIC_INLINE void nrf_pdm_psel_disconnect() +{ + NRF_PDM->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos) + & PDM_PSEL_CLK_CONNECT_Msk); + NRF_PDM->PSEL.DIN = ((PDM_PSEL_DIN_CONNECT_Disconnected << PDM_PSEL_DIN_CONNECT_Pos) + & PDM_PSEL_DIN_CONNECT_Msk); +} + + +/** + * @brief Function for setting the PDM gain. + * + * @param[in] gain_l Left channel gain. + * @param[in] gain_r Right channel gain. + */ +__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r) +{ + NRF_PDM->GAINL = gain_l; + NRF_PDM->GAINR = gain_r; +} + + +/** + * @brief Function for getting the PDM gain. + * + * @param[out] p_gain_l Left channel gain. + * @param[out] p_gain_r Right channel gain. + */ +__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r) +{ + *p_gain_l = NRF_PDM->GAINL; + *p_gain_r = NRF_PDM->GAINR; +} + + +/** + * @brief Function for setting the PDM sample buffer. + * + * @param[in] p_buffer Pointer to the RAM address where samples should be written with EasyDMA. + * @param[in] num Number of samples to allocate memory for in EasyDMA mode. + * + * The amount of allocated RAM depends on the operation mode. + * - For stereo mode: N 32-bit words. + * - For mono mode: Ceil(N/2) 32-bit words. + */ +__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num) +{ + NRF_PDM->SAMPLE.PTR = (uint32_t)p_buffer; + NRF_PDM->SAMPLE.MAXCNT = num; +} + +/** + * @brief Function for getting the current PDM sample buffer address. + * + * @return Pointer to the current sample buffer. + */ +__STATIC_INLINE uint32_t * nrf_pdm_buffer_get() +{ + return (uint32_t *)NRF_PDM->SAMPLE.PTR; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_PDM_H_ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_power.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_power.h new file mode 100755 index 0000000..b44e681 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_power.h @@ -0,0 +1,1036 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_POWER_H__ +#define NRF_POWER_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_power_hal POWER HAL + * @{ + * @ingroup nrf_power + * @brief Hardware access layer for managing the POWER peripheral. + */ + +#if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) +#define NRF_POWER_HAS_RAMSTATUS 1 +#else +#define NRF_POWER_HAS_RAMSTATUS 0 +#endif + +/** + * @name The implemented functionality + * @{ + * + * Macros that defines functionality that is implemented into POWER peripheral. + */ +#if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief The fact that sleep events are present + * + * In some MCUs there is possibility to process sleep entering and exiting + * events. + */ +#define NRF_POWER_HAS_SLEEPEVT 1 +#else +#define NRF_POWER_HAS_SLEEPEVT 0 +#endif + +#if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief The fact that RAMPOWER registers are present + * + * After nRF51, new way to manage RAM power was implemented. + * Special registers, one for every RAM block that makes it possible to + * power ON or OFF RAM segments and turn ON and OFF RAM retention in system OFF + * state. + */ +#define NRF_POWER_HAS_RAMPOWER_REGS 1 +#else +#define NRF_POWER_HAS_RAMPOWER_REGS 0 +#endif + +#if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Auxiliary definition to mark the fact that VDDH is present + * + * This definition can be used in a code to decide if the part with VDDH + * related settings should be implemented. + */ +#define NRF_POWER_HAS_VDDH 1 +#else +#define NRF_POWER_HAS_VDDH 0 +#endif + +#if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief The fact that power module manages USB regulator + * + * In devices that have USB, power peripheral manages also connection + * detection and USB power regulator, that converts 5 V to 3.3 V + * used by USBD peripheral. + */ +#define NRF_POWER_HAS_USBREG 1 +#else +#define NRF_POWER_HAS_USBREG 0 +#endif +/** @} */ + +/* ------------------------------------------------------------------------------------------------ + * Begin of automatically generated part + * ------------------------------------------------------------------------------------------------ + */ + +/** + * @brief POWER tasks + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode */ + NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR ), /**< Enable low power mode (variable latency) */ +}nrf_power_task_t; /*lint -restore */ + +/** + * @brief POWER events + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning */ +#if NRF_POWER_HAS_SLEEPEVT + NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep */ + NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT ), /**< CPU exited WFI/WFE sleep */ +#endif +#if NRF_POWER_HAS_USBREG + NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS */ + NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS */ + NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY ), /**< USB 3.3 V supply ready */ +#endif +}nrf_power_event_t; /*lint -restore */ + +/** + * @brief POWER interrupts + */ +typedef enum +{ + NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event */ +#if NRF_POWER_HAS_SLEEPEVT + NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event */ + NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk , /**< Write '1' to Enable interrupt for SLEEPEXIT event */ +#endif +#if NRF_POWER_HAS_USBREG + NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event */ + NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event */ + NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk , /**< Write '1' to Enable interrupt for USBPWRRDY event */ +#endif +}nrf_power_int_mask_t; + +/** + * @brief Function for activating a specific POWER task. + * + * @param task Task. + */ +__STATIC_INLINE void nrf_power_task_trigger(nrf_power_task_t task); + +/** + * @brief Function for returning the address of a specific POWER task register. + * + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_power_task_address_get(nrf_power_task_t task); + +/** + * @brief Function for clearing a specific event. + * + * @param event Event. + */ +__STATIC_INLINE void nrf_power_event_clear(nrf_power_event_t event); + +/** + * @brief Function for returning the state of a specific event. + * + * @param event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_power_event_check(nrf_power_event_t event); + +/** + * @brief Function for getting and clearing the state of specific event + * + * This function checks the state of the event and clears it. + * + * @param event Event. + * + * @retval true If the event was set. + * @retval false If the event was not set. + */ +__STATIC_INLINE bool nrf_power_event_get_and_clear(nrf_power_event_t event); + +/** + * @brief Function for returning the address of a specific POWER event register. + * + * @param event Event. + * + * @return Address. + */ +__STATIC_INLINE uint32_t nrf_power_event_address_get(nrf_power_event_t event); + +/** + * @brief Function for enabling selected interrupts. + * + * @param int_mask Interrupts mask. + */ +__STATIC_INLINE void nrf_power_int_enable(uint32_t int_mask); + +/** + * @brief Function for retrieving the state of selected interrupts. + * + * @param int_mask Interrupts mask. + * + * @retval true If any of selected interrupts is enabled. + * @retval false If none of selected interrupts is enabled. + */ +__STATIC_INLINE bool nrf_power_int_enable_check(uint32_t int_mask); + +/** + * @brief Function for retrieving the information about enabled interrupts. + * + * @return The flags of enabled interrupts. + */ +__STATIC_INLINE uint32_t nrf_power_int_enable_get(void); + +/** + * @brief Function for disabling selected interrupts. + * + * @param int_mask Interrupts mask. + */ +__STATIC_INLINE void nrf_power_int_disable(uint32_t int_mask); + + +/** @} */ /* End of nrf_power_hal */ + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +/* ------------------------------------------------------------------------------------------------ + * Internal functions + */ + +/** + * @internal + * @brief Internal function for getting task/event register address + * + * @oaram offset Offset of the register from the instance beginning + * + * @attention offset has to be modulo 4 value. In other case we can get hardware fault. + * @return Pointer to the register + */ +__STATIC_INLINE volatile uint32_t * nrf_power_regptr_get(uint32_t offset) +{ + return (volatile uint32_t *)(((uint8_t *)NRF_POWER) + (uint32_t)offset); +} + +/** + * @internal + * @brief Internal function for getting task/event register address - constant version + * + * @oaram offset Offset of the register from the instance beginning + * + * @attention offset has to be modulo 4 value. In other case we can get hardware fault. + * @return Pointer to the register + */ +__STATIC_INLINE volatile const uint32_t * nrf_power_regptr_get_c( + uint32_t offset) +{ + return (volatile const uint32_t *)(((uint8_t *)NRF_POWER) + + (uint32_t)offset); +} + +/* ------------------------------------------------------------------------------------------------ + * Interface functions definitions + */ + +void nrf_power_task_trigger(nrf_power_task_t task) +{ + *(nrf_power_regptr_get((uint32_t)task)) = 1UL; +} + +uint32_t nrf_power_task_address_get(nrf_power_task_t task) +{ + return (uint32_t)nrf_power_regptr_get_c((uint32_t)task); +} + +void nrf_power_event_clear(nrf_power_event_t event) +{ + *(nrf_power_regptr_get((uint32_t)event)) = 0UL; +} + +bool nrf_power_event_check(nrf_power_event_t event) +{ + return (bool)*nrf_power_regptr_get_c((uint32_t)event); +} + +bool nrf_power_event_get_and_clear(nrf_power_event_t event) +{ + bool ret = nrf_power_event_check(event); + if (ret) + { + nrf_power_event_clear(event); + } + return ret; +} + +uint32_t nrf_power_event_address_get(nrf_power_event_t event) +{ + return (uint32_t)nrf_power_regptr_get_c((uint32_t)event); +} + +void nrf_power_int_enable(uint32_t int_mask) +{ + NRF_POWER->INTENSET = int_mask; +} + +bool nrf_power_int_enable_check(uint32_t int_mask) +{ + return !!(NRF_POWER->INTENSET & int_mask); +} + +uint32_t nrf_power_int_enable_get(void) +{ + return NRF_POWER->INTENSET; +} + +void nrf_power_int_disable(uint32_t int_mask) +{ + NRF_POWER->INTENCLR = int_mask; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +/* ------------------------------------------------------------------------------------------------ + * End of automatically generated part + * ------------------------------------------------------------------------------------------------ + */ +/** + * @ingroup nrf_power_hal + * @{ + */ + +/** + * @brief Reset reason + */ +typedef enum +{ + NRF_POWER_RESETREAS_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, /*!< Bit mask of RESETPIN field. *///!< NRF_POWER_RESETREAS_RESETPIN_MASK + NRF_POWER_RESETREAS_DOG_MASK = POWER_RESETREAS_DOG_Msk , /*!< Bit mask of DOG field. */ //!< NRF_POWER_RESETREAS_DOG_MASK + NRF_POWER_RESETREAS_SREQ_MASK = POWER_RESETREAS_SREQ_Msk , /*!< Bit mask of SREQ field. */ //!< NRF_POWER_RESETREAS_SREQ_MASK + NRF_POWER_RESETREAS_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk , /*!< Bit mask of LOCKUP field. */ //!< NRF_POWER_RESETREAS_LOCKUP_MASK + NRF_POWER_RESETREAS_OFF_MASK = POWER_RESETREAS_OFF_Msk , /*!< Bit mask of OFF field. */ //!< NRF_POWER_RESETREAS_OFF_MASK +#if defined(POWER_RESETREAS_LPCOMP_Msk) || defined(__NRFX_DOXYGEN__) + NRF_POWER_RESETREAS_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk , /*!< Bit mask of LPCOMP field. */ //!< NRF_POWER_RESETREAS_LPCOMP_MASK +#endif + NRF_POWER_RESETREAS_DIF_MASK = POWER_RESETREAS_DIF_Msk , /*!< Bit mask of DIF field. */ //!< NRF_POWER_RESETREAS_DIF_MASK +#if defined(POWER_RESETREAS_NFC_Msk) || defined(__NRFX_DOXYGEN__) + NRF_POWER_RESETREAS_NFC_MASK = POWER_RESETREAS_NFC_Msk , /*!< Bit mask of NFC field. */ +#endif +#if defined(POWER_RESETREAS_VBUS_Msk) || defined(__NRFX_DOXYGEN__) + NRF_POWER_RESETREAS_VBUS_MASK = POWER_RESETREAS_VBUS_Msk , /*!< Bit mask of VBUS field. */ +#endif +}nrf_power_resetreas_mask_t; + +#if NRF_POWER_HAS_USBREG +/** + * @brief USBREGSTATUS register bit masks + * + * @sa nrf_power_usbregstatus_get + */ +typedef enum +{ + NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed */ + NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready */ +}nrf_power_usbregstatus_mask_t; +#endif + +#if NRF_POWER_HAS_RAMSTATUS +/** + * @brief RAM blocks numbers + * + * @sa nrf_power_ramblock_mask_t + * @note + * Ram blocks has to been used in nrf51. + * In new CPU ram is divided into segments and this functionality is depreciated. + * For the newer MCU see the PS for mapping between internal RAM and RAM blocks, + * because this mapping is not 1:1, and functions related to old style blocks + * should not be used. + */ +typedef enum +{ + NRF_POWER_RAMBLOCK0 = POWER_RAMSTATUS_RAMBLOCK0_Pos, + NRF_POWER_RAMBLOCK1 = POWER_RAMSTATUS_RAMBLOCK1_Pos, + NRF_POWER_RAMBLOCK2 = POWER_RAMSTATUS_RAMBLOCK2_Pos, + NRF_POWER_RAMBLOCK3 = POWER_RAMSTATUS_RAMBLOCK3_Pos +}nrf_power_ramblock_t; + +/** + * @brief RAM blocks masks + * + * @sa nrf_power_ramblock_t + */ +typedef enum +{ + NRF_POWER_RAMBLOCK0_MASK = POWER_RAMSTATUS_RAMBLOCK0_Msk, + NRF_POWER_RAMBLOCK1_MASK = POWER_RAMSTATUS_RAMBLOCK1_Msk, + NRF_POWER_RAMBLOCK2_MASK = POWER_RAMSTATUS_RAMBLOCK2_Msk, + NRF_POWER_RAMBLOCK3_MASK = POWER_RAMSTATUS_RAMBLOCK3_Msk +}nrf_power_ramblock_mask_t; +#endif // NRF_POWER_HAS_RAMSTATUS + +/** + * @brief RAM power state position of the bits + * + * @sa nrf_power_onoffram_mask_t + */ +typedef enum +{ + NRF_POWER_ONRAM0, /**< Keep RAM block 0 on or off in system ON Mode */ + NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */ + NRF_POWER_ONRAM1, /**< Keep RAM block 1 on or off in system ON Mode */ + NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */ + NRF_POWER_ONRAM2, /**< Keep RAM block 2 on or off in system ON Mode */ + NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */ + NRF_POWER_ONRAM3, /**< Keep RAM block 3 on or off in system ON Mode */ + NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */ +}nrf_power_onoffram_t; + +/** + * @brief RAM power state bit masks + * + * @sa nrf_power_onoffram_t + */ +typedef enum +{ + NRF_POWER_ONRAM0_MASK = 1U << NRF_POWER_ONRAM0, /**< Keep RAM block 0 on or off in system ON Mode */ + NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */ + NRF_POWER_ONRAM1_MASK = 1U << NRF_POWER_ONRAM1, /**< Keep RAM block 1 on or off in system ON Mode */ + NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */ + NRF_POWER_ONRAM2_MASK = 1U << NRF_POWER_ONRAM2, /**< Keep RAM block 2 on or off in system ON Mode */ + NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */ + NRF_POWER_ONRAM3_MASK = 1U << NRF_POWER_ONRAM3, /**< Keep RAM block 3 on or off in system ON Mode */ + NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */ +}nrf_power_onoffram_mask_t; + +/** + * @brief Power failure comparator thresholds + */ +typedef enum +{ + NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V */ + NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V */ + NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V */ + NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V */ +#if defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__) + NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7 V */ + NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8 V */ + NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V */ + NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V */ + NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V */ + NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V */ + NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V */ + NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V */ +#endif +}nrf_power_pof_thr_t; + +#if NRF_POWER_HAS_VDDH +/** + * @brief Power failure comparator thresholds for VDDH + */ +typedef enum +{ + NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V */ + NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V */ + NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V */ + NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V */ + NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V */ + NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V */ + NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V */ + NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V */ + NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V */ + NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V */ + NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V */ + NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V */ + NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V */ + NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V */ + NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V */ + NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V */ +}nrf_power_pof_thrvddh_t; + +/** + * @brief Main regulator status + */ +typedef enum +{ + NRF_POWER_MAINREGSTATUS_NORMAL = POWER_MAINREGSTATUS_MAINREGSTATUS_Normal, /**< Normal voltage mode. Voltage supplied on VDD. */ + NRF_POWER_MAINREGSTATUS_HIGH = POWER_MAINREGSTATUS_MAINREGSTATUS_High /**< High voltage mode. Voltage supplied on VDDH. */ +}nrf_power_mainregstatus_t; + +#endif /* NRF_POWER_HAS_VDDH */ + +#if NRF_POWER_HAS_RAMPOWER_REGS +/** + * @brief Bit positions for RAMPOWER register + * + * All possible bits described, even if they are not used in selected MCU. + */ +typedef enum +{ + /** Keep RAM section S0 ON in System ON mode */ + NRF_POWER_RAMPOWER_S0POWER = POWER_RAM_POWER_S0POWER_Pos, + NRF_POWER_RAMPOWER_S1POWER, /**< Keep RAM section S1 ON in System ON mode */ + NRF_POWER_RAMPOWER_S2POWER, /**< Keep RAM section S2 ON in System ON mode */ + NRF_POWER_RAMPOWER_S3POWER, /**< Keep RAM section S3 ON in System ON mode */ + NRF_POWER_RAMPOWER_S4POWER, /**< Keep RAM section S4 ON in System ON mode */ + NRF_POWER_RAMPOWER_S5POWER, /**< Keep RAM section S5 ON in System ON mode */ + NRF_POWER_RAMPOWER_S6POWER, /**< Keep RAM section S6 ON in System ON mode */ + NRF_POWER_RAMPOWER_S7POWER, /**< Keep RAM section S7 ON in System ON mode */ + NRF_POWER_RAMPOWER_S8POWER, /**< Keep RAM section S8 ON in System ON mode */ + NRF_POWER_RAMPOWER_S9POWER, /**< Keep RAM section S9 ON in System ON mode */ + NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode */ + NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode */ + NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode */ + NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode */ + NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode */ + NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode */ + + /** Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S0RETENTION = POWER_RAM_POWER_S0RETENTION_Pos, + NRF_POWER_RAMPOWER_S1RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S2RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S3RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S4RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S5RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S6RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S7RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S8RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S9RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF */ + NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF */ +}nrf_power_rampower_t; + +#if defined ( __CC_ARM ) +#pragma push +#pragma diag_suppress 66 +#endif +/** + * @brief Bit masks for RAMPOWER register + * + * All possible bits described, even if they are not used in selected MCU. + */ +typedef enum +{ + NRF_POWER_RAMPOWER_S0POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S0POWER , + NRF_POWER_RAMPOWER_S1POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S1POWER , + NRF_POWER_RAMPOWER_S2POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S2POWER , + NRF_POWER_RAMPOWER_S3POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S3POWER , + NRF_POWER_RAMPOWER_S4POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S4POWER , + NRF_POWER_RAMPOWER_S5POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S5POWER , + NRF_POWER_RAMPOWER_S7POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S7POWER , + NRF_POWER_RAMPOWER_S8POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S8POWER , + NRF_POWER_RAMPOWER_S9POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S9POWER , + NRF_POWER_RAMPOWER_S10POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S10POWER, + NRF_POWER_RAMPOWER_S11POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S11POWER, + NRF_POWER_RAMPOWER_S12POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S12POWER, + NRF_POWER_RAMPOWER_S13POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S13POWER, + NRF_POWER_RAMPOWER_S14POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S14POWER, + NRF_POWER_RAMPOWER_S15POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S15POWER, + + NRF_POWER_RAMPOWER_S0RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S0RETENTION , + NRF_POWER_RAMPOWER_S1RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S1RETENTION , + NRF_POWER_RAMPOWER_S2RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S2RETENTION , + NRF_POWER_RAMPOWER_S3RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S3RETENTION , + NRF_POWER_RAMPOWER_S4RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S4RETENTION , + NRF_POWER_RAMPOWER_S5RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S5RETENTION , + NRF_POWER_RAMPOWER_S7RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S7RETENTION , + NRF_POWER_RAMPOWER_S8RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S8RETENTION , + NRF_POWER_RAMPOWER_S9RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S9RETENTION , + NRF_POWER_RAMPOWER_S10RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S10RETENTION, + NRF_POWER_RAMPOWER_S11RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S11RETENTION, + NRF_POWER_RAMPOWER_S12RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S12RETENTION, + NRF_POWER_RAMPOWER_S13RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S13RETENTION, + NRF_POWER_RAMPOWER_S14RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S14RETENTION, + NRF_POWER_RAMPOWER_S15RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S15RETENTION, +}nrf_power_rampower_mask_t; +#if defined ( __CC_ARM ) +#pragma pop +#endif +#endif /* NRF_POWER_HAS_RAMPOWER_REGS */ + + +/** + * @brief Get reset reason mask + * + * Function returns the reset reason. + * Unless cleared, the RESETREAS register is cumulative. + * A field is cleared by writing '1' to it (see @ref nrf_power_resetreas_clear). + * If none of the reset sources are flagged, + * this indicates that the chip was reset from the on-chip reset generator, + * which indicates a power-on-reset or a brown out reset. + * + * @return The mask of reset reasons constructed with @ref nrf_power_resetreas_mask_t. + */ +__STATIC_INLINE uint32_t nrf_power_resetreas_get(void); + +/** + * @brief Clear selected reset reason field + * + * Function clears selected reset reason fields. + * + * @param[in] mask The mask constructed from @ref nrf_power_resetreas_mask_t enumerator values. + * @sa nrf_power_resetreas_get + */ +__STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask); + +#if NRF_POWER_HAS_RAMSTATUS +/** + * @brief Get RAMSTATUS register + * + * Returns the masks of RAM blocks that are powered ON. + * + * @return Value with bits sets according to masks in @ref nrf_power_ramblock_mask_t. + */ +__STATIC_INLINE uint32_t nrf_power_ramstatus_get(void); +#endif // NRF_POWER_HAS_RAMSTATUS + +/** + * @brief Go to system OFF + * + * This function puts the CPU into system off mode. + * The only way to wake up the CPU is by reset. + * + * @note This function never returns. + */ +__STATIC_INLINE void nrf_power_system_off(void); + +/** + * @brief Set power failure comparator configuration + * + * Sets power failure comparator threshold and enable/disable flag. + * + * @param enabled Set to true if power failure comparator should be enabled. + * @param thr Set the voltage threshold value. + * + * @note + * If VDDH settings is present in the device, this function would + * clear it settings (set to the lowest voltage). + * Use @ref nrf_power_pofcon_vddh_set function to set new value. + */ +__STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr); + +/** + * @brief Get power failure comparator configuration + * + * Get power failure comparator threshold and enable bit. + * + * @param[out] p_enabled Function would set this boolean variable to true + * if power failure comparator is enabled. + * The pointer can be NULL if we do not need this information. + * @return Threshold setting for power failure comparator + */ +__STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled); + +#if NRF_POWER_HAS_VDDH +/** + * @brief Set VDDH power failure comparator threshold + * + * @param thr Threshold to be set + */ +__STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr); + +/** + * @brief Get VDDH power failure comparator threshold + * + * @return VDDH threshold currently configured + */ +__STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void); +#endif + +/** + * @brief Set general purpose retention register + * + * @param val Value to be set in the register + */ +__STATIC_INLINE void nrf_power_gpregret_set(uint8_t val); + +/** + * @brief Get general purpose retention register + * + * @return The value from the register + */ +__STATIC_INLINE uint8_t nrf_power_gpregret_get(void); + +#if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Set general purpose retention register 2 + * + * @param val Value to be set in the register + * @note This register is not available in nrf51 MCU family + */ +__STATIC_INLINE void nrf_power_gpregret2_set(uint8_t val); + +/** + * @brief Get general purpose retention register 2 + * + * @return The value from the register + * @note This register is not available in all MCUs. + */ +__STATIC_INLINE uint8_t nrf_power_gpregret2_get(void); +#endif + +/** + * @brief Enable or disable DCDC converter + * + * @param enable Set true to enable or false to disable DCDC converter. + * + * @note + * If the device consist of high voltage power input (VDDH) this setting + * would relate to the converter on low voltage side (1.3 V output). + */ +__STATIC_INLINE void nrf_power_dcdcen_set(bool enable); + +/** + * @brief Get the state of DCDC converter + * + * @retval true Converter is enabled + * @retval false Converter is disabled + * + * @note + * If the device consist of high voltage power input (VDDH) this setting + * would relate to the converter on low voltage side (1.3 V output). + */ +__STATIC_INLINE bool nrf_power_dcdcen_get(void); + +#if NRF_POWER_HAS_RAMPOWER_REGS +/** + * @brief Turn ON sections in selected RAM block. + * + * This function turns ON sections in block and also block retention. + * + * @sa nrf_power_rampower_mask_t + * @sa nrf_power_rampower_mask_off + * + * @param block RAM block index. + * @param section_mask Mask of the sections created by merging + * @ref nrf_power_rampower_mask_t flags. + */ +__STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask); + +/** + * @brief Turn ON sections in selected RAM block. + * + * This function turns OFF sections in block and also block retention. + * + * @sa nrf_power_rampower_mask_t + * @sa nrf_power_rampower_mask_off + * + * @param block RAM block index. + * @param section_mask Mask of the sections created by merging + * @ref nrf_power_rampower_mask_t flags. + */ +__STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask); + +/** + * @brief Get the mask of ON and retention sections in selected RAM block. + * + * @param block RAM block index. + * @return Mask of sections state composed from @ref nrf_power_rampower_mask_t flags. + */ +__STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block); +#endif /* NRF_POWER_HAS_RAMPOWER_REGS */ + +#if NRF_POWER_HAS_VDDH +/** + * @brief Enable of disable DCDC converter on VDDH + * + * @param enable Set true to enable or false to disable DCDC converter. + */ +__STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable); + +/** + * @brief Get the state of DCDC converter on VDDH + * + * @retval true Converter is enabled + * @retval false Converter is disabled + */ +__STATIC_INLINE bool nrf_power_dcdcen_vddh_get(void); + +/** + * @brief Get main supply status + * + * @return Current main supply status + */ +__STATIC_INLINE nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void); +#endif /* NRF_POWER_HAS_VDDH */ + +#if NRF_POWER_HAS_USBREG +/** + * + * @return Get the whole USBREGSTATUS register + * + * @return The USBREGSTATUS register value. + * Use @ref nrf_power_usbregstatus_mask_t values for bit masking. + * + * @sa nrf_power_usbregstatus_vbusdet_get + * @sa nrf_power_usbregstatus_outrdy_get + */ +__STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void); + +/** + * @brief VBUS input detection status + * + * USBDETECTED and USBREMOVED events are derived from this information + * + * @retval false VBUS voltage below valid threshold + * @retval true VBUS voltage above valid threshold + * + * @sa nrf_power_usbregstatus_get + */ +__STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void); + +/** + * @brief USB supply output settling time elapsed + * + * @retval false USBREG output settling time not elapsed + * @retval true USBREG output settling time elapsed + * (same information as USBPWRRDY event) + * + * @sa nrf_power_usbregstatus_get + */ +__STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(void); +#endif /* NRF_POWER_HAS_USBREG */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrf_power_resetreas_get(void) +{ + return NRF_POWER->RESETREAS; +} + +__STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask) +{ + NRF_POWER->RESETREAS = mask; +} + +#if NRF_POWER_HAS_RAMSTATUS +__STATIC_INLINE uint32_t nrf_power_ramstatus_get(void) +{ + return NRF_POWER->RAMSTATUS; +} +#endif // NRF_POWER_HAS_RAMSTATUS + +__STATIC_INLINE void nrf_power_system_off(void) +{ + NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter; + __DSB(); + + /* Solution for simulated System OFF in debug mode */ + while (true) + { + __WFE(); + } +} + +__STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr) +{ + NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLD_Msk >> POWER_POFCON_THRESHOLD_Pos))); +#if NRF_POWER_HAS_VDDH + uint32_t pofcon = NRF_POWER->POFCON; + pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk); + pofcon |= +#else /* NRF_POWER_HAS_VDDH */ + NRF_POWER->POFCON = +#endif + (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) | + (enabled ? + (POWER_POFCON_POF_Enabled << POWER_POFCON_POF_Pos) + : + (POWER_POFCON_POF_Disabled << POWER_POFCON_POF_Pos)); +#if NRF_POWER_HAS_VDDH + NRF_POWER->POFCON = pofcon; +#endif +} + +__STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled) +{ + uint32_t pofcon = NRF_POWER->POFCON; + if (NULL != p_enabled) + { + (*p_enabled) = ((pofcon & POWER_POFCON_POF_Msk) >> POWER_POFCON_POF_Pos) + == POWER_POFCON_POF_Enabled; + } + return (nrf_power_pof_thr_t)((pofcon & POWER_POFCON_THRESHOLD_Msk) >> + POWER_POFCON_THRESHOLD_Pos); +} + +#if NRF_POWER_HAS_VDDH +__STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr) +{ + NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLDVDDH_Msk >> POWER_POFCON_THRESHOLDVDDH_Pos))); + uint32_t pofcon = NRF_POWER->POFCON; + pofcon &= ~POWER_POFCON_THRESHOLDVDDH_Msk; + pofcon |= (((uint32_t)thr) << POWER_POFCON_THRESHOLDVDDH_Pos); + NRF_POWER->POFCON = pofcon; +} + +__STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void) +{ + return (nrf_power_pof_thrvddh_t)((NRF_POWER->POFCON & + POWER_POFCON_THRESHOLDVDDH_Msk) >> POWER_POFCON_THRESHOLDVDDH_Pos); +} +#endif /* NRF_POWER_HAS_VDDH */ + +__STATIC_INLINE void nrf_power_gpregret_set(uint8_t val) +{ + NRF_POWER->GPREGRET = val; +} + +__STATIC_INLINE uint8_t nrf_power_gpregret_get(void) +{ + return NRF_POWER->GPREGRET; +} + +#if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__) +void nrf_power_gpregret2_set(uint8_t val) +{ + NRF_POWER->GPREGRET2 = val; +} + +__STATIC_INLINE uint8_t nrf_power_gpregret2_get(void) +{ + return NRF_POWER->GPREGRET2; +} +#endif + +__STATIC_INLINE void nrf_power_dcdcen_set(bool enable) +{ + NRF_POWER->DCDCEN = (enable ? + POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) << + POWER_DCDCEN_DCDCEN_Pos; +} + +__STATIC_INLINE bool nrf_power_dcdcen_get(void) +{ + return (NRF_POWER->DCDCEN & POWER_DCDCEN_DCDCEN_Msk) + == + (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos); +} + +#if NRF_POWER_HAS_RAMPOWER_REGS +__STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask) +{ + NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM)); + NRF_POWER->RAM[block].POWERSET = section_mask; +} + +__STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask) +{ + NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM)); + NRF_POWER->RAM[block].POWERCLR = section_mask; +} + +__STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block) +{ + NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM)); + return NRF_POWER->RAM[block].POWER; +} +#endif /* NRF_POWER_HAS_RAMPOWER_REGS */ + +#if NRF_POWER_HAS_VDDH +__STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable) +{ + NRF_POWER->DCDCEN0 = (enable ? + POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) << + POWER_DCDCEN0_DCDCEN_Pos; +} + +bool nrf_power_dcdcen_vddh_get(void) +{ + return (NRF_POWER->DCDCEN0 & POWER_DCDCEN0_DCDCEN_Msk) + == + (POWER_DCDCEN0_DCDCEN_Enabled << POWER_DCDCEN0_DCDCEN_Pos); +} + +nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void) +{ + return (nrf_power_mainregstatus_t)(((NRF_POWER->MAINREGSTATUS) & + POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) >> + POWER_MAINREGSTATUS_MAINREGSTATUS_Pos); +} +#endif /* NRF_POWER_HAS_VDDH */ + +#if NRF_POWER_HAS_USBREG +__STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void) +{ + return NRF_POWER->USBREGSTATUS; +} + +__STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void) +{ + return (nrf_power_usbregstatus_get() & + NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK) != 0; +} + +__STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(void) +{ + return (nrf_power_usbregstatus_get() & + NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK) != 0; +} +#endif /* NRF_POWER_HAS_USBREG */ + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_POWER_H__ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ppi.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ppi.h new file mode 100755 index 0000000..40f9124 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_ppi.h @@ -0,0 +1,515 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_PPI_H__ +#define NRF_PPI_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_ppi_hal PPI HAL + * @{ + * @ingroup nrf_ppi + * @brief Hardware access layer for managing the Programmable Peripheral Interconnect (PPI) + * channels. + */ + +#define NRF_PPI_TASK_SET (1UL) + +/** + * @enum nrf_ppi_channel_t + * @brief PPI channels. + */ +typedef enum +{ + NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */ + NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */ + NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */ + NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */ + NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */ + NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */ + NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */ + NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */ + NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */ + NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */ + NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */ + NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */ + NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */ + NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */ + NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */ + NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */ +#if (PPI_CH_NUM > 16) || defined(__NRFX_DOXYGEN__) + NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */ + NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */ + NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */ + NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */ +#endif + NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */ + NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */ + NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */ + NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */ + NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */ + NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */ + NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */ + NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */ + NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */ + NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */ + NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */ + NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */ +} nrf_ppi_channel_t; + +/** + * @enum nrf_ppi_channel_group_t + * @brief PPI channel groups. + */ +typedef enum +{ + NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */ + NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */ + NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */ + NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */ +#if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__) + NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */ + NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */ +#endif +} nrf_ppi_channel_group_t; + +/** + * @enum nrf_ppi_channel_include_t + * @brief Definition of which PPI channels belong to a group. + */ +typedef enum +{ + NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */ + NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */ +} nrf_ppi_channel_include_t; + +/** + * @enum nrf_ppi_channel_enable_t + * @brief Definition if a PPI channel is enabled. + */ +typedef enum +{ + NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */ + NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */ +} nrf_ppi_channel_enable_t; + +/** + * @enum nrf_ppi_task_t + * @brief PPI tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0 */ + NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */ + NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1 */ + NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */ + NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */ + NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */ + NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */ + NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */ +#if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__) + NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */ + NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */ + NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */ + NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */ +#endif + /*lint -restore*/ +} nrf_ppi_task_t; + +/** + * @brief Function for enabling a given PPI channel. + * + * @details This function enables only one channel. + * + * @param[in] channel Channel to enable. + * + * */ +__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel); + +/** + * @brief Function for disabling a given PPI channel. + * + * @details This function disables only one channel. + * + * @param[in] channel Channel to disable. + */ +__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel); + +/** + * @brief Function for checking if a given PPI channel is enabled. + * + * @details This function checks only one channel. + * + * @param[in] channel Channel to check. + * + * @retval NRF_PPI_CHANNEL_ENABLED If the channel is enabled. + * @retval NRF_PPI_CHANNEL_DISABLED If the channel is not enabled. + * + */ +__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel); + +/** + * @brief Function for disabling all PPI channels. + */ +__STATIC_INLINE void nrf_ppi_channel_disable_all(void); + +/** + * @brief Function for enabling multiple PPI channels. + * + * @param[in] mask Channel mask. + */ +__STATIC_INLINE void nrf_ppi_channels_enable(uint32_t mask); + +/** + * @brief Function for disabling multiple PPI channels. + * + * @param[in] mask Channel mask. + */ +__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask); + +/** + * @brief Function for setting up event and task endpoints for a given PPI channel. + * + * @param[in] eep Event register address. + * + * @param[in] tep Task register address. + * + * @param[in] channel Channel to which the given endpoints are assigned. + */ +__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t eep, + uint32_t tep); + +/** + * @brief Function for setting up the event endpoint for a given PPI channel. + * + * @param[in] eep Event register address. + * @param[in] channel Channel to which the given endpoint is assigned. + */ +__STATIC_INLINE void nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t eep); + +/** + * @brief Function for setting up the task endpoint for a given PPI channel. + * + * @param[in] tep Task register address. + * @param[in] channel Channel to which the given endpoint is assigned. + */ +__STATIC_INLINE void nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t tep); + + +#if defined(PPI_FEATURE_FORKS_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting up task endpoint for a given PPI fork. + * + * @param[in] fork_tep Task register address. + * + * @param[in] channel Channel to which the given fork endpoint is assigned. + */ +__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t fork_tep); + +/** + * @brief Function for setting up event and task endpoints for a given PPI channel and fork. + * + * @param[in] eep Event register address. + * + * @param[in] tep Task register address. + * + * @param[in] fork_tep Fork task register address (register value). + * + * @param[in] channel Channel to which the given endpoints are assigned. + */ +__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t eep, + uint32_t tep, + uint32_t fork_tep); +#endif + +/** + * @brief Function for including a PPI channel in a channel group. + * + * @details This function adds only one channel to the group. + * + * @param[in] channel Channel to be included in the group. + * + * @param[in] channel_group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel, + nrf_ppi_channel_group_t channel_group); + +/** + * @brief Function for including multiple PPI channels in a channel group. + * + * @details This function adds all specified channels to the group. + * + * @param[in] channel_mask Channels to be included in the group. + * + * @param[in] channel_group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask, + nrf_ppi_channel_group_t channel_group); + +/** + * @brief Function for removing a PPI channel from a channel group. + * + * @details This function removes only one channel from the group. + * + * @param[in] channel Channel to be removed from the group. + * + * @param[in] channel_group Channel group. + */ +__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel, + nrf_ppi_channel_group_t channel_group); + +/** + * @brief Function for removing multiple PPI channels from a channel group. + * + * @details This function removes all specified channels from the group. + * + * @param[in] channel_mask Channels to be removed from the group. + * + * @param[in] channel_group Channel group. + */ +__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask, + nrf_ppi_channel_group_t channel_group); + +/** + * @brief Function for removing all PPI channels from a channel group. + * + * @param[in] group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group); + +/** + * @brief Function for enabling a channel group. + * + * @param[in] group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group); + +/** + * @brief Function for disabling a channel group. + * + * @param[in] group Channel group. + * + */ +__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group); + +/** + * @brief Function for setting a PPI task. + * + * @param[in] ppi_task PPI task to set. + */ +__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task); + +/** + * @brief Function for returning the address of a specific PPI task register. + * + * @param[in] ppi_task PPI task. + */ +__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task); + +/** + * @brief Function for returning the PPI enable task address of a specific group. + * + * @param[in] group PPI group. + */ +__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group); + +/** + * @brief Function for returning the PPI disable task address of a specific group. + * + * @param[in] group PPI group. + */ +__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel) +{ + NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel); +} + +__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel) +{ + NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel); +} + +__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel) +{ + if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel))) + { + return NRF_PPI_CHANNEL_ENABLED; + } + else + { + return NRF_PPI_CHANNEL_DISABLED; + } +} + +__STATIC_INLINE void nrf_ppi_channel_disable_all(void) +{ + NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL); +} + +__STATIC_INLINE void nrf_ppi_channels_enable(uint32_t mask) +{ + NRF_PPI->CHENSET = mask; +} + +__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask) +{ + NRF_PPI->CHENCLR = mask; +} + +__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t eep, + uint32_t tep) +{ + NRF_PPI->CH[(uint32_t) channel].EEP = eep; + NRF_PPI->CH[(uint32_t) channel].TEP = tep; +} + +__STATIC_INLINE void nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t eep) +{ + NRF_PPI->CH[(uint32_t) channel].EEP = eep; +} + +__STATIC_INLINE void nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t tep) +{ + NRF_PPI->CH[(uint32_t) channel].TEP = tep; +} + +#if defined(PPI_FEATURE_FORKS_PRESENT) + +__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t fork_tep) +{ + NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep; +} + +__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel, + uint32_t eep, + uint32_t tep, + uint32_t fork_tep) +{ + nrf_ppi_channel_endpoint_setup(channel, eep, tep); + nrf_ppi_fork_endpoint_setup(channel, fork_tep); +} +#endif + +__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel, + nrf_ppi_channel_group_t channel_group) +{ + NRF_PPI->CHG[(uint32_t) channel_group] = + NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t) channel)); +} + +__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask, + nrf_ppi_channel_group_t channel_group) +{ + NRF_PPI->CHG[(uint32_t) channel_group] = + NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask); +} + +__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel, + nrf_ppi_channel_group_t channel_group) +{ + NRF_PPI->CHG[(uint32_t) channel_group] = + NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel)); +} + +__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask, + nrf_ppi_channel_group_t channel_group) +{ + NRF_PPI->CHG[(uint32_t) channel_group] = + NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask); +} + +__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group) +{ + NRF_PPI->CHG[(uint32_t) group] = 0; +} + +__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group) +{ + NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET; +} + +__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group) +{ + NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET; +} + +__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task) +{ + *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET; +} + +__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task) +{ + return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task); +} + +__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group) +{ + return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN; +} + +__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group) +{ + return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_PPI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_pwm.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_pwm.h new file mode 100755 index 0000000..74d2744 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_pwm.h @@ -0,0 +1,685 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_PWM_H__ +#define NRF_PWM_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_pwm_hal PWM HAL + * @{ + * @ingroup nrf_pwm + * @brief Hardware access layer for managing the Pulse Width Modulation (PWM) peripheral. + */ + +/** + * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set + * function call to specify that a given output channel shall not be + * connected to a physical pin. + */ +#define NRF_PWM_PIN_NOT_CONNECTED 0xFFFFFFFF + +/** + * @brief Number of channels in each Pointer to the peripheral registers structure. + */ +#define NRF_PWM_CHANNEL_COUNT 4 + + +/** + * @brief PWM tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_PWM_TASK_STOP = offsetof(NRF_PWM_Type, TASKS_STOP), ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback. + NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0. + NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1. + NRF_PWM_TASK_NEXTSTEP = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP) ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode. + /*lint -restore*/ +} nrf_pwm_task_t; + +/** + * @brief PWM events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_PWM_EVENT_STOPPED = offsetof(NRF_PWM_Type, EVENTS_STOPPED), ///< Response to STOP task, emitted when PWM pulses are no longer generated. + NRF_PWM_EVENT_SEQSTARTED0 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0. + NRF_PWM_EVENT_SEQSTARTED1 = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1. + NRF_PWM_EVENT_SEQEND0 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]), ///< Emitted at the end of every sequence 0 when its last value has been read from RAM. + NRF_PWM_EVENT_SEQEND1 = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]), ///< Emitted at the end of every sequence 1 when its last value has been read from RAM. + NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND), ///< Emitted at the end of each PWM period. + NRF_PWM_EVENT_LOOPSDONE = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE) ///< Concatenated sequences have been played the requested number of times. + /*lint -restore*/ +} nrf_pwm_event_t; + +/** + * @brief PWM interrupts. + */ +typedef enum +{ + NRF_PWM_INT_STOPPED_MASK = PWM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_PWM_INT_SEQSTARTED0_MASK = PWM_INTENSET_SEQSTARTED0_Msk, ///< Interrupt on SEQSTARTED[0] event. + NRF_PWM_INT_SEQSTARTED1_MASK = PWM_INTENSET_SEQSTARTED1_Msk, ///< Interrupt on SEQSTARTED[1] event. + NRF_PWM_INT_SEQEND0_MASK = PWM_INTENSET_SEQEND0_Msk, ///< Interrupt on SEQEND[0] event. + NRF_PWM_INT_SEQEND1_MASK = PWM_INTENSET_SEQEND1_Msk, ///< Interrupt on SEQEND[1] event. + NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event. + NRF_PWM_INT_LOOPSDONE_MASK = PWM_INTENSET_LOOPSDONE_Msk ///< Interrupt on LOOPSDONE event. +} nrf_pwm_int_mask_t; + +/** + * @brief PWM shortcuts. + */ +typedef enum +{ + NRF_PWM_SHORT_SEQEND0_STOP_MASK = PWM_SHORTS_SEQEND0_STOP_Msk, ///< Shortcut between SEQEND[0] event and STOP task. + NRF_PWM_SHORT_SEQEND1_STOP_MASK = PWM_SHORTS_SEQEND1_STOP_Msk, ///< Shortcut between SEQEND[1] event and STOP task. + NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task. + NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task. + NRF_PWM_SHORT_LOOPSDONE_STOP_MASK = PWM_SHORTS_LOOPSDONE_STOP_Msk ///< Shortcut between LOOPSDONE event and STOP task. +} nrf_pwm_short_mask_t; + +/** + * @brief PWM modes of operation. + */ +typedef enum +{ + NRF_PWM_MODE_UP = PWM_MODE_UPDOWN_Up, ///< Up counter (edge-aligned PWM duty cycle). + NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle). +} nrf_pwm_mode_t; + +/** + * @brief PWM base clock frequencies. + */ +typedef enum +{ + NRF_PWM_CLK_16MHz = PWM_PRESCALER_PRESCALER_DIV_1, ///< 16 MHz / 1 = 16 MHz. + NRF_PWM_CLK_8MHz = PWM_PRESCALER_PRESCALER_DIV_2, ///< 16 MHz / 2 = 8 MHz. + NRF_PWM_CLK_4MHz = PWM_PRESCALER_PRESCALER_DIV_4, ///< 16 MHz / 4 = 4 MHz. + NRF_PWM_CLK_2MHz = PWM_PRESCALER_PRESCALER_DIV_8, ///< 16 MHz / 8 = 2 MHz. + NRF_PWM_CLK_1MHz = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz. + NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz. + NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz. + NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz. +} nrf_pwm_clk_t; + +/** + * @brief PWM decoder load modes. + * + * The selected mode determines how the sequence data is read from RAM and + * spread to the compare registers. + */ +typedef enum +{ + NRF_PWM_LOAD_COMMON = PWM_DECODER_LOAD_Common, ///< 1st half word (16-bit) used in all PWM channels (0-3). + NRF_PWM_LOAD_GROUPED = PWM_DECODER_LOAD_Grouped, ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3. + NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3. + NRF_PWM_LOAD_WAVE_FORM = PWM_DECODER_LOAD_WaveForm ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter. +} nrf_pwm_dec_load_t; + +/** + * @brief PWM decoder next step modes. + * + * The selected mode determines when the next value from the active sequence + * is loaded. + */ +typedef enum +{ + NRF_PWM_STEP_AUTO = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times. + NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered. +} nrf_pwm_dec_step_t; + + +/** + * @brief Type used for defining duty cycle values for a sequence + * loaded in @ref NRF_PWM_LOAD_COMMON mode. + */ +typedef uint16_t nrf_pwm_values_common_t; + +/** + * @brief Structure for defining duty cycle values for a sequence + * loaded in @ref NRF_PWM_LOAD_GROUPED mode. + */ +typedef struct { + uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1). + uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3). +} nrf_pwm_values_grouped_t; + +/** + * @brief Structure for defining duty cycle values for a sequence + * loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode. + */ +typedef struct +{ + uint16_t channel_0; ///< Duty cycle value for channel 0. + uint16_t channel_1; ///< Duty cycle value for channel 1. + uint16_t channel_2; ///< Duty cycle value for channel 2. + uint16_t channel_3; ///< Duty cycle value for channel 3. +} nrf_pwm_values_individual_t; + +/** + * @brief Structure for defining duty cycle values for a sequence + * loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode. + */ +typedef struct { + uint16_t channel_0; ///< Duty cycle value for channel 0. + uint16_t channel_1; ///< Duty cycle value for channel 1. + uint16_t channel_2; ///< Duty cycle value for channel 2. + uint16_t counter_top; ///< Top value for the pulse generator counter. +} nrf_pwm_values_wave_form_t; + +/** + * @brief Union grouping pointers to arrays of duty cycle values applicable to + * various loading modes. + */ +typedef union { + nrf_pwm_values_common_t const * p_common; ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode. + nrf_pwm_values_grouped_t const * p_grouped; ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode. + nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode. + nrf_pwm_values_wave_form_t const * p_wave_form; ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode. + uint16_t const * p_raw; ///< Pointer providing raw access to the values. +} nrf_pwm_values_t; + +/** + * @brief Structure for defining a sequence of PWM duty cycles. + * + * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the + * provided duty cycle values are not copied. The @p values pointer is stored + * in the peripheral's internal register, and the values are loaded from RAM + * during the sequence playback. Therefore, you must ensure that the values + * do not change before and during the sequence playback (for example, + * the values cannot be placed in a local variable that is allocated on stack). + * If the sequence is played in a loop and the values should be updated + * before the next iteration, it is safe to modify them when the corresponding + * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0 + * or @ref NRF_PWM_EVENT_SEQEND1, respectively). + * + * @note The @p repeats and @p end_delay values (which are written to the + * SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral, + * respectively) are ignored at the end of a complex sequence + * playback, indicated by the LOOPSDONE event. + * See the @linkProductSpecification52 for more information. + */ +typedef struct +{ + nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM. + /**< This field is defined as an union of pointers + * to provide a convenient way to define duty + * cycle values in various loading modes + * (see @ref nrf_pwm_dec_load_t). + * In each value, the most significant bit (15) + * determines the polarity of the output and the + * others (14-0) compose the 15-bit value to be + * compared with the pulse generator counter. */ + uint16_t length; ///< Number of 16-bit values in the array pointed by @p values. + uint32_t repeats; ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode. + uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode. +} nrf_pwm_sequence_t; + +/** + * @brief Helper macro for calculating the number of 16-bit values in specified + * array of duty cycle values. + */ +#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t)) + + +/** + * @brief Function for activating a specific PWM task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg, + nrf_pwm_task_t task); + +/** + * @brief Function for getting the address of a specific PWM task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg, + nrf_pwm_task_t task); + +/** + * @brief Function for clearing a specific PWM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg, + nrf_pwm_event_t event); + +/** + * @brief Function for checking the state of a specific PWM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg, + nrf_pwm_event_t event); + +/** + * @brief Function for getting the address of a specific PWM event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg, + nrf_pwm_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pwm_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, + uint32_t pwm_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pwm_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, + uint32_t pwm_shorts_mask); + +/** + * @brief Function for setting the configuration of PWM shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pwm_shorts_mask Shortcuts configuration to set. + */ +__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, + uint32_t pwm_shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pwm_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, + uint32_t pwm_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pwm_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, + uint32_t pwm_int_mask); + +/** + * @brief Function for setting the configuration of PWM interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pwm_int_mask Interrupts configuration to set. + */ +__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, + uint32_t pwm_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pwm_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, + nrf_pwm_int_mask_t pwm_int); + +/** + * @brief Function for enabling the PWM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg); + +/** + * @brief Function for disabling the PWM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg); + +/** + * @brief Function for assigning pins to PWM output channels. + * + * Usage of all PWM output channels is optional. If a given channel is not + * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin + * number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] out_pins Array with pin numbers for individual PWM output channels. + */ +__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg, + uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]); + +/** + * @brief Function for configuring the PWM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] base_clock Base clock frequency. + * @param[in] mode Operating mode of the pulse generator counter. + * @param[in] top_value Value up to which the pulse generator counter counts. + */ +__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg, + nrf_pwm_clk_t base_clock, + nrf_pwm_mode_t mode, + uint16_t top_value); + +/** + * @brief Function for defining a sequence of PWM duty cycles. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] p_seq Pointer to the sequence definition. + */ +__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + nrf_pwm_sequence_t const * p_seq); + +/** + * @brief Function for modifying the pointer to the duty cycle values + * in the specified sequence. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] p_values Pointer to an array with duty cycle values. + */ +__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + uint16_t const * p_values); + +/** + * @brief Function for modifying the total number of duty cycle values + * in the specified sequence. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] length Number of duty cycle values. + */ +__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + uint16_t length); + +/** + * @brief Function for modifying the additional number of PWM periods spent + * on each duty cycle value in the specified sequence. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] refresh Number of additional PWM periods for each duty cycle value. + */ +__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + uint32_t refresh); + +/** + * @brief Function for modifying the additional time added after the sequence + * is played. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] seq_id Identifier of the sequence (0 or 1). + * @param[in] end_delay Number of PWM periods added at the end of the sequence. + */ +__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + uint32_t end_delay); + +/** + * @brief Function for setting the mode of loading sequence data from RAM + * and advancing the sequence. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] dec_load Mode of loading sequence data from RAM. + * @param[in] dec_step Mode of advancing the active sequence. + */ +__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg, + nrf_pwm_dec_load_t dec_load, + nrf_pwm_dec_step_t dec_step); + +/** + * @brief Function for setting the number of times the sequence playback + * should be performed. + * + * This function applies to two-sequence playback (concatenated sequence 0 and 1). + * A single sequence can be played back only once. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] loop_count Number of times to perform the sequence playback. + */ +__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, + uint16_t loop_count); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg, + nrf_pwm_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg, + nrf_pwm_task_t task) +{ + return ((uint32_t)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg, + nrf_pwm_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg, + nrf_pwm_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg, + nrf_pwm_event_t event) +{ + return ((uint32_t)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg, + uint32_t pwm_shorts_mask) +{ + p_reg->SHORTS |= pwm_shorts_mask; +} + +__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg, + uint32_t pwm_shorts_mask) +{ + p_reg->SHORTS &= ~(pwm_shorts_mask); +} + +__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg, + uint32_t pwm_shorts_mask) +{ + p_reg->SHORTS = pwm_shorts_mask; +} + +__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg, + uint32_t pwm_int_mask) +{ + p_reg->INTENSET = pwm_int_mask; +} + +__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg, + uint32_t pwm_int_mask) +{ + p_reg->INTENCLR = pwm_int_mask; +} + +__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg, + uint32_t pwm_int_mask) +{ + p_reg->INTEN = pwm_int_mask; +} + +__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg, + nrf_pwm_int_mask_t pwm_int) +{ + return (bool)(p_reg->INTENSET & pwm_int); +} + +__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg) +{ + p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg) +{ + p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg, + uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]) +{ + uint8_t i; + for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i) + { + p_reg->PSEL.OUT[i] = out_pins[i]; + } +} + +__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg, + nrf_pwm_clk_t base_clock, + nrf_pwm_mode_t mode, + uint16_t top_value) +{ + NRFX_ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk); + + p_reg->PRESCALER = base_clock; + p_reg->MODE = mode; + p_reg->COUNTERTOP = top_value; +} + +__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + nrf_pwm_sequence_t const * p_seq) +{ + NRFX_ASSERT(p_seq != NULL); + + nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw); + nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length); + nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats); + nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay); +} + +__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + uint16_t const * p_values) +{ + NRFX_ASSERT(seq_id <= 1); + NRFX_ASSERT(p_values != NULL); + p_reg->SEQ[seq_id].PTR = (uint32_t)p_values; +} + +__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + uint16_t length) +{ + NRFX_ASSERT(seq_id <= 1); + NRFX_ASSERT(length != 0); + NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk); + p_reg->SEQ[seq_id].CNT = length; +} + +__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + uint32_t refresh) +{ + NRFX_ASSERT(seq_id <= 1); + NRFX_ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk); + p_reg->SEQ[seq_id].REFRESH = refresh; +} + +__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg, + uint8_t seq_id, + uint32_t end_delay) +{ + NRFX_ASSERT(seq_id <= 1); + NRFX_ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk); + p_reg->SEQ[seq_id].ENDDELAY = end_delay; +} + +__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg, + nrf_pwm_dec_load_t dec_load, + nrf_pwm_dec_step_t dec_step) +{ + p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) | + ((uint32_t)dec_step << PWM_DECODER_MODE_Pos); +} + +__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg, + uint16_t loop_count) +{ + p_reg->LOOP = loop_count; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_PWM_H__ + diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_qdec.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_qdec.h new file mode 100755 index 0000000..e87c65d --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_qdec.h @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef NRF_QDEC_H__ +#define NRF_QDEC_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_qdec_hal QDEC HAL + * @{ + * @ingroup nrf_qdec + * @brief Hardware access layer for managing the Quadrature Decoder (QDEC) peripheral. + */ + +/** + * @brief This value can be provided as a parameter for the @ref nrf_qdec_pio_assign + * function call to specify that a LED signal shall not be use by the QDEC and + * connected to a physical pin. + */ +#define NRF_QDEC_LED_NOT_CONNECTED 0xFFFFFFFF + +/** + * @enum nrf_qdec_task_t + * @brief QDEC tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_QDEC_TASK_START = offsetof(NRF_QDEC_Type, TASKS_START), /**< Starting the quadrature decoder. */ + NRF_QDEC_TASK_STOP = offsetof(NRF_QDEC_Type, TASKS_STOP), /**< Stopping the quadrature decoder. */ + NRF_QDEC_TASK_READCLRACC = offsetof(NRF_QDEC_Type, TASKS_READCLRACC) /**< Reading and clearing ACC and ACCDBL registers. */ +} nrf_qdec_task_t; + +/** + * @enum nrf_qdec_event_t + * @brief QDEC events. + */ +typedef enum +{ + NRF_QDEC_EVENT_SAMPLERDY = offsetof(NRF_QDEC_Type, EVENTS_SAMPLERDY), /**< Event generated for every new sample. */ + NRF_QDEC_EVENT_REPORTRDY = offsetof(NRF_QDEC_Type, EVENTS_REPORTRDY), /**< Event generated for every new report. */ + NRF_QDEC_EVENT_ACCOF = offsetof(NRF_QDEC_Type, EVENTS_ACCOF) /**< Event generated for every accumulator overflow. */ +} nrf_qdec_event_t; /*lint -restore */ + +/** + * @enum nrf_qdec_short_mask_t + * @brief QDEC shortcuts. + */ +typedef enum +{ + NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk, /**< Shortcut between REPORTRDY event and READCLRACC task. */ + NRF_QDEC_SHORT_SAMPLERDY_STOP_MASK = QDEC_SHORTS_SAMPLERDY_STOP_Msk /**< Shortcut between SAMPLERDY event and STOP task. */ +} nrf_qdec_short_mask_t; + +/** + * @enum nrf_qdec_int_mask_t + * @brief QDEC interrupts. + */ +typedef enum +{ + NRF_QDEC_INT_SAMPLERDY_MASK = QDEC_INTENSET_SAMPLERDY_Msk, /**< Mask for enabling or disabling an interrupt on SAMPLERDY event. */ + NRF_QDEC_INT_REPORTRDY_MASK = QDEC_INTENSET_REPORTRDY_Msk, /**< Mask for enabling or disabling an interrupt on REPORTRDY event. */ + NRF_QDEC_INT_ACCOF_MASK = QDEC_INTENSET_ACCOF_Msk /**< Mask for enabling or disabling an interrupt on ACCOF event. */ +} nrf_qdec_int_mask_t; + +/** + * @enum nrf_qdec_enable_t + * @brief States of the enable bit. + */ +typedef enum +{ + NRF_QDEC_DISABLE = QDEC_ENABLE_ENABLE_Disabled, /**< Mask for disabling the QDEC periperal. When disabled, the QDEC decoder pins are not active. */ + NRF_QDEC_ENABLE = QDEC_ENABLE_ENABLE_Enabled /**< Mask for enabling the QDEC periperal. When enabled, the QDEC pins are active. */ +} nrf_qdec_enable_t; + + +/** + * @enum nrf_qdec_dbfen_t + * @brief States of the debounce filter enable bit. + */ +typedef enum +{ + NRF_QDEC_DBFEN_DISABLE = QDEC_DBFEN_DBFEN_Disabled, /**< Mask for disabling the debounce filter. */ + NRF_QDEC_DBFEN_ENABLE = QDEC_DBFEN_DBFEN_Enabled /**< Mask for enabling the debounce filter. */ +} nrf_qdec_dbfen_t; + +/** + * @enum nrf_qdec_ledpol_t + * @brief Active LED polarity. + */ +typedef enum +{ + NRF_QDEC_LEPOL_ACTIVE_LOW = QDEC_LEDPOL_LEDPOL_ActiveLow, /**< QDEC LED active on output pin low. */ + NRF_QDEC_LEPOL_ACTIVE_HIGH = QDEC_LEDPOL_LEDPOL_ActiveHigh /**< QDEC LED active on output pin high. */ +} nrf_qdec_ledpol_t; + + +/** + * @enum nrf_qdec_sampleper_t + * @brief Available sampling periods. + */ +typedef enum +{ + NRF_QDEC_SAMPLEPER_128us = QDEC_SAMPLEPER_SAMPLEPER_128us, /**< QDEC sampling period 128 microseconds. */ + NRF_QDEC_SAMPLEPER_256us = QDEC_SAMPLEPER_SAMPLEPER_256us, /**< QDEC sampling period 256 microseconds. */ + NRF_QDEC_SAMPLEPER_512us = QDEC_SAMPLEPER_SAMPLEPER_512us, /**< QDEC sampling period 512 microseconds. */ + NRF_QDEC_SAMPLEPER_1024us = QDEC_SAMPLEPER_SAMPLEPER_1024us, /**< QDEC sampling period 1024 microseconds. */ + NRF_QDEC_SAMPLEPER_2048us = QDEC_SAMPLEPER_SAMPLEPER_2048us, /**< QDEC sampling period 2048 microseconds. */ + NRF_QDEC_SAMPLEPER_4096us = QDEC_SAMPLEPER_SAMPLEPER_4096us, /**< QDEC sampling period 4096 microseconds. */ + NRF_QDEC_SAMPLEPER_8192us = QDEC_SAMPLEPER_SAMPLEPER_8192us, /**< QDEC sampling period 8192 microseconds. */ + NRF_QDEC_SAMPLEPER_16384us = QDEC_SAMPLEPER_SAMPLEPER_16384us /**< QDEC sampling period 16384 microseconds. */ +} nrf_qdec_sampleper_t; + +/** + * @enum nrf_qdec_reportper_t + * @brief Available report periods. + */ +typedef enum +{ + NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */ + NRF_QDEC_REPORTPER_40 = QDEC_REPORTPER_REPORTPER_40Smpl, /**< QDEC report period 40 samples. */ + NRF_QDEC_REPORTPER_80 = QDEC_REPORTPER_REPORTPER_80Smpl, /**< QDEC report period 80 samples. */ + NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */ + NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */ + NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */ + NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */ + NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */ + NRF_QDEC_REPORTPER_DISABLED /**< QDEC reporting disabled. */ +} nrf_qdec_reportper_t; + +/** + * @brief Function for enabling QDEC. + */ +__STATIC_INLINE void nrf_qdec_enable(void) +{ + NRF_QDEC->ENABLE = NRF_QDEC_ENABLE; +} + + +/** + * @brief Function for disabling QDEC. + */ +__STATIC_INLINE void nrf_qdec_disable(void) +{ + NRF_QDEC->ENABLE = NRF_QDEC_DISABLE; +} + + +/** + * @brief Function for returning the enable state of QDEC. + * @return State of the register. + */ +__STATIC_INLINE uint32_t nrf_qdec_enable_get(void) +{ + return NRF_QDEC->ENABLE; +} + + +/** + * @brief Function for enabling QDEC interrupts by mask. + * @param[in] qdec_int_mask Sources of the interrupts to enable. + */ +__STATIC_INLINE void nrf_qdec_int_enable(uint32_t qdec_int_mask) +{ + NRF_QDEC->INTENSET = qdec_int_mask; // writing 0 has no effect +} + + +/** + * @brief Function for disabling QDEC interrupts by mask. + * @param[in] qdec_int_mask Sources of the interrupts to disable. + * + */ +__STATIC_INLINE void nrf_qdec_int_disable(uint32_t qdec_int_mask) +{ + NRF_QDEC->INTENCLR = qdec_int_mask; // writing 0 has no effect +} + + +/** + * @brief Function for getting the enabled interrupts of the QDEC. + */ +__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t qdec_int_mask) +{ + return NRF_QDEC->INTENSET & qdec_int_mask; // when read this register will return the value of INTEN. +} + + +/** + * @brief Function for enabling the debouncing filter of the QED. + */ +__STATIC_INLINE void nrf_qdec_dbfen_enable(void) +{ + NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_ENABLE; +} + + +/** + * @brief Function for disabling the debouncing filter of the QED. + */ +__STATIC_INLINE void nrf_qdec_dbfen_disable(void) +{ + NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_DISABLE; +} + + +/** + * @brief Function for getting the state of the QDEC's debouncing filter. + * @retval NRF_QDEC_DBFEN_DISABLE If the debouncing filter is disabled. + * @retval NRF_QDEC_DBFEN_ENABLE If the debouncing filter is enabled. + */ +__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void) +{ + return NRF_QDEC->DBFEN; +} + + +/** + * @brief Function for assigning QDEC pins. + * @param[in] psela Pin number. + * @param[in] pselb Pin number. + * @param[in] pselled Pin number. + */ +__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled) +{ + NRF_QDEC->PSELA = psela; + NRF_QDEC->PSELB = pselb; + NRF_QDEC->PSELLED = pselled; + +} + +/** + * @brief Function for setting a specific QDEC task. + * @param[in] qdec_task QDEC task to be set. + */ +__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task) ) = 1; +} + + +/** + * @brief Function for retrieving the address of a QDEC task register. + * @param[in] qdec_task QDEC task. + */ +__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t qdec_task) +{ + return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task); +} + + +/** + * @brief Function for clearing a specific QDEC event. + * @param[in] qdec_event QDEC event to clear. + */ +__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t qdec_event) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event) ) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_QDEC + qdec_event)); + (void)dummy; +#endif +} + + +/** + * @brief Function for retrieving the state of a specific QDEC event. + * @return State of the QDEC event. + */ +__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t qdec_event) +{ + return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event); +} + + +/** + * @brief Function for retrieving the address of a specific QDEC event register. + * @param[in] qdec_event QDEC event. + * @return Address of the specified QDEC event. + */ +__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t qdec_event) +{ + return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event); +} + + +/** + * @brief Function for setting QDEC shortcuts. + * @param[in] qdec_short_mask QDEC shortcut by mask. + */ +__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t qdec_short_mask) +{ + NRF_QDEC->SHORTS |= qdec_short_mask; +} + + +/** + * @brief Function for clearing shortcuts of the QDEC by mask. + * @param[in] qdec_short_mask QDEC shortcute to be cleared. + */ +__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t qdec_short_mask) +{ + NRF_QDEC->SHORTS &= ~qdec_short_mask; +} + + +/** + * @brief Function for retrieving the value of QDEC's SAMPLEPER register. + * @return Value of the SAMPLEPER register. + */ +__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void) +{ + return NRF_QDEC->SAMPLEPER; +} + + +/** + * @brief Function for converting the value of QDEC's SAMPLE PERIOD to microseconds. + * @retval sampling period in microseconds. + */ +__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper) +{ + return (1 << (7 + sampleper)); +} + +/** + * @brief Function for setting the value of QDEC's SAMPLEPER register. + * @param[in] sample_per Sampling period. + */ +__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per) +{ + NRF_QDEC->SAMPLEPER = sample_per; +} + + +/** + * @brief Function for retrieving the value of QDEC's SAMPLE register. + * @return Value of the SAMPLE register. + */ +__STATIC_INLINE int32_t nrf_qdec_sample_get(void) +{ + return NRF_QDEC->SAMPLE; +} + + +/** + * @brief Function for retrieving the value of QDEC's ACC register. + * @return Value of the ACC register. + */ +__STATIC_INLINE int32_t nrf_qdec_acc_get(void) +{ + return NRF_QDEC->ACC; +} + + +/** + * @brief Function for retrieving the value of QDEC's ACCREAD register. + * @return Value of the ACCREAD register. + */ +__STATIC_INLINE int32_t nrf_qdec_accread_get(void) +{ + return NRF_QDEC->ACCREAD; +} + + +/** + * @brief Function for retrieving the value of QDEC's ACCDBL register. + * @return Value of the ACCDBL register. + */ +__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void) +{ + return NRF_QDEC->ACCDBL; +} + + +/** + * @brief Function for retrieving the value of QDEC's ACCDBLREAD register. + * @return Value of the ACCDBLREAD register. + */ +__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void) +{ + return NRF_QDEC->ACCDBLREAD; +} + + +/** + * @brief Function for setting how long the LED is switched on before sampling. + * @param[in] time_us Time (in microseconds) how long the LED is switched on before sampling. + */ +__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us) +{ + NRF_QDEC->LEDPRE = time_us; +} + + +/** + * @brief Function for retrieving how long the LED is switched on before sampling. + * @retval time_us Time (in microseconds) how long the LED is switched on before sampling. + */ +__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void) +{ + return NRF_QDEC->LEDPRE; +} + + +/** + * @brief Function for setting the report period (in samples). + * @param[in] reportper Number of samples. + */ +__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper) +{ + NRF_QDEC->REPORTPER = reportper; +} + + +/** + * @brief Function for retrieving the report period. + * @retval reportper Number of samples as encoded in the register. + */ +__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void) +{ + return NRF_QDEC->REPORTPER; +} + + +/** + * @brief Function for retrieving the value of QDEC's SAMPLEPER register. + * @param [in] reportper Reportper to be converted to amount of samples per report. + + */ +__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper) +{ + return (reportper == NRF_QDEC_REPORTPER_10) ? 10 : reportper * 40; +} + + +/** + * @brief Function for setting the active level for the LED. + * @param[in] pol Active level for the LED. + */ +__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol) +{ + NRF_QDEC->LEDPOL = pol; +} + + +/** + * @brief Function for retrieving the active level for the LED. + * @return Active level for the LED. + */ +__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void) +{ + return NRF_QDEC->LEDPOL; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_qspi.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_qspi.h new file mode 100755 index 0000000..57b2c0c --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_qspi.h @@ -0,0 +1,769 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_QSPI_H__ +#define NRF_QSPI_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_qspi_hal QSPI HAL + * @{ + * @ingroup nrf_qspi + * @brief Hardware access layer for managing the QSPI peripheral. + */ + +/** + * @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set + * function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3) + * will not be connected to a physical pin. + */ +#define NRF_QSPI_PIN_NOT_CONNECTED 0xFF + +/** + * @brief Macro for setting proper values to pin registers. + */ + +#define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin) + +/** + * @brief QSPI tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */ + NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */ + NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */ + NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */ + NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE), /**< Deactivate the QSPI interface. */ + /*lint -restore*/ +} nrf_qspi_task_t; + +/** + * @brief QSPI events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */ + /*lint -restore*/ +} nrf_qspi_event_t; + +/** + * @brief QSPI interrupts. + */ +typedef enum +{ + NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */ +} nrf_qspi_int_mask_t; + +/** + * @brief QSPI frequency divider values. + */ +typedef enum +{ + NRF_QSPI_FREQ_32MDIV1, /**< 32.0 MHz. */ + NRF_QSPI_FREQ_32MDIV2, /**< 16.0 MHz. */ + NRF_QSPI_FREQ_32MDIV3, /**< 10.6 MHz. */ + NRF_QSPI_FREQ_32MDIV4, /**< 8.00 MHz. */ + NRF_QSPI_FREQ_32MDIV5, /**< 6.40 MHz. */ + NRF_QSPI_FREQ_32MDIV6, /**< 5.33 MHz. */ + NRF_QSPI_FREQ_32MDIV7, /**< 4.57 MHz. */ + NRF_QSPI_FREQ_32MDIV8, /**< 4.00 MHz. */ + NRF_QSPI_FREQ_32MDIV9, /**< 3.55 MHz. */ + NRF_QSPI_FREQ_32MDIV10, /**< 3.20 MHz. */ + NRF_QSPI_FREQ_32MDIV11, /**< 2.90 MHz. */ + NRF_QSPI_FREQ_32MDIV12, /**< 2.66 MHz. */ + NRF_QSPI_FREQ_32MDIV13, /**< 2.46 MHz. */ + NRF_QSPI_FREQ_32MDIV14, /**< 2.29 MHz. */ + NRF_QSPI_FREQ_32MDIV15, /**< 2.13 MHz. */ + NRF_QSPI_FREQ_32MDIV16, /**< 2.00 MHz. */ +} nrf_qspi_frequency_t; + +/** + * @brief Interface configuration for a read operation. + */ +typedef enum +{ + NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */ + NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */ + NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */ + NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */ + NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */ +} nrf_qspi_readoc_t; + +/** + * @brief Interface configuration for a write operation. + */ +typedef enum +{ + NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */ + NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */ + NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */ + NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */ +} nrf_qspi_writeoc_t; + +/** + * @brief Interface configuration for addressing mode. + */ +typedef enum +{ + NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */ + NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */ +} nrf_qspi_addrmode_t; + +/** + * @brief QSPI SPI mode. Polarization and phase configuration. + */ +typedef enum +{ + NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */ + NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */ +} nrf_qspi_spi_mode_t; + +/** + * @brief Addressing configuration mode. + */ +typedef enum +{ + NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */ + NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */ + NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */ + NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */ +} nrf_qspi_addrconfig_mode_t; + +/** + * @brief Erasing data length. + */ +typedef enum +{ + NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */ + NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */ + NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */ +} nrf_qspi_erase_len_t; + +/** + * @brief Custom instruction length. + */ +typedef enum +{ + NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */ + NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */ + NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */ + NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */ + NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */ + NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */ + NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */ + NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */ + NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */ +} nrf_qspi_cinstr_len_t; + +/** + * @brief Pins configuration. + */ +typedef struct +{ + uint8_t sck_pin; /**< SCK pin number. */ + uint8_t csn_pin; /**< Chip select pin number. */ + uint8_t io0_pin; /**< IO0/MOSI pin number. */ + uint8_t io1_pin; /**< IO1/MISO pin number. */ + uint8_t io2_pin; /**< IO2 pin number (optional). + * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed. + */ + uint8_t io3_pin; /**< IO3 pin number (optional). + * Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed. + */ +} nrf_qspi_pins_t; + +/** + * @brief Custom instruction configuration. + */ +typedef struct +{ + uint8_t opcode; /**< Opcode used in custom instruction transmission. */ + nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */ + bool io2_level; /**< I/O line level during transmission. */ + bool io3_level; /**< I/O line level during transmission. */ + bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */ + bool wren; /**< Send write enable before instruction. */ +} nrf_qspi_cinstr_conf_t; + +/** + * @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set + */ +typedef struct +{ + uint8_t opcode; /**< Opcode used to enter proper addressing mode. */ + uint8_t byte0; /**< Byte following the opcode. */ + uint8_t byte1; /**< Byte following byte0. */ + nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */ + bool wipwait; /**< Enable/disable waiting for complete operation execution. */ + bool wren; /**< Send write enable before instruction. */ +} nrf_qspi_addrconfig_conf_t; + +/** + * @brief Structure with QSPI protocol interface configuration. + */ +typedef struct +{ + nrf_qspi_readoc_t readoc; /**< Read operation code. */ + nrf_qspi_writeoc_t writeoc; /**< Write operation code. */ + nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */ + bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */ +} nrf_qspi_prot_conf_t; + +/** + * @brief QSPI physical interface configuration. + */ +typedef struct +{ + uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */ + bool dpmen; /**< Enable the DPM feature. */ + nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */ + nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as enum @ref nrf_qspi_frequency_t. */ +} nrf_qspi_phy_conf_t; + +/** + * @brief Function for activating a specific QSPI task. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task); + +/** + * @brief Function for getting the address of a specific QSPI task register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_task_t task); + +/** + * @brief Function for clearing a specific QSPI event. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_event Event to clear. + */ +__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event); + +/** + * @brief Function for checking the state of a specific SPI event. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event); + +/** + * @brief Function for getting the address of a specific QSPI event register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_event_t qspi_event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] qspi_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, + nrf_qspi_int_mask_t qspi_int); + +/** + * @brief Function for enabling the QSPI peripheral. + * + * @param[in] p_reg Pointer to the peripheral register structure. + */ +__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg); + +/** + * @brief Function for disabling the QSPI peripheral. + * + * @param[in] p_reg Pointer to the peripheral register structure. + */ +__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg); + +/** + * @brief Function for configuring QSPI pins. + * + * If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t. + */ +__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_pins_t * p_pins); + +/** + * @brief Function for setting the QSPI XIPOFFSET register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] xip_offset Address offset in the external memory for Execute in Place operation. + */ +__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg, + uint32_t xip_offset); + +/** + * @brief Function for setting the QSPI IFCONFIG0 register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_config Pointer to the QSPI protocol interface configuration structure. See @ref nrf_qspi_prot_conf_t. + */ +__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_prot_conf_t * p_config); + +/** + * @brief Function for setting the QSPI IFCONFIG1 register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_config Pointer to the QSPI physical interface configuration structure. See @ref nrf_qspi_phy_conf_t. + */ +__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_phy_conf_t * p_config); + +/** + * @brief Function for setting the QSPI ADDRCONF register. + * + * Function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure + * is sent during the start of the peripheral. Remember that the reset instruction can set + * addressing mode to default in the memory device. If memory reset is necessary before configuring + * the addressing mode, use custom instruction feature instead of this function. + * Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions + * using a custom instruction feature (reset enable and then reset), set proper addressing mode + * using the custom instruction feature. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_config Pointer to the addressing mode configuration structure. See @ref nrf_qspi_addrconfig_conf_t. +*/ +__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_addrconfig_conf_t * p_config); + +/** + * @brief Function for setting write data into the peripheral register (without starting the process). + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_buffer Pointer to the writing buffer. + * @param[in] length Lenght of the writing data. + * @param[in] dest_addr Address in memory to write to. + */ +__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg, + void const * p_buffer, + uint32_t length, + uint32_t dest_addr); + +/** + * @brief Function for setting read data into the peripheral register (without starting the process). + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[out] p_buffer Pointer to the reading buffer. + * @param[in] length Length of the read data. + * @param[in] src_addr Address in memory to read from. + */ +__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg, + void * p_buffer, + uint32_t length, + uint32_t src_addr); + +/** + * @brief Function for setting erase data into the peripheral register (without starting the process). + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes. + * @param[in] len Size of erasing area. + */ +__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg, + uint32_t erase_addr, + nrf_qspi_erase_len_t len); + +/** + * @brief Function for getting the peripheral status register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * + * @return Peripheral status register. + */ +__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg); + +/** + * @brief Function for getting the device status register stored in the peripheral status register. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * + * @return Device status register (lower byte). + */ +__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg); + +/** + * @brief Function for checking if the peripheral is busy or not. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * + * @retval true If QSPI is busy. + * @retval false If QSPI is ready. + */ +__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg); + +/** + * @brief Function for setting registers sending with custom instruction transmission. + * + * This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument + * (sending only opcode without data). + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] length Length of the custom instruction data. + * @param[in] p_tx_data Pointer to the data to send with the custom instruction. + */ +__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg, + nrf_qspi_cinstr_len_t length, + void const * p_tx_data); + +/** + * @brief Function for getting data from register after custom instruction transmission. + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] length Length of the custom instruction data. + * @param[in] p_rx_data Pointer to the reading buffer. + */ +__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_cinstr_len_t length, + void * p_rx_data); + +/** + * @brief Function for sending custom instruction to external memory. + * + * @param[in] p_reg Pointer to the peripheral register structure. + * @param[in] p_config Pointer to the custom instruction configuration structure. See @ref nrf_qspi_cinstr_conf_t. + */ + +__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg, + const nrf_qspi_cinstr_conf_t * p_config); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_task_t task) +{ + return ((uint32_t)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t qspi_event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event)) = 0x0UL; +} + +__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t qspi_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event); +} + +__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_event_t qspi_event) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)qspi_event); +} + +__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask) +{ + p_reg->INTENSET = qspi_int_mask; +} + +__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t qspi_int_mask) +{ + p_reg->INTENCLR = qspi_int_mask; +} + +__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg, + nrf_qspi_int_mask_t qspi_int) +{ + return (bool)(p_reg->INTENSET & qspi_int); +} + +__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg) +{ + p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg) +{ + p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, const nrf_qspi_pins_t * p_pins) +{ + p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin); + p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin); + p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin); + p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin); + p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin); + p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin); +} + +__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg, + uint32_t xip_offset) +{ + p_reg->XIPOFFSET = xip_offset; +} + +__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_prot_conf_t * p_config) +{ + uint32_t config = p_config->readoc; + config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos; + config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos; + config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos; + + p_reg->IFCONFIG0 = config; +} + +__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_phy_conf_t * p_config) +{ + // IFCONFIG1 mask for reserved fields in the register. + uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00; + config |= p_config->sck_delay; + config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos; + config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos; + config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos; + + p_reg->IFCONFIG1 = config; +} + +__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg, + const nrf_qspi_addrconfig_conf_t * p_config) +{ + uint32_t config = p_config->opcode; + config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos; + config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos; + config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos; + config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos; + config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos; + + p_reg->ADDRCONF = config; +} + +__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg, + void const * p_buffer, + uint32_t length, + uint32_t dest_addr) +{ + p_reg->WRITE.DST = dest_addr; + p_reg->WRITE.SRC = (uint32_t) p_buffer; + p_reg->WRITE.CNT = length; +} + +__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg, + void * p_buffer, + uint32_t length, + uint32_t src_addr) +{ + p_reg->READ.SRC = src_addr; + p_reg->READ.DST = (uint32_t) p_buffer; + p_reg->READ.CNT = length; +} + +__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg, + uint32_t erase_addr, + nrf_qspi_erase_len_t len) +{ + p_reg->ERASE.PTR = erase_addr; + p_reg->ERASE.LEN = len; +} + +__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg) +{ + return p_reg->STATUS; +} + +__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg) +{ + return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos; +} + +__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg) +{ + return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >> + QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY; +} + +__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg, + nrf_qspi_cinstr_len_t length, + void const * p_tx_data) +{ + uint32_t reg = 0; + uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data; + + // Load custom instruction. + switch (length) + { + case NRF_QSPI_CINSTR_LEN_9B: + reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_8B: + reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_7B: + reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_6B: + reg |= ((uint32_t)p_tx_data_8[4]); + p_reg->CINSTRDAT1 = reg; + reg = 0; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_5B: + reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_4B: + reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_3B: + reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_2B: + reg |= ((uint32_t)p_tx_data_8[0]); + p_reg->CINSTRDAT0 = reg; + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_1B: + /* Send only opcode. Case to avoid compiler warnings. */ + break; + default: + break; + } +} + +__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_cinstr_len_t length, + void * p_rx_data) +{ + uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data; + + uint32_t reg = p_reg->CINSTRDAT1; + switch (length) + { + case NRF_QSPI_CINSTR_LEN_9B: + p_rx_data_8[7] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE7_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_8B: + p_rx_data_8[6] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE6_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_7B: + p_rx_data_8[5] = (uint8_t)(reg >> QSPI_CINSTRDAT1_BYTE5_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_6B: + p_rx_data_8[4] = (uint8_t)(reg); + /* fall-through */ + default: + break; + } + + reg = p_reg->CINSTRDAT0; + switch (length) + { + case NRF_QSPI_CINSTR_LEN_5B: + p_rx_data_8[3] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE3_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_4B: + p_rx_data_8[2] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE2_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_3B: + p_rx_data_8[1] = (uint8_t)(reg >> QSPI_CINSTRDAT0_BYTE1_Pos); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_2B: + p_rx_data_8[0] = (uint8_t)(reg); + /* fall-through */ + case NRF_QSPI_CINSTR_LEN_1B: + /* Send only opcode. Case to avoid compiler warnings. */ + break; + default: + break; + } +} + +__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg, + const nrf_qspi_cinstr_conf_t * p_config) +{ + p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) | + ((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) | + ((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) | + ((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) | + ((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) | + ((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos)); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_QSPI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_radio.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_radio.h new file mode 100755 index 0000000..4861d04 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_radio.h @@ -0,0 +1,1422 @@ +/* + * Copyright (c) 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_RADIO_H__ +#define NRF_RADIO_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_radio_hal RADIO HAL + * @{ + * @ingroup nrf_radio + * @brief Hardware access layer for managing the RADIO peripheral. + */ + +/** + * @brief RADIO tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_RADIO_TASK_TXEN = offsetof(NRF_RADIO_Type, TASKS_TXEN), /**< Enable RADIO in TX mode. */ + NRF_RADIO_TASK_RXEN = offsetof(NRF_RADIO_Type, TASKS_RXEN), /**< Enable RADIO in RX mode. */ + NRF_RADIO_TASK_START = offsetof(NRF_RADIO_Type, TASKS_START), /**< Start RADIO. */ + NRF_RADIO_TASK_STOP = offsetof(NRF_RADIO_Type, TASKS_STOP), /**< Stop RADIO. */ + NRF_RADIO_TASK_DISABLE = offsetof(NRF_RADIO_Type, TASKS_DISABLE), /**< Disable RADIO. */ + NRF_RADIO_TASK_RSSISTART = offsetof(NRF_RADIO_Type, TASKS_RSSISTART), /**< Start the RSSI and take one single sample of the receive signal strength. */ + NRF_RADIO_TASK_RSSISTOP = offsetof(NRF_RADIO_Type, TASKS_RSSISTOP), /**< Stop the RSSI measurement. */ + NRF_RADIO_TASK_BCSTART = offsetof(NRF_RADIO_Type, TASKS_BCSTART), /**< Start the bit counter. */ + NRF_RADIO_TASK_BCSTOP = offsetof(NRF_RADIO_Type, TASKS_BCSTOP), /**< Stop the bit counter. */ +#if defined(RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TASK_EDSTART = offsetof(NRF_RADIO_Type, TASKS_EDSTART), /**< Start the Energy Detect measurement used in IEEE 802.15.4 mode. */ +#endif +#if defined(RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TASK_EDSTOP = offsetof(NRF_RADIO_Type, TASKS_EDSTOP), /**< Stop the Energy Detect measurement. */ +#endif +#if defined(RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TASK_CCASTART = offsetof(NRF_RADIO_Type, TASKS_CCASTART), /**< Start the Clear Channel Assessment used in IEEE 802.15.4 mode. */ +#endif +#if defined(RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TASK_CCASTOP = offsetof(NRF_RADIO_Type, TASKS_CCASTOP), /**< Stop the Clear Channel Assessment. */ +#endif + /*lint -restore*/ +} nrf_radio_task_t; + +/** + * @brief RADIO events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_RADIO_EVENT_READY = offsetof(NRF_RADIO_Type, EVENTS_READY), /**< Radio has ramped up and is ready to be started. */ + NRF_RADIO_EVENT_ADDRESS = offsetof(NRF_RADIO_Type, EVENTS_ADDRESS), /**< Address sent or received. */ + NRF_RADIO_EVENT_PAYLOAD = offsetof(NRF_RADIO_Type, EVENTS_PAYLOAD), /**< Packet payload sent or received. */ + NRF_RADIO_EVENT_END = offsetof(NRF_RADIO_Type, EVENTS_END), /**< Packet transmitted or received. */ + NRF_RADIO_EVENT_DISABLED = offsetof(NRF_RADIO_Type, EVENTS_DISABLED), /**< RADIO has been disabled. */ + NRF_RADIO_EVENT_DEVMATCH = offsetof(NRF_RADIO_Type, EVENTS_DEVMATCH), /**< A device address match occurred on the last received packet. */ + NRF_RADIO_EVENT_DEVMISS = offsetof(NRF_RADIO_Type, EVENTS_DEVMISS), /**< No device address match occurred on the last received packet. */ + NRF_RADIO_EVENT_RSSIEND = offsetof(NRF_RADIO_Type, EVENTS_RSSIEND), /**< Sampling of receive signal strength complete. */ + NRF_RADIO_EVENT_BCMATCH = offsetof(NRF_RADIO_Type, EVENTS_BCMATCH), /**< Bit counter reached bit count value. */ +#if defined(RADIO_INTENSET_CRCOK_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_CRCOK = offsetof(NRF_RADIO_Type, EVENTS_CRCOK), /**< Packet received with correct CRC. */ +#endif +#if defined(RADIO_INTENSET_CRCERROR_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_CRCERROR = offsetof(NRF_RADIO_Type, EVENTS_CRCERROR), /**< Packet received with incorrect CRC. */ +#endif +#if defined(RADIO_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_FRAMESTART = offsetof(NRF_RADIO_Type, EVENTS_FRAMESTART), /**< IEEE 802.15.4 length field received. */ +#endif +#if defined(RADIO_INTENSET_EDEND_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_EDEND = offsetof(NRF_RADIO_Type, EVENTS_EDEND), /**< Energy Detection procedure ended. */ +#endif +#if defined(RADIO_INTENSET_EDSTOPPED_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_EDSTOPPED = offsetof(NRF_RADIO_Type, EVENTS_EDSTOPPED), /**< The sampling of Energy Detection has stopped. */ +#endif +#if defined(RADIO_INTENSET_CCAIDLE_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_CCAIDLE = offsetof(NRF_RADIO_Type, EVENTS_CCAIDLE), /**< Wireless medium in idle - clear to send. */ +#endif +#if defined(RADIO_INTENSET_CCABUSY_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_CCABUSY = offsetof(NRF_RADIO_Type, EVENTS_CCABUSY), /**< Wireless medium busy - do not send. */ +#endif +#if defined(RADIO_INTENSET_CCASTOPPED_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_CCASTOPPED = offsetof(NRF_RADIO_Type, EVENTS_CCASTOPPED), /**< The CCA has stopped. */ +#endif +#if defined(RADIO_INTENSET_RATEBOOST_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_RATEBOOST = offsetof(NRF_RADIO_Type, EVENTS_RATEBOOST), /**< Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ +#endif +#if defined(RADIO_INTENSET_TXREADY_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_TXREADY = offsetof(NRF_RADIO_Type, EVENTS_TXREADY), /**< RADIO has ramped up and is ready to be started TX path. */ +#endif +#if defined(RADIO_INTENSET_RXREADY_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_RXREADY = offsetof(NRF_RADIO_Type, EVENTS_RXREADY), /**< RADIO has ramped up and is ready to be started RX path. */ +#endif +#if defined(RADIO_INTENSET_MHRMATCH_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_MHRMATCH = offsetof(NRF_RADIO_Type, EVENTS_MHRMATCH), /**< MAC Header match found. */ +#endif +#if defined(RADIO_INTENSET_PHYEND_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_EVENT_PHYEND = offsetof(NRF_RADIO_Type, EVENTS_PHYEND), /**< Generated in Ble_LR125Kbit, Ble_LR500Kbit + and BleIeee802154_250Kbit modes when last + bit is sent on the air. */ +#endif + /*lint -restore*/ +} nrf_radio_event_t; + +/** + * @brief RADIO interrupts. + */ +typedef enum +{ + NRF_RADIO_INT_READY_MASK = RADIO_INTENSET_READY_Msk, /**< Interrupt on READY event. */ + NRF_RADIO_INT_ADDRESS_MASK = RADIO_INTENSET_ADDRESS_Msk, /**< Interrupt on ADDRESS event. */ + NRF_RADIO_INT_PAYLOAD_MASK = RADIO_INTENSET_PAYLOAD_Msk, /**< Interrupt on PAYLOAD event. */ + NRF_RADIO_INT_END_MASK = RADIO_INTENSET_END_Msk, /**< Interrupt on END event. */ + NRF_RADIO_INT_DISABLED_MASK = RADIO_INTENSET_DISABLED_Msk, /**< Interrupt on DISABLED event. */ + NRF_RADIO_INT_DEVMATCH_MASK = RADIO_INTENSET_DEVMATCH_Msk, /**< Interrupt on DEVMATCH event. */ + NRF_RADIO_INT_DEVMISS_MASK = RADIO_INTENSET_DEVMISS_Msk, /**< Interrupt on DEVMISS event. */ + NRF_RADIO_INT_RSSIEND_MASK = RADIO_INTENSET_RSSIEND_Msk, /**< Interrupt on RSSIEND event. */ + NRF_RADIO_INT_BCMATCH_MASK = RADIO_INTENSET_BCMATCH_Msk, /**< Interrupt on BCMATCH event. */ +#if defined(RADIO_INTENSET_CRCOK_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_CRCOK_MASK = RADIO_INTENSET_CRCOK_Msk, /**< Interrupt on CRCOK event. */ +#endif +#if defined(RADIO_INTENSET_CRCERROR_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_CRCERROR_MASK = RADIO_INTENSET_CRCERROR_Msk, /**< Interrupt on CRCERROR event. */ +#endif +#if defined(RADIO_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_FRAMESTART_MASK = RADIO_INTENSET_FRAMESTART_Msk, /**< Interrupt on FRAMESTART event. */ +#endif +#if defined(RADIO_INTENSET_EDEND_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_EDEND_MASK = RADIO_INTENSET_EDEND_Msk, /**< Interrupt on EDEND event. */ +#endif +#if defined(RADIO_INTENSET_EDSTOPPED_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_EDSTOPPED_MASK = RADIO_INTENSET_EDSTOPPED_Msk, /**< Interrupt on EDSTOPPED event. */ +#endif +#if defined(RADIO_INTENSET_CCAIDLE_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_CCAIDLE_MASK = RADIO_INTENSET_CCAIDLE_Msk, /**< Interrupt on CCAIDLE event. */ +#endif +#if defined(RADIO_INTENSET_CCABUSY_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_CCABUSY_MASK = RADIO_INTENSET_CCABUSY_Msk, /**< Interrupt on CCABUSY event. */ +#endif +#if defined(RADIO_INTENSET_CCASTOPPED_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_CCASTOPPED_MASK = RADIO_INTENSET_CCASTOPPED_Msk, /**< Interrupt on CCASTOPPED event. */ +#endif +#if defined(RADIO_INTENSET_RATEBOOST_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_RATEBOOST_MASK = RADIO_INTENSET_RATEBOOST_Msk, /**< Interrupt on RATEBOOST event. */ +#endif +#if defined(RADIO_INTENSET_TXREADY_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_TXREADY_MASK = RADIO_INTENSET_TXREADY_Msk, /**< Interrupt on TXREADY event. */ +#endif +#if defined(RADIO_INTENSET_RXREADY_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_RXREADY_MASK = RADIO_INTENSET_RXREADY_Msk, /**< Interrupt on RXREADY event. */ +#endif +#if defined(RADIO_INTENSET_MHRMATCH_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_MHRMATCH_MASK = RADIO_INTENSET_MHRMATCH_Msk, /**< Interrupt on MHRMATCH event. */ +#endif +#if defined(RADIO_INTENSET_PHYEND_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_INT_PHYEND_MASK = RADIO_INTENSET_PHYEND_Msk, /**< Interrupt on PHYEND event. */ +#endif +} nrf_radio_int_mask_t; + +/** + * @brief RADIO shortcuts. + */ +typedef enum +{ + NRF_RADIO_SHORT_READY_START_MASK = RADIO_SHORTS_READY_START_Msk, /**< Shortcut between READY event and START task. */ + NRF_RADIO_SHORT_END_DISABLE_MASK = RADIO_SHORTS_END_DISABLE_Msk, /**< Shortcut between END event and DISABLE task. */ + NRF_RADIO_SHORT_DISABLED_TXEN_MASK = RADIO_SHORTS_DISABLED_TXEN_Msk, /**< Shortcut between DISABLED event and TXEN task. */ + NRF_RADIO_SHORT_DISABLED_RXEN_MASK = RADIO_SHORTS_DISABLED_RXEN_Msk, /**< Shortcut between DISABLED event and RXEN task. */ + NRF_RADIO_SHORT_ADDRESS_RSSISTART_MASK = RADIO_SHORTS_ADDRESS_RSSISTART_Msk, /**< Shortcut between ADDRESS event and RSSISTART task. */ + NRF_RADIO_SHORT_END_START_MASK = RADIO_SHORTS_END_START_Msk, /**< Shortcut between END event and START task. */ + NRF_RADIO_SHORT_ADDRESS_BCSTART_MASK = RADIO_SHORTS_ADDRESS_BCSTART_Msk, /**< Shortcut between ADDRESS event and BCSTART task. */ + NRF_RADIO_SHORT_DISABLED_RSSISTOP_MASK = RADIO_SHORTS_DISABLED_RSSISTOP_Msk, /**< Shortcut between DISABLED event and RSSISTOP task. */ +#if defined(RADIO_SHORTS_RXREADY_CCASTART_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_RXREADY_CCASTART_MASK = RADIO_SHORTS_RXREADY_CCASTART_Msk, /**< Shortcut between RXREADY event and CCASTART task. */ +#endif +#if defined(RADIO_SHORTS_CCAIDLE_TXEN_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_CCAIDLE_TXEN_MASK = RADIO_SHORTS_CCAIDLE_TXEN_Msk, /**< Shortcut between CCAIDLE event and TXEN task. */ +#endif +#if defined(RADIO_SHORTS_CCABUSY_DISABLE_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_CCABUSY_DISABLE_MASK = RADIO_SHORTS_CCABUSY_DISABLE_Msk, /**< Shortcut between CCABUSY event and DISABLE task. */ +#endif +#if defined(RADIO_SHORTS_FRAMESTART_BCSTART_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_FRAMESTART_BCSTART_MASK = RADIO_SHORTS_FRAMESTART_BCSTART_Msk, /**< Shortcut between FRAMESTART event and BCSTART task. */ +#endif +#if defined(RADIO_SHORTS_READY_EDSTART_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_READY_EDSTART_MASK = RADIO_SHORTS_READY_EDSTART_Msk, /**< Shortcut between READY event and EDSTART task. */ +#endif +#if defined(RADIO_SHORTS_EDEND_DISABLE_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_EDEND_DISABLE_MASK = RADIO_SHORTS_EDEND_DISABLE_Msk, /**< Shortcut between EDEND event and DISABLE task. */ +#endif +#if defined(RADIO_SHORTS_CCAIDLE_STOP_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_CCAIDLE_STOP_MASK = RADIO_SHORTS_CCAIDLE_STOP_Msk, /**< Shortcut between CCAIDLE event and STOP task. */ +#endif +#if defined(RADIO_SHORTS_TXREADY_START_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_TXREADY_START_MASK = RADIO_SHORTS_TXREADY_START_Msk, /**< Shortcut between TXREADY event and START task. */ +#endif +#if defined(RADIO_SHORTS_RXREADY_START_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_RXREADY_START_MASK = RADIO_SHORTS_RXREADY_START_Msk, /**< Shortcut between RXREADY event and START task. */ +#endif +#if defined(RADIO_SHORTS_PHYEND_DISABLE_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_PHYEND_DISABLE_MASK = RADIO_SHORTS_PHYEND_DISABLE_Msk, /**< Shortcut between PHYEND event and DISABLE task. */ +#endif +#if defined(RADIO_SHORTS_PHYEND_START_Msk) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_SHORT_PHYEND_START_MASK = RADIO_SHORTS_PHYEND_START_Msk, /**< Shortcut between PHYEND event and START task. */ +#endif +} nrf_radio_short_mask_t; + +#if defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief RADIO Clear Channel Assessment modes. + */ +typedef enum +{ + NRF_RADIO_CCA_MODE_ED = RADIO_CCACTRL_CCAMODE_EdMode, /**< Energy Above Threshold. Will report busy whenever energy is detected above set threshold. */ + NRF_RADIO_CCA_MODE_CARRIER = RADIO_CCACTRL_CCAMODE_CarrierMode, /**< Carrier Seen. Will report busy whenever compliant IEEE 802.15.4 signal is seen. */ + NRF_RADIO_CCA_MODE_CARRIER_AND_ED = RADIO_CCACTRL_CCAMODE_CarrierAndEdMode, /**< Energy Above Threshold AND Carrier Seen. */ + NRF_RADIO_CCA_MODE_CARRIER_OR_ED = RADIO_CCACTRL_CCAMODE_CarrierOrEdMode, /**< Energy Above Threshold OR Carrier Seen. */ + NRF_RADIO_CCA_MODE_ED_TEST1 = RADIO_CCACTRL_CCAMODE_EdModeTest1, /**< Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ +} nrf_radio_cca_mode_t; +#endif // defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Types of RADIO States. + */ +typedef enum +{ + NRF_RADIO_STATE_DISABLED = RADIO_STATE_STATE_Disabled, /**< No operations are going on inside the radio and the power consumption is at a minimum. */ + NRF_RADIO_STATE_RXRU = RADIO_STATE_STATE_RxRu, /**< The radio is ramping up and preparing for reception. */ + NRF_RADIO_STATE_RXIDLE = RADIO_STATE_STATE_RxIdle, /**< The radio is ready for reception to start. */ + NRF_RADIO_STATE_RX = RADIO_STATE_STATE_Rx, /**< Reception has been started. */ + NRF_RADIO_STATE_RXDISABLE = RADIO_STATE_STATE_RxDisable, /**< The radio is disabling the receiver. */ + NRF_RADIO_STATE_TXRU = RADIO_STATE_STATE_TxRu, /**< The radio is ramping up and preparing for transmission. */ + NRF_RADIO_STATE_TXIDLE = RADIO_STATE_STATE_TxIdle, /**< The radio is ready for transmission to start. */ + NRF_RADIO_STATE_TX = RADIO_STATE_STATE_Tx, /**< The radio is transmitting a packet. */ + NRF_RADIO_STATE_TXDISABLE = RADIO_STATE_STATE_TxDisable, /**< The radio is disabling the transmitter. */ +} nrf_radio_state_t; + +/** + * @brief Types of RADIO TX power. + */ +typedef enum +{ +#if defined(RADIO_TXPOWER_TXPOWER_Pos8dBm) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TXPOWER_POS8DBM = RADIO_TXPOWER_TXPOWER_Pos8dBm, /**< 8 dBm. */ +#endif +#if defined(RADIO_TXPOWER_TXPOWER_Pos7dBm) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TXPOWER_POS7DBM = RADIO_TXPOWER_TXPOWER_Pos7dBm, /**< 7 dBm. */ +#endif +#if defined(RADIO_TXPOWER_TXPOWER_Pos6dBm) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TXPOWER_POS6DBM = RADIO_TXPOWER_TXPOWER_Pos6dBm, /**< 6 dBm. */ +#endif +#if defined(RADIO_TXPOWER_TXPOWER_Pos5dBm) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TXPOWER_POS5DBM = RADIO_TXPOWER_TXPOWER_Pos5dBm, /**< 5 dBm. */ +#endif + NRF_RADIO_TXPOWER_POS4DBM = RADIO_TXPOWER_TXPOWER_Pos4dBm, /**< 4 dBm. */ +#if defined(RADIO_TXPOWER_TXPOWER_Pos3dBm) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TXPOWER_POS3DBM = RADIO_TXPOWER_TXPOWER_Pos3dBm, /**< 3 dBm. */ +#endif +#if defined(RADIO_TXPOWER_TXPOWER_Pos2dBm) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TXPOWER_POS2DBM = RADIO_TXPOWER_TXPOWER_Pos2dBm, /**< 2 dBm. */ +#endif + NRF_RADIO_TXPOWER_0DBM = RADIO_TXPOWER_TXPOWER_0dBm, /**< 0 dBm. */ + NRF_RADIO_TXPOWER_NEG4DBM = RADIO_TXPOWER_TXPOWER_Neg4dBm, /**< -4 dBm. */ + NRF_RADIO_TXPOWER_NEG8DBM = RADIO_TXPOWER_TXPOWER_Neg8dBm, /**< -8 dBm. */ + NRF_RADIO_TXPOWER_NEG12DBM = RADIO_TXPOWER_TXPOWER_Neg12dBm, /**< -12 dBm. */ + NRF_RADIO_TXPOWER_NEG16DBM = RADIO_TXPOWER_TXPOWER_Neg16dBm, /**< -16 dBm. */ + NRF_RADIO_TXPOWER_NEG20DBM = RADIO_TXPOWER_TXPOWER_Neg20dBm, /**< -20 dBm. */ + NRF_RADIO_TXPOWER_NEG30DBM = RADIO_TXPOWER_TXPOWER_Neg30dBm, /**< -30 dBm. */ +#if defined(RADIO_TXPOWER_TXPOWER_Neg40dBm) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_TXPOWER_NEG40DBM = RADIO_TXPOWER_TXPOWER_Neg40dBm, /**< -40 dBm. */ +#endif +} nrf_radio_txpower_t; + +/** + * @brief Types of RADIO modes (data rate and modulation). + */ +typedef enum +{ + NRF_RADIO_MODE_NRF_1MBIT = RADIO_MODE_MODE_Nrf_1Mbit, /**< 1Mbit/s Nordic proprietary radio mode. */ + NRF_RADIO_MODE_NRF_2MBIT = RADIO_MODE_MODE_Nrf_2Mbit, /**< 2Mbit/s Nordic proprietary radio mode. */ +#if defined(RADIO_MODE_MODE_Nrf_250Kbit) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_MODE_NRF_250KBIT = RADIO_MODE_MODE_Nrf_250Kbit, /**< 250Kbit/s Nordic proprietary radio mode. */ +#endif + NRF_RADIO_MODE_BLE_1MBIT = RADIO_MODE_MODE_Ble_1Mbit, /**< 1 Mbit/s Bluetooth Low Energy. */ +#if defined(RADIO_MODE_MODE_Ble_2Mbit) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_MODE_BLE_2MBIT = RADIO_MODE_MODE_Ble_2Mbit, /**< 2 Mbit/s Bluetooth Low Energy. */ +#endif +#if defined(RADIO_MODE_MODE_Ble_LR125Kbit) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_MODE_BLE_LR125KBIT = RADIO_MODE_MODE_Ble_LR125Kbit, /*!< Bluetooth Low Energy Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#endif +#if defined(RADIO_MODE_MODE_Ble_LR500Kbit) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_MODE_BLE_LR500KBIT = RADIO_MODE_MODE_Ble_LR500Kbit, /*!< Bluetooth Low Energy Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#endif +#if defined(RADIO_MODE_MODE_Ieee802154_250Kbit) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_MODE_IEEE802154_250KBIT = RADIO_MODE_MODE_Ieee802154_250Kbit, /**< IEEE 802.15.4-2006 250 kbit/s. */ +#endif +} nrf_radio_mode_t; + +#if defined(RADIO_PCNF0_PLEN_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Types of preamble length. + */ +typedef enum +{ + NRF_RADIO_PREAMBLE_LENGTH_8BIT = RADIO_PCNF0_PLEN_8bit, /**< 8-bit preamble. */ + NRF_RADIO_PREAMBLE_LENGTH_16BIT = RADIO_PCNF0_PLEN_16bit, /**< 16-bit preamble. */ +#if defined(RADIO_PCNF0_PLEN_32bitZero) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_PREAMBLE_LENGTH_32BIT_ZERO = RADIO_PCNF0_PLEN_32bitZero, /**< 32-bit zero preamble used for IEEE 802.15.4. */ +#endif +#if defined(RADIO_PCNF0_PLEN_LongRange) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_PREAMBLE_LENGTH_LONG_RANGE = RADIO_PCNF0_PLEN_LongRange, /**< Preamble - used for BTLE Long Range. */ +#endif +} nrf_radio_preamble_length_t; +#endif // defined(RADIO_PCNF0_PLEN_Msk) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Types of CRC calculatons regarding address. + */ +typedef enum +{ + NRF_RADIO_CRC_ADDR_INCLUDE = RADIO_CRCCNF_SKIPADDR_Include, /**< CRC calculation includes address field. */ + NRF_RADIO_CRC_ADDR_SKIP = RADIO_CRCCNF_SKIPADDR_Skip, /**< CRC calculation does not include address field. */ +#if defined(RADIO_CRCCNF_SKIPADDR_Ieee802154) || defined(__NRFX_DOXYGEN__) + NRF_RADIO_CRC_ADDR_IEEE802154 = RADIO_CRCCNF_SKIPADDR_Ieee802154, /**< CRC calculation as per 802.15.4 standard. */ +#endif +} nrf_radio_crc_addr_t; + +/** + * @brief Packet configuration. + */ +typedef struct +{ + uint8_t lflen; /**< Length on air of LENGTH field in number of bits. */ + uint8_t s0len; /**< Length on air of S0 field in number of bytes. */ + uint8_t s1len; /**< Length on air of S1 field in number of bits. */ +#if defined(RADIO_PCNF0_S1INCL_Msk) || defined(__NRFX_DOXYGEN__) + bool s1incl; /**< Include or exclude S1 field in RAM. */ +#endif +#if defined(RADIO_PCNF0_CILEN_Msk) || defined(__NRFX_DOXYGEN__) + uint8_t cilen; /**< Length of code indicator - long range. */ +#endif +#if defined(RADIO_PCNF0_PLEN_Msk) || defined(__NRFX_DOXYGEN__) + nrf_radio_preamble_length_t plen; /**< Length of preamble on air. Decision point: TASKS_START task. */ +#endif +#if defined(RADIO_PCNF0_CRCINC_Msk) || defined(__NRFX_DOXYGEN__) + bool crcinc; /**< Indicates if LENGTH field contains CRC or not. */ +#endif +#if defined(RADIO_PCNF0_TERMLEN_Msk) || defined(__NRFX_DOXYGEN__) + uint8_t termlen; /**< Length of TERM field in Long Range operation. */ +#endif + uint8_t maxlen; /**< Maximum length of packet payload. */ + uint8_t statlen; /**< Static length in number of bytes. */ + uint8_t balen; /**< Base address length in number of bytes. */ + bool big_endian; /**< On air endianness of packet. */ + bool whiteen; /**< Enable or disable packet whitening. */ +} nrf_radio_packet_conf_t; + +/** + * @brief Function for activating a specific RADIO task. + * + * @param[in] radio_task Task to activate. + */ +__STATIC_INLINE void nrf_radio_task_trigger(nrf_radio_task_t radio_task); + +/** + * @brief Function for getting the address of a specific RADIO task register. + * + * This function can be used by the PPI module. + * + * @param[in] radio_task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_radio_task_address_get(nrf_radio_task_t radio_task); + +/** + * @brief Function for clearing a specific RADIO event. + * + * @param[in] radio_event Event to clean. + */ +__STATIC_INLINE void nrf_radio_event_clear(nrf_radio_event_t radio_event); + +/** + * @brief Function for checking the state of a specific RADIO event. + * + * @param[in] radio_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_radio_event_check(nrf_radio_event_t radio_event); + +/** + * @brief Function for getting the address of a specific RADIO event register. + * + * This function can be used by the PPI module. + * + * @param[in] radio_event Requested Event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_radio_event_address_get(nrf_radio_event_t radio_event); + +/** + * @brief Function for enabling specified RADIO shortcuts. + * + * @param[in] radio_shorts_mask Mask of shortcuts. + * + */ +__STATIC_INLINE void nrf_radio_shorts_enable(uint32_t radio_shorts_mask); + +/** + * @brief Function for disabling specified RADIO shortcuts. + * + * @param[in] radio_shorts_mask Mask of shortcuts. + */ +__STATIC_INLINE void nrf_radio_shorts_disable(uint32_t radio_shorts_mask); + +/** + * @brief Function for setting the configuration of RADIO shortcuts. + * + * @param[in] radio_shorts_mask Shortcuts configuration to set. + */ +__STATIC_INLINE void nrf_radio_shorts_set(uint32_t radio_shorts_mask); + +/** + * @brief Function for getting the configuration of RADIO shortcuts. + * + * @return Mask of currently enabled shortcuts. + */ +__STATIC_INLINE uint32_t nrf_radio_shorts_get(void); + +/** + * @brief Function for enabling specified RADIO interrupts. + * + * @param[in] radio_int_mask Mask of interrupts. + */ +__STATIC_INLINE void nrf_radio_int_enable(uint32_t radio_int_mask); + +/** + * @brief Function for disabling specified RADIO interrupts. + * + * @param[in] radio_int_mask Mask of interrupts. + */ +__STATIC_INLINE void nrf_radio_int_disable(uint32_t radio_int_mask); + +/** + * @brief Function for getting the state of a specific interrupt. + * + * @param[in] radio_int_mask Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_radio_int_enable_check(nrf_radio_int_mask_t radio_int_mask); + +/** + * @brief Function for getting CRC status of last received packet. + * + * @retval true If the packet was received without CRC error . + * @retval false If the packet was received with CRC error. + */ +__STATIC_INLINE bool nrf_radio_crc_status_check(void); + +/** + * @brief Function for getting the received address. + * + * @return Received address. + */ +__STATIC_INLINE uint8_t nrf_radio_rxmatch_get(void); + +/** + * @brief Function for getting CRC field of the last received packet. + * + * @return CRC field of previously received packet. + */ +__STATIC_INLINE uint32_t nrf_radio_rxcrc_get(void); + +/** + * @brief Function for getting the device address match index. + * + * @return Device adress match index. + */ +__STATIC_INLINE uint8_t nrf_radio_dai_get(void); + +#if defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for getting status on payload length. + * + * @retval 0 If the payload is lesser than PCNF1.MAXLEN. + * @retval 1 If the payload is greater than PCNF1.MAXLEN. + */ +__STATIC_INLINE uint8_t nrf_radio_pdustat_get(void); + +/** + * @brief Function for getting status on what rate packet is received with in Long Range. + * + * @retval 0 If the frame is received at 125kbps. + * @retval 1 If the frame is received at 500kbps. + */ +__STATIC_INLINE uint8_t nrf_radio_cistat_get(void); +#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for setting packet pointer to given location in memory. + * + * @param[in] p_packet Packet pointer. + */ +__STATIC_INLINE void nrf_radio_packetptr_set(const void * p_packet); + +/** + * @brief Function for getting packet pointer. + * + * @return Pointer to tx or rx packet buffer. + */ +__STATIC_INLINE void * nrf_radio_packetptr_get(void); + +/** + * @brief Function for setting the radio frequency. + * + * @param[in] radio_frequency Frequency in MHz. + */ +__STATIC_INLINE void nrf_radio_frequency_set(uint16_t radio_frequency); + +/** + * @brief Function for getting the radio frequency. + * + * @return Frequency in MHz. + */ +__STATIC_INLINE uint16_t nrf_radio_frequency_get(void); + +/** + * @brief Function for setting the radio transmit power. + * + * @param[in] tx_power Transmit power of the radio [dBm]. + */ +__STATIC_INLINE void nrf_radio_txpower_set(nrf_radio_txpower_t tx_power); + +/** + * @brief Function for getting the radio transmit power. + * + * @return Transmit power of the radio. + */ +__STATIC_INLINE nrf_radio_txpower_t nrf_radio_txpower_get(void); + +/** + * @brief Function for setting the radio data rate and modulation settings. + * + * @param[in] radio_mode Radio data rate and modulation. + */ +__STATIC_INLINE void nrf_radio_mode_set(nrf_radio_mode_t radio_mode); + +/** + * @brief Function for getting Radio data rate and modulation settings. + * + * @return Radio data rate and modulation. + */ +__STATIC_INLINE nrf_radio_mode_t nrf_radio_mode_get(void); + +/** + * @brief Function for setting the packet configuration. + * + * @param[in] p_config Pointer to the structure with packet configuration. + */ +__STATIC_INLINE void nrf_radio_packet_configure(const nrf_radio_packet_conf_t * p_config); + +/** + * @brief Function for setting the base address 0. + * + * @param address Base address 0 value. + */ +__STATIC_INLINE void nrf_radio_base0_set(uint32_t address); + +/** + * @brief Function for getting the base address 0. + * + * @return Base address 0. + */ +__STATIC_INLINE uint32_t nrf_radio_base0_get(void); + +/** + * @brief Function for setting Base address 1. + * + * @param address Base address 1 value. + */ +__STATIC_INLINE void nrf_radio_base1_set(uint32_t address); + +/** + * @brief Function for getting base address 1. + * + * @return Base address 1. + */ +__STATIC_INLINE uint32_t nrf_radio_base1_get(void); + +/** + * @brief Function for setting prefixes bytes for logical addresses 0-3. + * + * @param prefixes Prefixes bytes for logical addresses 0-3. + */ +__STATIC_INLINE void nrf_radio_prefix0_set(uint32_t prefixes); + +/** + * @brief Function for getting prefixes bytes for logical addresses 0-3 + * + * @return Prefixes bytes for logical addresses 0-3 + */ +__STATIC_INLINE uint32_t nrf_radio_prefix0_get(void); + +/** + * @brief Function for setting prefixes bytes for logical addresses 4-7. + * + * @param prefixes Prefixes bytes for logical addresses 4-7. + */ +__STATIC_INLINE void nrf_radio_prefix1_set(uint32_t prefixes); + +/** + * @brief Function for getting prefixes bytes for logical addresses 4-7 + * + * @return Prefixes bytes for logical addresses 4-7 + */ +__STATIC_INLINE uint32_t nrf_radio_prefix1_get(void); + +/** + * @brief Function for setting the transmit address. + * + * @param txaddress Logical address to be used when transmitting a packet. + */ +__STATIC_INLINE void nrf_radio_txaddress_set(uint8_t txaddress); + +/** + * @brief Function for getting the transmit address select. + * + * @return Logical address to be used when transmitting a packet. + */ +__STATIC_INLINE uint8_t nrf_radio_txaddress_get(void); + +/** + * @brief Function for for selecting the receive addresses. + * + * @param rxaddresses Enable or disable reception on logical address i. + * Read more in the Product Specification. + */ +__STATIC_INLINE void nrf_radio_rxaddresses_set(uint8_t rxaddresses); + +/** + * @brief Function for getting receive address select. + * + * @return Receive address select. + */ +__STATIC_INLINE uint8_t nrf_radio_rxaddresses_get(void); + +/** + * @brief Function for configure CRC. + * + * @param[in] crc_length CRC length in number of bytes [0-3]. + * @param[in] crc_address Include or exclude packet address field out of CRC. + * @param[in] crc_polynominal CRC polynominal to set. + */ +__STATIC_INLINE void nrf_radio_crc_configure(uint8_t crc_length, + nrf_radio_crc_addr_t crc_address, + uint32_t crc_polynominal); + +/** + * @brief Function for setting CRC initial value. + * + * @param crc_init_value CRC initial value + */ +__STATIC_INLINE void nrf_radio_crcinit_set(uint32_t crc_init_value); + +/** + * @brief Function for getting CRC initial value. + * + * @return CRC initial value. + */ +__STATIC_INLINE uint32_t nrf_radio_crcinit_get(void); + +/** + * @brief Function for setting Inter Frame Spacing interval. + * + * @param[in] radio_ifs Inter frame spacing interval [us]. + */ +__STATIC_INLINE void nrf_radio_ifs_set(uint32_t radio_ifs); + +/** + * @brief Function for getting Inter Frame Spacing interval. + * + * @return Inter frame spacing interval [us]. + */ +__STATIC_INLINE uint32_t nrf_radio_ifs_get(void); + +/** + * @brief Function for getting RSSI sample result. + * + * @note The read value is a positive value while the actual received signal + * is a negative value. Actual received signal strength is therefore as follows: + * received signal strength = - read_value dBm . + * + * @return RSSI sample result. + */ +__STATIC_INLINE uint8_t nrf_radio_rssi_sample_get(void); + +/** + * @brief Function for getting the current state of the radio module. + * + * @return Current radio state. + */ +__STATIC_INLINE nrf_radio_state_t nrf_radio_state_get(void); + +/** + * @brief Function for setting the data whitening initial value. + * + * @param datawhiteiv Data whitening initial value. + */ +__STATIC_INLINE void nrf_radio_datawhiteiv_set(uint8_t datawhiteiv); + +/** + * @brief Function for getting the data whitening initial value. + * + * @return Data whitening initial value. + */ +__STATIC_INLINE uint8_t nrf_radio_datawhiteiv_get(void); + +/** + * @brief Function for setting Bit counter compare. + * + * @param[in] radio_bcc Bit counter compare [bits]. + */ +__STATIC_INLINE void nrf_radio_bcc_set(uint32_t radio_bcc); + +/** + * @brief Function for getting Bit counter compare. + * + * @return Bit counter compare. + */ +__STATIC_INLINE uint32_t nrf_radio_bcc_get(void); + +/** + * @brief Function for setting Device address base segment. + * + * @param dab_value Particular base segment value. + * @param segment Index of the particular Device address base segment register. + */ +__STATIC_INLINE void nrf_radio_dab_set(uint32_t dab_value, uint8_t segment); + +/** + * @brief Function for getting Device address base segment. + * + * @param segment Number of the Device address base segment. + * + * @return Particular segment of the Device address base. + */ +__STATIC_INLINE uint32_t nrf_radio_dab_get(uint8_t segment); + +/** + * @brief Function for setting device address prefix. + * + * @param dap_value Particular device address prefix value. + * @param prefix_index Index of the particular device address prefix register. + */ +__STATIC_INLINE void nrf_radio_dap_set(uint16_t dap_value, uint8_t prefix_index); + +/** + * @brief Function for getting Device address prefix. + * + * @param prefix_index Number of the Device address prefix segment. + * + * @return Particular segment of the Device address prefix. + */ +__STATIC_INLINE uint32_t nrf_radio_dap_get(uint8_t prefix_index); + +/** + * @brief Function for setting device address match configuration. + * + * @note Read more about configuring device address match in the Product Specification. + * + * @param ena Device address matching bitmask. + * @param txadd TxAdd bitmask. + */ +__STATIC_INLINE void nrf_radio_dacnf_set(uint8_t ena, uint8_t txadd); + +/** + * @brief Function for getting ENA field of the Device address match configuration register. + * + * @return ENA field of the Device address match configuration register. + */ +__STATIC_INLINE uint8_t nrf_radio_dacnf_ena_get(void); + +/** + * @brief Function for getting TXADD field of the Device address match configuration register. + * + * @return TXADD field of the Device address match configuration register. + */ +__STATIC_INLINE uint8_t nrf_radio_dacnf_txadd_get(void); + +#if defined(RADIO_INTENSET_MHRMATCH_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting MAC Header Match Unit search pattern configuration. + * + * @param[in] radio_mhmu_search_pattern Search Pattern Configuration. + */ +__STATIC_INLINE void nrf_radio_mhmu_search_pattern_set(uint32_t radio_mhmu_search_pattern); + +/** + * @brief Function for getting MAC Header Match Unit search pattern configuration. + * + * @return Search Pattern Configuration. + */ +__STATIC_INLINE uint32_t nrf_radio_mhmu_search_pattern_get(void); + +/** + * @brief Function for setting MAC Header Match Unit pattern mask configuration. + * + * @param[in] radio_mhmu_pattern_mask Pattern mask. + */ +__STATIC_INLINE void nrf_radio_mhmu_pattern_mask_set(uint32_t radio_mhmu_pattern_mask); + +/** + * @brief Function for getting MAC Header Match Unit pattern mask configuration. + * + * @return Pattern mask. + */ +__STATIC_INLINE uint32_t nrf_radio_mhmu_pattern_mask_get(void); +#endif // defined(RADIO_INTENSET_MHRMATCH_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(RADIO_MODECNF0_RU_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting Radio mode configuration register 0. + * + * @param fast_ramp_up Use fast radio ramp-up time + * @param default_tx Default TX value during inactivity. + */ +__STATIC_INLINE void nrf_radio_modecnf0_set(bool fast_ramp_up, uint8_t default_tx); + +/** + * @brief Function for getting ramp-up time configuration of the Radio mode configuration register 0. + * + * @retval true If the ramp-up time is set to fast. + * @retval false If the ramp-up time is set to default. + */ +__STATIC_INLINE bool nrf_radio_modecnf0_ru_get(void); + +/** + * @brief Function for getting default TX value of the Radio mode configuration register 0. + * + * @return Default TX value. + */ +__STATIC_INLINE uint8_t nrf_radio_modecnf0_dtx_get(void); +#endif // defined(RADIO_MODECNF0_RU_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(RADIO_SFD_SFD_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting IEEE 802.15.4 start of frame delimiter. + * + * @param sfd IEEE 802.15.4 start of frame delimiter. + */ +__STATIC_INLINE void nrf_radio_sfd_set(uint8_t sfd); + +/** + * @brief Function for getting IEEE 802.15.4 start of frame delimiter. + * + * @return IEEE 802.15.4 start of frame delimiter. + */ +__STATIC_INLINE uint8_t nrf_radio_sfd_get(void); +#endif // defined(RADIO_SFD_SFD_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(RADIO_EDCNT_EDCNT_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for setting number of iterations to perform ED scan. + * + * @param[in] ed_loop_count Number of iterations during ED procedure. + */ +__STATIC_INLINE void nrf_radio_ed_loop_count_set(uint32_t ed_loop_count); +#endif // defined(RADIO_EDCNT_EDCNT_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(RADIO_EDSAMPLE_EDLVL_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for getting Energy Detection level. + * + * @return IEEE 802.15.4 energy detect level. + */ +__STATIC_INLINE uint8_t nrf_radio_ed_sample_get(void); +#endif // defined(RADIO_EDSAMPLE_EDLVL_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for configuring the IEEE 802.15.4 clear channel assessment. + * + * @param cca_mode Mode of CCA. + * @param cca_ed_threshold Energy Detection threshold value. + * @param cca_corr_threshold Correlator Busy Threshold. + * @param cca_corr_cnt Limit of occurances above Correlator Threshold. + * When not equal to zero the correlator based + * signal detect is enabled. + */ +__STATIC_INLINE void nrf_radio_cca_configure(nrf_radio_cca_mode_t cca_mode, + uint8_t cca_ed_threshold, + uint8_t cca_corr_threshold, + uint8_t cca_corr_cnt); +#endif // defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for setting power mode of the radio peripheral. + * + * @param[in] radio_power If radio should be powered on. + */ +__STATIC_INLINE void nrf_radio_power_set(bool radio_power); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_radio_task_trigger(nrf_radio_task_t radio_task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_radio_task_address_get(nrf_radio_task_t radio_task) +{ + return ((uint32_t)NRF_RADIO + (uint32_t)radio_task); +} + +__STATIC_INLINE void nrf_radio_event_clear(nrf_radio_event_t radio_event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_radio_event_check(nrf_radio_event_t radio_event) +{ + return (bool) *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event)); +} + +__STATIC_INLINE uint32_t nrf_radio_event_address_get(nrf_radio_event_t radio_event) +{ + return ((uint32_t)NRF_RADIO + (uint32_t)radio_event); +} + +__STATIC_INLINE void nrf_radio_shorts_enable(uint32_t radio_shorts_mask) +{ + NRF_RADIO->SHORTS |= radio_shorts_mask; +} + +__STATIC_INLINE void nrf_radio_shorts_disable(uint32_t radio_shorts_mask) +{ + NRF_RADIO->SHORTS &= ~radio_shorts_mask; +} + +__STATIC_INLINE void nrf_radio_shorts_set(uint32_t radio_shorts_mask) +{ + NRF_RADIO->SHORTS = radio_shorts_mask; +} + +__STATIC_INLINE uint32_t nrf_radio_shorts_get(void) +{ + return NRF_RADIO->SHORTS; +} + +__STATIC_INLINE void nrf_radio_int_enable(uint32_t radio_int_mask) +{ + NRF_RADIO->INTENSET = radio_int_mask; +} + +__STATIC_INLINE void nrf_radio_int_disable(uint32_t radio_int_mask) +{ + NRF_RADIO->INTENCLR = radio_int_mask; +} + +__STATIC_INLINE bool nrf_radio_int_enable_check(nrf_radio_int_mask_t radio_int_mask) +{ + return (bool)(NRF_RADIO->INTENSET & radio_int_mask); +} + +__STATIC_INLINE bool nrf_radio_crc_status_check(void) +{ + return ((NRF_RADIO->CRCSTATUS & RADIO_CRCSTATUS_CRCSTATUS_Msk) >> RADIO_CRCSTATUS_CRCSTATUS_Pos) + == RADIO_CRCSTATUS_CRCSTATUS_CRCOk ; +} + +__STATIC_INLINE uint8_t nrf_radio_rxmatch_get(void) +{ + return (uint8_t)NRF_RADIO->RXMATCH; +} + +__STATIC_INLINE uint32_t nrf_radio_rxcrc_get(void) +{ + return NRF_RADIO->RXCRC; +} + +__STATIC_INLINE uint8_t nrf_radio_dai_get(void) +{ + return (uint8_t)NRF_RADIO->DAI; +} + +#if defined(RADIO_PDUSTAT_PDUSTAT_Msk) +__STATIC_INLINE uint8_t nrf_radio_pdustat_get(void) +{ + return (uint8_t)(NRF_RADIO->PDUSTAT & RADIO_PDUSTAT_PDUSTAT_Msk); +} + +__STATIC_INLINE uint8_t nrf_radio_cistat_get(void) +{ + return (uint8_t)((NRF_RADIO->PDUSTAT & RADIO_PDUSTAT_CISTAT_Msk) >> RADIO_PDUSTAT_CISTAT_Pos); +} +#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) + +__STATIC_INLINE void nrf_radio_packetptr_set(const void * p_packet) +{ + NRF_RADIO->PACKETPTR = (uint32_t)p_packet; +} + +__STATIC_INLINE void * nrf_radio_packetptr_get(void) +{ + return (void *)NRF_RADIO->PACKETPTR; +} + +__STATIC_INLINE void nrf_radio_frequency_set(uint16_t radio_frequency) +{ + NRFX_ASSERT(radio_frequency <= 2500); + +#if defined(RADIO_FREQUENCY_MAP_Msk) + NRFX_ASSERT(radio_frequency >= 2360); + + uint32_t delta; + if (radio_frequency < 2400) + { + delta = ((uint32_t)(radio_frequency - 2360)) | + (RADIO_FREQUENCY_MAP_Low << RADIO_FREQUENCY_MAP_Pos); + } + else + { + delta = ((uint32_t)(radio_frequency - 2400)) | + (RADIO_FREQUENCY_MAP_Default << RADIO_FREQUENCY_MAP_Pos); + } + + NRF_RADIO->FREQUENCY = delta; +#else + NRFX_ASSERT(radio_frequency >= 2400); + NRF_RADIO->FREQUENCY = (uint32_t)(2400 - radio_frequency); +#endif //defined(RADIO_FREQUENCY_MAP_Msk) +} + +__STATIC_INLINE uint16_t nrf_radio_frequency_get(void) +{ + uint32_t freq; + +#if defined(RADIO_FREQUENCY_MAP_Msk) + if (((NRF_RADIO->FREQUENCY & RADIO_FREQUENCY_MAP_Msk) >> RADIO_FREQUENCY_MAP_Pos) == + RADIO_FREQUENCY_MAP_Low) + { + freq = 2360; + } + else +#endif + { + freq = 2400; + } + freq += NRF_RADIO->FREQUENCY & RADIO_FREQUENCY_FREQUENCY_Msk; + + return freq; +} + +__STATIC_INLINE void nrf_radio_txpower_set(nrf_radio_txpower_t tx_power) +{ + NRF_RADIO->TXPOWER = (((uint32_t)tx_power) << RADIO_TXPOWER_TXPOWER_Pos); +} + +__STATIC_INLINE nrf_radio_txpower_t nrf_radio_txpower_get(void) +{ + return (nrf_radio_txpower_t)(NRF_RADIO->TXPOWER >> RADIO_TXPOWER_TXPOWER_Pos); +} + +__STATIC_INLINE void nrf_radio_mode_set(nrf_radio_mode_t radio_mode) +{ + NRF_RADIO->MODE = ((uint32_t) radio_mode << RADIO_MODE_MODE_Pos); +} + +__STATIC_INLINE nrf_radio_mode_t nrf_radio_mode_get(void) +{ + return (nrf_radio_mode_t)((NRF_RADIO->MODE & RADIO_MODE_MODE_Msk) >> RADIO_MODE_MODE_Pos); +} + +__STATIC_INLINE void nrf_radio_packet_configure(const nrf_radio_packet_conf_t * p_config) +{ + NRF_RADIO->PCNF0 = (((uint32_t)p_config->lflen << RADIO_PCNF0_LFLEN_Pos) | + ((uint32_t)p_config->s0len << RADIO_PCNF0_S0LEN_Pos) | + ((uint32_t)p_config->s1len << RADIO_PCNF0_S1LEN_Pos) | +#if defined(RADIO_PCNF0_S1INCL_Msk) + (p_config->s1incl ? + (RADIO_PCNF0_S1INCL_Include << RADIO_PCNF0_S1INCL_Pos) : + (RADIO_PCNF0_S1INCL_Automatic << RADIO_PCNF0_S1INCL_Pos) ) | +#endif +#if defined(RADIO_PCNF0_CILEN_Msk) + ((uint32_t)p_config->cilen << RADIO_PCNF0_CILEN_Pos) | +#endif +#if defined(RADIO_PCNF0_PLEN_Msk) + ((uint32_t)p_config->plen << RADIO_PCNF0_PLEN_Pos) | +#endif +#if defined(RADIO_PCNF0_CRCINC_Msk) + (p_config->crcinc ? + (RADIO_PCNF0_CRCINC_Include << RADIO_PCNF0_CRCINC_Pos) : + (RADIO_PCNF0_CRCINC_Exclude << RADIO_PCNF0_CRCINC_Pos) ) | +#endif +#if defined(RADIO_PCNF0_TERMLEN_Msk) + ((uint32_t)p_config->termlen << RADIO_PCNF0_TERMLEN_Pos) | +#endif + 0); + + NRF_RADIO->PCNF1 = (((uint32_t)p_config->maxlen << RADIO_PCNF1_MAXLEN_Pos) | + ((uint32_t)p_config->statlen << RADIO_PCNF1_STATLEN_Pos) | + ((uint32_t)p_config->balen << RADIO_PCNF1_BALEN_Pos) | + (p_config->big_endian ? + (RADIO_PCNF1_ENDIAN_Big << RADIO_PCNF1_ENDIAN_Pos) : + (RADIO_PCNF1_ENDIAN_Little << RADIO_PCNF1_ENDIAN_Pos) ) | + (p_config->whiteen ? + (RADIO_PCNF1_WHITEEN_Enabled << RADIO_PCNF1_WHITEEN_Pos) : + (RADIO_PCNF1_WHITEEN_Disabled << RADIO_PCNF1_WHITEEN_Pos) )); +} + +__STATIC_INLINE void nrf_radio_base0_set(uint32_t address) +{ + NRF_RADIO->BASE0 = address; +} + +__STATIC_INLINE uint32_t nrf_radio_base0_get(void) +{ + return NRF_RADIO->BASE0; +} + +__STATIC_INLINE void nrf_radio_base1_set(uint32_t address) +{ + NRF_RADIO->BASE1 = address; +} + +__STATIC_INLINE uint32_t nrf_radio_base1_get(void) +{ + return NRF_RADIO->BASE1; +} + +__STATIC_INLINE void nrf_radio_prefix0_set(uint32_t prefix0_value) +{ + NRF_RADIO->PREFIX0 = prefix0_value; +} + +__STATIC_INLINE uint32_t nrf_radio_prefix0_get(void) +{ + return NRF_RADIO->PREFIX0; +} + +__STATIC_INLINE void nrf_radio_prefix1_set(uint32_t prefix1_value) +{ + NRF_RADIO->PREFIX1 = prefix1_value; +} + +__STATIC_INLINE uint32_t nrf_radio_prefix1_get(void) +{ + return NRF_RADIO->PREFIX1; +} + +__STATIC_INLINE void nrf_radio_txaddress_set(uint8_t txaddress) +{ + NRF_RADIO->TXADDRESS = ((uint32_t)txaddress) << RADIO_TXADDRESS_TXADDRESS_Pos; +} + +__STATIC_INLINE uint8_t nrf_radio_txaddress_get(void) +{ + return (uint8_t)((NRF_RADIO->TXADDRESS & RADIO_TXADDRESS_TXADDRESS_Msk) >> + RADIO_TXADDRESS_TXADDRESS_Pos); +} + +__STATIC_INLINE void nrf_radio_rxaddresses_set(uint8_t rxaddresses) +{ + NRF_RADIO->RXADDRESSES = (uint32_t)(rxaddresses); +} + +__STATIC_INLINE uint8_t nrf_radio_rxaddresses_get(void) +{ + return (uint8_t)(NRF_RADIO->RXADDRESSES); +} + +__STATIC_INLINE void nrf_radio_crc_configure(uint8_t crc_length, + nrf_radio_crc_addr_t crc_address, + uint32_t crc_polynominal) +{ + NRF_RADIO->CRCCNF = ((uint32_t)crc_length << RADIO_CRCCNF_LEN_Pos) | + ((uint32_t)crc_address << RADIO_CRCCNF_SKIPADDR_Pos); + NRF_RADIO->CRCPOLY = (crc_polynominal << RADIO_CRCPOLY_CRCPOLY_Pos); +} + +__STATIC_INLINE void nrf_radio_crcinit_set(uint32_t crc_init_value) +{ + NRF_RADIO->CRCINIT = crc_init_value; +} + +__STATIC_INLINE uint32_t nrf_radio_crcinit_get(void) +{ + return NRF_RADIO->CRCINIT; +} + +__STATIC_INLINE void nrf_radio_ifs_set(uint32_t radio_ifs) +{ + NRF_RADIO->TIFS = radio_ifs; +} + +__STATIC_INLINE uint32_t nrf_radio_ifs_get(void) +{ + return NRF_RADIO->TIFS; +} + +__STATIC_INLINE uint8_t nrf_radio_rssi_sample_get(void) +{ + return (uint8_t)((NRF_RADIO->RSSISAMPLE & RADIO_RSSISAMPLE_RSSISAMPLE_Msk) >> + RADIO_RSSISAMPLE_RSSISAMPLE_Pos); +} + +__STATIC_INLINE nrf_radio_state_t nrf_radio_state_get(void) +{ + return (nrf_radio_state_t) NRF_RADIO->STATE; +} + +__STATIC_INLINE void nrf_radio_datawhiteiv_set(uint8_t datawhiteiv) +{ + NRF_RADIO->DATAWHITEIV = (((uint32_t)datawhiteiv) & RADIO_DATAWHITEIV_DATAWHITEIV_Msk); +} + +__STATIC_INLINE uint8_t nrf_radio_datawhiteiv_get(void) +{ + return (uint8_t)(NRF_RADIO->DATAWHITEIV & RADIO_DATAWHITEIV_DATAWHITEIV_Msk); +} + +__STATIC_INLINE void nrf_radio_bcc_set(uint32_t radio_bcc) +{ + NRF_RADIO->BCC = radio_bcc; +} + +__STATIC_INLINE uint32_t nrf_radio_bcc_get(void) +{ + return NRF_RADIO->BCC; +} + +__STATIC_INLINE void nrf_radio_dab_set(uint32_t dab_value, uint8_t segment) +{ + NRFX_ASSERT(segment < 8); + NRF_RADIO->DAB[segment] = dab_value; +} + +__STATIC_INLINE uint32_t nrf_radio_dab_get(uint8_t segment) +{ + NRFX_ASSERT(segment < 8); + return NRF_RADIO->DAB[segment]; +} + +__STATIC_INLINE void nrf_radio_dap_set(uint16_t dap_value, uint8_t prefix_index) +{ + NRFX_ASSERT(prefix_index < 8); + NRF_RADIO->DAP[prefix_index] = (uint32_t)dap_value; +} + +__STATIC_INLINE uint32_t nrf_radio_dap_get(uint8_t prefix_index) +{ + NRFX_ASSERT(prefix_index < 8); + return NRF_RADIO->DAP[prefix_index]; +} + +__STATIC_INLINE void nrf_radio_dacnf_set(uint8_t ena, uint8_t txadd) +{ + NRF_RADIO->DACNF = (((uint32_t)ena << RADIO_DACNF_ENA0_Pos) | + ((uint32_t)txadd << RADIO_DACNF_TXADD0_Pos)); +} + +__STATIC_INLINE uint8_t nrf_radio_dacnf_ena_get(void) +{ + return (NRF_RADIO->DACNF & (RADIO_DACNF_ENA0_Msk | + RADIO_DACNF_ENA1_Msk | + RADIO_DACNF_ENA2_Msk | + RADIO_DACNF_ENA3_Msk | + RADIO_DACNF_ENA4_Msk | + RADIO_DACNF_ENA5_Msk | + RADIO_DACNF_ENA6_Msk | + RADIO_DACNF_ENA7_Msk)) >> RADIO_DACNF_ENA0_Pos; +} + +__STATIC_INLINE uint8_t nrf_radio_dacnf_txadd_get(void) +{ + return (NRF_RADIO->DACNF & (RADIO_DACNF_TXADD0_Msk | + RADIO_DACNF_TXADD1_Msk | + RADIO_DACNF_TXADD2_Msk | + RADIO_DACNF_TXADD3_Msk | + RADIO_DACNF_TXADD4_Msk | + RADIO_DACNF_TXADD5_Msk | + RADIO_DACNF_TXADD6_Msk | + RADIO_DACNF_TXADD7_Msk)) >> RADIO_DACNF_TXADD0_Pos; +} + +#if defined(RADIO_INTENSET_MHRMATCH_Msk) +__STATIC_INLINE void nrf_radio_mhmu_search_pattern_set(uint32_t radio_mhmu_search_pattern) +{ + NRF_RADIO->MHRMATCHCONF = radio_mhmu_search_pattern; +} + +__STATIC_INLINE uint32_t nrf_radio_mhmu_search_pattern_get(void) +{ + return NRF_RADIO->MHRMATCHCONF; +} + +__STATIC_INLINE void nrf_radio_mhmu_pattern_mask_set(uint32_t radio_mhmu_pattern_mask) +{ + NRF_RADIO->MHRMATCHMAS = radio_mhmu_pattern_mask; +} + +__STATIC_INLINE uint32_t nrf_radio_mhmu_pattern_mask_get(void) +{ + return NRF_RADIO->MHRMATCHMAS; +} +#endif // defined(RADIO_INTENSET_MHRMATCH_Msk) + +#if defined(RADIO_MODECNF0_RU_Msk) +__STATIC_INLINE void nrf_radio_modecnf0_set(bool fast_ramp_up, uint8_t default_tx) +{ + NRF_RADIO->MODECNF0 = (fast_ramp_up ? (RADIO_MODECNF0_RU_Fast << RADIO_MODECNF0_RU_Pos) : + (RADIO_MODECNF0_RU_Default << RADIO_MODECNF0_RU_Pos) ) | + (((uint32_t)default_tx) << RADIO_MODECNF0_DTX_Pos); +} + +__STATIC_INLINE bool nrf_radio_modecnf0_ru_get(void) +{ + return ((NRF_RADIO->MODECNF0 & RADIO_MODECNF0_RU_Msk) >> RADIO_MODECNF0_RU_Pos) == + RADIO_MODECNF0_RU_Fast; +} + +__STATIC_INLINE uint8_t nrf_radio_modecnf0_dtx_get(void) +{ + return (uint8_t)((NRF_RADIO->MODECNF0 & RADIO_MODECNF0_DTX_Msk) >> RADIO_MODECNF0_DTX_Pos); +} +#endif // defined(RADIO_MODECNF0_RU_Msk) + +#if defined(RADIO_SFD_SFD_Msk) +__STATIC_INLINE void nrf_radio_sfd_set(uint8_t sfd) +{ + NRF_RADIO->SFD = ((uint32_t)sfd) << RADIO_SFD_SFD_Pos; +} + +__STATIC_INLINE uint8_t nrf_radio_sfd_get(void) +{ + return (uint8_t)((NRF_RADIO->SFD & RADIO_SFD_SFD_Msk) >> RADIO_SFD_SFD_Pos); +} +#endif // defined(RADIO_SFD_SFD_Msk) + +#if defined(RADIO_EDCNT_EDCNT_Msk) +__STATIC_INLINE void nrf_radio_ed_loop_count_set(uint32_t ed_loop_count) +{ + NRF_RADIO->EDCNT = (ed_loop_count & RADIO_EDCNT_EDCNT_Msk); +} +#endif + +#if defined(RADIO_EDSAMPLE_EDLVL_Msk) +__STATIC_INLINE uint8_t nrf_radio_ed_sample_get(void) +{ + return (uint8_t) NRF_RADIO->EDSAMPLE; +} +#endif + +#if defined(RADIO_CCACTRL_CCAMODE_Msk) + +__STATIC_INLINE void nrf_radio_cca_configure(nrf_radio_cca_mode_t cca_mode, + uint8_t cca_ed_threshold, + uint8_t cca_corr_threshold, + uint8_t cca_corr_cnt) +{ + NRF_RADIO->CCACTRL = (((uint32_t)cca_mode << RADIO_CCACTRL_CCAMODE_Pos) | + ((uint32_t)cca_ed_threshold << RADIO_CCACTRL_CCAEDTHRES_Pos) | + ((uint32_t)cca_corr_threshold << RADIO_CCACTRL_CCACORRTHRES_Pos) | + ((uint32_t)cca_corr_cnt << RADIO_CCACTRL_CCACORRCNT_Pos)); +} +#endif + +__STATIC_INLINE void nrf_radio_power_set(bool radio_power) +{ + NRF_RADIO->POWER = (uint32_t) radio_power; +} +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_RADIO_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_rng.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_rng.h new file mode 100755 index 0000000..21cee2d --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_rng.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_RNG_H__ +#define NRF_RNG_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_rng_hal RNG HAL + * @{ + * @ingroup nrf_rng + * @brief Hardware access layer for managing the Random Number Generator (RNG) peripheral. + */ + +#define NRF_RNG_TASK_SET (1UL) +#define NRF_RNG_EVENT_CLEAR (0UL) +/** + * @enum nrf_rng_task_t + * @brief RNG tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_RNG_TASK_START = offsetof(NRF_RNG_Type, TASKS_START), /**< Start the random number generator. */ + NRF_RNG_TASK_STOP = offsetof(NRF_RNG_Type, TASKS_STOP) /**< Stop the random number generator. */ +} nrf_rng_task_t; /*lint -restore */ + +/** + * @enum nrf_rng_event_t + * @brief RNG events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_RNG_EVENT_VALRDY = offsetof(NRF_RNG_Type, EVENTS_VALRDY) /**< New random number generated event. */ +} nrf_rng_event_t; /*lint -restore */ + +/** + * @enum nrf_rng_int_mask_t + * @brief RNG interrupts. + */ +typedef enum +{ + NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event. */ +} nrf_rng_int_mask_t; + +/** + * @enum nrf_rng_short_mask_t + * @brief Types of RNG shortcuts. + */ +typedef enum +{ + NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**< Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */ +} nrf_rng_short_mask_t; + +/** + * @brief Function for enabling interrupts. + * + * @param[in] rng_int_mask Mask of interrupts. + */ +__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask); + +/** + * @brief Function for disabling interrupts. + * + * @param[in] rng_int_mask Mask of interrupts. + */ +__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask); + +/** + * @brief Function for getting the state of a specific interrupt. + * + * @param[in] rng_int_mask Interrupt. + * + * @retval true If the interrupt is not enabled. + * @retval false If the interrupt is enabled. + */ +__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask); + +/** + * @brief Function for getting the address of a specific task. + * + * This function can be used by the PPI module. + * + * @param[in] rng_task Task. + */ +__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task); + +/** + * @brief Function for setting a specific task. + * + * @param[in] rng_task Task. + */ +__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task); + +/** + * @brief Function for getting address of a specific event. + * + * This function can be used by the PPI module. + * + * @param[in] rng_event Event. + */ +__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event); + +/** + * @brief Function for clearing a specific event. + * + * @param[in] rng_event Event. + */ +__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event); + +/** + * @brief Function for getting the state of a specific event. + * + * @param[in] rng_event Event. + * + * @retval true If the event is not set. + * @retval false If the event is set. + */ +__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event); + +/** + * @brief Function for setting shortcuts. + * + * @param[in] rng_short_mask Mask of shortcuts. + * + */ +__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask); + +/** + * @brief Function for clearing shortcuts. + * + * @param[in] rng_short_mask Mask of shortcuts. + * + */ +__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask); + +/** + * @brief Function for getting the previously generated random value. + * + * @return Previously generated random value. + */ +__STATIC_INLINE uint8_t nrf_rng_random_value_get(void); + +/** + * @brief Function for enabling digital error correction. + */ +__STATIC_INLINE void nrf_rng_error_correction_enable(void); + +/** + * @brief Function for disabling digital error correction. + */ +__STATIC_INLINE void nrf_rng_error_correction_disable(void); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask) +{ + NRF_RNG->INTENSET = rng_int_mask; +} + +__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask) +{ + NRF_RNG->INTENCLR = rng_int_mask; +} + +__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask) +{ + return (bool)(NRF_RNG->INTENCLR & rng_int_mask); +} + +__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task) +{ + return (uint32_t *)((uint8_t *)NRF_RNG + rng_task); +} + +__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_task)) = NRF_RNG_TASK_SET; +} + +__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event) +{ + return (uint32_t *)((uint8_t *)NRF_RNG + rng_event); +} + +__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)) = NRF_RNG_EVENT_CLEAR; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event) +{ + return (bool) * ((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)); +} + +__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask) +{ + NRF_RNG->SHORTS |= rng_short_mask; +} + +__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask) +{ + NRF_RNG->SHORTS &= ~rng_short_mask; +} + +__STATIC_INLINE uint8_t nrf_rng_random_value_get(void) +{ + return (uint8_t)(NRF_RNG->VALUE & RNG_VALUE_VALUE_Msk); +} + +__STATIC_INLINE void nrf_rng_error_correction_enable(void) +{ + NRF_RNG->CONFIG |= RNG_CONFIG_DERCEN_Msk; +} + +__STATIC_INLINE void nrf_rng_error_correction_disable(void) +{ + NRF_RNG->CONFIG &= ~RNG_CONFIG_DERCEN_Msk; +} + +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_RNG_H__ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_rtc.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_rtc.h new file mode 100755 index 0000000..a104ab8 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_rtc.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_RTC_H +#define NRF_RTC_H + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_rtc_hal RTC HAL + * @{ + * @ingroup nrf_rtc + * @brief Hardware access layer for managing the Real Time Counter (RTC) peripheral. + */ + +/** + * @brief Macro for getting the number of compare channels available + * in a given RTC instance. + */ + +#define NRF_RTC_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(RTC, id, _CC_NUM) + +#define RTC_INPUT_FREQ 32768 /**< Input frequency of the RTC instance. */ + +/** + * @brief Macro for converting expected frequency to prescaler setting. + */ +#define RTC_FREQ_TO_PRESCALER(FREQ) (uint16_t)(((RTC_INPUT_FREQ) / (FREQ)) - 1) + +/**< Macro for wrapping values to RTC capacity. */ +#define RTC_WRAP(val) ((val) & RTC_COUNTER_COUNTER_Msk) + +#define RTC_CHANNEL_INT_MASK(ch) ((uint32_t)(NRF_RTC_INT_COMPARE0_MASK) << (ch)) +#define RTC_CHANNEL_EVENT_ADDR(ch) (nrf_rtc_event_t)((NRF_RTC_EVENT_COMPARE_0) + (ch) * sizeof(uint32_t)) +/** + * @enum nrf_rtc_task_t + * @brief RTC tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_RTC_TASK_START = offsetof(NRF_RTC_Type,TASKS_START), /**< Start. */ + NRF_RTC_TASK_STOP = offsetof(NRF_RTC_Type,TASKS_STOP), /**< Stop. */ + NRF_RTC_TASK_CLEAR = offsetof(NRF_RTC_Type,TASKS_CLEAR), /**< Clear. */ + NRF_RTC_TASK_TRIGGER_OVERFLOW = offsetof(NRF_RTC_Type,TASKS_TRIGOVRFLW),/**< Trigger overflow. */ + /*lint -restore*/ +} nrf_rtc_task_t; + +/** + * @enum nrf_rtc_event_t + * @brief RTC events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_RTC_EVENT_TICK = offsetof(NRF_RTC_Type,EVENTS_TICK), /**< Tick event. */ + NRF_RTC_EVENT_OVERFLOW = offsetof(NRF_RTC_Type,EVENTS_OVRFLW), /**< Overflow event. */ + NRF_RTC_EVENT_COMPARE_0 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[0]), /**< Compare 0 event. */ + NRF_RTC_EVENT_COMPARE_1 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[1]), /**< Compare 1 event. */ + NRF_RTC_EVENT_COMPARE_2 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[2]), /**< Compare 2 event. */ + NRF_RTC_EVENT_COMPARE_3 = offsetof(NRF_RTC_Type,EVENTS_COMPARE[3]) /**< Compare 3 event. */ + /*lint -restore*/ +} nrf_rtc_event_t; + +/** + * @enum nrf_rtc_int_t + * @brief RTC interrupts. + */ +typedef enum +{ + NRF_RTC_INT_TICK_MASK = RTC_INTENSET_TICK_Msk, /**< RTC interrupt from tick event. */ + NRF_RTC_INT_OVERFLOW_MASK = RTC_INTENSET_OVRFLW_Msk, /**< RTC interrupt from overflow event. */ + NRF_RTC_INT_COMPARE0_MASK = RTC_INTENSET_COMPARE0_Msk, /**< RTC interrupt from compare event on channel 0. */ + NRF_RTC_INT_COMPARE1_MASK = RTC_INTENSET_COMPARE1_Msk, /**< RTC interrupt from compare event on channel 1. */ + NRF_RTC_INT_COMPARE2_MASK = RTC_INTENSET_COMPARE2_Msk, /**< RTC interrupt from compare event on channel 2. */ + NRF_RTC_INT_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk /**< RTC interrupt from compare event on channel 3. */ +} nrf_rtc_int_t; + +/**@brief Function for setting a compare value for a channel. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] ch Channel. + * @param[in] cc_val Compare value to set. + */ +__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val); + +/**@brief Function for returning the compare value for a channel. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] ch Channel. + * + * @return COMPARE[ch] value. + */ +__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch); + +/**@brief Function for enabling interrupts. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] mask Interrupt mask to be enabled. + */ +__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask); + +/**@brief Function for disabling interrupts. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] mask Interrupt mask to be disabled. + */ +__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask); + +/**@brief Function for checking if interrupts are enabled. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] mask Mask of interrupt flags to check. + * + * @return Mask with enabled interrupts. + */ +__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask); + +/**@brief Function for returning the status of currently enabled interrupts. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * + * @return Value in INTEN register. + */ +__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc); + +/**@brief Function for checking if an event is pending. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] event Address of the event. + * + * @return Mask of pending events. + */ +__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); + +/**@brief Function for clearing an event. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); + +/**@brief Function for returning a counter value. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * + * @return Counter value. + */ +__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc); + +/**@brief Function for setting a prescaler value. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] val Value to set the prescaler to. + */ +__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val); + +/**@brief Function for returning the address of an event. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] event Requested event. + * + * @return Address of the requested event register. + */ +__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event); + +/**@brief Function for returning the address of a task. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] task Requested task. + * + * @return Address of the requested task register. + */ +__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task); + +/**@brief Function for starting a task. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] task Requested task. + */ +__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task); + +/**@brief Function for enabling events. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] mask Mask of event flags to enable. + */ +__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask); + +/**@brief Function for disabling an event. + * + * @param[in] p_rtc Pointer to the peripheral registers structure. + * @param[in] event Requested event. + */ +__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t event); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val) +{ + p_rtc->CC[ch] = cc_val; +} + +__STATIC_INLINE uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch) +{ + return p_rtc->CC[ch]; +} + +__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + p_rtc->INTENSET = mask; +} + +__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + p_rtc->INTENCLR = mask; +} + +__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + return (p_rtc->INTENSET & mask); +} + +__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc) +{ + return p_rtc->INTENSET; +} + +__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) +{ + return *(volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event); +} + +__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc) +{ + return p_rtc->COUNTER; +} + +__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val) +{ + NRFX_ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos)); + p_rtc->PRESCALER = val; +} +__STATIC_INLINE uint32_t rtc_prescaler_get(NRF_RTC_Type * p_rtc) +{ + return p_rtc->PRESCALER; +} + +__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event) +{ + return (uint32_t)p_rtc + event; +} + +__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task) +{ + return (uint32_t)p_rtc + task; +} + +__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task) +{ + *(__IO uint32_t *)((uint32_t)p_rtc + task) = 1; +} + +__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + p_rtc->EVTENSET = mask; +} +__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t mask) +{ + p_rtc->EVTENCLR = mask; +} +#endif + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_RTC_H */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_saadc.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_saadc.h new file mode 100755 index 0000000..5371418 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_saadc.h @@ -0,0 +1,658 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_SAADC_H_ +#define NRF_SAADC_H_ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_saadc_hal SAADC HAL + * @{ + * @ingroup nrf_saadc + * @brief Hardware access layer for managing the SAADC peripheral. + */ + +#define NRF_SAADC_CHANNEL_COUNT 8 + +/** + * @brief Resolution of the analog-to-digital converter. + */ +typedef enum +{ + NRF_SAADC_RESOLUTION_8BIT = SAADC_RESOLUTION_VAL_8bit, ///< 8 bit resolution. + NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution. + NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution. + NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit ///< 14 bit resolution. +} nrf_saadc_resolution_t; + + +/** + * @brief Input selection for the analog-to-digital converter. + */ +typedef enum +{ + NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC, ///< Not connected. + NRF_SAADC_INPUT_AIN0 = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0). + NRF_SAADC_INPUT_AIN1 = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1). + NRF_SAADC_INPUT_AIN2 = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2). + NRF_SAADC_INPUT_AIN3 = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3). + NRF_SAADC_INPUT_AIN4 = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4). + NRF_SAADC_INPUT_AIN5 = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5). + NRF_SAADC_INPUT_AIN6 = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6). + NRF_SAADC_INPUT_AIN7 = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7). + NRF_SAADC_INPUT_VDD = SAADC_CH_PSELP_PSELP_VDD ///< VDD as input. +} nrf_saadc_input_t; + + +/** + * @brief Analog-to-digital converter oversampling mode. + */ +typedef enum +{ + NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass, ///< No oversampling. + NRF_SAADC_OVERSAMPLE_2X = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x, ///< Oversample 2x. + NRF_SAADC_OVERSAMPLE_4X = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x, ///< Oversample 4x. + NRF_SAADC_OVERSAMPLE_8X = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x, ///< Oversample 8x. + NRF_SAADC_OVERSAMPLE_16X = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x, ///< Oversample 16x. + NRF_SAADC_OVERSAMPLE_32X = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x, ///< Oversample 32x. + NRF_SAADC_OVERSAMPLE_64X = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x, ///< Oversample 64x. + NRF_SAADC_OVERSAMPLE_128X = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x. + NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x. +} nrf_saadc_oversample_t; + + +/** + * @brief Analog-to-digital converter channel resistor control. + */ +typedef enum +{ + NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass, ///< Bypass resistor ladder. + NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND. + NRF_SAADC_RESISTOR_PULLUP = SAADC_CH_CONFIG_RESP_Pullup, ///< Pull-up to VDD. + NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDD1_2 ///< Set input at VDD/2. +} nrf_saadc_resistor_t; + + +/** + * @brief Gain factor of the analog-to-digital converter input. + */ +typedef enum +{ + NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6. + NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5. + NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4. + NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3. + NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2. + NRF_SAADC_GAIN1 = SAADC_CH_CONFIG_GAIN_Gain1, ///< Gain factor 1. + NRF_SAADC_GAIN2 = SAADC_CH_CONFIG_GAIN_Gain2, ///< Gain factor 2. + NRF_SAADC_GAIN4 = SAADC_CH_CONFIG_GAIN_Gain4, ///< Gain factor 4. +} nrf_saadc_gain_t; + + +/** + * @brief Reference selection for the analog-to-digital converter. + */ +typedef enum +{ + NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V). + NRF_SAADC_REFERENCE_VDD4 = SAADC_CH_CONFIG_REFSEL_VDD1_4 ///< VDD/4 as reference. +} nrf_saadc_reference_t; + + +/** + * @brief Analog-to-digital converter acquisition time. + */ +typedef enum +{ + NRF_SAADC_ACQTIME_3US = SAADC_CH_CONFIG_TACQ_3us, ///< 3 us. + NRF_SAADC_ACQTIME_5US = SAADC_CH_CONFIG_TACQ_5us, ///< 5 us. + NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us. + NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us. + NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us. + NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us ///< 40 us. +} nrf_saadc_acqtime_t; + + +/** + * @brief Analog-to-digital converter channel mode. + */ +typedef enum +{ + NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE, ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND. + NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode. +} nrf_saadc_mode_t; + + +/** + * @brief Analog-to-digital converter channel burst mode. + */ +typedef enum +{ + NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation). + NRF_SAADC_BURST_ENABLED = SAADC_CH_CONFIG_BURST_Enabled ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. +} nrf_saadc_burst_t; + + +/** + * @brief Analog-to-digital converter tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM. + NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled. + NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any on-going conversion. + NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration. +} nrf_saadc_task_t; + + +/** + * @brief Analog-to-digital converter events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started. + NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer. + NRF_SAADC_EVENT_DONE = offsetof(NRF_SAADC_Type, EVENTS_DONE), ///< A conversion task has been completed. + NRF_SAADC_EVENT_RESULTDONE = offsetof(NRF_SAADC_Type, EVENTS_RESULTDONE), ///< A result is ready to get transferred to RAM. + NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete. + NRF_SAADC_EVENT_STOPPED = offsetof(NRF_SAADC_Type, EVENTS_STOPPED), ///< The ADC has stopped. + NRF_SAADC_EVENT_CH0_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH), ///< Last result is equal or above CH[0].LIMIT.HIGH. + NRF_SAADC_EVENT_CH0_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL), ///< Last result is equal or below CH[0].LIMIT.LOW. + NRF_SAADC_EVENT_CH1_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH), ///< Last result is equal or above CH[1].LIMIT.HIGH. + NRF_SAADC_EVENT_CH1_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL), ///< Last result is equal or below CH[1].LIMIT.LOW. + NRF_SAADC_EVENT_CH2_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH), ///< Last result is equal or above CH[2].LIMIT.HIGH. + NRF_SAADC_EVENT_CH2_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL), ///< Last result is equal or below CH[2].LIMIT.LOW. + NRF_SAADC_EVENT_CH3_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH), ///< Last result is equal or above CH[3].LIMIT.HIGH. + NRF_SAADC_EVENT_CH3_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL), ///< Last result is equal or below CH[3].LIMIT.LOW. + NRF_SAADC_EVENT_CH4_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH), ///< Last result is equal or above CH[4].LIMIT.HIGH. + NRF_SAADC_EVENT_CH4_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL), ///< Last result is equal or below CH[4].LIMIT.LOW. + NRF_SAADC_EVENT_CH5_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH), ///< Last result is equal or above CH[5].LIMIT.HIGH. + NRF_SAADC_EVENT_CH5_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL), ///< Last result is equal or below CH[5].LIMIT.LOW. + NRF_SAADC_EVENT_CH6_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH), ///< Last result is equal or above CH[6].LIMIT.HIGH. + NRF_SAADC_EVENT_CH6_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL), ///< Last result is equal or below CH[6].LIMIT.LOW. + NRF_SAADC_EVENT_CH7_LIMITH = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH), ///< Last result is equal or above CH[7].LIMIT.HIGH. + NRF_SAADC_EVENT_CH7_LIMITL = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL) ///< Last result is equal or below CH[7].LIMIT.LOW. +} nrf_saadc_event_t; + + +/** + * @brief Analog-to-digital converter interrupt masks. + */ +typedef enum +{ + NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event. + NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event. + NRF_SAADC_INT_DONE = SAADC_INTENSET_DONE_Msk, ///< Interrupt on EVENTS_DONE event. + NRF_SAADC_INT_RESULTDONE = SAADC_INTENSET_RESULTDONE_Msk, ///< Interrupt on EVENTS_RESULTDONE event. + NRF_SAADC_INT_CALIBRATEDONE = SAADC_INTENSET_CALIBRATEDONE_Msk, ///< Interrupt on EVENTS_CALIBRATEDONE event. + NRF_SAADC_INT_STOPPED = SAADC_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event. + NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event. + NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event. + NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event. + NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event. + NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event. + NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event. + NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event. + NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event. + NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event. + NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event. + NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event. + NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event. + NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event. + NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event. + NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event. + NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event. + NRF_SAADC_INT_ALL = 0x7FFFFFFFUL ///< Mask of all interrupts. +} nrf_saadc_int_mask_t; + + +/** + * @brief Analog-to-digital converter value limit type. + */ +typedef enum +{ + NRF_SAADC_LIMIT_LOW = 0, + NRF_SAADC_LIMIT_HIGH = 1 +} nrf_saadc_limit_t; + + +typedef int16_t nrf_saadc_value_t; ///< Type of a single ADC conversion result. + + +/** + * @brief Analog-to-digital converter configuration structure. + */ +typedef struct +{ + nrf_saadc_resolution_t resolution; + nrf_saadc_oversample_t oversample; + nrf_saadc_value_t * buffer; + uint32_t buffer_size; +} nrf_saadc_config_t; + + +/** + * @brief Analog-to-digital converter channel configuration structure. + */ +typedef struct +{ + nrf_saadc_resistor_t resistor_p; + nrf_saadc_resistor_t resistor_n; + nrf_saadc_gain_t gain; + nrf_saadc_reference_t reference; + nrf_saadc_acqtime_t acq_time; + nrf_saadc_mode_t mode; + nrf_saadc_burst_t burst; + nrf_saadc_input_t pin_p; + nrf_saadc_input_t pin_n; +} nrf_saadc_channel_config_t; + + +/** + * @brief Function for triggering a specific SAADC task. + * + * @param[in] saadc_task SAADC task. + */ +__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL; +} + + +/** + * @brief Function for getting the address of a specific SAADC task register. + * + * @param[in] saadc_task SAADC task. + * + * @return Address of the specified SAADC task. + */ +__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task) +{ + return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task); +} + + +/** + * @brief Function for getting the state of a specific SAADC event. + * + * @param[in] saadc_event SAADC event. + * + * @return State of the specified SAADC event. + */ +__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event); +} + + +/** + * @brief Function for clearing the specific SAADC event. + * + * @param[in] saadc_event SAADC event. + */ +__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)); + (void)dummy; +#endif +} + + +/** + * @brief Function for getting the address of a specific SAADC event register. + * + * @param[in] saadc_event SAADC event. + * + * @return Address of the specified SAADC event. + */ +__STATIC_INLINE uint32_t nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event) +{ + return (uint32_t )((uint8_t *)NRF_SAADC + (uint32_t)saadc_event); +} + + +/** + * @brief Function for getting the address of a specific SAADC limit event register. + * + * @param[in] channel Channel number. + * @param[in] limit_type Low limit or high limit. + * + * @return Address of the specified SAADC limit event. + */ +__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type) +{ + NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); + if (limit_type == NRF_SAADC_LIMIT_HIGH) + { + return &NRF_SAADC->EVENTS_CH[channel].LIMITH; + } + else + { + return &NRF_SAADC->EVENTS_CH[channel].LIMITL; + } +} + + +/** + * @brief Function for getting the SAADC channel monitoring limit events. + * + * @param[in] channel Channel number. + * @param[in] limit_type Low limit or high limit. + */ +__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type) +{ + if (limit_type == NRF_SAADC_LIMIT_HIGH) + { + return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITH + + (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITH - NRF_SAADC_EVENT_CH0_LIMITH) + * (uint32_t) channel ); + } + else + { + return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITL + + (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITL - NRF_SAADC_EVENT_CH0_LIMITL) + * (uint32_t) channel ); + } +} + + +/** + * @brief Function for configuring the input pins for a specific SAADC channel. + * + * @param[in] channel Channel number. + * @param[in] pselp Positive input. + * @param[in] pseln Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode. + */ +__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel, + nrf_saadc_input_t pselp, + nrf_saadc_input_t pseln) +{ + NRF_SAADC->CH[channel].PSELN = pseln; + NRF_SAADC->CH[channel].PSELP = pselp; +} + + +/** + * @brief Function for configuring the positive input pin for a specific SAADC channel. + * + * @param[in] channel Channel number. + * @param[in] pselp Positive input. + */ +__STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel, + nrf_saadc_input_t pselp) +{ + NRF_SAADC->CH[channel].PSELP = pselp; +} + + +/** + * @brief Function for setting the SAADC channel monitoring limits. + * + * @param[in] channel Channel number. + * @param[in] low Low limit. + * @param[in] high High limit. + */ +__STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high) +{ + NRF_SAADC->CH[channel].LIMIT = ( + (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk) + | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk)); +} + + +/** + * @brief Function for enabling specified SAADC interrupts. + * + * @param[in] saadc_int_mask Interrupt(s) to enable. + */ +__STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask) +{ + NRF_SAADC->INTENSET = saadc_int_mask; +} + + +/** + * @brief Function for retrieving the state of specified SAADC interrupts. + * + * @param[in] saadc_int_mask Interrupt(s) to check. + * + * @retval true If all specified interrupts are enabled. + * @retval false If at least one of the given interrupts is not enabled. + */ +__STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask) +{ + return (bool)(NRF_SAADC->INTENSET & saadc_int_mask); +} + + +/** + * @brief Function for disabling specified interrupts. + * + * @param saadc_int_mask Interrupt(s) to disable. + */ +__STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask) +{ + NRF_SAADC->INTENCLR = saadc_int_mask; +} + + +/** + * @brief Function for generating masks for SAADC channel limit interrupts. + * + * @param[in] channel SAADC channel number. + * @param[in] limit_type Limit type. + * + * @returns Interrupt mask. + */ +__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type) +{ + NRFX_ASSERT(channel < NRF_SAADC_CHANNEL_COUNT); + uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH; + return mask << (channel * 2); +} + + +/** + * @brief Function for checking whether the SAADC is busy. + * + * This function checks whether the analog-to-digital converter is busy with a conversion. + * + * @retval true If the SAADC is busy. + * @retval false If the SAADC is not busy. + */ +__STATIC_INLINE bool nrf_saadc_busy_check(void) +{ + //return ((NRF_SAADC->STATUS & SAADC_STATUS_STATUS_Msk) == SAADC_STATUS_STATUS_Msk); + //simplified for performance + return NRF_SAADC->STATUS; +} + + +/** + * @brief Function for enabling the SAADC. + * + * The analog-to-digital converter must be enabled before use. + */ +__STATIC_INLINE void nrf_saadc_enable(void) +{ + NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos); +} + + +/** + * @brief Function for disabling the SAADC. + */ +__STATIC_INLINE void nrf_saadc_disable(void) +{ + NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos); +} + + +/** + * @brief Function for checking if the SAADC is enabled. + * + * @retval true If the SAADC is enabled. + * @retval false If the SAADC is not enabled. + */ +__STATIC_INLINE bool nrf_saadc_enable_check(void) +{ + //simplified for performance + return NRF_SAADC->ENABLE; +} + + +/** + * @brief Function for initializing the SAADC result buffer. + * + * @param[in] p_buffer Pointer to the result buffer. + * @param[in] size Size of the buffer (in 16-bit samples). + */ +__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * p_buffer, + uint32_t size) +{ + NRF_SAADC->RESULT.PTR = (uint32_t)p_buffer; + NRF_SAADC->RESULT.MAXCNT = size; +} + + +/** + * @brief Function for setting the SAADC result buffer pointer. + * + * @param[in] p_buffer Pointer to the result buffer. + */ +__STATIC_INLINE void nrf_saadc_buffer_pointer_set(nrf_saadc_value_t * p_buffer) +{ + NRF_SAADC->RESULT.PTR = (uint32_t)p_buffer; +} + + +/** + * @brief Function for getting the SAADC result buffer pointer. + * + * @return Pointer to the result buffer. + */ +__STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(void) +{ + return (nrf_saadc_value_t *)NRF_SAADC->RESULT.PTR; +} + + +/** + * @brief Function for getting the number of samples written to the result + * buffer since the previous START task. + * + * @returns Number of 16-bit samples written to the buffer. + */ +__STATIC_INLINE uint16_t nrf_saadc_amount_get(void) +{ + return NRF_SAADC->RESULT.AMOUNT; +} + + +/** + * @brief Function for setting the SAADC sample resolution. + * + * @param[in] resolution Bit resolution. + */ +__STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution) +{ + NRF_SAADC->RESOLUTION = resolution; +} + + +/** + * @brief Function for configuring the oversampling feature. + * + * @param[in] oversample Oversampling mode. + */ +__STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample) +{ + NRF_SAADC->OVERSAMPLE = oversample; +} + +/** + * @brief Function for getting the oversampling feature configuration. + * + * @return Oversampling configuration. + */ +__STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void) +{ + return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE; +} + +/** + * @brief Function for initializing the SAADC channel. + * + * @param[in] channel Channel number. + * @param[in] config Pointer to the channel configuration structure. + */ +__STATIC_INLINE void nrf_saadc_channel_init(uint8_t channel, + nrf_saadc_channel_config_t const * const config) +{ + NRF_SAADC->CH[channel].CONFIG = + ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk) + | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk) + | ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk) + | ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk) + | ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk) + | ((config->mode << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk) + | ((config->burst << SAADC_CH_CONFIG_BURST_Pos) & SAADC_CH_CONFIG_BURST_Msk); + nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n); +} + +/** + * @brief Function for configuring the burst mode for the specified channel. + * + * @param[in] channel Channel number. + * @param[in] burst Burst mode setting. + */ +__STATIC_INLINE void nrf_saadc_burst_set(uint8_t channel, + nrf_saadc_burst_t burst) +{ + NRF_SAADC->CH[channel].CONFIG = + (NRF_SAADC->CH[channel].CONFIG & ~SAADC_CH_CONFIG_BURST_Msk) | + (burst << SAADC_CH_CONFIG_BURST_Pos); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_SAADC_H_ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spi.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spi.h new file mode 100755 index 0000000..d942d2d --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spi.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_SPI_H__ +#define NRF_SPI_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_spi_hal SPI HAL + * @{ + * @ingroup nrf_spi + * @brief Hardware access layer for managing the SPI peripheral. + */ + +/** + * @brief This value can be used as a parameter for the @ref nrf_spi_pins_set + * function to specify that a given SPI signal (SCK, MOSI, or MISO) + * shall not be connected to a physical pin. + */ +#define NRF_SPI_PIN_NOT_CONNECTED 0xFFFFFFFF + + +/** + * @brief SPI events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received. + /*lint -restore*/ +} nrf_spi_event_t; + +/** + * @brief SPI interrupts. + */ +typedef enum +{ + NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk, ///< Interrupt on READY event. + NRF_SPI_ALL_INTS_MASK = SPI_INTENSET_READY_Msk ///< All SPI interrupts. +} nrf_spi_int_mask_t; + +/** + * @brief SPI data rates. + */ +typedef enum +{ + NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125, ///< 125 kbps. + NRF_SPI_FREQ_250K = SPI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_SPI_FREQ_500K = SPI_FREQUENCY_FREQUENCY_K500, ///< 500 kbps. + NRF_SPI_FREQ_1M = SPI_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps. + NRF_SPI_FREQ_2M = SPI_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps. + NRF_SPI_FREQ_4M = SPI_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps. + // [conversion to 'int' needed to prevent compilers from complaining + // that the provided value (0x80000000UL) is out of range of "int"] + NRF_SPI_FREQ_8M = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps. +} nrf_spi_frequency_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_SPI_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_spi_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. + NRF_SPI_BIT_ORDER_LSB_FIRST = SPI_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. +} nrf_spi_bit_order_t; + + +/** + * @brief Function for clearing a specific SPI event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_event Event to clear. + */ +__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event); + +/** + * @brief Function for checking the state of a specific SPI event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event); + +/** + * @brief Function for getting the address of a specific SPI event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg, + uint32_t spi_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg, + uint32_t spi_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg, + nrf_spi_int_mask_t spi_int); + +/** + * @brief Function for enabling the SPI peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg); + +/** + * @brief Function for disabling the SPI peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg); + +/** + * @brief Function for configuring SPI pins. + * + * If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] sck_pin SCK pin number. + * @param[in] mosi_pin MOSI pin number. + * @param[in] miso_pin MISO pin number. + */ +__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin); + +/** + * @brief Function for writing data to the SPI transmitter register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] data TX data to send. + */ +__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data); + +/** + * @brief Function for reading data from the SPI receiver register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return RX data received. + */ +__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg); + +/** + * @brief Function for setting the SPI master data rate. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] frequency SPI frequency. + */ +__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg, + nrf_spi_frequency_t frequency); + +/** + * @brief Function for setting the SPI configuration. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_mode SPI mode. + * @param[in] spi_bit_order SPI bit order. + */ +__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg, + nrf_spi_mode_t spi_mode, + nrf_spi_bit_order_t spi_bit_order); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event); +} + +__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg, + nrf_spi_event_t spi_event) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event); +} + +__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg, + uint32_t spi_int_mask) +{ + p_reg->INTENSET = spi_int_mask; +} + +__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg, + uint32_t spi_int_mask) +{ + p_reg->INTENCLR = spi_int_mask; +} + +__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg, + nrf_spi_int_mask_t spi_int) +{ + return (bool)(p_reg->INTENSET & spi_int); +} + +__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg) +{ + p_reg->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg) +{ + p_reg->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin) +{ + p_reg->PSELSCK = sck_pin; + p_reg->PSELMOSI = mosi_pin; + p_reg->PSELMISO = miso_pin; +} + +__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data) +{ + p_reg->TXD = data; +} + +__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg) +{ + return p_reg->RXD; +} + +__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg, + nrf_spi_frequency_t frequency) +{ + p_reg->FREQUENCY = frequency; +} + +__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg, + nrf_spi_mode_t spi_mode, + nrf_spi_bit_order_t spi_bit_order) +{ + uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ? + SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst); + switch (spi_mode) + { + default: + case NRF_SPI_MODE_0: + config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_1: + config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_2: + config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos); + break; + + case NRF_SPI_MODE_3: + config |= (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos) | + (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos); + break; + } + p_reg->CONFIG = config; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_SPI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spim.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spim.h new file mode 100755 index 0000000..46717bc --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spim.h @@ -0,0 +1,727 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_SPIM_H__ +#define NRF_SPIM_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_spim_hal SPIM HAL + * @{ + * @ingroup nrf_spim + * @brief Hardware access layer for managing the SPIM peripheral. + */ + +/** + * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set + * function to specify that a given SPI signal (SCK, MOSI, or MISO) + * shall not be connected to a physical pin. + */ +#define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF + +#if defined(SPIM_DCXCNT_DCXCNT_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief This value specified in the DCX line configuration causes this line + * to be set low during whole transmission (all transmitted bytes are + * marked as command bytes). Any lower value causes the DCX line to be + * switched from low to high after this number of bytes is transmitted + * (all remaining bytes are marked as data bytes). + */ +#define NRF_SPIM_DCX_CNT_ALL_CMD 0xF +#endif + +#define NRF_SPIM_HW_CSN_PRESENT \ + (NRFX_CHECK(SPIM0_FEATURE_HARDWARE_CSN_PRESENT) || \ + NRFX_CHECK(SPIM1_FEATURE_HARDWARE_CSN_PRESENT) || \ + NRFX_CHECK(SPIM2_FEATURE_HARDWARE_CSN_PRESENT) || \ + NRFX_CHECK(SPIM3_FEATURE_HARDWARE_CSN_PRESENT)) + +/** + * @brief SPIM tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction. + NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction. + NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction. + NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME) ///< Resume SPI transaction. + /*lint -restore*/ +} nrf_spim_task_t; + +/** + * @brief SPIM events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped. + NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached. + NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END), ///< End of RXD buffer and TXD buffer reached. + NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached. + NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED) ///< Transaction started. + /*lint -restore*/ +} nrf_spim_event_t; + +/** + * @brief SPIM shortcuts. + */ +typedef enum +{ + NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk, ///< Shortcut between END event and START task. + NRF_SPIM_ALL_SHORTS_MASK = SPIM_SHORTS_END_START_Msk ///< All SPIM shortcuts. +} nrf_spim_short_mask_t; + +/** + * @brief SPIM interrupts. + */ +typedef enum +{ + NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event. + NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event. + NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event. + NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk, ///< Interrupt on STARTED event. + NRF_SPIM_ALL_INTS_MASK = SPIM_INTENSET_STOPPED_Msk | + SPIM_INTENSET_ENDRX_Msk | + SPIM_INTENSET_END_Msk | + SPIM_INTENSET_ENDTX_Msk | + SPIM_INTENSET_STARTED_Msk ///< All SPIM interrupts. +} nrf_spim_int_mask_t; + +/** + * @brief SPI master data rates. + */ +typedef enum +{ + NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps. + NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps. + NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps. + NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps. + NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps. + // [conversion to 'int' needed to prevent compilers from complaining + // that the provided value (0x80000000UL) is out of range of "int"] + NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8, ///< 8 Mbps. +#if defined(SPIM_FREQUENCY_FREQUENCY_M16) || defined(__NRFX_DOXYGEN__) + NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16, ///< 16 Mbps. +#endif +#if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__) + NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32 ///< 32 Mbps. +#endif +} nrf_spim_frequency_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_spim_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. + NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. +} nrf_spim_bit_order_t; + +#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief SPI CSN pin polarity. + */ +typedef enum +{ + NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high). + NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH ///< Active high (idle state low). +} nrf_spim_csn_pol_t; +#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for activating a specific SPIM task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_task Task to activate. + */ +__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg, + nrf_spim_task_t spim_task); + +/** + * @brief Function for getting the address of a specific SPIM task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg, + nrf_spim_task_t spim_task); + +/** + * @brief Function for clearing a specific SPIM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_event Event to clear. + */ +__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event); + +/** + * @brief Function for checking the state of a specific SPIM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event); + +/** + * @brief Function for getting the address of a specific SPIM event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event); +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg, + uint32_t spim_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg, + uint32_t spim_shorts_mask); + +/** + * @brief Function for getting shorts setting. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg, + uint32_t spim_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg, + uint32_t spim_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spim_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg, + nrf_spim_int_mask_t spim_int); + +/** + * @brief Function for enabling the SPIM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for disabling the SPIM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for configuring SPIM pins. + * + * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] sck_pin SCK pin number. + * @param[in] mosi_pin MOSI pin number. + * @param[in] miso_pin MISO pin number. + */ +__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin); + +#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for configuring the SPIM hardware CSN pin. + * + * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] pin CSN pin number. + * @param[in] polarity CSN pin polarity. + * @param[in] duration Minimum duration between the edge of CSN and the edge of SCK + * and minimum duration of CSN must stay unselected between transactions. + * The value is specified in number of 64 MHz clock cycles (15.625 ns). + */ +__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg, + uint32_t pin, + nrf_spim_csn_pol_t polarity, + uint32_t duration); +#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__) + +#if defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for configuring the SPIM DCX pin. + * + * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] dcx_pin DCX pin number. + */ +__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, + uint32_t dcx_pin); + +/** + * @brief Function for configuring the number of command bytes. + * + * Maximum value available for dividing the transmitted bytes into command + * bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1. + * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the @c count parameter + * causes all transmitted bytes to be marked as command bytes. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] count Number of command bytes preceding the data bytes. + */ +__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, + uint32_t count); +#endif // defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for configuring the extended SPIM interface. + * @param p_reg Pointer to the peripheral registers structure. + * @param rxdelay Sample delay for input serial data on MISO, + * specified in 64 MHz clock cycles (15.625 ns) from the sampling edge of SCK. + */ +__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg, + uint32_t rxdelay); +#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for clearing stall status for RX EasyDMA RAM accesses. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for getting stall status for RX EasyDMA RAM accesses. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @return Stall status of RX EasyDMA RAM accesses. + */ +__STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg); +#endif // defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__) + +#if defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__) +/** + * @brief Function for clearing stall status for TX EasyDMA RAM accesses. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for getting stall status for TX EasyDMA RAM accesses. + * + * @param p_reg Pointer to the peripheral registers structure. + * + * @return Stall status of TX EasyDMA RAM accesses. + */ +__STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg); +#endif // defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__) + +/** + * @brief Function for setting the SPI master data rate. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] frequency SPI frequency. + */ +__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg, + nrf_spim_frequency_t frequency); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg, + uint8_t const * p_buffer, + size_t length); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg, + uint8_t * p_buffer, + size_t length); + +/** + * @brief Function for setting the SPI configuration. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_mode SPI mode. + * @param[in] spi_bit_order SPI bit order. + */ +__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg, + nrf_spim_mode_t spi_mode, + nrf_spim_bit_order_t spi_bit_order); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] orc Over-read character that is clocked out in case of + * an over-read of the TXD buffer. + */ +__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg, + uint8_t orc); + +/** + * @brief Function for enabling the TX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for disabling the TX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for enabling the RX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg); + +/** + * @brief Function for disabling the RX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg, + nrf_spim_task_t spim_task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg, + nrf_spim_task_t spim_task) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_task); +} + +__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event); +} + +__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg, + nrf_spim_event_t spim_event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_event); +} + +__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg, + uint32_t spim_shorts_mask) +{ + p_reg->SHORTS |= spim_shorts_mask; +} + +__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg, + uint32_t spim_shorts_mask) +{ + p_reg->SHORTS &= ~(spim_shorts_mask); +} + +__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg) +{ + return p_reg->SHORTS; +} + +__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg, + uint32_t spim_int_mask) +{ + p_reg->INTENSET = spim_int_mask; +} + +__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg, + uint32_t spim_int_mask) +{ + p_reg->INTENCLR = spim_int_mask; +} + +__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg, + nrf_spim_int_mask_t spim_int) +{ + return (bool)(p_reg->INTENSET & spim_int); +} + +__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg) +{ + p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg) +{ + p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin) +{ + p_reg->PSEL.SCK = sck_pin; + p_reg->PSEL.MOSI = mosi_pin; + p_reg->PSEL.MISO = miso_pin; +} + +#if (NRF_SPIM_HW_CSN_PRESENT) +__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg, + uint32_t pin, + nrf_spim_csn_pol_t polarity, + uint32_t duration) +{ + p_reg->PSEL.CSN = pin; + p_reg->CSNPOL = polarity; + p_reg->IFTIMING.CSNDUR = duration; +} +#endif // defined(NRF_SPIM_HW_CSN_PRESENT) + +#if defined(SPIM_PSELDCX_CONNECT_Msk) +__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, + uint32_t dcx_pin) +{ + p_reg->PSELDCX = dcx_pin; +} + +__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, + uint32_t dcx_cnt) +{ + p_reg->DCXCNT = dcx_cnt; +} +#endif // defined(SPIM_PSELDCX_CONNECT_Msk) + +#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) +__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg, + uint32_t rxdelay) +{ + p_reg->IFTIMING.RXDELAY = rxdelay; +} +#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) + +#if defined(SPIM_STALLSTAT_RX_Msk) +__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg) +{ + p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk); +} + +__STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg) +{ + return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0; +} +#endif // defined(SPIM_STALLSTAT_RX_Msk) + +#if defined(SPIM_STALLSTAT_TX_Msk) +__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg) +{ + p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk); +} + +__STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg) +{ + return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0; +} +#endif // defined(SPIM_STALLSTAT_TX_Msk) + +__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg, + nrf_spim_frequency_t frequency) +{ + p_reg->FREQUENCY = frequency; +} + +__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg, + uint8_t const * p_buffer, + size_t length) +{ + p_reg->TXD.PTR = (uint32_t)p_buffer; + p_reg->TXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg, + uint8_t * p_buffer, + size_t length) +{ + p_reg->RXD.PTR = (uint32_t)p_buffer; + p_reg->RXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg, + nrf_spim_mode_t spi_mode, + nrf_spim_bit_order_t spi_bit_order) +{ + uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ? + SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst); + switch (spi_mode) + { + default: + case NRF_SPIM_MODE_0: + config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_1: + config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_2: + config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos); + break; + + case NRF_SPIM_MODE_3: + config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) | + (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos); + break; + } + p_reg->CONFIG = config; +} + +__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg, + uint8_t orc) +{ + p_reg->ORC = orc; +} + + +__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg) +{ + p_reg->TXD.LIST = 1; +} + +__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg) +{ + p_reg->TXD.LIST = 0; +} + +__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg) +{ + p_reg->RXD.LIST = 1; +} + +__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg) +{ + p_reg->RXD.LIST = 0; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_SPIM_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spis.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spis.h new file mode 100755 index 0000000..a644c46 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_spis.h @@ -0,0 +1,562 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_SPIS_H__ +#define NRF_SPIS_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_spis_hal SPIS HAL + * @{ + * @ingroup nrf_spis + * @brief Hardware access layer for managing the SPIS peripheral. + */ + +/** + * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set + * function to specify that a given SPI signal (SCK, MOSI, or MISO) + * shall not be connected to a physical pin. + */ +#define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF + + +/** + * @brief SPIS tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore. + NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it. + /*lint -restore*/ +} nrf_spis_task_t; + +/** + * @brief SPIS events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed. + NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired. + /*lint -restore*/ +} nrf_spis_event_t; + +/** + * @brief SPIS shortcuts. + */ +typedef enum +{ + NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task. +} nrf_spis_short_mask_t; + +/** + * @brief SPIS interrupts. + */ +typedef enum +{ + NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event. + NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event. +} nrf_spis_int_mask_t; + +/** + * @brief SPI modes. + */ +typedef enum +{ + NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock. + NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock. + NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock. + NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock. +} nrf_spis_mode_t; + +/** + * @brief SPI bit orders. + */ +typedef enum +{ + NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first. + NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first. +} nrf_spis_bit_order_t; + +/** + * @brief SPI semaphore status. + */ +typedef enum +{ + NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free. + NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU. + NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave. + NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending. +} nrf_spis_semstat_t; + +/** + * @brief SPIS status. + */ +typedef enum +{ + NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented. + NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented. +} nrf_spis_status_mask_t; + +/** + * @brief Function for activating a specific SPIS task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_task Task to activate. + */ +__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg, + nrf_spis_task_t spis_task); + +/** + * @brief Function for getting the address of a specific SPIS task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg, + nrf_spis_task_t spis_task); + +/** + * @brief Function for clearing a specific SPIS event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_event Event to clear. + */ +__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg, + nrf_spis_event_t spis_event); + +/** + * @brief Function for checking the state of a specific SPIS event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg, + nrf_spis_event_t spis_event); + +/** + * @brief Function for getting the address of a specific SPIS event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg, + nrf_spis_event_t spis_event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg, + uint32_t spis_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg, + uint32_t spis_shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg, + uint32_t spis_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg, + uint32_t spis_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spis_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, + nrf_spis_int_mask_t spis_int); + +/** + * @brief Function for enabling the SPIS peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg); + +/** + * @brief Function for disabling the SPIS peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg); + +/** + * @brief Function for retrieving the SPIS semaphore status. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @returns Current semaphore status. + */ +__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg); + +/** + * @brief Function for retrieving the SPIS status. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @returns Current SPIS status. + */ +__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg); + +/** + * @brief Function for configuring SPIS pins. + * + * If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED + * value instead of its pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] sck_pin SCK pin number. + * @param[in] mosi_pin MOSI pin number. + * @param[in] miso_pin MISO pin number. + * @param[in] csn_pin CSN pin number. + */ +__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin, + uint32_t csn_pin); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer that contains the data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg, + uint8_t const * p_buffer, + size_t length); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg, + uint8_t * p_buffer, + size_t length); + +/** + * @brief Function for getting the number of bytes transmitted + * in the last granted transaction. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @returns Number of bytes transmitted. + */ +__STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg); + +/** + * @brief Function for getting the number of bytes received + * in the last granted transaction. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @returns Number of bytes received. + */ +__STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg); + +/** + * @brief Function for setting the SPI configuration. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] spi_mode SPI mode. + * @param[in] spi_bit_order SPI bit order. + */ +__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg, + nrf_spis_mode_t spi_mode, + nrf_spis_bit_order_t spi_bit_order); + +/** + * @brief Function for setting the default character. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] def Default character that is clocked out in case of + * an overflow of the RXD buffer. + */ +__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg, + uint8_t def); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] orc Over-read character that is clocked out in case of + * an over-read of the TXD buffer. + */ +__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg, + uint8_t orc); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg, + nrf_spis_task_t spis_task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg, + nrf_spis_task_t spis_task) +{ + return (uint32_t)p_reg + (uint32_t)spis_task; +} + +__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg, + nrf_spis_event_t spis_event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg, + nrf_spis_event_t spis_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event); +} + +__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg, + nrf_spis_event_t spis_event) +{ + return (uint32_t)p_reg + (uint32_t)spis_event; +} + +__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg, + uint32_t spis_shorts_mask) +{ + p_reg->SHORTS |= spis_shorts_mask; +} + +__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg, + uint32_t spis_shorts_mask) +{ + p_reg->SHORTS &= ~(spis_shorts_mask); +} + +__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg, + uint32_t spis_int_mask) +{ + p_reg->INTENSET = spis_int_mask; +} + +__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg, + uint32_t spis_int_mask) +{ + p_reg->INTENCLR = spis_int_mask; +} + +__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg, + nrf_spis_int_mask_t spis_int) +{ + return (bool)(p_reg->INTENSET & spis_int); +} + +__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg) +{ + p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg) +{ + p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg) +{ + return (nrf_spis_semstat_t) ((p_reg->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk) + >> SPIS_SEMSTAT_SEMSTAT_Pos); +} + +__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg) +{ + return (nrf_spis_status_mask_t) p_reg->STATUS; +} + +__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg, + uint32_t sck_pin, + uint32_t mosi_pin, + uint32_t miso_pin, + uint32_t csn_pin) +{ +#if defined (NRF51) + p_reg->PSELSCK = sck_pin; + p_reg->PSELMOSI = mosi_pin; + p_reg->PSELMISO = miso_pin; + p_reg->PSELCSN = csn_pin; +#else + p_reg->PSEL.SCK = sck_pin; + p_reg->PSEL.MOSI = mosi_pin; + p_reg->PSEL.MISO = miso_pin; + p_reg->PSEL.CSN = csn_pin; +#endif +} + +__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg, + uint8_t const * p_buffer, + size_t length) +{ +#if defined (NRF51) + p_reg->TXDPTR = (uint32_t)p_buffer; + p_reg->MAXTX = length; +#else + p_reg->TXD.PTR = (uint32_t)p_buffer; + p_reg->TXD.MAXCNT = length; +#endif +} + +__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg, + uint8_t * p_buffer, + size_t length) +{ +#if defined (NRF51) + p_reg->RXDPTR = (uint32_t)p_buffer; + p_reg->MAXRX = length; +#else + p_reg->RXD.PTR = (uint32_t)p_buffer; + p_reg->RXD.MAXCNT = length; +#endif +} + +__STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg) +{ +#if defined (NRF51) + return p_reg->AMOUNTTX; +#else + return p_reg->TXD.AMOUNT; +#endif +} + +__STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg) +{ +#if defined (NRF51) + return p_reg->AMOUNTRX; +#else + return p_reg->RXD.AMOUNT; +#endif +} + +__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg, + nrf_spis_mode_t spi_mode, + nrf_spis_bit_order_t spi_bit_order) +{ + uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ? + SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst); + + switch (spi_mode) + { + default: + case NRF_SPIS_MODE_0: + config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); + break; + + case NRF_SPIS_MODE_1: + config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); + break; + + case NRF_SPIS_MODE_2: + config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos); + break; + + case NRF_SPIS_MODE_3: + config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) | + (SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos); + break; + } + p_reg->CONFIG = config; +} + +__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg, + uint8_t orc) +{ + p_reg->ORC = orc; +} + +__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg, + uint8_t def) +{ + p_reg->DEF = def; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_SPIS_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_systick.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_systick.h new file mode 100755 index 0000000..3058089 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_systick.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_SYSTICK_H__ +#define NRF_SYSTICK_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_systick_hal SYSTICK HAL + * @{ + * @ingroup nrf_systick + * @brief Hardware access layer for managing the SYSTICK peripheral. + * + * SYSTICK is ARM peripheral, not Nordic design. + * It means that it has no Nordic-typical interface with Tasks and Events. + * + * Its usage is limited here to implement simple delays. + * Also keep in mind that this timer would be stopped when CPU is sleeping + * (WFE/WFI instruction is successfully executed). + */ + +/** + * @brief Mask of usable bits in the SysTick value + */ +#define NRF_SYSTICK_VAL_MASK SysTick_VAL_CURRENT_Msk + +/** + * @brief Flags used by SysTick configuration. + * + * @sa nrf_systick_csr_set + * @sa nrf_systick_csr_get + */ +typedef enum { + NRF_SYSTICK_CSR_COUNTFLAG_MASK = SysTick_CTRL_COUNTFLAG_Msk, /**< Status flag: Returns 1 if timer counted to 0 since the last read of this register. */ + + NRF_SYSTICK_CSR_CLKSOURCE_MASK = SysTick_CTRL_CLKSOURCE_Msk, /**< Configuration bit: Select the SysTick clock source. */ + NRF_SYSTICK_CSR_CLKSOURCE_REF = 0U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select reference clock. */ + NRF_SYSTICK_CSR_CLKSOURCE_CPU = 1U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select CPU clock. */ + + NRF_SYSTICK_CSR_TICKINT_MASK = SysTick_CTRL_TICKINT_Msk, /**< Configuration bit: Enables SysTick exception request. */ + NRF_SYSTICK_CSR_TICKINT_ENABLE = 1U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero does not assert the SysTick exception request. */ + NRF_SYSTICK_CSR_TICKINT_DISABLE = 0U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero to asserts the SysTick exception request. */ + + NRF_SYSTICK_CSR_ENABLE_MASK = SysTick_CTRL_ENABLE_Msk, /**< Configuration bit: Enable the SysTick timer. */ + NRF_SYSTICK_CSR_ENABLE = 1U << SysTick_CTRL_ENABLE_Pos, /**< Configuration value: Counter enabled. */ + NRF_SYSTICK_CSR_DISABLE = 0U << SysTick_CTRL_ENABLE_Pos /**< Configuration value: Counter disabled. */ +} nrf_systick_csr_flags_t; + +/** + * @brief Get Configuration and Status Register + * + * @return Values composed by @ref nrf_systick_csr_flags_t. + * @note The @ref NRF_SYSTICK_CSR_COUNTFLAG_MASK value is cleared when CSR register is read. + */ +__STATIC_INLINE uint32_t nrf_systick_csr_get(void); + +/** + * @brief Set Configuration and Status Register + * + * @param[in] val The value composed from @ref nrf_systick_csr_flags_t. + */ +__STATIC_INLINE void nrf_systick_csr_set(uint32_t val); + +/** + * @brief Get the current reload value. + * + * @return The reload register value. + */ +__STATIC_INLINE uint32_t nrf_systick_load_get(void); + +/** + * @brief Configure the reload value. + * + * @param[in] val The value to set in the reload register. + */ +__STATIC_INLINE void nrf_systick_load_set(uint32_t val); + +/** + * @brief Read the SysTick current value + * + * @return The current SysTick value + * @sa NRF_SYSTICK_VAL_MASK + */ +__STATIC_INLINE uint32_t nrf_systick_val_get(void); + +/** + * @brief Clear the SysTick current value + * + * @note The SysTick does not allow setting current value. + * Any write to VAL register would clear the timer. + */ +__STATIC_INLINE void nrf_systick_val_clear(void); + +/** + * @brief Read the calibration register + * + * @return The calibration register value + */ +__STATIC_INLINE uint32_t nrf_systick_calib_get(void); + + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t nrf_systick_csr_get(void) +{ + return SysTick->CTRL; +} + +__STATIC_INLINE void nrf_systick_csr_set(uint32_t val) +{ + SysTick->CTRL = val; +} + +__STATIC_INLINE uint32_t nrf_systick_load_get(void) +{ + return SysTick->LOAD; +} + +__STATIC_INLINE void nrf_systick_load_set(uint32_t val) +{ + SysTick->LOAD = val; +} + +__STATIC_INLINE uint32_t nrf_systick_val_get(void) +{ + return SysTick->VAL; +} + +__STATIC_INLINE void nrf_systick_val_clear(void) +{ + SysTick->VAL = 0; +} + +__STATIC_INLINE uint32_t nrf_systick_calib_get(void) +{ + return SysTick->CALIB; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_SYSTICK_H__ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_temp.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_temp.h new file mode 100755 index 0000000..b08b423 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_temp.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_TEMP_H__ +#define NRF_TEMP_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @defgroup nrf_temp_hal TEMP HAL +* @{ +* @ingroup nrf_temp temperature_example +* @brief Temperature module init and read functions. +*/ + +#define MASK_SIGN (0x00000200UL) +#define MASK_SIGN_EXTENSION (0xFFFFFC00UL) + +/** + * @brief Function for preparing the temp module for temperature measurement. + * + * This function initializes the TEMP module and writes to the hidden configuration register. + */ +static __INLINE void nrf_temp_init(void) +{ + /**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */ + *(uint32_t *) 0x4000C504 = 0; +} + +/** + * @brief Function for reading temperature measurement. + * + * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value. + */ +static __INLINE int32_t nrf_temp_read(void) +{ + /**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */ + return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (int32_t)(NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP); +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_timer.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_timer.h new file mode 100755 index 0000000..f925acf --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_timer.h @@ -0,0 +1,625 @@ +/* + * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_TIMER_H__ +#define NRF_TIMER_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_timer_hal TIMER HAL + * @{ + * @ingroup nrf_timer + * @brief Hardware access layer for managing the TIMER peripheral. + */ + +/** + * @brief Macro for validating the correctness of the BIT_WIDTH setting. + */ + +#define TIMER_MAX_SIZE(id) NRFX_CONCAT_3(TIMER, id, _MAX_SIZE) + +#define TIMER_BIT_WIDTH_MAX(id, bit_width) \ + (TIMER_MAX_SIZE(id) == 8 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) : \ + (TIMER_MAX_SIZE(id) == 16 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_16) : \ + (TIMER_MAX_SIZE(id) == 24 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_16) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_24) : \ + (TIMER_MAX_SIZE(id) == 32 ? (bit_width == NRF_TIMER_BIT_WIDTH_8) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_16) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_24) || \ + (bit_width == NRF_TIMER_BIT_WIDTH_32) : \ + false)))) + +#if TIMER_COUNT > 3 +#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \ + ((p_reg == NRF_TIMER0) && (TIMER_BIT_WIDTH_MAX(0, bit_width))) \ + || ((p_reg == NRF_TIMER1) && (TIMER_BIT_WIDTH_MAX(1, bit_width))) \ + || ((p_reg == NRF_TIMER2) && (TIMER_BIT_WIDTH_MAX(2, bit_width))) \ + || ((p_reg == NRF_TIMER3) && (TIMER_BIT_WIDTH_MAX(3, bit_width))) \ + || ((p_reg == NRF_TIMER4) && (TIMER_BIT_WIDTH_MAX(4, bit_width))) ) + +#else +#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \ + ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \ + || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \ + || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) ) + +#endif + +/** + * @brief Macro for getting the number of capture/compare channels available + * in a given timer instance. + */ +#define NRF_TIMER_CC_CHANNEL_COUNT(id) NRFX_CONCAT_3(TIMER, id, _CC_NUM) + +/** + * @brief Timer tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_TIMER_TASK_START = offsetof(NRF_TIMER_Type, TASKS_START), ///< Task for starting the timer. + NRF_TIMER_TASK_STOP = offsetof(NRF_TIMER_Type, TASKS_STOP), ///< Task for stopping the timer. + NRF_TIMER_TASK_COUNT = offsetof(NRF_TIMER_Type, TASKS_COUNT), ///< Task for incrementing the timer (in counter mode). + NRF_TIMER_TASK_CLEAR = offsetof(NRF_TIMER_Type, TASKS_CLEAR), ///< Task for resetting the timer value. + NRF_TIMER_TASK_SHUTDOWN = offsetof(NRF_TIMER_Type, TASKS_SHUTDOWN), ///< Task for powering off the timer. + NRF_TIMER_TASK_CAPTURE0 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0. + NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1. + NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2. + NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5. +#endif + /*lint -restore*/ +} nrf_timer_task_t; + +/** + * @brief Timer events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0. + NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1. + NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2. + NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5. +#endif + /*lint -restore*/ +} nrf_timer_event_t; + +/** + * @brief Types of timer shortcuts. + */ +typedef enum +{ + NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk, ///< Shortcut for stopping the timer based on compare 0. + NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk, ///< Shortcut for stopping the timer based on compare 1. + NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk, ///< Shortcut for stopping the timer based on compare 2. + NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk, ///< Shortcut for stopping the timer based on compare 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk, ///< Shortcut for stopping the timer based on compare 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5. +#endif + NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0. + NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1. + NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2. + NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5. +#endif +} nrf_timer_short_mask_t; + +/** + * @brief Timer modes. + */ +typedef enum +{ + NRF_TIMER_MODE_TIMER = TIMER_MODE_MODE_Timer, ///< Timer mode: timer. + NRF_TIMER_MODE_COUNTER = TIMER_MODE_MODE_Counter, ///< Timer mode: counter. +#if defined(TIMER_MODE_MODE_LowPowerCounter) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter. +#endif +} nrf_timer_mode_t; + +/** + * @brief Timer bit width. + */ +typedef enum +{ + NRF_TIMER_BIT_WIDTH_8 = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit. + NRF_TIMER_BIT_WIDTH_16 = TIMER_BITMODE_BITMODE_16Bit, ///< Timer bit width 16 bit. + NRF_TIMER_BIT_WIDTH_24 = TIMER_BITMODE_BITMODE_24Bit, ///< Timer bit width 24 bit. + NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit ///< Timer bit width 32 bit. +} nrf_timer_bit_width_t; + +/** + * @brief Timer prescalers. + */ +typedef enum +{ + NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz. + NRF_TIMER_FREQ_8MHz, ///< Timer frequency 8 MHz. + NRF_TIMER_FREQ_4MHz, ///< Timer frequency 4 MHz. + NRF_TIMER_FREQ_2MHz, ///< Timer frequency 2 MHz. + NRF_TIMER_FREQ_1MHz, ///< Timer frequency 1 MHz. + NRF_TIMER_FREQ_500kHz, ///< Timer frequency 500 kHz. + NRF_TIMER_FREQ_250kHz, ///< Timer frequency 250 kHz. + NRF_TIMER_FREQ_125kHz, ///< Timer frequency 125 kHz. + NRF_TIMER_FREQ_62500Hz, ///< Timer frequency 62500 Hz. + NRF_TIMER_FREQ_31250Hz ///< Timer frequency 31250 Hz. +} nrf_timer_frequency_t; + +/** + * @brief Timer capture/compare channels. + */ +typedef enum +{ + NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0. + NRF_TIMER_CC_CHANNEL1, ///< Timer capture/compare channel 1. + NRF_TIMER_CC_CHANNEL2, ///< Timer capture/compare channel 2. + NRF_TIMER_CC_CHANNEL3, ///< Timer capture/compare channel 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_CC_CHANNEL4, ///< Timer capture/compare channel 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5. +#endif +} nrf_timer_cc_channel_t; + +/** + * @brief Timer interrupts. + */ +typedef enum +{ + NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0. + NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1. + NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2. + NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3. +#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4. +#endif +#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__) + NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5. +#endif +} nrf_timer_int_mask_t; + + +/** + * @brief Function for activating a specific timer task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task); + +/** + * @brief Function for getting the address of a specific timer task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task); + +/** + * @brief Function for clearing a specific timer event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event); + +/** + * @brief Function for checking the state of a specific timer event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event); + +/** + * @brief Function for getting the address of a specific timer event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg, + uint32_t timer_shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, + uint32_t timer_shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg, + uint32_t timer_int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg, + uint32_t timer_int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] timer_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg, + uint32_t timer_int); + +/** + * @brief Function for setting the timer mode. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] mode Timer mode. + */ +__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg, + nrf_timer_mode_t mode); + +/** + * @brief Function for retrieving the timer mode. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Timer mode. + */ +__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg); + +/** + * @brief Function for setting the timer bit width. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] bit_width Timer bit width. + */ +__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg, + nrf_timer_bit_width_t bit_width); + +/** + * @brief Function for retrieving the timer bit width. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Timer bit width. + */ +__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg); + +/** + * @brief Function for setting the timer frequency. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] frequency Timer frequency. + */ +__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg, + nrf_timer_frequency_t frequency); + +/** + * @brief Function for retrieving the timer frequency. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Timer frequency. + */ +__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg); + +/** + * @brief Function for writing the capture/compare register for a specified channel. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] cc_channel Requested capture/compare channel. + * @param[in] cc_value Value to write to the capture/compare register. + */ +__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value); + +/** + * @brief Function for retrieving the capture/compare value for a specified channel. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] cc_channel Requested capture/compare channel. + * + * @return Value from the requested capture/compare register. + */ +__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg, + nrf_timer_cc_channel_t cc_channel); + +/** + * @brief Function for getting a specific timer capture task. + * + * @param[in] channel Capture channel. + * + * @return Capture task. + */ +__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel); + +/** + * @brief Function for getting a specific timer compare event. + * + * @param[in] channel Compare channel. + * + * @return Compare event. + */ +__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel); + +/** + * @brief Function for getting a specific timer compare interrupt. + * + * @param[in] channel Compare channel. + * + * @return Compare interrupt. + */ +__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel); + +/** + * @brief Function for calculating the number of timer ticks for a given time + * (in microseconds) and timer frequency. + * + * @param[in] time_us Time in microseconds. + * @param[in] frequency Timer frequency. + * + * @return Number of timer ticks. + */ +__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us, + nrf_timer_frequency_t frequency); + +/** + * @brief Function for calculating the number of timer ticks for a given time + * (in milliseconds) and timer frequency. + * + * @param[in] time_ms Time in milliseconds. + * @param[in] frequency Timer frequency. + * + * @return Number of timer ticks. + */ +__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms, + nrf_timer_frequency_t frequency); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg, + nrf_timer_task_t task) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg, + nrf_timer_event_t event) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg, + uint32_t timer_shorts_mask) +{ + p_reg->SHORTS |= timer_shorts_mask; +} + +__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, + uint32_t timer_shorts_mask) +{ + p_reg->SHORTS &= ~(timer_shorts_mask); +} + +__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg, + uint32_t timer_int_mask) +{ + p_reg->INTENSET = timer_int_mask; +} + +__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg, + uint32_t timer_int_mask) +{ + p_reg->INTENCLR = timer_int_mask; +} + +__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg, + uint32_t timer_int) +{ + return (bool)(p_reg->INTENSET & timer_int); +} + +__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg, + nrf_timer_mode_t mode) +{ + p_reg->MODE = (p_reg->MODE & ~TIMER_MODE_MODE_Msk) | + ((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk); +} + +__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg) +{ + return (nrf_timer_mode_t)(p_reg->MODE); +} + +__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg, + nrf_timer_bit_width_t bit_width) +{ + p_reg->BITMODE = (p_reg->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) | + ((bit_width << TIMER_BITMODE_BITMODE_Pos) & + TIMER_BITMODE_BITMODE_Msk); +} + +__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg) +{ + return (nrf_timer_bit_width_t)(p_reg->BITMODE); +} + +__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg, + nrf_timer_frequency_t frequency) +{ + p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) | + ((frequency << TIMER_PRESCALER_PRESCALER_Pos) & + TIMER_PRESCALER_PRESCALER_Msk); +} + +__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg) +{ + return (nrf_timer_frequency_t)(p_reg->PRESCALER); +} + +__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg, + nrf_timer_cc_channel_t cc_channel, + uint32_t cc_value) +{ + p_reg->CC[cc_channel] = cc_value; +} + +__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg, + nrf_timer_cc_channel_t cc_channel) +{ + return (uint32_t)p_reg->CC[cc_channel]; +} + +__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel) +{ + return (nrf_timer_task_t) + ((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t))); +} + +__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel) +{ + return (nrf_timer_event_t) + ((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t))); +} + +__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel) +{ + return (nrf_timer_int_mask_t) + ((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel); +} + +__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us, + nrf_timer_frequency_t frequency) +{ + // The "frequency" parameter here is actually the prescaler value, and the + // timer runs at the following frequency: f = 16 MHz / 2^prescaler. + uint32_t prescaler = (uint32_t)frequency; + NRFX_ASSERT(time_us <= (UINT32_MAX / 16UL)); + return ((time_us * 16UL) >> prescaler); +} + +__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms, + nrf_timer_frequency_t frequency) +{ + // The "frequency" parameter here is actually the prescaler value, and the + // timer runs at the following frequency: f = 16000 kHz / 2^prescaler. + uint32_t prescaler = (uint32_t)frequency; + NRFX_ASSERT(time_ms <= (UINT32_MAX / 16000UL)); + return ((time_ms * 16000UL) >> prescaler); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_TIMER_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twi.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twi.h new file mode 100755 index 0000000..2aa275e --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twi.h @@ -0,0 +1,442 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_TWI_H__ +#define NRF_TWI_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_twi_hal TWI HAL + * @{ + * @ingroup nrf_twi + * @brief Hardware access layer for managing the TWI peripheral. + */ + +/** + * @brief TWI tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence. + NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence. + NRF_TWI_TASK_STOP = offsetof(NRF_TWI_Type, TASKS_STOP), ///< Stop TWI transaction. + NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction. + NRF_TWI_TASK_RESUME = offsetof(NRF_TWI_Type, TASKS_RESUME) ///< Resume TWI transaction. + /*lint -restore*/ +} nrf_twi_task_t; + +/** + * @brief TWI events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWI_EVENT_STOPPED = offsetof(NRF_TWI_Type, EVENTS_STOPPED), ///< TWI stopped. + NRF_TWI_EVENT_RXDREADY = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received. + NRF_TWI_EVENT_TXDSENT = offsetof(NRF_TWI_Type, EVENTS_TXDSENT), ///< TWI TXD byte sent. + NRF_TWI_EVENT_ERROR = offsetof(NRF_TWI_Type, EVENTS_ERROR), ///< TWI error. + NRF_TWI_EVENT_BB = offsetof(NRF_TWI_Type, EVENTS_BB), ///< TWI byte boundary, generated before each byte that is sent or received. + NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state. + /*lint -restore*/ +} nrf_twi_event_t; + +/** + * @brief TWI shortcuts. + */ +typedef enum +{ + NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk, ///< Shortcut between BB event and SUSPEND task. + NRF_TWI_SHORT_BB_STOP_MASK = TWI_SHORTS_BB_STOP_Msk, ///< Shortcut between BB event and STOP task. + NRF_TWI_ALL_SHORTS_MASK = TWI_SHORTS_BB_SUSPEND_Msk | + TWI_SHORTS_BB_STOP_Msk ///< All TWI shortcuts. +} nrf_twi_short_mask_t; + +/** + * @brief TWI interrupts. + */ +typedef enum +{ + NRF_TWI_INT_STOPPED_MASK = TWI_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_TWI_INT_RXDREADY_MASK = TWI_INTENSET_RXDREADY_Msk, ///< Interrupt on RXDREADY event. + NRF_TWI_INT_TXDSENT_MASK = TWI_INTENSET_TXDSENT_Msk, ///< Interrupt on TXDSENT event. + NRF_TWI_INT_ERROR_MASK = TWI_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. + NRF_TWI_INT_BB_MASK = TWI_INTENSET_BB_Msk, ///< Interrupt on BB event. + NRF_TWI_INT_SUSPENDED_MASK = TWI_INTENSET_SUSPENDED_Msk, ///< Interrupt on SUSPENDED event. + NRF_TWI_ALL_INTS_MASK = TWI_INTENSET_STOPPED_Msk | + TWI_INTENSET_RXDREADY_Msk | + TWI_INTENSET_TXDSENT_Msk | + TWI_INTENSET_ERROR_Msk | + TWI_INTENSET_BB_Msk | + TWI_INTENSET_SUSPENDED_Msk ///< All TWI interrupts. +} nrf_twi_int_mask_t; + +/** + * @brief TWI error source. + */ +typedef enum +{ + NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address. + NRF_TWI_ERROR_DATA_NACK = TWI_ERRORSRC_DNACK_Msk, ///< NACK received after sending a data byte. + NRF_TWI_ERROR_OVERRUN = TWI_ERRORSRC_OVERRUN_Msk ///< Overrun error. + /**< A new byte was received before the previous byte was read + * from the RXD register (previous data is lost). */ +} nrf_twi_error_t; + +/** + * @brief TWI master clock frequency. + */ +typedef enum +{ + NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps. + NRF_TWI_FREQ_250K = TWI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_TWI_FREQ_400K = TWI_FREQUENCY_FREQUENCY_K400 ///< 400 kbps. +} nrf_twi_frequency_t; + + +/** + * @brief Function for activating a specific TWI task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg, + nrf_twi_task_t task); + +/** + * @brief Function for getting the address of a specific TWI task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg, + nrf_twi_task_t task); + +/** + * @brief Function for clearing a specific TWI event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg, + nrf_twi_event_t event); + +/** + * @brief Function for checking the state of a specific event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_reg, + nrf_twi_event_t event); + +/** + * @brief Function for getting the address of a specific TWI event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg, + nrf_twi_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg, + uint32_t shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg, + uint32_t shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg, + uint32_t int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg, + uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] int_mask Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg, + nrf_twi_int_mask_t int_mask); + +/** + * @brief Function for enabling the TWI peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg); + +/** + * @brief Function for disabling the TWI peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg); + +/** + * @brief Function for configuring TWI pins. + * + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] scl_pin SCL pin number. + * @param[in] sda_pin SDA pin number. + */ +__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg, + uint32_t scl_pin, + uint32_t sda_pin); + +/** + * @brief Function for setting the TWI master clock frequency. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] frequency TWI frequency. + */ +__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg, + nrf_twi_frequency_t frequency); + +/** + * @brief Function for checking the TWI error source. + * + * The error flags are cleared after reading. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg); + +/** + * @brief Function for setting the address to be used in TWI transfers. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] address Address to be used in transfers. + */ +__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address); + +/** + * @brief Function for reading data received by TWI. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Received data. + */ +__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg); + +/** + * @brief Function for writing data to be transmitted by TWI. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] data Data to be transmitted. + */ +__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data); + +__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg, + uint32_t shorts_mask); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg, + nrf_twi_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg, + nrf_twi_task_t task) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg, + nrf_twi_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type * p_reg, + nrf_twi_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg, + nrf_twi_event_t event) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg, + uint32_t shorts_mask) +{ + p_reg->SHORTS |= shorts_mask; +} + +__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg, + uint32_t shorts_mask) +{ + p_reg->SHORTS &= ~(shorts_mask); +} + +__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg, + uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg, + uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg, + nrf_twi_int_mask_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg) +{ + p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg) +{ + p_reg->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg, + uint32_t scl_pin, + uint32_t sda_pin) +{ +#if defined(TWI_PSEL_SCL_CONNECT_Pos) + p_reg->PSEL.SCL = scl_pin; +#else + p_reg->PSELSCL = scl_pin; +#endif + +#if defined(TWI_PSEL_SDA_CONNECT_Pos) + p_reg->PSEL.SDA = sda_pin; +#else + p_reg->PSELSDA = sda_pin; +#endif +} + +__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg, + nrf_twi_frequency_t frequency) +{ + p_reg->FREQUENCY = frequency; +} + +__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg) +{ + uint32_t error_source = p_reg->ERRORSRC; + + // [error flags are cleared by writing '1' on their position] + p_reg->ERRORSRC = error_source; + + return error_source; +} + +__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address) +{ + p_reg->ADDRESS = address; +} + +__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg) +{ + return (uint8_t)p_reg->RXD; +} + +__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data) +{ + p_reg->TXD = data; +} + +__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg, + uint32_t shorts_mask) +{ + p_reg->SHORTS = shorts_mask; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_TWI_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twim.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twim.h new file mode 100755 index 0000000..d1eb5ad --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twim.h @@ -0,0 +1,513 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_TWIM_H__ +#define NRF_TWIM_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_twim_hal TWIM HAL + * @{ + * @ingroup nrf_twim + * @brief Hardware access layer for managing the TWIM peripheral. + */ + +/** + * @brief TWIM tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence. + NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence. + NRF_TWIM_TASK_STOP = offsetof(NRF_TWIM_Type, TASKS_STOP), ///< Stop TWI transaction. + NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction. + NRF_TWIM_TASK_RESUME = offsetof(NRF_TWIM_Type, TASKS_RESUME) ///< Resume TWI transaction. + /*lint -restore*/ +} nrf_twim_task_t; + +/** + * @brief TWIM events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWIM_EVENT_STOPPED = offsetof(NRF_TWIM_Type, EVENTS_STOPPED), ///< TWI stopped. + NRF_TWIM_EVENT_ERROR = offsetof(NRF_TWIM_Type, EVENTS_ERROR), ///< TWI error. + NRF_TWIM_EVENT_SUSPENDED = 0x148, ///< TWI suspended. + NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started. + NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started. + NRF_TWIM_EVENT_LASTRX = offsetof(NRF_TWIM_Type, EVENTS_LASTRX), ///< Byte boundary, starting to receive the last byte. + NRF_TWIM_EVENT_LASTTX = offsetof(NRF_TWIM_Type, EVENTS_LASTTX) ///< Byte boundary, starting to transmit the last byte. + /*lint -restore*/ +} nrf_twim_event_t; + +/** + * @brief TWIM shortcuts. + */ +typedef enum +{ + NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task. + NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task. + NRF_TWIM_SHORT_LASTTX_STOP_MASK = TWIM_SHORTS_LASTTX_STOP_Msk, ///< Shortcut between LASTTX event and STOP task. + NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task. + NRF_TWIM_SHORT_LASTRX_STOP_MASK = TWIM_SHORTS_LASTRX_STOP_Msk, ///< Shortcut between LASTRX event and STOP task. + NRF_TWIM_ALL_SHORTS_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk | + TWIM_SHORTS_LASTTX_SUSPEND_Msk | + TWIM_SHORTS_LASTTX_STOP_Msk | + TWIM_SHORTS_LASTRX_STARTTX_Msk | + TWIM_SHORTS_LASTRX_STOP_Msk ///< All TWIM shortcuts. +} nrf_twim_short_mask_t; + +/** + * @brief TWIM interrupts. + */ +typedef enum +{ + NRF_TWIM_INT_STOPPED_MASK = TWIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event. + NRF_TWIM_INT_ERROR_MASK = TWIM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. + NRF_TWIM_INT_SUSPENDED_MASK = TWIM_INTENSET_SUSPENDED_Msk, ///< Interrupt on SUSPENDED event. + NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event. + NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event. + NRF_TWIM_INT_LASTRX_MASK = TWIM_INTENSET_LASTRX_Msk, ///< Interrupt on LASTRX event. + NRF_TWIM_INT_LASTTX_MASK = TWIM_INTENSET_LASTTX_Msk, ///< Interrupt on LASTTX event. + NRF_TWIM_ALL_INTS_MASK = TWIM_INTENSET_STOPPED_Msk | + TWIM_INTENSET_ERROR_Msk | + TWIM_INTENSET_SUSPENDED_Msk | + TWIM_INTENSET_RXSTARTED_Msk | + TWIM_INTENSET_TXSTARTED_Msk | + TWIM_INTENSET_LASTRX_Msk | + TWIM_INTENSET_LASTTX_Msk ///< Interrupt on LASTTX event. +} nrf_twim_int_mask_t; + +/** + * @brief TWIM master clock frequency. + */ +typedef enum +{ + NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps. + NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. + NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400 ///< 400 kbps. +} nrf_twim_frequency_t; + +/** + * @brief TWIM error source. + */ +typedef enum +{ + NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address. + NRF_TWIM_ERROR_DATA_NACK = TWIM_ERRORSRC_DNACK_Msk ///< NACK received after sending a data byte. +} nrf_twim_error_t; + + +/** + * @brief Function for activating a specific TWIM task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Task to activate. + */ +__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg, + nrf_twim_task_t task); + +/** + * @brief Function for getting the address of a specific TWIM task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] task Requested task. + * + * @return Address of the specified task register. + */ +__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg, + nrf_twim_task_t task); + +/** + * @brief Function for clearing a specific TWIM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg, + nrf_twim_event_t event); + +/** + * @brief Function for checking the state of a specific TWIM event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg, + nrf_twim_event_t event); + +/** + * @brief Function for getting the address of a specific TWIM event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg, + nrf_twim_event_t event); + +/** + * @brief Function for enabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg, + uint32_t shorts_mask); + +/** + * @brief Function for disabling specified shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg, + uint32_t shorts_mask); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg, + uint32_t int_mask); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg, + uint32_t int_mask); + +/** + * @brief Function for checking the state of a given interrupt. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] int_mask Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg, + nrf_twim_int_mask_t int_mask); + +/** + * @brief Function for enabling the TWIM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg); + +/** + * @brief Function for disabling the TWIM peripheral. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg); + +/** + * @brief Function for configuring TWI pins. + * + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] scl_pin SCL pin number. + * @param[in] sda_pin SDA pin number. + */ +__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg, + uint32_t scl_pin, + uint32_t sda_pin); + +/** + * @brief Function for setting the TWI master clock frequency. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] frequency TWI frequency. + */ +__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg, + nrf_twim_frequency_t frequency); + +/** + * @brief Function for checking the TWI error source. + * + * The error flags are cleared after reading. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg); + +/** + * @brief Function for setting the address to be used in TWI transfers. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] address Address to be used in transfers. + */ +__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg, + uint8_t address); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg, + uint8_t const * p_buffer, + size_t length); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg, + uint8_t * p_buffer, + size_t length); + +__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg, + uint32_t shorts_mask); + +__STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg); + +__STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg); + +/** + * @brief Function for enabling the TX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg); + +/** + * @brief Function for disabling the TX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg); + +/** + * @brief Function for enabling the RX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg); + +/** + * @brief Function for disabling the RX list feature. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg, + nrf_twim_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg, + nrf_twim_task_t task) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task); +} + +__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg, + nrf_twim_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg, + nrf_twim_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type * p_reg, + nrf_twim_event_t event) +{ + return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg, + uint32_t shorts_mask) +{ + p_reg->SHORTS |= shorts_mask; +} + +__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg, + uint32_t shorts_mask) +{ + p_reg->SHORTS &= ~(shorts_mask); +} + +__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg, + uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg, + uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg, + nrf_twim_int_mask_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg) +{ + p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg) +{ + p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos); +} + +__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg, + uint32_t scl_pin, + uint32_t sda_pin) +{ + p_reg->PSEL.SCL = scl_pin; + p_reg->PSEL.SDA = sda_pin; +} + +__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg, + nrf_twim_frequency_t frequency) +{ + p_reg->FREQUENCY = frequency; +} + +__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg) +{ + uint32_t error_source = p_reg->ERRORSRC; + + // [error flags are cleared by writing '1' on their position] + p_reg->ERRORSRC = error_source; + + return error_source; +} + +__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg, + uint8_t address) +{ + p_reg->ADDRESS = address; +} + +__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg, + uint8_t const * p_buffer, + size_t length) +{ + p_reg->TXD.PTR = (uint32_t)p_buffer; + p_reg->TXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg, + uint8_t * p_buffer, + size_t length) +{ + p_reg->RXD.PTR = (uint32_t)p_buffer; + p_reg->RXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg, + uint32_t shorts_mask) +{ + p_reg->SHORTS = shorts_mask; +} + +__STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg) +{ + return p_reg->TXD.AMOUNT; +} + +__STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg) +{ + return p_reg->RXD.AMOUNT; +} + +__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg) +{ + p_reg->TXD.LIST = 1; +} + +__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg) +{ + p_reg->TXD.LIST = 0; +} + +__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg) +{ + p_reg->RXD.LIST = 1; +} + +__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg) +{ + p_reg->RXD.LIST = 0; +} +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_TWIM_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twis.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twis.h new file mode 100755 index 0000000..f689bb6 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_twis.h @@ -0,0 +1,693 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_TWIS_H__ +#define NRF_TWIS_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_twis_hal TWIS HAL + * @{ + * @ingroup nrf_twis + * @brief Hardware access layer for managing the Two Wire Interface Slave with EasyDMA + * (TWIS) peripheral. + */ + +/** + * @brief TWIS tasks + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction */ + NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction */ + NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction */ + NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command */ + NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command */ + /*lint -restore*/ +} nrf_twis_task_t; + +/** + * @brief TWIS events + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped */ + NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error */ + NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started */ + NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started */ + NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received */ + NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received */ + /*lint -restore*/ +} nrf_twis_event_t; + +/** + * @brief TWIS shortcuts + */ +typedef enum +{ + NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task */ + NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task */ +} nrf_twis_short_mask_t; + +/** + * @brief TWIS interrupts + */ +typedef enum +{ + NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event */ + NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event */ + NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event */ + NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event */ + NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event */ + NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event */ +} nrf_twis_int_mask_t; + +/** + * @brief TWIS error source + */ +typedef enum +{ + NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented */ + NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte */ + NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented */ +} nrf_twis_error_t; + +/** + * @brief TWIS address matching configuration + */ +typedef enum +{ + NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0] */ + NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1] */ + NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching */ +} nrf_twis_config_addr_mask_t; + +/** + * @brief Variable type to hold amount of data for EasyDMA + * + * Variable of the minimum size that can hold the amount of data to transfer. + * + * @note + * Defined to make it simple to change if EasyDMA would be updated to support more data in + * the future devices to. + */ +typedef uint8_t nrf_twis_amount_t; + +/** + * @brief Smallest variable type to hold TWI address + * + * Variable of the minimum size that can hold single TWI address. + * + * @note + * Defined to make it simple to change if new TWI would support for example + * 10 bit addressing mode. + */ +typedef uint8_t nrf_twis_address_t; + + +/** + * @brief Function for activating a specific TWIS task. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param task Task. + */ +__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task); + +/** + * @brief Function for returning the address of a specific TWIS task register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_twis_task_address_get( + NRF_TWIS_Type const * const p_reg, + nrf_twis_task_t task); + +/** + * @brief Function for clearing a specific event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param event Event. + */ +__STATIC_INLINE void nrf_twis_event_clear( + NRF_TWIS_Type * const p_reg, + nrf_twis_event_t event); +/** + * @brief Function for returning the state of a specific event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_twis_event_check( + NRF_TWIS_Type const * const p_reg, + nrf_twis_event_t event); + + +/** + * @brief Function for getting and clearing the state of specific event + * + * This function checks the state of the event and clears it. + * @param[in,out] p_reg Pointer to the peripheral registers structure. + * @param event Event. + * + * @retval true If the event was set. + * @retval false If the event was not set. + */ +__STATIC_INLINE bool nrf_twis_event_get_and_clear( + NRF_TWIS_Type * const p_reg, + nrf_twis_event_t event); + + +/** + * @brief Function for returning the address of a specific TWIS event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param event Event. + * + * @return Address. + */ +__STATIC_INLINE uint32_t nrf_twis_event_address_get( + NRF_TWIS_Type const * const p_reg, + nrf_twis_event_t event); + +/** + * @brief Function for setting a shortcut. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param short_mask Shortcuts mask. + */ +__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask); + +/** + * @brief Function for clearing shortcuts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param short_mask Shortcuts mask. + */ +__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask); + +/** + * @brief Get the shorts mask + * + * Function returns shorts register. + * @param[in] p_reg Pointer to the peripheral registers structure. + * @return Flags of currently enabled shortcuts + */ +__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg); + +/** + * @brief Function for enabling selected interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts mask. + */ +__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of selected interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts mask. + * + * @retval true If any of selected interrupts is enabled. + * @retval false If none of selected interrupts is enabled. + */ +__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask); + +/** + * @brief Function for disabling selected interrupts. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts mask. + */ +__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving and clearing the TWIS error source. + * + * @attention Error sources are cleared after read. + * @param[in] p_reg Pointer to the peripheral registers structure. + * @return Error source mask with values from @ref nrf_twis_error_t. + */ +__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg); + +/** + * @brief Get information which of addresses matched + * + * Function returns index in the address table + * that points to the address that already matched. + * @param[in] p_reg Pointer to the peripheral registers structure. + * @return Index of matched address + */ +__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg); + +/** + * @brief Function for enabling TWIS. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * const p_reg); + +/** + * @brief Function for disabling TWIS. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * const p_reg); + +/** + * @brief Function for configuring TWIS pins. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param scl SCL pin number. + * @param sda SDA pin number. + */ +__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param p_buf Pointer to the buffer for received data. + * @param length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_twis_rx_buffer_set( + NRF_TWIS_Type * const p_reg, + uint8_t * p_buf, + nrf_twis_amount_t length); + +/** + * @brief Function that prepares TWIS for receiving + * + * This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task. + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param p_buf Pointer to the buffer for received data. + * @param length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_twis_rx_prepare( + NRF_TWIS_Type * const p_reg, + uint8_t * p_buf, + nrf_twis_amount_t length); + +/** + * @brief Function for getting number of bytes received in the last transaction. + * + * @param[in] p_reg TWIS instance. + * @return Amount of bytes received. + * */ +__STATIC_INLINE nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param p_buf Pointer to the buffer with data to send. + * @param length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_twis_tx_buffer_set( + NRF_TWIS_Type * const p_reg, + uint8_t const * p_buf, + nrf_twis_amount_t length); + +/** + * @brief Function that prepares TWIS for transmitting + * + * This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task. + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param p_buf Pointer to the buffer with data to send. + * @param length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_twis_tx_prepare( + NRF_TWIS_Type * const p_reg, + uint8_t const * p_buf, + nrf_twis_amount_t length); + +/** + * @brief Function for getting number of bytes transmitted in the last transaction. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @return Amount of bytes transmitted. + */ +__STATIC_INLINE nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg); + +/** + * @brief Function for setting slave address + * + * Function sets the selected address for this TWI interface. + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param n Index of address to set + * @param addr Addres to set + * @sa nrf_twis_config_address_set + * @sa nrf_twis_config_address_get + */ +__STATIC_INLINE void nrf_twis_address_set( + NRF_TWIS_Type * const p_reg, + uint_fast8_t n, + nrf_twis_address_t addr); + +/** + * @brief Function for retrieving configured slave address + * + * Function gets the selected address for this TWI interface. + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param n Index of address to get + */ +__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get( + NRF_TWIS_Type const * const p_reg, + uint_fast8_t n); + +/** + * @brief Function for setting the device address configuration. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param addr_mask Mask of address indexes of what device should answer to. + * + * @sa nrf_twis_address_set + */ +__STATIC_INLINE void nrf_twis_config_address_set( + NRF_TWIS_Type * const p_reg, + nrf_twis_config_addr_mask_t addr_mask); + +/** + * @brief Function for retrieving the device address configuration. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Mask of address indexes of what device should answer to. + */ +__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get( + NRF_TWIS_Type const * const p_reg); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] orc Over-read character. Character clocked out in case of + * over-read of the TXD buffer. + */ +__STATIC_INLINE void nrf_twis_orc_set( + NRF_TWIS_Type * const p_reg, + uint8_t orc); + +/** + * @brief Function for setting the over-read character. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @return Over-read character configured for selected instance. + */ +__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg); + + +/** @} */ /* End of nrf_twis_hal */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +/* ------------------------------------------------------------------------------------------------ + * Internal functions + */ + +/** + * @internal + * @brief Internal function for getting task/event register address + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @oaram offset Offset of the register from the instance beginning + * + * @attention offset has to be modulo 4 value. In other case we can get hardware fault. + * @return Pointer to the register + */ +__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * const p_reg, uint32_t offset) +{ + return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset); +} + +/** + * @internal + * @brief Internal function for getting task/event register address - constant version + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @oaram offset Offset of the register from the instance beginning + * + * @attention offset has to be modulo 4 value. In other case we can get hardware fault. + * @return Pointer to the register + */ +__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_reg, uint32_t offset) +{ + return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset); +} + + +/* ------------------------------------------------------------------------------------------------ + * Interface functions definitions + */ + + +void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task) +{ + *(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL; +} + +uint32_t nrf_twis_task_address_get( + NRF_TWIS_Type const * const p_reg, + nrf_twis_task_t task) +{ + return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task); +} + +void nrf_twis_event_clear( + NRF_TWIS_Type * const p_reg, + nrf_twis_event_t event) +{ + *(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif +} + +bool nrf_twis_event_check( + NRF_TWIS_Type const * const p_reg, + nrf_twis_event_t event) +{ + return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event); +} + +bool nrf_twis_event_get_and_clear( + NRF_TWIS_Type * const p_reg, + nrf_twis_event_t event) +{ + bool ret = nrf_twis_event_check(p_reg, event); + if (ret) + { + nrf_twis_event_clear(p_reg, event); + } + return ret; +} + +uint32_t nrf_twis_event_address_get( + NRF_TWIS_Type const * const p_reg, + nrf_twis_event_t event) +{ + return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event); +} + +void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask) +{ + p_reg->SHORTS |= short_mask; +} + +void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask) +{ + if (~0U == short_mask) + { + /* Optimized version for "disable all" */ + p_reg->SHORTS = 0; + } + else + { + p_reg->SHORTS &= ~short_mask; + } +} + +uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg) +{ + return p_reg->SHORTS; +} + +void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg) +{ + uint32_t ret = p_reg->ERRORSRC; + p_reg->ERRORSRC = ret; + return ret; +} + +uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg) +{ + return (uint_fast8_t)p_reg->MATCH; +} + +void nrf_twis_enable(NRF_TWIS_Type * const p_reg) +{ + p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos); +} + +void nrf_twis_disable(NRF_TWIS_Type * const p_reg) +{ + p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos); +} + +void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda) +{ + p_reg->PSEL.SCL = scl; + p_reg->PSEL.SDA = sda; +} + +void nrf_twis_rx_buffer_set( + NRF_TWIS_Type * const p_reg, + uint8_t * p_buf, + nrf_twis_amount_t length) +{ + p_reg->RXD.PTR = (uint32_t)p_buf; + p_reg->RXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twis_rx_prepare( + NRF_TWIS_Type * const p_reg, + uint8_t * p_buf, + nrf_twis_amount_t length) +{ + nrf_twis_rx_buffer_set(p_reg, p_buf, length); + nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX); +} + +nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg) +{ + return (nrf_twis_amount_t)p_reg->RXD.AMOUNT; +} + +void nrf_twis_tx_buffer_set( + NRF_TWIS_Type * const p_reg, + uint8_t const * p_buf, + nrf_twis_amount_t length) +{ + p_reg->TXD.PTR = (uint32_t)p_buf; + p_reg->TXD.MAXCNT = length; +} + +__STATIC_INLINE void nrf_twis_tx_prepare( + NRF_TWIS_Type * const p_reg, + uint8_t const * p_buf, + nrf_twis_amount_t length) +{ + nrf_twis_tx_buffer_set(p_reg, p_buf, length); + nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX); +} + +nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg) +{ + return (nrf_twis_amount_t)p_reg->TXD.AMOUNT; +} + +void nrf_twis_address_set( + NRF_TWIS_Type * const p_reg, + uint_fast8_t n, + nrf_twis_address_t addr) +{ + p_reg->ADDRESS[n] = addr; +} + +nrf_twis_address_t nrf_twis_address_get( + NRF_TWIS_Type const * const p_reg, + uint_fast8_t n) +{ + return (nrf_twis_address_t)p_reg->ADDRESS[n]; +} +void nrf_twis_config_address_set( + NRF_TWIS_Type * const p_reg, + nrf_twis_config_addr_mask_t addr_mask) +{ + /* This is the only configuration in TWIS - just write it without masking */ + p_reg->CONFIG = addr_mask; +} + +nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * const p_reg) +{ + return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk); +} + +void nrf_twis_orc_set( + NRF_TWIS_Type * const p_reg, + uint8_t orc) +{ + p_reg->ORC = orc; +} + +uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg) +{ + return (uint8_t)p_reg->ORC; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_TWIS_H__ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_uart.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_uart.h new file mode 100755 index 0000000..cc00c74 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_uart.h @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_UART_H__ +#define NRF_UART_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_uart_hal UART HAL + * @{ + * @ingroup nrf_uart + * @brief Hardware access layer for managing the UART peripheral. + */ + +#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF + +/** + * @enum nrf_uart_task_t + * @brief UART tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */ + NRF_UART_TASK_STOPRX = offsetof(NRF_UART_Type, TASKS_STOPRX), /**< Task for stopping reception. */ + NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */ + NRF_UART_TASK_STOPTX = offsetof(NRF_UART_Type, TASKS_STOPTX), /**< Task for stopping transmission. */ + NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */ + /*lint -restore*/ +} nrf_uart_task_t; + +/** + * @enum nrf_uart_event_t + * @brief UART events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UART_EVENT_CTS = offsetof(NRF_UART_Type, EVENTS_CTS), /**< Event from CTS line activation. */ + NRF_UART_EVENT_NCTS = offsetof(NRF_UART_Type, EVENTS_NCTS), /**< Event from CTS line deactivation. */ + NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */ + NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */ + NRF_UART_EVENT_ERROR = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */ + NRF_UART_EVENT_RXTO = offsetof(NRF_UART_Type, EVENTS_RXTO) /**< Event from receiver timeout. */ + /*lint -restore*/ +} nrf_uart_event_t; + +/** + * @enum nrf_uart_int_mask_t + * @brief UART interrupts. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UART_INT_MASK_CTS = UART_INTENCLR_CTS_Msk, /**< CTS line activation interrupt. */ + NRF_UART_INT_MASK_NCTS = UART_INTENCLR_NCTS_Msk, /**< CTS line deactivation interrupt. */ + NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */ + NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk, /**< Data sent from TXD interrupt. */ + NRF_UART_INT_MASK_ERROR = UART_INTENCLR_ERROR_Msk, /**< Error detection interrupt. */ + NRF_UART_INT_MASK_RXTO = UART_INTENCLR_RXTO_Msk /**< Receiver timeout interrupt. */ + /*lint -restore*/ +} nrf_uart_int_mask_t; + +/** + * @enum nrf_uart_baudrate_t + * @brief Baudrates supported by UART. + */ +typedef enum +{ + NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */ + NRF_UART_BAUDRATE_2400 = UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */ + NRF_UART_BAUDRATE_4800 = UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */ + NRF_UART_BAUDRATE_9600 = UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */ + NRF_UART_BAUDRATE_14400 = UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */ + NRF_UART_BAUDRATE_19200 = UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */ + NRF_UART_BAUDRATE_28800 = UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */ + NRF_UART_BAUDRATE_31250 = UART_BAUDRATE_BAUDRATE_Baud31250, /**< 31250 baud. */ + NRF_UART_BAUDRATE_38400 = UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */ + NRF_UART_BAUDRATE_56000 = UART_BAUDRATE_BAUDRATE_Baud56000, /**< 56000 baud. */ + NRF_UART_BAUDRATE_57600 = UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */ + NRF_UART_BAUDRATE_76800 = UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */ + NRF_UART_BAUDRATE_115200 = UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */ + NRF_UART_BAUDRATE_230400 = UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */ + NRF_UART_BAUDRATE_250000 = UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */ + NRF_UART_BAUDRATE_460800 = UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */ + NRF_UART_BAUDRATE_921600 = UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */ + NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */ +} nrf_uart_baudrate_t; + +/** + * @enum nrf_uart_error_mask_t + * @brief Types of UART error masks. + */ +typedef enum +{ + NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk, /**< Overrun error. */ + NRF_UART_ERROR_PARITY_MASK = UART_ERRORSRC_PARITY_Msk, /**< Parity error. */ + NRF_UART_ERROR_FRAMING_MASK = UART_ERRORSRC_FRAMING_Msk, /**< Framing error. */ + NRF_UART_ERROR_BREAK_MASK = UART_ERRORSRC_BREAK_Msk, /**< Break error. */ +} nrf_uart_error_mask_t; + +/** + * @enum nrf_uart_parity_t + * @brief Types of UART parity modes. + */ +typedef enum +{ + NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */ + NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */ +} nrf_uart_parity_t; + +/** + * @enum nrf_uart_hwfc_t + * @brief Types of UART flow control modes. + */ +typedef enum +{ + NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */ + NRF_UART_HWFC_ENABLED = UART_CONFIG_HWFC_Enabled, /**< HW flow control enabled. */ +} nrf_uart_hwfc_t; + +/** + * @brief Function for clearing a specific UART event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event); + +/** + * @brief Function for checking the state of a specific UART event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval True if event is set, False otherwise. + */ +__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event); + +/** + * @brief Function for returning the address of a specific UART event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Desired event. + * + * @retval Address of specified event register. + */ +__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg, + nrf_uart_event_t event); + +/** + * @brief Function for enabling a specific interrupt. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Mask of interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for disabling specific interrupts. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for getting error source mask. Function is clearing error source flags after reading. + * + * @param p_reg Pointer to the peripheral registers structure. + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg); + +/** + * @brief Function for enabling UART. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg); + +/** + * @brief Function for disabling UART. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg); + +/** + * @brief Function for configuring TX/RX pins. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param pseltxd TXD pin number. + * @param pselrxd RXD pin number. + */ +__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd); + +/** + * @brief Function for disconnecting TX/RX pins. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting TX pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting RX pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting RTS pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for getting CTS pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg); + + +/** + * @brief Function for configuring flow control pins. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param pselrts RTS pin number. + * @param pselcts CTS pin number. + */ +__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, + uint32_t pselrts, + uint32_t pselcts); + +/** + * @brief Function for disconnecting flow control pins. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg); + +/** + * @brief Function for reading RX data. + * + * @param p_reg Pointer to the peripheral registers structure. + * @return Received byte. + */ +__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg); + +/** + * @brief Function for setting Tx data. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param txd Byte. + */ +__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd); + +/** + * @brief Function for starting an UART task. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param task Task. + */ +__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task); + +/** + * @brief Function for returning the address of a specific task register. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task); + +/** + * @brief Function for configuring UART. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param hwfc Hardware flow control. Enabled if true. + * @param parity Parity. Included if true. + */ +__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg, + nrf_uart_parity_t parity, + nrf_uart_hwfc_t hwfc); + +/** + * @brief Function for setting UART baudrate. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param baudrate Baudrate. + */ +__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif + +} + +__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type * p_reg, + nrf_uart_event_t event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg) +{ + uint32_t errsrc_mask = p_reg->ERRORSRC; + p_reg->ERRORSRC = errsrc_mask; + return errsrc_mask; +} + +__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg) +{ + p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled; +} + +__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg) +{ + p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled; +} + +__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd) +{ +#if defined(UART_PSEL_RXD_CONNECT_Pos) + p_reg->PSEL.RXD = pselrxd; +#else + p_reg->PSELRXD = pselrxd; +#endif +#if defined(UART_PSEL_TXD_CONNECT_Pos) + p_reg->PSEL.TXD = pseltxd; +#else + p_reg->PSELTXD = pseltxd; +#endif +} + +__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg) +{ + nrf_uart_txrx_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg) +{ +#if defined(UART_PSEL_TXD_CONNECT_Pos) + return p_reg->PSEL.TXD; +#else + return p_reg->PSELTXD; +#endif +} + +__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg) +{ +#if defined(UART_PSEL_RXD_CONNECT_Pos) + return p_reg->PSEL.RXD; +#else + return p_reg->PSELRXD; +#endif +} + +__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg) +{ +#if defined(UART_PSEL_RTS_CONNECT_Pos) + return p_reg->PSEL.RTS; +#else + return p_reg->PSELRTS; +#endif +} + +__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg) +{ +#if defined(UART_PSEL_RTS_CONNECT_Pos) + return p_reg->PSEL.CTS; +#else + return p_reg->PSELCTS; +#endif +} + +__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, uint32_t pselrts, uint32_t pselcts) +{ +#if defined(UART_PSEL_RTS_CONNECT_Pos) + p_reg->PSEL.RTS = pselrts; +#else + p_reg->PSELRTS = pselrts; +#endif + +#if defined(UART_PSEL_RTS_CONNECT_Pos) + p_reg->PSEL.CTS = pselcts; +#else + p_reg->PSELCTS = pselcts; +#endif +} + +__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg) +{ + nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg) +{ + return p_reg->RXD; +} + +__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd) +{ + p_reg->TXD = txd; +} + +__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task) +{ + return (uint32_t)p_reg + (uint32_t)task; +} + +__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type * p_reg, + nrf_uart_parity_t parity, + nrf_uart_hwfc_t hwfc) +{ + p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc; +} + +__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_baudrate_t baudrate) +{ + p_reg->BAUDRATE = baudrate; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif //NRF_UART_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_uarte.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_uarte.h new file mode 100755 index 0000000..03cb513 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_uarte.h @@ -0,0 +1,570 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_UARTE_H__ +#define NRF_UARTE_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF + +/** + * @defgroup nrf_uarte_hal UARTE HAL + * @{ + * @ingroup nrf_uarte + * @brief Hardware access layer for managing the UARTE peripheral. + */ + +/** + * @enum nrf_uarte_task_t + * @brief UARTE tasks. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver. + NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver. + NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter. + NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter. + NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer. + /*lint -restore*/ +} nrf_uarte_task_t; + +/** + * @enum nrf_uarte_event_t + * @brief UARTE events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated. + NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated. + NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM). + NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up. + NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD. + NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted. + NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected. + NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout. + NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started. + NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started. + NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped. + /*lint -restore*/ +} nrf_uarte_event_t; + +/** + * @brief Types of UARTE shortcuts. + */ +typedef enum +{ + NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task. + NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk ///< Shortcut between ENDRX event and STOPRX task. +} nrf_uarte_short_t; + + +/** + * @enum nrf_uarte_int_mask_t + * @brief UARTE interrupts. + */ +typedef enum +{ + NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event. + NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event. + NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event. + NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event. + NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event. + NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event. + NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event. + NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event. + NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event. + NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event. + NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event. +} nrf_uarte_int_mask_t; + +/** + * @enum nrf_uarte_baudrate_t + * @brief Baudrates supported by UARTE. + */ +typedef enum +{ + NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud. + NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud. + NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud. + NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud. + NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud. + NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud. + NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud. + NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud. + NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud. + NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud. + NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud. + NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud. + NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud. + NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud. + NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud. + NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud. + NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud. + NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud. +} nrf_uarte_baudrate_t; + +/** + * @enum nrf_uarte_error_mask_t + * @brief Types of UARTE error masks. + */ +typedef enum +{ + NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error. + NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error. + NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error. + NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error. +} nrf_uarte_error_mask_t; + +/** + * @enum nrf_uarte_parity_t + * @brief Types of UARTE parity modes. + */ +typedef enum +{ + NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded. + NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included. +} nrf_uarte_parity_t; + +/** + * @enum nrf_uarte_hwfc_t + * @brief Types of UARTE flow control modes. + */ +typedef enum +{ + NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled. + NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< HW flow control enabled. +} nrf_uarte_hwfc_t; + + +/** + * @brief Function for clearing a specific UARTE event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to clear. + */ +__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event); + +/** + * @brief Function for checking the state of a specific UARTE event. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Event to check. + * + * @retval True if event is set, False otherwise. + */ +__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event); + +/** + * @brief Function for returning the address of a specific UARTE event register. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] event Desired event. + * + * @retval Address of specified event register. + */ +__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event); + +/** + * @brief Function for enabling UARTE shortcuts. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param shorts_mask Shortcuts to enable. + */ +__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask); + +/** + * @brief Function for disabling UARTE shortcuts. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param shorts_mask Shortcuts to disable. + */ +__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask); + +/** + * @brief Function for enabling UARTE interrupts. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a given interrupt. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param int_mask Mask of interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask); + +/** + * @brief Function for disabling specific interrupts. + * + * @param p_reg Instance. + * @param int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for getting error source mask. Function is clearing error source flags after reading. + * + * @param p_reg Pointer to the peripheral registers structure. + * @return Mask with error source flags. + */ +__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for enabling UARTE. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for disabling UARTE. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for configuring TX/RX pins. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param pseltxd TXD pin number. + * @param pselrxd RXD pin number. + */ +__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd); + +/** + * @brief Function for disconnecting TX/RX pins. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting TX pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting RX pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting RTS pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for getting CTS pin. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg); + + +/** + * @brief Function for configuring flow control pins. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param pselrts RTS pin number. + * @param pselcts CTS pin number. + */ +__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, + uint32_t pselrts, + uint32_t pselcts); + +/** + * @brief Function for disconnecting flow control pins. + * + * @param p_reg Pointer to the peripheral registers structure. + */ +__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for starting an UARTE task. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param task Task. + */ +__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task); + +/** + * @brief Function for returning the address of a specific task register. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task); + +/** + * @brief Function for configuring UARTE. + * + * @param p_reg Pointer to the peripheral registers structure. + * @param hwfc Hardware flow control. Enabled if true. + * @param parity Parity. Included if true. + */ +__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg, + nrf_uarte_parity_t parity, + nrf_uarte_hwfc_t hwfc); + + +/** + * @brief Function for setting UARTE baudrate. + * + * @param p_reg Instance. + * @param baudrate Baudrate. + */ +__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate); + +/** + * @brief Function for setting the transmit buffer. + * + * @param[in] p_reg Instance. + * @param[in] p_buffer Pointer to the buffer with data to send. + * @param[in] length Maximum number of data bytes to transmit. + */ +__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t const * p_buffer, + size_t length); + +/** + * @brief Function for getting number of bytes transmitted in the last transaction. + * + * @param[in] p_reg Instance. + * + * @retval Amount of bytes transmitted. + */ +__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg); + +/** + * @brief Function for setting the receive buffer. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * @param[in] p_buffer Pointer to the buffer for received data. + * @param[in] length Maximum number of data bytes to receive. + */ +__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t * p_buffer, + size_t length); + +/** + * @brief Function for getting number of bytes received in the last transaction. + * + * @param[in] p_reg Pointer to the peripheral registers structure. + * + * @retval Amount of bytes received. + */ +__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); + (void)dummy; +#endif + +} + +__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type * p_reg, + nrf_uarte_event_t event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)event); +} + +__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask) +{ + p_reg->SHORTS |= shorts_mask; +} + +__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask) +{ + p_reg->SHORTS &= ~(shorts_mask); +} + +__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask) +{ + return (bool)(p_reg->INTENSET & int_mask); +} + +__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg) +{ + uint32_t errsrc_mask = p_reg->ERRORSRC; + p_reg->ERRORSRC = errsrc_mask; + return errsrc_mask; +} + +__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg) +{ + p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled; +} + +__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg) +{ + p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled; +} + +__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd) +{ + p_reg->PSEL.TXD = pseltxd; + p_reg->PSEL.RXD = pselrxd; +} + +__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg) +{ + nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED); +} + +__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.TXD; +} + +__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.RXD; +} + +__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.RTS; +} + +__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->PSEL.CTS; +} + +__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts) +{ + p_reg->PSEL.RTS = pselrts; + p_reg->PSEL.CTS = pselcts; +} + +__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg) +{ + nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED); +} + +__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task) +{ + return (uint32_t)p_reg + (uint32_t)task; +} + +__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg, + nrf_uarte_parity_t parity, + nrf_uarte_hwfc_t hwfc) +{ + p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc; +} + +__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate) +{ + p_reg->BAUDRATE = baudrate; +} + +__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t const * p_buffer, + size_t length) +{ + p_reg->TXD.PTR = (uint32_t)p_buffer; + p_reg->TXD.MAXCNT = length; +} + +__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->TXD.AMOUNT; +} + +__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg, + uint8_t * p_buffer, + size_t length) +{ + p_reg->RXD.PTR = (uint32_t)p_buffer; + p_reg->RXD.MAXCNT = length; +} + +__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg) +{ + return p_reg->RXD.AMOUNT; +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif //NRF_UARTE_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_usbd.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_usbd.h new file mode 100755 index 0000000..681367f --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_usbd.h @@ -0,0 +1,1413 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_USBD_H__ +#define NRF_USBD_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_usbd_hal USBD HAL + * @{ + * @ingroup nrf_usbd + * @brief Hardware access layer for managing the Universal Serial Bus Device (USBD) + * peripheral. + */ + +/** + * @brief USBD tasks + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_USBD_TASK_STARTEPIN0 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[0] ), /**< Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables control endpoint IN 0 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPIN1 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[1] ), /**< Captures the EPIN[1].PTR, EPIN[1].MAXCNT and EPIN[1].CONFIG registers values, and enables data endpoint IN 1 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPIN2 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[2] ), /**< Captures the EPIN[2].PTR, EPIN[2].MAXCNT and EPIN[2].CONFIG registers values, and enables data endpoint IN 2 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPIN3 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[3] ), /**< Captures the EPIN[3].PTR, EPIN[3].MAXCNT and EPIN[3].CONFIG registers values, and enables data endpoint IN 3 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPIN4 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[4] ), /**< Captures the EPIN[4].PTR, EPIN[4].MAXCNT and EPIN[4].CONFIG registers values, and enables data endpoint IN 4 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPIN5 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[5] ), /**< Captures the EPIN[5].PTR, EPIN[5].MAXCNT and EPIN[5].CONFIG registers values, and enables data endpoint IN 5 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPIN6 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[6] ), /**< Captures the EPIN[6].PTR, EPIN[6].MAXCNT and EPIN[6].CONFIG registers values, and enables data endpoint IN 6 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPIN7 = offsetof(NRF_USBD_Type, TASKS_STARTEPIN[7] ), /**< Captures the EPIN[7].PTR, EPIN[7].MAXCNT and EPIN[7].CONFIG registers values, and enables data endpoint IN 7 to respond to traffic from host */ + NRF_USBD_TASK_STARTISOIN = offsetof(NRF_USBD_Type, TASKS_STARTISOIN ), /**< Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers values, and enables sending data on iso endpoint 8 */ + NRF_USBD_TASK_STARTEPOUT0 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[0]), /**< Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables control endpoint 0 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPOUT1 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[1]), /**< Captures the EPOUT[1].PTR, EPOUT[1].MAXCNT and EPOUT[1].CONFIG registers values, and enables data endpoint 1 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPOUT2 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[2]), /**< Captures the EPOUT[2].PTR, EPOUT[2].MAXCNT and EPOUT[2].CONFIG registers values, and enables data endpoint 2 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPOUT3 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[3]), /**< Captures the EPOUT[3].PTR, EPOUT[3].MAXCNT and EPOUT[3].CONFIG registers values, and enables data endpoint 3 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPOUT4 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[4]), /**< Captures the EPOUT[4].PTR, EPOUT[4].MAXCNT and EPOUT[4].CONFIG registers values, and enables data endpoint 4 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPOUT5 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[5]), /**< Captures the EPOUT[5].PTR, EPOUT[5].MAXCNT and EPOUT[5].CONFIG registers values, and enables data endpoint 5 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPOUT6 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[6]), /**< Captures the EPOUT[6].PTR, EPOUT[6].MAXCNT and EPOUT[6].CONFIG registers values, and enables data endpoint 6 to respond to traffic from host */ + NRF_USBD_TASK_STARTEPOUT7 = offsetof(NRF_USBD_Type, TASKS_STARTEPOUT[7]), /**< Captures the EPOUT[7].PTR, EPOUT[7].MAXCNT and EPOUT[7].CONFIG registers values, and enables data endpoint 7 to respond to traffic from host */ + NRF_USBD_TASK_STARTISOOUT = offsetof(NRF_USBD_Type, TASKS_STARTISOOUT ), /**< Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers values, and enables receiving of data on iso endpoint 8 */ + NRF_USBD_TASK_EP0RCVOUT = offsetof(NRF_USBD_Type, TASKS_EP0RCVOUT ), /**< Allows OUT data stage on control endpoint 0 */ + NRF_USBD_TASK_EP0STATUS = offsetof(NRF_USBD_Type, TASKS_EP0STATUS ), /**< Allows status stage on control endpoint 0 */ + NRF_USBD_TASK_EP0STALL = offsetof(NRF_USBD_Type, TASKS_EP0STALL ), /**< STALLs data and status stage on control endpoint 0 */ + NRF_USBD_TASK_DRIVEDPDM = offsetof(NRF_USBD_Type, TASKS_DPDMDRIVE ), /**< Forces D+ and D-lines to the state defined in the DPDMVALUE register */ + NRF_USBD_TASK_NODRIVEDPDM = offsetof(NRF_USBD_Type, TASKS_DPDMNODRIVE ), /**< Stops forcing D+ and D- lines to any state (USB engine takes control) */ + /*lint -restore*/ +}nrf_usbd_task_t; + +/** + * @brief USBD events + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_USBD_EVENT_USBRESET = offsetof(NRF_USBD_Type, EVENTS_USBRESET ), /**< Signals that a USB reset condition has been detected on the USB lines */ + NRF_USBD_EVENT_STARTED = offsetof(NRF_USBD_Type, EVENTS_STARTED ), /**< Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers have been captured on all endpoints reported in the EPSTATUS register */ + NRF_USBD_EVENT_ENDEPIN0 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[0] ), /**< The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPIN1 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[1] ), /**< The whole EPIN[1] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPIN2 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[2] ), /**< The whole EPIN[2] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPIN3 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[3] ), /**< The whole EPIN[3] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPIN4 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[4] ), /**< The whole EPIN[4] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPIN5 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[5] ), /**< The whole EPIN[5] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPIN6 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[6] ), /**< The whole EPIN[6] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPIN7 = offsetof(NRF_USBD_Type, EVENTS_ENDEPIN[7] ), /**< The whole EPIN[7] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_EP0DATADONE = offsetof(NRF_USBD_Type, EVENTS_EP0DATADONE), /**< An acknowledged data transfer has taken place on the control endpoint */ + NRF_USBD_EVENT_ENDISOIN0 = offsetof(NRF_USBD_Type, EVENTS_ENDISOIN ), /**< The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPOUT0 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[0]), /**< The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPOUT1 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[1]), /**< The whole EPOUT[1] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPOUT2 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[2]), /**< The whole EPOUT[2] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPOUT3 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[3]), /**< The whole EPOUT[3] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPOUT4 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[4]), /**< The whole EPOUT[4] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPOUT5 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[5]), /**< The whole EPOUT[5] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPOUT6 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[6]), /**< The whole EPOUT[6] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDEPOUT7 = offsetof(NRF_USBD_Type, EVENTS_ENDEPOUT[7]), /**< The whole EPOUT[7] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_ENDISOOUT0 = offsetof(NRF_USBD_Type, EVENTS_ENDISOOUT ), /**< The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ + NRF_USBD_EVENT_SOF = offsetof(NRF_USBD_Type, EVENTS_SOF ), /**< Signals that a SOF (start of frame) condition has been detected on the USB lines */ + NRF_USBD_EVENT_USBEVENT = offsetof(NRF_USBD_Type, EVENTS_USBEVENT ), /**< An event or an error not covered by specific events has occurred, check EVENTCAUSE register to find the cause */ + NRF_USBD_EVENT_EP0SETUP = offsetof(NRF_USBD_Type, EVENTS_EP0SETUP ), /**< A valid SETUP token has been received (and acknowledged) on the control endpoint */ + NRF_USBD_EVENT_DATAEP = offsetof(NRF_USBD_Type, EVENTS_EPDATA ), /**< A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ + /*lint -restore*/ +}nrf_usbd_event_t; + +/** + * @brief USBD shorts + */ +typedef enum +{ + NRF_USBD_SHORT_EP0DATADONE_STARTEPIN0_MASK = USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk , /**< Shortcut between EP0DATADONE event and STARTEPIN0 task */ + NRF_USBD_SHORT_EP0DATADONE_STARTEPOUT0_MASK = USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk, /**< Shortcut between EP0DATADONE event and STARTEPOUT0 task */ + NRF_USBD_SHORT_EP0DATADONE_EP0STATUS_MASK = USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk , /**< Shortcut between EP0DATADONE event and EP0STATUS task */ + NRF_USBD_SHORT_ENDEPOUT0_EP0STATUS_MASK = USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk , /**< Shortcut between ENDEPOUT[0] event and EP0STATUS task */ + NRF_USBD_SHORT_ENDEPOUT0_EP0RCVOUT_MASK = USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk , /**< Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */ +}nrf_usbd_short_mask_t; + +/** + * @brief USBD interrupts + */ +typedef enum +{ + NRF_USBD_INT_USBRESET_MASK = USBD_INTEN_USBRESET_Msk , /**< Enable or disable interrupt for USBRESET event */ + NRF_USBD_INT_STARTED_MASK = USBD_INTEN_STARTED_Msk , /**< Enable or disable interrupt for STARTED event */ + NRF_USBD_INT_ENDEPIN0_MASK = USBD_INTEN_ENDEPIN0_Msk , /**< Enable or disable interrupt for ENDEPIN[0] event */ + NRF_USBD_INT_ENDEPIN1_MASK = USBD_INTEN_ENDEPIN1_Msk , /**< Enable or disable interrupt for ENDEPIN[1] event */ + NRF_USBD_INT_ENDEPIN2_MASK = USBD_INTEN_ENDEPIN2_Msk , /**< Enable or disable interrupt for ENDEPIN[2] event */ + NRF_USBD_INT_ENDEPIN3_MASK = USBD_INTEN_ENDEPIN3_Msk , /**< Enable or disable interrupt for ENDEPIN[3] event */ + NRF_USBD_INT_ENDEPIN4_MASK = USBD_INTEN_ENDEPIN4_Msk , /**< Enable or disable interrupt for ENDEPIN[4] event */ + NRF_USBD_INT_ENDEPIN5_MASK = USBD_INTEN_ENDEPIN5_Msk , /**< Enable or disable interrupt for ENDEPIN[5] event */ + NRF_USBD_INT_ENDEPIN6_MASK = USBD_INTEN_ENDEPIN6_Msk , /**< Enable or disable interrupt for ENDEPIN[6] event */ + NRF_USBD_INT_ENDEPIN7_MASK = USBD_INTEN_ENDEPIN7_Msk , /**< Enable or disable interrupt for ENDEPIN[7] event */ + NRF_USBD_INT_EP0DATADONE_MASK = USBD_INTEN_EP0DATADONE_Msk, /**< Enable or disable interrupt for EP0DATADONE event */ + NRF_USBD_INT_ENDISOIN0_MASK = USBD_INTEN_ENDISOIN_Msk , /**< Enable or disable interrupt for ENDISOIN[0] event */ + NRF_USBD_INT_ENDEPOUT0_MASK = USBD_INTEN_ENDEPOUT0_Msk , /**< Enable or disable interrupt for ENDEPOUT[0] event */ + NRF_USBD_INT_ENDEPOUT1_MASK = USBD_INTEN_ENDEPOUT1_Msk , /**< Enable or disable interrupt for ENDEPOUT[1] event */ + NRF_USBD_INT_ENDEPOUT2_MASK = USBD_INTEN_ENDEPOUT2_Msk , /**< Enable or disable interrupt for ENDEPOUT[2] event */ + NRF_USBD_INT_ENDEPOUT3_MASK = USBD_INTEN_ENDEPOUT3_Msk , /**< Enable or disable interrupt for ENDEPOUT[3] event */ + NRF_USBD_INT_ENDEPOUT4_MASK = USBD_INTEN_ENDEPOUT4_Msk , /**< Enable or disable interrupt for ENDEPOUT[4] event */ + NRF_USBD_INT_ENDEPOUT5_MASK = USBD_INTEN_ENDEPOUT5_Msk , /**< Enable or disable interrupt for ENDEPOUT[5] event */ + NRF_USBD_INT_ENDEPOUT6_MASK = USBD_INTEN_ENDEPOUT6_Msk , /**< Enable or disable interrupt for ENDEPOUT[6] event */ + NRF_USBD_INT_ENDEPOUT7_MASK = USBD_INTEN_ENDEPOUT7_Msk , /**< Enable or disable interrupt for ENDEPOUT[7] event */ + NRF_USBD_INT_ENDISOOUT0_MASK = USBD_INTEN_ENDISOOUT_Msk , /**< Enable or disable interrupt for ENDISOOUT[0] event */ + NRF_USBD_INT_SOF_MASK = USBD_INTEN_SOF_Msk , /**< Enable or disable interrupt for SOF event */ + NRF_USBD_INT_USBEVENT_MASK = USBD_INTEN_USBEVENT_Msk , /**< Enable or disable interrupt for USBEVENT event */ + NRF_USBD_INT_EP0SETUP_MASK = USBD_INTEN_EP0SETUP_Msk , /**< Enable or disable interrupt for EP0SETUP event */ + NRF_USBD_INT_DATAEP_MASK = USBD_INTEN_EPDATA_Msk , /**< Enable or disable interrupt for EPDATA event */ +}nrf_usbd_int_mask_t; + + +/** + * @brief Function for activating a specific USBD task. + * + * @param task Task. + */ +__STATIC_INLINE void nrf_usbd_task_trigger(nrf_usbd_task_t task); + +/** + * @brief Function for returning the address of a specific USBD task register. + * + * @param task Task. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_usbd_task_address_get(nrf_usbd_task_t task); + +/** + * @brief Function for clearing a specific event. + * + * @param event Event. + */ +__STATIC_INLINE void nrf_usbd_event_clear(nrf_usbd_event_t event); + +/** + * @brief Function for returning the state of a specific event. + * + * @param event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_usbd_event_check(nrf_usbd_event_t event); + +/** + * @brief Function for getting and clearing the state of specific event + * + * This function checks the state of the event and clears it. + * + * @param event Event. + * + * @retval true If the event was set. + * @retval false If the event was not set. + */ +__STATIC_INLINE bool nrf_usbd_event_get_and_clear(nrf_usbd_event_t event); + +/** + * @brief Function for returning the address of a specific USBD event register. + * + * @param event Event. + * + * @return Address. + */ +__STATIC_INLINE uint32_t nrf_usbd_event_address_get(nrf_usbd_event_t event); + +/** + * @brief Function for setting a shortcut. + * + * @param short_mask Shortcuts mask. + */ +__STATIC_INLINE void nrf_usbd_shorts_enable(uint32_t short_mask); + +/** + * @brief Function for clearing shortcuts. + * + * @param short_mask Shortcuts mask. + */ +__STATIC_INLINE void nrf_usbd_shorts_disable(uint32_t short_mask); + +/** + * @brief Get the shorts mask + * + * Function returns shorts register. + * + * @return Flags of currently enabled shortcuts + */ +__STATIC_INLINE uint32_t nrf_usbd_shorts_get(void); + +/** + * @brief Function for enabling selected interrupts. + * + * @param int_mask Interrupts mask. + */ +__STATIC_INLINE void nrf_usbd_int_enable(uint32_t int_mask); + +/** + * @brief Function for retrieving the state of selected interrupts. + * + * @param int_mask Interrupts mask. + * + * @retval true If any of selected interrupts is enabled. + * @retval false If none of selected interrupts is enabled. + */ +__STATIC_INLINE bool nrf_usbd_int_enable_check(uint32_t int_mask); + +/** + * @brief Function for retrieving the information about enabled interrupts. + * + * @return The flags of enabled interrupts. + */ +__STATIC_INLINE uint32_t nrf_usbd_int_enable_get(void); + +/** + * @brief Function for disabling selected interrupts. + * + * @param int_mask Interrupts mask. + */ +__STATIC_INLINE void nrf_usbd_int_disable(uint32_t int_mask); + + +/** @} */ /* End of nrf_usbd_hal */ + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +/* ------------------------------------------------------------------------------------------------ + * Internal functions + */ + +/** + * @internal + * @brief Internal function for getting task/event register address + * + * @oaram offset Offset of the register from the instance beginning + * + * @attention offset has to be modulo 4 value. In other case we can get hardware fault. + * @return Pointer to the register + */ +__STATIC_INLINE volatile uint32_t* nrf_usbd_getRegPtr(uint32_t offset) +{ + return (volatile uint32_t*)(((uint8_t *)NRF_USBD) + (uint32_t)offset); +} + +/** + * @internal + * @brief Internal function for getting task/event register address - constant version + * + * @oaram offset Offset of the register from the instance beginning + * + * @attention offset has to be modulo 4 value. In other case we can get hardware fault. + * @return Pointer to the register + */ +__STATIC_INLINE volatile const uint32_t* nrf_usbd_getRegPtr_c(uint32_t offset) +{ + return (volatile const uint32_t*)(((uint8_t *)NRF_USBD) + (uint32_t)offset); +} + +/* ------------------------------------------------------------------------------------------------ + * Interface functions definitions + */ + +void nrf_usbd_task_trigger(nrf_usbd_task_t task) +{ + *(nrf_usbd_getRegPtr((uint32_t)task)) = 1UL; + __ISB(); + __DSB(); +} + +uint32_t nrf_usbd_task_address_get(nrf_usbd_task_t task) +{ + return (uint32_t)nrf_usbd_getRegPtr_c((uint32_t)task); +} + +void nrf_usbd_event_clear(nrf_usbd_event_t event) +{ + *(nrf_usbd_getRegPtr((uint32_t)event)) = 0UL; + __ISB(); + __DSB(); +} + +bool nrf_usbd_event_check(nrf_usbd_event_t event) +{ + return (bool)*nrf_usbd_getRegPtr_c((uint32_t)event); +} + +bool nrf_usbd_event_get_and_clear(nrf_usbd_event_t event) +{ + bool ret = nrf_usbd_event_check(event); + if (ret) + { + nrf_usbd_event_clear(event); + } + return ret; +} + +uint32_t nrf_usbd_event_address_get(nrf_usbd_event_t event) +{ + return (uint32_t)nrf_usbd_getRegPtr_c((uint32_t)event); +} + +void nrf_usbd_shorts_enable(uint32_t short_mask) +{ + NRF_USBD->SHORTS |= short_mask; +} + +void nrf_usbd_shorts_disable(uint32_t short_mask) +{ + if (~0U == short_mask) + { + /* Optimized version for "disable all" */ + NRF_USBD->SHORTS = 0; + } + else + { + NRF_USBD->SHORTS &= ~short_mask; + } +} + +uint32_t nrf_usbd_shorts_get(void) +{ + return NRF_USBD->SHORTS; +} + +void nrf_usbd_int_enable(uint32_t int_mask) +{ + NRF_USBD->INTENSET = int_mask; +} + +bool nrf_usbd_int_enable_check(uint32_t int_mask) +{ + return !!(NRF_USBD->INTENSET & int_mask); +} + +uint32_t nrf_usbd_int_enable_get(void) +{ + return NRF_USBD->INTENSET; +} + +void nrf_usbd_int_disable(uint32_t int_mask) +{ + NRF_USBD->INTENCLR = int_mask; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +/* ------------------------------------------------------------------------------------------------ + * End of automatically generated part + * ------------------------------------------------------------------------------------------------ + */ +/** + * @addtogroup nrf_usbd_hal + * @{ + */ + +/** + * @brief Frame counter size + * + * The number of counts that can be fitted into frame counter + */ +#define NRF_USBD_FRAMECNTR_SIZE \ + ( (USBD_FRAMECNTR_FRAMECNTR_Msk >> USBD_FRAMECNTR_FRAMECNTR_Pos) + 1UL ) +#ifndef USBD_FRAMECNTR_FRAMECNTR_Msk +#error USBD_FRAMECNTR_FRAMECNTR_Msk should be changed into USBD_FRAMECNTR_FRAMECNTR_Msk +#endif + +/** + * @brief First isochronous endpoint number + * + * The number of the first isochronous endpoint + */ +#define NRF_USBD_EPISO_FIRST 8 + +/** + * @brief Total number of IN endpoints + * + * Total number of IN endpoint (including ISOCHRONOUS). + */ +#define NRF_USBD_EPIN_CNT 9 + +/** + * @brief Total number of OUT endpoints + * + * Total number of OUT endpoint (including ISOCHRONOUS). + */ +#define NRF_USBD_EPOUT_CNT 9 + +/** + * @brief Mask of the direction bit in endpoint number + */ +#define NRF_USBD_EP_DIR_Msk (1U << 7) + +/** + * @brief The value of direction bit for IN endpoint direction + */ +#define NRF_USBD_EP_DIR_IN (1U << 7) + +/** + * @brief The value of direction bit for OUT endpoint direction + */ +#define NRF_USBD_EP_DIR_OUT (0U << 7) + +/** + * @brief Macro for making IN endpoint identifier from endpoint number + * + * Macro that sets direction bit to make IN endpoint + * @param[in] epnr Endpoint number + * @return IN Endpoint identifier + */ +#define NRF_USBD_EPIN(epnr) (((uint8_t)(epnr)) | NRF_USBD_EP_DIR_IN) + +/** + * @brief Macro for making OUT endpoint identifier from endpoint number + * + * Macro that sets direction bit to make OUT endpoint + * @param[in] epnr Endpoint number + * @return OUT Endpoint identifier + */ +#define NRF_USBD_EPOUT(epnr) (((uint8_t)(epnr)) | NRF_USBD_EP_DIR_OUT) + +/** + * @brief Macro for extracting the endpoint number from endpoint identifier + * + * Macro that strips out the information about endpoint direction. + * @param[in] ep Endpoint identifier + * @return Endpoint number + */ +#define NRF_USBD_EP_NR_GET(ep) ((uint8_t)(((uint8_t)(ep)) & 0xFU)) + +/** + * @brief Macro for checking endpoint direction + * + * This macro checks if given endpoint has IN direction + * @param ep Endpoint identifier + * @retval true If the endpoint direction is IN + * @retval false If the endpoint direction is OUT + */ +#define NRF_USBD_EPIN_CHECK(ep) ( (((uint8_t)(ep)) & NRF_USBD_EP_DIR_Msk) == NRF_USBD_EP_DIR_IN ) + +/** + * @brief Macro for checking endpoint direction + * + * This macro checks if given endpoint has OUT direction + * @param ep Endpoint identifier + * @retval true If the endpoint direction is OUT + * @retval false If the endpoint direction is IN + */ +#define NRF_USBD_EPOUT_CHECK(ep) ( (((uint8_t)(ep)) & NRF_USBD_EP_DIR_Msk) == NRF_USBD_EP_DIR_OUT ) + +/** + * @brief Macro for checking if endpoint is isochronous + * + * @param ep It can be endpoint identifier or just endpoint number to check + * @retval true The endpoint is isochronous type + * @retval false The endpoint is bulk of interrupt type + */ +#define NRF_USBD_EPISO_CHECK(ep) (NRF_USBD_EP_NR_GET(ep) >= NRF_USBD_EPISO_FIRST) + +/** + * @brief Macro for checking if given number is valid endpoint number + * + * @param ep Endpoint number to check + * @retval true The endpoint is valid + * @retval false The endpoint is not valid + */ +#define NRF_USBD_EP_VALIDATE(ep) ( \ + (NRF_USBD_EPIN_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRF_USBD_EPIN_CNT)) \ + || \ + (NRF_USBD_EPOUT_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRF_USBD_EPOUT_CNT)) \ + ) + +/** + * @brief Not isochronous data frame received + * + * Special value returned by @ref nrf_usbd_episoout_size_get function that means that + * data frame was not received at all. + * This allows differentiate between situations when zero size data comes or no data comes at all + * on isochronous endpoint. + */ +#define NRF_USBD_EPISOOUT_NO_DATA ((size_t)(-1)) + +/** + * @brief EVENTCAUSE register bit masks + */ +typedef enum +{ + NRF_USBD_EVENTCAUSE_ISOOUTCRC_MASK = USBD_EVENTCAUSE_ISOOUTCRC_Msk, /**< CRC error was detected on isochronous OUT endpoint 8. */ + NRF_USBD_EVENTCAUSE_SUSPEND_MASK = USBD_EVENTCAUSE_SUSPEND_Msk, /**< Signals that the USB lines have been seen idle long enough for the device to enter suspend. */ + NRF_USBD_EVENTCAUSE_RESUME_MASK = USBD_EVENTCAUSE_RESUME_Msk, /**< Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. */ + NRF_USBD_EVENTCAUSE_WUREQ_MASK = USBD_EVENTCAUSE_USBWUALLOWED_Msk, /**< The USBD peripheral has exited Low Power mode */ + NRF_USBD_EVENTCAUSE_READY_MASK = USBD_EVENTCAUSE_READY_Msk, /**< MAC is ready for normal operation, rised few us after USBD enabling */ +}nrf_usbd_eventcause_mask_t; + +/** + * @brief DPDMVALUE register + */ +typedef enum +{ + /**Generate Resume signal. Signal is generated for 50 us or 5 ms, + * depending on bus state */ + NRF_USBD_DPDMVALUE_RESUME = USBD_DPDMVALUE_STATE_Resume, + /** D+ Forced high, D- forced low (J state) */ + NRF_USBD_DPDMVALUE_J = USBD_DPDMVALUE_STATE_J, + /** D+ Forced low, D- forced high (K state) */ + NRF_USBD_DPMVALUE_K = USBD_DPDMVALUE_STATE_K +}nrf_usbd_dpdmvalue_t; + +/** + * @brief Dtoggle value or operation + */ +typedef enum +{ + NRF_USBD_DTOGGLE_NOP = USBD_DTOGGLE_VALUE_Nop, /**< No operation - do not change current data toggle on selected endpoint */ + NRF_USBD_DTOGGLE_DATA0 = USBD_DTOGGLE_VALUE_Data0,/**< Data toggle is DATA0 on selected endpoint */ + NRF_USBD_DTOGGLE_DATA1 = USBD_DTOGGLE_VALUE_Data1 /**< Data toggle is DATA1 on selected endpoint */ +}nrf_usbd_dtoggle_t; + +/** + * @brief EPSTATUS bit masks + */ +typedef enum +{ + NRF_USBD_EPSTATUS_EPIN0_MASK = USBD_EPSTATUS_EPIN0_Msk, + NRF_USBD_EPSTATUS_EPIN1_MASK = USBD_EPSTATUS_EPIN1_Msk, + NRF_USBD_EPSTATUS_EPIN2_MASK = USBD_EPSTATUS_EPIN2_Msk, + NRF_USBD_EPSTATUS_EPIN3_MASK = USBD_EPSTATUS_EPIN3_Msk, + NRF_USBD_EPSTATUS_EPIN4_MASK = USBD_EPSTATUS_EPIN4_Msk, + NRF_USBD_EPSTATUS_EPIN5_MASK = USBD_EPSTATUS_EPIN5_Msk, + NRF_USBD_EPSTATUS_EPIN6_MASK = USBD_EPSTATUS_EPIN6_Msk, + NRF_USBD_EPSTATUS_EPIN7_MASK = USBD_EPSTATUS_EPIN7_Msk, + + NRF_USBD_EPSTATUS_EPOUT0_MASK = USBD_EPSTATUS_EPOUT0_Msk, + NRF_USBD_EPSTATUS_EPOUT1_MASK = USBD_EPSTATUS_EPOUT1_Msk, + NRF_USBD_EPSTATUS_EPOUT2_MASK = USBD_EPSTATUS_EPOUT2_Msk, + NRF_USBD_EPSTATUS_EPOUT3_MASK = USBD_EPSTATUS_EPOUT3_Msk, + NRF_USBD_EPSTATUS_EPOUT4_MASK = USBD_EPSTATUS_EPOUT4_Msk, + NRF_USBD_EPSTATUS_EPOUT5_MASK = USBD_EPSTATUS_EPOUT5_Msk, + NRF_USBD_EPSTATUS_EPOUT6_MASK = USBD_EPSTATUS_EPOUT6_Msk, + NRF_USBD_EPSTATUS_EPOUT7_MASK = USBD_EPSTATUS_EPOUT7_Msk, +}nrf_usbd_epstatus_mask_t; + +/** + * @brief DATAEPSTATUS bit masks + */ +typedef enum +{ + NRF_USBD_EPDATASTATUS_EPIN1_MASK = USBD_EPDATASTATUS_EPIN1_Msk, + NRF_USBD_EPDATASTATUS_EPIN2_MASK = USBD_EPDATASTATUS_EPIN2_Msk, + NRF_USBD_EPDATASTATUS_EPIN3_MASK = USBD_EPDATASTATUS_EPIN3_Msk, + NRF_USBD_EPDATASTATUS_EPIN4_MASK = USBD_EPDATASTATUS_EPIN4_Msk, + NRF_USBD_EPDATASTATUS_EPIN5_MASK = USBD_EPDATASTATUS_EPIN5_Msk, + NRF_USBD_EPDATASTATUS_EPIN6_MASK = USBD_EPDATASTATUS_EPIN6_Msk, + NRF_USBD_EPDATASTATUS_EPIN7_MASK = USBD_EPDATASTATUS_EPIN7_Msk, + + NRF_USBD_EPDATASTATUS_EPOUT1_MASK = USBD_EPDATASTATUS_EPOUT1_Msk, + NRF_USBD_EPDATASTATUS_EPOUT2_MASK = USBD_EPDATASTATUS_EPOUT2_Msk, + NRF_USBD_EPDATASTATUS_EPOUT3_MASK = USBD_EPDATASTATUS_EPOUT3_Msk, + NRF_USBD_EPDATASTATUS_EPOUT4_MASK = USBD_EPDATASTATUS_EPOUT4_Msk, + NRF_USBD_EPDATASTATUS_EPOUT5_MASK = USBD_EPDATASTATUS_EPOUT5_Msk, + NRF_USBD_EPDATASTATUS_EPOUT6_MASK = USBD_EPDATASTATUS_EPOUT6_Msk, + NRF_USBD_EPDATASTATUS_EPOUT7_MASK = USBD_EPDATASTATUS_EPOUT7_Msk, +}nrf_usbd_dataepstatus_mask_t; + +/** + * @brief ISOSPLIT configurations + */ +typedef enum +{ + NRF_USBD_ISOSPLIT_ONEDIR = USBD_ISOSPLIT_SPLIT_OneDir, /**< Full buffer dedicated to either iso IN or OUT */ + NRF_USBD_ISOSPLIT_HALF = USBD_ISOSPLIT_SPLIT_HalfIN, /**< Buffer divided in half */ +}nrf_usbd_isosplit_t; + +/** + * @brief ISOINCONFIG configurations + */ +typedef enum +{ + NRF_USBD_ISOINCONFIG_NORESP = USBD_ISOINCONFIG_RESPONSE_NoResp, /**< Endpoint does not respond to an ISO IN token when no data is ready */ + NRF_USBD_ISOINCONFIG_ZERODATA = USBD_ISOINCONFIG_RESPONSE_ZeroData, /**< Endpoint responds with a zero-length data packet to an ISO IN token when no data is ready */ +}nrf_usbd_isoinconfig_t; + +/** + * @brief Function for enabling USBD + */ +__STATIC_INLINE void nrf_usbd_enable(void); + +/** + * @brief Function for disabling USBD + */ +__STATIC_INLINE void nrf_usbd_disable(void); + +/** + * @brief Function for getting EVENTCAUSE register + * + * @return Flag values defined in @ref nrf_usbd_eventcause_mask_t + */ +__STATIC_INLINE uint32_t nrf_usbd_eventcause_get(void); + +/** + * @brief Function for clearing EVENTCAUSE flags + * + * @param flags Flags defined in @ref nrf_usbd_eventcause_mask_t + */ +__STATIC_INLINE void nrf_usbd_eventcause_clear(uint32_t flags); + +/** + * @brief Function for getting EVENTCAUSE register and clear flags that are set + * + * The safest way to return current EVENTCAUSE register. + * All the flags that are returned would be cleared inside EVENTCAUSE register. + * + * @return Flag values defined in @ref nrf_usbd_eventcause_mask_t + */ +__STATIC_INLINE uint32_t nrf_usbd_eventcause_get_and_clear(void); + +/** + * @brief Function for getting HALTEDEPIN register value + * + * @param ep Endpoint number with IN/OUT flag + * + * @return The value of HALTEDEPIN or HALTEDOUT register for selected endpoint + * + * @note + * Use this function for the response for GetStatus() request to endpoint. + * To check if endpoint is stalled in the code use @ref nrf_usbd_ep_is_stall. + */ +__STATIC_INLINE uint32_t nrf_usbd_haltedep(uint8_t ep); + +/** + * @brief Function for checking if selected endpoint is stalled + * + * Function to be used as a syntax sweeter for @ref nrf_usbd_haltedep. + * + * Also as the isochronous endpoint cannot be halted - it returns always false + * if isochronous endpoint is checked. + * + * @param ep Endpoint number with IN/OUT flag + * + * @return The information if the enepoint is halted. + */ +__STATIC_INLINE bool nrf_usbd_ep_is_stall(uint8_t ep); + +/** + * @brief Function for getting EPSTATUS register value + * + * @return Flag values defined in @ref nrf_usbd_epstatus_mask_t + */ +__STATIC_INLINE uint32_t nrf_usbd_epstatus_get(void); + +/** + * @brief Function for clearing EPSTATUS register value + * + * @param flags Flags defined in @ref nrf_usbd_epstatus_mask_t + */ +__STATIC_INLINE void nrf_usbd_epstatus_clear(uint32_t flags); + +/** + * @brief Function for getting and clearing EPSTATUS register value + * + * Function clears all flags in register set before returning its value. + * @return Flag values defined in @ref nrf_usbd_epstatus_mask_t + */ +__STATIC_INLINE uint32_t nrf_usbd_epstatus_get_and_clear(void); + +/** + * @brief Function for getting DATAEPSTATUS register value + * + * @return Flag values defined in @ref nrf_usbd_dataepstatus_mask_t + */ +__STATIC_INLINE uint32_t nrf_usbd_epdatastatus_get(void); + +/** + * @brief Function for clearing DATAEPSTATUS register value + * + * @param flags Flags defined in @ref nrf_usbd_dataepstatus_mask_t + */ +__STATIC_INLINE void nrf_usbd_epdatastatus_clear(uint32_t flags); + +/** + * @brief Function for getting and clearing DATAEPSTATUS register value + * + * Function clears all flags in register set before returning its value. + * @return Flag values defined in @ref nrf_usbd_dataepstatus_mask_t + */ +__STATIC_INLINE uint32_t nrf_usbd_epdatastatus_get_and_clear(void); + +/** + * @name Setup command frame functions + * + * Functions for setup command frame parts access + * @{ + */ + /** + * @brief Function for reading BMREQUESTTYPE - part of SETUP packet + * + * @return the value of BREQUESTTYPE on last received SETUP frame + */ + __STATIC_INLINE uint8_t nrf_usbd_setup_bmrequesttype_get(void); + + /** + * @brief Function for reading BMREQUEST - part of SETUP packet + * + * @return the value of BREQUEST on last received SETUP frame + */ + __STATIC_INLINE uint8_t nrf_usbd_setup_brequest_get(void); + + /** + * @brief Function for reading WVALUE - part of SETUP packet + * + * @return the value of WVALUE on last received SETUP frame + */ + __STATIC_INLINE uint16_t nrf_usbd_setup_wvalue_get(void); + + /** + * @brief Function for reading WINDEX - part of SETUP packet + * + * @return the value of WINDEX on last received SETUP frame + */ + __STATIC_INLINE uint16_t nrf_usbd_setup_windex_get(void); + + /** + * @brief Function for reading WLENGTH - part of SETUP packet + * + * @return the value of WLENGTH on last received SETUP frame + */ + __STATIC_INLINE uint16_t nrf_usbd_setup_wlength_get(void); +/** @} */ + +/** + * @brief Function for getting number of received bytes on selected endpoint + * + * @param ep Endpoint identifier. + * + * @return Number of received bytes. + * + * @note This function may be used on Bulk/Interrupt and Isochronous endpoints. + * @note For the function that returns different value for ISOOUT zero transfer or no transfer at all, + * see @ref nrf_usbd_episoout_size_get function. This function would return 0 for both cases. + */ +__STATIC_INLINE size_t nrf_usbd_epout_size_get(uint8_t ep); + +/** + * @brief Function for getting number of received bytes on isochronous endpoint. + * + * @param ep Endpoint identifier, has to be isochronous out endpoint. + * + * @return Number of bytes received or @ref NRF_USBD_EPISOOUT_NO_DATA + */ +__STATIC_INLINE size_t nrf_usbd_episoout_size_get(uint8_t ep); + +/** + * @brief Function for clearing out endpoint to accept any new incoming traffic + * + * @param ep ep Endpoint identifier. Only OUT Interrupt/Bulk endpoints are accepted. + */ +__STATIC_INLINE void nrf_usbd_epout_clear(uint8_t ep); + +/** + * @brief Function for enabling USB pullup + */ +__STATIC_INLINE void nrf_usbd_pullup_enable(void); + +/** + * @brief Function for disabling USB pullup + */ +__STATIC_INLINE void nrf_usbd_pullup_disable(void); + +/** + * @brief Function for returning current USB pullup state + * + * @retval true USB pullup is enabled + * @retval false USB pullup is disabled + */ +__STATIC_INLINE bool nrf_usbd_pullup_check(void); + +/** + * @brief Function for configuring the value to be forced on the bus on DRIVEDPDM task + * + * Selected state would be forced on the bus when @ref NRF_USBD_TASK_DRIVEDPDM is set. + * The state would be removed from the bus on @ref NRF_USBD_TASK_NODRIVEDPDM and + * the control would be returned to the USBD peripheral. + * @param val State to be set + */ +__STATIC_INLINE void nrf_usbd_dpdmvalue_set(nrf_usbd_dpdmvalue_t val); + +/** + * @brief Function for setting data toggle + * + * Configuration of current state of data toggling + * @param ep Endpoint number with the information about its direction + * @param op Operation to execute + */ +__STATIC_INLINE void nrf_usbd_dtoggle_set(uint8_t ep, nrf_usbd_dtoggle_t op); + +/** + * @brief Function for getting data toggle + * + * Get the current state of data toggling + * @param ep Endpoint number to return the information about current data toggling + * @retval NRF_USBD_DTOGGLE_DATA0 Data toggle is DATA0 on selected endpoint + * @retval NRF_USBD_DTOGGLE_DATA1 Data toggle is DATA1 on selected endpoint + */ +__STATIC_INLINE nrf_usbd_dtoggle_t nrf_usbd_dtoggle_get(uint8_t ep); + +/** + * @brief Function for checking if endpoint is enabled + * + * @param ep Endpoint id to check + * + * @retval true Endpoint is enabled + * @retval false Endpoint is disabled + */ +__STATIC_INLINE bool nrf_usbd_ep_enable_check(uint8_t ep); + +/** + * @brief Function for enabling selected endpoint + * + * Enabled endpoint responds for the tokens on the USB bus + * + * @param ep Endpoint id to enable + */ +__STATIC_INLINE void nrf_usbd_ep_enable(uint8_t ep); + +/** + * @brief Function for disabling selected endpoint + * + * Disabled endpoint does not respond for the tokens on the USB bus + * + * @param ep Endpoint id to disable + */ +__STATIC_INLINE void nrf_usbd_ep_disable(uint8_t ep); + +/** + * @brief Function for disabling all endpoints + * + * Auxiliary function to simply disable all aviable endpoints. + * It lefts only EP0 IN and OUT enabled. + */ +__STATIC_INLINE void nrf_usbd_ep_all_disable(void); + +/** + * @brief Function for stalling selected endpoint + * + * @param ep Endpoint identifier + * @note This function cannot be called on isochronous endpoint + */ +__STATIC_INLINE void nrf_usbd_ep_stall(uint8_t ep); + +/** + * @brief Function for unstalling selected endpoint + * + * @param ep Endpoint identifier + * @note This function cannot be called on isochronous endpoint + */ +__STATIC_INLINE void nrf_usbd_ep_unstall(uint8_t ep); + +/** + * @brief Function for configuration of isochronous buffer splitting + * + * Configure isochronous buffer splitting between IN and OUT endpoints. + * + * @param split Required configuration + */ +__STATIC_INLINE void nrf_usbd_isosplit_set(nrf_usbd_isosplit_t split); + +/** + * @brief Function for getting the isochronous buffer splitting configuration + * + * Get the current isochronous buffer splitting configuration. + * + * @return Current configuration + */ +__STATIC_INLINE nrf_usbd_isosplit_t nrf_usbd_isosplit_get(void); + +/** + * @brief Function for getting current frame counter + * + * @return Current frame counter + */ +__STATIC_INLINE uint32_t nrf_usbd_framecntr_get(void); + +/** + * @brief Function for entering into low power mode + * + * After this function is called the clock source from the USBD is disconnected internally. + * After this function is called most of the USBD registers cannot be accessed anymore. + * + * @sa nrf_usbd_lowpower_disable + * @sa nrf_usbd_lowpower_check + */ +__STATIC_INLINE void nrf_usbd_lowpower_enable(void); + +/** + * @brief Function for exiting from low power mode + * + * After this function is called the clock source for the USBD is connected internally. + * The @ref NRF_USBD_EVENTCAUSE_WUREQ_MASK event would be generated and + * then the USBD registers may be accessed. + * + * @sa nrf_usbd_lowpower_enable + * @sa nrf_usbd_lowpower_check + */ +__STATIC_INLINE void nrf_usbd_lowpower_disable(void); + +/** + * @brief Function for checking the state of the low power mode + * + * @retval true USBD is in low power mode + * @retval false USBD is not in low power mode + */ +__STATIC_INLINE bool nrf_usbd_lowpower_check(void); + +/** + * @brief Function for configuring ISO IN endpoint response to an IN token when no data is ready to be sent. + * + * @param config Required configuration + */ +__STATIC_INLINE void nrf_usbd_isoinconfig_set(nrf_usbd_isoinconfig_t config); + +/** + * @brief Function for getting the cofiguration of ISO IN endpoint response to an IN token when no data is ready to be sent. + * + * @return Current configuration + */ +__STATIC_INLINE nrf_usbd_isoinconfig_t nrf_usbd_isoinconfig_get(void); + +/** + * @brief Function for configuring EasyDMA channel + * + * Configures EasyDMA for the transfer. + * + * @param ep Endpoint identifier (with direction) + * @param ptr Pointer to the data + * @param maxcnt Number of bytes to transfer + */ +__STATIC_INLINE void nrf_usbd_ep_easydma_set(uint8_t ep, uint32_t ptr, uint32_t maxcnt); + +/** + * @brief Function for getting number of transferred bytes + * + * Get number of transferred bytes in the last transaction + * + * @param ep Endpoint identifier + * + * @return The content of the AMOUNT register + */ +__STATIC_INLINE uint32_t nrf_usbd_ep_amount_get(uint8_t ep); + + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +void nrf_usbd_enable(void) +{ +#ifdef NRF_FPGA_IMPLEMENTATION + *(volatile uint32_t *)0x400005F4 = 3; + __ISB(); + __DSB(); + *(volatile uint32_t *)0x400005F0 = 3; + __ISB(); + __DSB(); +#endif + + NRF_USBD->ENABLE = USBD_ENABLE_ENABLE_Enabled << USBD_ENABLE_ENABLE_Pos; + __ISB(); + __DSB(); +} + +void nrf_usbd_disable(void) +{ + NRF_USBD->ENABLE = USBD_ENABLE_ENABLE_Disabled << USBD_ENABLE_ENABLE_Pos; + __ISB(); + __DSB(); +} + +uint32_t nrf_usbd_eventcause_get(void) +{ + return NRF_USBD->EVENTCAUSE; +} + +void nrf_usbd_eventcause_clear(uint32_t flags) +{ + NRF_USBD->EVENTCAUSE = flags; + __ISB(); + __DSB(); +} + +uint32_t nrf_usbd_eventcause_get_and_clear(void) +{ + uint32_t ret; + ret = nrf_usbd_eventcause_get(); + nrf_usbd_eventcause_clear(ret); + __ISB(); + __DSB(); + return ret; +} + +uint32_t nrf_usbd_haltedep(uint8_t ep) +{ + uint8_t epnr = NRF_USBD_EP_NR_GET(ep); + if (NRF_USBD_EPIN_CHECK(ep)) + { + NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->HALTED.EPIN)); + return NRF_USBD->HALTED.EPIN[epnr]; + } + else + { + NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->HALTED.EPOUT)); + return NRF_USBD->HALTED.EPOUT[epnr]; + } +} + +bool nrf_usbd_ep_is_stall(uint8_t ep) +{ + if (NRF_USBD_EPISO_CHECK(ep)) + return false; + return USBD_HALTED_EPOUT_GETSTATUS_Halted == nrf_usbd_haltedep(ep); +} + +uint32_t nrf_usbd_epstatus_get(void) +{ + return NRF_USBD->EPSTATUS; +} + +void nrf_usbd_epstatus_clear(uint32_t flags) +{ + NRF_USBD->EPSTATUS = flags; + __ISB(); + __DSB(); +} + +uint32_t nrf_usbd_epstatus_get_and_clear(void) +{ + uint32_t ret; + ret = nrf_usbd_epstatus_get(); + nrf_usbd_epstatus_clear(ret); + return ret; +} + +uint32_t nrf_usbd_epdatastatus_get(void) +{ + return NRF_USBD->EPDATASTATUS; +} + +void nrf_usbd_epdatastatus_clear(uint32_t flags) +{ + NRF_USBD->EPDATASTATUS = flags; + __ISB(); + __DSB(); +} + +uint32_t nrf_usbd_epdatastatus_get_and_clear(void) +{ + uint32_t ret; + ret = nrf_usbd_epdatastatus_get(); + nrf_usbd_epdatastatus_clear(ret); + return ret; +} + +uint8_t nrf_usbd_setup_bmrequesttype_get(void) +{ + return (uint8_t)(NRF_USBD->BMREQUESTTYPE); +} + +uint8_t nrf_usbd_setup_brequest_get(void) +{ + return (uint8_t)(NRF_USBD->BREQUEST); +} + +uint16_t nrf_usbd_setup_wvalue_get(void) +{ + const uint16_t val = NRF_USBD->WVALUEL; + return (uint16_t)(val | ((NRF_USBD->WVALUEH) << 8)); +} + +uint16_t nrf_usbd_setup_windex_get(void) +{ + const uint16_t val = NRF_USBD->WINDEXL; + return (uint16_t)(val | ((NRF_USBD->WINDEXH) << 8)); +} + +uint16_t nrf_usbd_setup_wlength_get(void) +{ + const uint16_t val = NRF_USBD->WLENGTHL; + return (uint16_t)(val | ((NRF_USBD->WLENGTHH) << 8)); +} + +size_t nrf_usbd_epout_size_get(uint8_t ep) +{ + NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); + NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep)); + if (NRF_USBD_EPISO_CHECK(ep)) + { + size_t size_isoout = NRF_USBD->SIZE.ISOOUT; + if ((size_isoout & USBD_SIZE_ISOOUT_ZERO_Msk) == (USBD_SIZE_ISOOUT_ZERO_ZeroData << USBD_SIZE_ISOOUT_ZERO_Pos)) + { + size_isoout = 0; + } + return size_isoout; + } + + NRFX_ASSERT(NRF_USBD_EP_NR_GET(ep) < NRFX_ARRAY_SIZE(NRF_USBD->SIZE.EPOUT)); + return NRF_USBD->SIZE.EPOUT[NRF_USBD_EP_NR_GET(ep)]; +} + +size_t nrf_usbd_episoout_size_get(uint8_t ep) +{ + NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); + NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep)); + NRFX_ASSERT(NRF_USBD_EPISO_CHECK(ep)); + + size_t size_isoout = NRF_USBD->SIZE.ISOOUT; + if (size_isoout == 0) + { + size_isoout = NRF_USBD_EPISOOUT_NO_DATA; + } + else if ((size_isoout & USBD_SIZE_ISOOUT_ZERO_Msk) == (USBD_SIZE_ISOOUT_ZERO_ZeroData << USBD_SIZE_ISOOUT_ZERO_Pos)) + { + size_isoout = 0; + } + return size_isoout; +} + +void nrf_usbd_epout_clear(uint8_t ep) +{ + NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRFX_ARRAY_SIZE(NRF_USBD->SIZE.EPOUT))); + NRF_USBD->SIZE.EPOUT[NRF_USBD_EP_NR_GET(ep)] = 0; + __ISB(); + __DSB(); +} + +void nrf_usbd_pullup_enable(void) +{ + NRF_USBD->USBPULLUP = USBD_USBPULLUP_CONNECT_Enabled << USBD_USBPULLUP_CONNECT_Pos; + __ISB(); + __DSB(); +} + +void nrf_usbd_pullup_disable(void) +{ + NRF_USBD->USBPULLUP = USBD_USBPULLUP_CONNECT_Disabled << USBD_USBPULLUP_CONNECT_Pos; + __ISB(); + __DSB(); +} + +bool nrf_usbd_pullup_check(void) +{ + return NRF_USBD->USBPULLUP == (USBD_USBPULLUP_CONNECT_Enabled << USBD_USBPULLUP_CONNECT_Pos); +} + +void nrf_usbd_dpdmvalue_set(nrf_usbd_dpdmvalue_t val) +{ + NRF_USBD->DPDMVALUE = ((uint32_t)val) << USBD_DPDMVALUE_STATE_Pos; +} + +void nrf_usbd_dtoggle_set(uint8_t ep, nrf_usbd_dtoggle_t op) +{ + NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); + NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep)); + NRF_USBD->DTOGGLE = ep | (NRF_USBD_DTOGGLE_NOP << USBD_DTOGGLE_VALUE_Pos); + __DSB(); + NRF_USBD->DTOGGLE = ep | (op << USBD_DTOGGLE_VALUE_Pos); + __ISB(); + __DSB(); +} + +nrf_usbd_dtoggle_t nrf_usbd_dtoggle_get(uint8_t ep) +{ + uint32_t retval; + /* Select the endpoint to read */ + NRF_USBD->DTOGGLE = ep | (NRF_USBD_DTOGGLE_NOP << USBD_DTOGGLE_VALUE_Pos); + retval = ((NRF_USBD->DTOGGLE) & USBD_DTOGGLE_VALUE_Msk) >> USBD_DTOGGLE_VALUE_Pos; + return (nrf_usbd_dtoggle_t)retval; +} + +bool nrf_usbd_ep_enable_check(uint8_t ep) +{ + NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); + uint8_t epnr = NRF_USBD_EP_NR_GET(ep); + + if (NRF_USBD_EPIN_CHECK(ep)) + { + return 0 != (NRF_USBD->EPINEN & (1UL << epnr)); + } + else + { + return 0 != (NRF_USBD->EPOUTEN & (1UL << epnr)); + } +} + +void nrf_usbd_ep_enable(uint8_t ep) +{ + NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); + uint8_t epnr = NRF_USBD_EP_NR_GET(ep); + + if (NRF_USBD_EPIN_CHECK(ep)) + { + NRF_USBD->EPINEN |= 1UL << epnr; + } + else + { + NRF_USBD->EPOUTEN |= 1UL << epnr; + } + __ISB(); + __DSB(); +} + +void nrf_usbd_ep_disable(uint8_t ep) +{ + NRFX_ASSERT(NRF_USBD_EP_VALIDATE(ep)); + uint8_t epnr = NRF_USBD_EP_NR_GET(ep); + + if (NRF_USBD_EPIN_CHECK(ep)) + { + NRF_USBD->EPINEN &= ~(1UL << epnr); + } + else + { + NRF_USBD->EPOUTEN &= ~(1UL << epnr); + } + __ISB(); + __DSB(); +} + +void nrf_usbd_ep_all_disable(void) +{ + NRF_USBD->EPINEN = USBD_EPINEN_IN0_Enable << USBD_EPINEN_IN0_Pos; + NRF_USBD->EPOUTEN = USBD_EPOUTEN_OUT0_Enable << USBD_EPOUTEN_OUT0_Pos; + __ISB(); + __DSB(); +} + +void nrf_usbd_ep_stall(uint8_t ep) +{ + NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep)); + NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_Stall << USBD_EPSTALL_STALL_Pos) | ep; + __ISB(); + __DSB(); +} + +void nrf_usbd_ep_unstall(uint8_t ep) +{ + NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep)); + NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep; + __ISB(); + __DSB(); +} + +void nrf_usbd_isosplit_set(nrf_usbd_isosplit_t split) +{ + NRF_USBD->ISOSPLIT = split << USBD_ISOSPLIT_SPLIT_Pos; +} + +nrf_usbd_isosplit_t nrf_usbd_isosplit_get(void) +{ + return (nrf_usbd_isosplit_t) + (((NRF_USBD->ISOSPLIT) & USBD_ISOSPLIT_SPLIT_Msk) >> USBD_ISOSPLIT_SPLIT_Pos); +} + +uint32_t nrf_usbd_framecntr_get(void) +{ + return NRF_USBD->FRAMECNTR; +} + +void nrf_usbd_lowpower_enable(void) +{ + NRF_USBD->LOWPOWER = USBD_LOWPOWER_LOWPOWER_LowPower << USBD_LOWPOWER_LOWPOWER_Pos; +} + +void nrf_usbd_lowpower_disable(void) +{ + NRF_USBD->LOWPOWER = USBD_LOWPOWER_LOWPOWER_ForceNormal << USBD_LOWPOWER_LOWPOWER_Pos; +} + +bool nrf_usbd_lowpower_check(void) +{ + return (NRF_USBD->LOWPOWER != (USBD_LOWPOWER_LOWPOWER_ForceNormal << USBD_LOWPOWER_LOWPOWER_Pos)); +} + +void nrf_usbd_isoinconfig_set(nrf_usbd_isoinconfig_t config) +{ + NRF_USBD->ISOINCONFIG = ((uint32_t)config) << USBD_ISOINCONFIG_RESPONSE_Pos; +} + +nrf_usbd_isoinconfig_t nrf_usbd_isoinconfig_get(void) +{ + return (nrf_usbd_isoinconfig_t) + (((NRF_USBD->ISOINCONFIG) & USBD_ISOINCONFIG_RESPONSE_Msk) >> USBD_ISOINCONFIG_RESPONSE_Pos); +} + +void nrf_usbd_ep_easydma_set(uint8_t ep, uint32_t ptr, uint32_t maxcnt) +{ + if (NRF_USBD_EPIN_CHECK(ep)) + { + if (NRF_USBD_EPISO_CHECK(ep)) + { + NRF_USBD->ISOIN.PTR = ptr; + NRF_USBD->ISOIN.MAXCNT = maxcnt; + } + else + { + uint8_t epnr = NRF_USBD_EP_NR_GET(ep); + NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->EPIN)); + NRF_USBD->EPIN[epnr].PTR = ptr; + NRF_USBD->EPIN[epnr].MAXCNT = maxcnt; + } + } + else + { + if (NRF_USBD_EPISO_CHECK(ep)) + { + NRF_USBD->ISOOUT.PTR = ptr; + NRF_USBD->ISOOUT.MAXCNT = maxcnt; + } + else + { + uint8_t epnr = NRF_USBD_EP_NR_GET(ep); + NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->EPOUT)); + NRF_USBD->EPOUT[epnr].PTR = ptr; + NRF_USBD->EPOUT[epnr].MAXCNT = maxcnt; + } + } +} + +uint32_t nrf_usbd_ep_amount_get(uint8_t ep) +{ + uint32_t ret; + + if (NRF_USBD_EPIN_CHECK(ep)) + { + if (NRF_USBD_EPISO_CHECK(ep)) + { + ret = NRF_USBD->ISOIN.AMOUNT; + } + else + { + uint8_t epnr = NRF_USBD_EP_NR_GET(ep); + NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->EPOUT)); + ret = NRF_USBD->EPIN[epnr].AMOUNT; + } + } + else + { + if (NRF_USBD_EPISO_CHECK(ep)) + { + ret = NRF_USBD->ISOOUT.AMOUNT; + } + else + { + uint8_t epnr = NRF_USBD_EP_NR_GET(ep); + NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->EPOUT)); + ret = NRF_USBD->EPOUT[epnr].AMOUNT; + } + } + + return ret; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_USBD_H__ */ diff --git a/arduino/cores/nRF5/nordic/nrfx/hal/nrf_wdt.h b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_wdt.h new file mode 100755 index 0000000..81c88bf --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/hal/nrf_wdt.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_WDT_H__ +#define NRF_WDT_H__ + +#include <nrfx.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_wdt_hal WDT HAL + * @{ + * @ingroup nrf_wdt + * @brief Hardware access layer for managing the Watchdog Timer (WDT) peripheral. + */ + +#define NRF_WDT_CHANNEL_NUMBER 0x8UL +#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, shouldn't be modified.*/ + +#define NRF_WDT_TASK_SET 1UL +#define NRF_WDT_EVENT_CLEAR 0UL + +/** + * @enum nrf_wdt_task_t + * @brief WDT tasks. + */ +typedef enum +{ + /*lint -save -e30 -esym(628,__INTADDR__)*/ + NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */ + /*lint -restore*/ +} nrf_wdt_task_t; + +/** + * @enum nrf_wdt_event_t + * @brief WDT events. + */ +typedef enum +{ + /*lint -save -e30*/ + NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */ + /*lint -restore*/ +} nrf_wdt_event_t; + +/** + * @enum nrf_wdt_behaviour_t + * @brief WDT behavior in CPU SLEEP or HALT mode. + */ +typedef enum +{ + NRF_WDT_BEHAVIOUR_RUN_SLEEP = WDT_CONFIG_SLEEP_Msk, /**< WDT will run when CPU is in SLEEP mode. */ + NRF_WDT_BEHAVIOUR_RUN_HALT = WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in HALT mode. */ + NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT = WDT_CONFIG_SLEEP_Msk | WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in SLEEP or HALT mode. */ + NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0, /**< WDT will be paused when CPU is in SLEEP or HALT mode. */ +} nrf_wdt_behaviour_t; + +/** + * @enum nrf_wdt_rr_register_t + * @brief WDT reload request registers. + */ +typedef enum +{ + NRF_WDT_RR0 = 0, /**< Reload request register 0. */ + NRF_WDT_RR1, /**< Reload request register 1. */ + NRF_WDT_RR2, /**< Reload request register 2. */ + NRF_WDT_RR3, /**< Reload request register 3. */ + NRF_WDT_RR4, /**< Reload request register 4. */ + NRF_WDT_RR5, /**< Reload request register 5. */ + NRF_WDT_RR6, /**< Reload request register 6. */ + NRF_WDT_RR7 /**< Reload request register 7. */ +} nrf_wdt_rr_register_t; + +/** + * @enum nrf_wdt_int_mask_t + * @brief WDT interrupts. + */ +typedef enum +{ + NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */ +} nrf_wdt_int_mask_t; + +/** + * @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted. + * + * @param behaviour Watchdog behavior when CPU is in SLEEP or HALT mode. + */ +__STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour) +{ + NRF_WDT->CONFIG = behaviour; +} + + +/** + * @brief Function for starting the watchdog. + * + * @param[in] task Task. + */ +__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET; +} + + +/** + * @brief Function for clearing the WDT event. + * + * @param[in] event Event. + */ +__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)); + (void)dummy; +#endif +} + + +/** + * @brief Function for retrieving the state of the WDT event. + * + * @param[in] event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event) +{ + return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event)); +} + + +/** + * @brief Function for enabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask) +{ + NRF_WDT->INTENSET = int_mask; +} + + +/** + * @brief Function for retrieving the state of given interrupt. + * + * @param[in] int_mask Interrupt. + * + * @retval true Interrupt is enabled. + * @retval false Interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask) +{ + return (bool)(NRF_WDT->INTENSET & int_mask); +} + + +/** + * @brief Function for disabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask) +{ + NRF_WDT->INTENCLR = int_mask; +} + + +/** + * @brief Function for returning the address of a specific WDT task register. + * + * @param[in] task Task. + */ +__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task) +{ + return ((uint32_t)NRF_WDT + task); +} + + +/** + * @brief Function for returning the address of a specific WDT event register. + * + * @param[in] event Event. + * + * @retval address of requested event register + */ +__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event) +{ + return ((uint32_t)NRF_WDT + event); +} + + +/** + * @brief Function for retrieving the watchdog status. + * + * @retval true If the watchdog is started. + * @retval false If the watchdog is not started. + */ +__STATIC_INLINE bool nrf_wdt_started(void) +{ + return (bool)(NRF_WDT->RUNSTATUS); +} + + +/** + * @brief Function for retrieving the watchdog reload request status. + * + * @param[in] rr_register Reload request register to check. + * + * @retval true If a reload request is running. + * @retval false If no reload request is running. + */ +__STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register) +{ + return (bool)(((NRF_WDT->REQSTATUS) >> rr_register) & 0x1UL); +} + + +/** + * @brief Function for setting the watchdog reload value. + * + * @param[in] reload_value Watchdog counter initial value. + */ +__STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value) +{ + NRF_WDT->CRV = reload_value; +} + + +/** + * @brief Function for retrieving the watchdog reload value. + * + * @retval Reload value. + */ +__STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void) +{ + return (uint32_t)NRF_WDT->CRV; +} + + +/** + * @brief Function for enabling a specific reload request register. + * + * @param[in] rr_register Reload request register to enable. + */ +__STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register) +{ + NRF_WDT->RREN |= 0x1UL << rr_register; +} + + +/** + * @brief Function for disabling a specific reload request register. + * + * @param[in] rr_register Reload request register to disable. + */ +__STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register) +{ + NRF_WDT->RREN &= ~(0x1UL << rr_register); +} + + +/** + * @brief Function for retrieving the status of a specific reload request register. + * + * @param[in] rr_register Reload request register to check. + * + * @retval true If the reload request register is enabled. + * @retval false If the reload request register is not enabled. + */ +__STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register) +{ + return (bool)(NRF_WDT->RREN & (0x1UL << rr_register)); +} + + +/** + * @brief Function for setting a specific reload request register. + * + * @param[in] rr_register Reload request register to set. + */ +__STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register) +{ + NRF_WDT->RR[rr_register] = NRF_WDT_RR_VALUE; +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/compiler_abstraction.h b/arduino/cores/nRF5/nordic/nrfx/mdk/compiler_abstraction.h new file mode 100755 index 0000000..f636469 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/compiler_abstraction.h @@ -0,0 +1,146 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _COMPILER_ABSTRACTION_H +#define _COMPILER_ABSTRACTION_H + +/*lint ++flb "Enter library region" */ + +#if defined ( __CC_ARM ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE __inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #define GET_SP() __current_sp() + +#elif defined ( __ICCARM__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __weak + #endif + + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif + + #define GET_SP() __get_SP() + +#elif defined ( __GNUC__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(n))) + #endif + + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + #define GET_SP() gcc_current_sp() + + static inline unsigned int gcc_current_sp(void) + { + register unsigned sp __ASM("sp"); + return sp; + } + +#elif defined ( __TASKING__ ) + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + + #ifndef __ALIGN + #define __ALIGN(n) __align(n) + #endif + + /* Not defined for TASKING. */ + #ifndef __PACKED + #define __PACKED + #endif + + #define GET_SP() __get_MSP() + +#endif + +/*lint --flb "Leave library region" */ + +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf.h new file mode 100755 index 0000000..5cd8040 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf.h @@ -0,0 +1,95 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 17 +#define MDK_MICRO_VERSION 0 + +/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ +#if defined (NRF52) + #ifndef NRF52832_XXAA + #define NRF52832_XXAA + #endif +#endif + +/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ +#if defined (NRF52810_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52840_XXAA) + #ifndef NRF52_SERIES + #define NRF52_SERIES + #endif +#endif + + +#if defined(_WIN32) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__unix) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__APPLE__) + /* Do not include nrf specific files when building for PC host */ +#else + + /* Device selection for device includes. */ + #if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + + #elif defined (NRF52810_XXAA) + #include "nrf52810.h" + #include "nrf52810_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" + #elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + + #else + #error "Device must be defined. See nrf.h." + #endif /* NRF51, NRF52810_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52840_XXAA */ + + #include "compiler_abstraction.h" + +#endif /* _WIN32 || __unix || __APPLE__ */ + +#endif /* NRF_H */ + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51.h new file mode 100755 index 0000000..6dea9a4 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51.h @@ -0,0 +1,1301 @@ +/* + * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf51.h + * @brief CMSIS HeaderFile + * @version 522 + * @date 06. June 2018 + * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:38 + * from File 'nrf51.svd', + * last modified on Wednesday, 06.06.2018 13:21:34 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf51 + * @{ + */ + + +#ifndef NRF51_H +#define NRF51_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== nrf51 Specific Interrupt Numbers ============================================ */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UART0_IRQn = 2, /*!< 2 UART0 */ + SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ + SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + ADC_IRQn = 7, /*!< 7 ADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ + SWI0_IRQn = 20, /*!< 20 SWI0 */ + SWI1_IRQn = 21, /*!< 21 SWI1 */ + SWI2_IRQn = 22, /*!< 22 SWI2 */ + SWI3_IRQn = 23, /*!< 23 SWI3 */ + SWI4_IRQn = 24, /*!< 24 SWI4 */ + SWI5_IRQn = 25 /*!< 25 SWI5 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ +#define __CM0_REV 0x0301U /*!< CM0 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ +#include "system_nrf51.h" /*!< nrf51 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks.) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group. */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group. */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel.) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Channel event end-point. */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Channel task end-point. */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power Control. (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency). */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning. */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED3[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason. */ + __IM uint32_t RESERVED4[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Ram status register. */ + __IM uint32_t RESERVED5[53]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System off register. */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure configuration. */ + __IM uint32_t RESERVED7[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register. This register + is a retained register. */ + __IM uint32_t RESERVED8; + __IOM uint32_t RAMON; /*!< (@ 0x00000524) Ram on/off. */ + __IM uint32_t RESERVED9[7]; + __IOM uint32_t RESET; /*!< (@ 0x00000544) Pin reset functionality configuration register. + This register is a retained register. */ + __IM uint32_t RESERVED10[3]; + __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Ram on/off. */ + __IM uint32_t RESERVED11[8]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DCDC converter enable configuration register. */ + __IM uint32_t RESERVED12[291]; + __IOM uint32_t DCDCFORCE; /*!< (@ 0x00000A08) DCDC power-up force register. */ +} NRF_POWER_Type; /*!< Size = 2572 (0xa0c) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control. (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK clock source. */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK clock source. */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK clock source. */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK clock source. */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFCLK RC oscillator. */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer. */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer. */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started. */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK oscillator started. */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator completed. */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout. */ + __IM uint32_t RESERVED2[124]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED3[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Task HFCLKSTART trigger status. */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) High frequency clock status. */ + __IM uint32_t RESERVED4; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Task LFCLKSTART triggered status. */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Low frequency clock status. */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Clock source for the LFCLK clock, set when task + LKCLKSTART is triggered. */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK clock. */ + __IM uint32_t RESERVED6[7]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval. */ + __IM uint32_t RESERVED7[5]; + __IOM uint32_t XTALFREQ; /*!< (@ 0x00000550) Crystal frequency. */ +} NRF_CLOCK_Type; /*!< Size = 1364 (0x554) */ + + + +/* =========================================================================================================================== */ +/* ================ MPU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Memory Protection Unit. (MPU) + */ + +typedef struct { /*!< (@ 0x40000000) MPU Structure */ + __IM uint32_t RESERVED[330]; + __IOM uint32_t PERR0; /*!< (@ 0x00000528) Configuration of peripherals in mpu regions. */ + __IOM uint32_t RLENR0; /*!< (@ 0x0000052C) Length of RAM region 0. */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t PROTENSET0; /*!< (@ 0x00000600) Erase and write protection bit enable set register. */ + __IOM uint32_t PROTENSET1; /*!< (@ 0x00000604) Erase and write protection bit enable set register. */ + __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable erase and write protection mechanism + in debug mode. */ + __IOM uint32_t PROTBLOCKSIZE; /*!< (@ 0x0000060C) Erase and write protection block size. */ +} NRF_MPU_Type; /*!< Size = 1552 (0x610) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief The radio. (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable radio in TX mode. */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable radio in RX mode. */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start radio. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop radio. */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable radio. */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sample of the receive + signal strength. */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement. */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter. */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter. */ + __IM uint32_t RESERVED[55]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) Ready event. */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address event. */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Payload event. */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) End event. */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) Disable event. */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet. */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet. */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of the receive signal strength complete. + A new RSSI sample is ready for readout at + the RSSISAMPLE register. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value specified + in BCC register. */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the radio. */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED4[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status of received packet. */ + __IM uint32_t RESERVED5; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address. */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) Received CRC. */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index. */ + __IM uint32_t RESERVED6[60]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer. Decision point: START task. */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency. */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power. */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation. */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration 0. */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration 1. */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Radio base address 0. Decision point: START task. */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Radio base address 1. Decision point: START task. */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0 to 3. */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4 to 7. */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select. */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select. */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration. */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial. */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value. */ + __IOM uint32_t TEST; /*!< (@ 0x00000540) Test features enable register. */ + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in microseconds. */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample. */ + __IM uint32_t RESERVED7; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state. */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value. */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare. */ + __IM uint32_t RESERVED9[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Device address base segment. */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Device address prefix. */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration. */ + __IM uint32_t RESERVED10[56]; + __IOM uint32_t OVERRIDE0; /*!< (@ 0x00000724) Trim value override register 0. */ + __IOM uint32_t OVERRIDE1; /*!< (@ 0x00000728) Trim value override register 1. */ + __IOM uint32_t OVERRIDE2; /*!< (@ 0x0000072C) Trim value override register 2. */ + __IOM uint32_t OVERRIDE3; /*!< (@ 0x00000730) Trim value override register 3. */ + __IOM uint32_t OVERRIDE4; /*!< (@ 0x00000734) Trim value override register 4. */ + __IM uint32_t RESERVED11[561]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter. (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver. */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver. */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter. */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter. */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART. */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS activated. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS deactivated. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD. */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD. */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected. */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout. */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for UART. */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source. Write error field to 1 to clear + error. */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART and acquire IOs. */ + __IM uint32_t RESERVED9; + __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS. */ + __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD. */ + __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS. */ + __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD. */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. On read action the buffer pointer + is displaced. Once read the character is + consumed. If read when no character available, + the UART will stop working. */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register. */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) UART Baudrate. */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control + register. */ + __IM uint32_t RESERVED12[675]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_UART_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI master 0. (SPI0) + */ + +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received. */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI. */ + __IM uint32_t RESERVED3; + __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ + __IOM uint32_t PSELMOSI; /*!< (@ 0x0000050C) Pin select for MOSI. */ + __IOM uint32_t PSELMISO; /*!< (@ 0x00000510) Pin select for MISO. */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RX data. */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data. */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ + __IM uint32_t RESERVED7[681]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_SPI_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Two-wire interface master 0. (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start 2-Wire master receive sequence. */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start 2-Wire master transmit sequence. */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop 2-Wire transaction. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend 2-Wire transaction. */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume 2-Wire transaction. */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Two-wire stopped. */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) Two-wire ready to deliver new RXD byte received. */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) Two-wire finished sending last TXD byte. */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Two-wire error detected. */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) Two-wire byte boundary. */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Two-wire suspended. */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for TWI. */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Two-wire error source. Write error field to 1 + to clear error. */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable two-wire master. */ + __IM uint32_t RESERVED12; + __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL. */ + __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA. */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RX data register. */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data register. */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) Two-wire frequency. */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the two-wire transfer. */ + __IM uint32_t RESERVED16[668]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_TWI_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI slave 1. (SPIS1) + */ + +typedef struct { /*!< (@ 0x40004000) SPIS1 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore. */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore. */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed. */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired. */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for SPIS. */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status. */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction. */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIS. */ + __IM uint32_t RESERVED9; + __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ + __IOM uint32_t PSELMISO; /*!< (@ 0x0000050C) Pin select for MISO. */ + __IOM uint32_t PSELMOSI; /*!< (@ 0x00000510) Pin select for MOSI. */ + __IOM uint32_t PSELCSN; /*!< (@ 0x00000514) Pin select for CSN. */ + __IM uint32_t RESERVED10[7]; + __IOM uint32_t RXDPTR; /*!< (@ 0x00000534) RX data pointer. */ + __IOM uint32_t MAXRX; /*!< (@ 0x00000538) Maximum number of bytes in the receive buffer. */ + __IM uint32_t AMOUNTRX; /*!< (@ 0x0000053C) Number of bytes received in last granted transaction. */ + __IM uint32_t RESERVED11; + __IOM uint32_t TXDPTR; /*!< (@ 0x00000544) TX data pointer. */ + __IOM uint32_t MAXTX; /*!< (@ 0x00000548) Maximum number of bytes in the transmit buffer. */ + __IM uint32_t AMOUNTTX; /*!< (@ 0x0000054C) Number of bytes transmitted in last granted transaction. */ + __IM uint32_t RESERVED12; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ + __IM uint32_t RESERVED13; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. */ + __IM uint32_t RESERVED14[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. */ + __IM uint32_t RESERVED15[654]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_SPIS_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO tasks and events. (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[4]; /*!< (@ 0x00000000) Tasks asssociated with GPIOTE channels. */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_IN[4]; /*!< (@ 0x00000100) Tasks asssociated with GPIOTE channels. */ + __IM uint32_t RESERVED1[27]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple pins. */ + __IM uint32_t RESERVED2[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED3[129]; + __IOM uint32_t CONFIG[4]; /*!< (@ 0x00000510) Channel configuration registers. */ + __IM uint32_t RESERVED4[695]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_GPIOTE_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog to digital converter. (ADC) + */ + +typedef struct { /*!< (@ 0x40007000) ADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start an ADC conversion. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop ADC. */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) ADC conversion complete. */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t BUSY; /*!< (@ 0x00000400) ADC busy register. */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) ADC enable. */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) ADC configuration register. */ + __IM uint32_t RESULT; /*!< (@ 0x00000508) Result of ADC conversion. */ + __IM uint32_t RESERVED4[700]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_ADC_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer 0. (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer. */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (In counter mode). */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear timer. */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Shutdown timer. */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Capture Timer value to CC[n] registers. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ + __IM uint32_t RESERVED2[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for Timer. */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer Mode selection. */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Sets timer behaviour. */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) 4-bit prescaler to source clock frequency (max + value 9). Source clock frequency is divided + by 2^SCALE. */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ + __IM uint32_t RESERVED7[683]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_TIMER_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0. (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC Counter. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC Counter. */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC Counter. */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFFFF0. */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment. */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow. */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Configures event enable routing to PPI for each + RTC event. */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable events routing to PPI. The reading of + this register gives the value of EVTEN. */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable events routing to PPI. The reading of + this register gives the value of EVTEN. */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value. */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is STOPed. */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ + __IM uint32_t RESERVED6[683]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_RTC_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor. (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement. */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready + event. */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Die temperature in degC, 2's complement format, + 0.25 degC pecision. */ + __IM uint32_t RESERVED3[700]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_TEMP_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator. (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the random number generator. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the random number generator. */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) New random number generated and written to VALUE + register. */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the RNG. */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) RNG random number. */ + __IM uint32_t RESERVED4[700]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_RNG_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption. (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt. If a crypto operation + is running, this will not initiate a new + encryption and the ERRORECB event will be + triggered. */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Stop current ECB encryption. If a crypto operation + is running, this will will trigger the ERRORECB + event. */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete. */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted due to a STOPECB task + or due to an error. */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointer. */ + __IM uint32_t RESERVED3[701]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_ECB_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver. (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure. */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses. */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure completed. */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved. */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved. */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status. */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR. */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of Identity root Keys in the IRK data + structure. */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to the IRK data structure. */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address (6 bytes). */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary + storage during resolution. A minimum of + 3 bytes must be reserved. */ + __IM uint32_t RESERVED6[697]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_AAR_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption. (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encrypt/decrypt. This operation will stop + by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encrypt/decrypt. */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation completed. */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt completed. */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Error happened. */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the CCM. */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) CCM RX MIC check result. */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) CCM enable. */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode. */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to a data structure holding AES key and + NONCE vector. */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Pointer to the input packet. */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Pointer to the output packet. */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary + storage during resolution. A minimum of + 43 bytes must be reserved. */ + __IM uint32_t RESERVED5[697]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_CCM_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer. (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout. */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Watchdog running status. */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status. */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value in number of 32kiHz clock + cycles. */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Reload request enable. */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register. */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Reload requests registers. */ + __IM uint32_t RESERVED5[631]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_WDT_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Rotary decoder. (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the quadrature decoder. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the quadrature decoder. */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Transfers the content from ACC registers to ACCREAD + registers, and clears the ACC registers. */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) A new sample is written to the sample register. */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) REPORTPER number of samples accumulated in ACC + register, and ACC register different than + zero. */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow. */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the QDEC. */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the QDEC. */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity. */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period. */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value. */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to generate an EVENT_REPORTRDY. */ + __IM int32_t ACC; /*!< (@ 0x00000514) Accumulated valid transitions register. */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of ACC register. Value generated by + the TASKS_READCLEACC task. */ + __IOM uint32_t PSELLED; /*!< (@ 0x0000051C) Pin select for LED output. */ + __IOM uint32_t PSELA; /*!< (@ 0x00000520) Pin select for phase A input. */ + __IOM uint32_t PSELB; /*!< (@ 0x00000524) Pin select for phase B input. */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable debouncer input filters. */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time LED is switched ON before the sample. */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Accumulated double (error) transitions register. */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of ACCDBL register. Value generated + by the TASKS_READCLEACC task. */ + __IM uint32_t RESERVED5[684]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_QDEC_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low power comparator. (LPCOMP) + */ + +typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the comparator. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the comparator. */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value. */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid. */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Input voltage crossed the threshold going down. */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Input voltage crossed the threshold going up. */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Input voltage crossed the threshold in any direction. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the LPCOMP. */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Result of last compare. */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the LPCOMP. */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select. */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select. */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select. */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration. */ + __IM uint32_t RESERVED6[694]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ +} NRF_LPCOMP_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SW Interrupts. (SWI) + */ + +typedef struct { /*!< (@ 0x40014000) SWI Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non Volatile Memory Controller. (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag. */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ + + union { + __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile + memory page. */ + __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile + memory page. */ + }; + __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory. */ + __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Register for erasing a protected non-volatile + memory page. */ + __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for start erasing User Information Congfiguration + Registers. */ +} NRF_NVMC_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PPI controller. (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __IOM PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< (@ 0x00000000) Channel group tasks. */ + __IM uint32_t RESERVED[312]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable. */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set. */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear. */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[16]; /*!< (@ 0x00000510) PPI Channel. */ + __IM uint32_t RESERVED2[156]; + __IOM uint32_t CHG[4]; /*!< (@ 0x00000800) Channel group configuration. */ +} NRF_PPI_Type; /*!< Size = 2064 (0x810) */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory Information Configuration. (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size in bytes. */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size in pages. */ + __IM uint32_t RESERVED1[4]; + __IM uint32_t CLENR0; /*!< (@ 0x00000028) Length of code region 0 in bytes. */ + __IM uint32_t PPFC; /*!< (@ 0x0000002C) Pre-programmed factory code present. */ + __IM uint32_t RESERVED2; + __IM uint32_t NUMRAMBLOCK; /*!< (@ 0x00000034) Number of individualy controllable RAM blocks. */ + + union { + __IM uint32_t SIZERAMBLOCKS; /*!< (@ 0x00000038) Size of RAM blocks in bytes. */ + __IM uint32_t SIZERAMBLOCK[4]; /*!< (@ 0x00000038) Deprecated array of size of RAM block in bytes. + This name is kept for backward compatinility + purposes. Use SIZERAMBLOCKS instead. */ + }; + __IM uint32_t RESERVED3[5]; + __IM uint32_t CONFIGID; /*!< (@ 0x0000005C) Configuration identifier. */ + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Device identifier. */ + __IM uint32_t RESERVED4[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Encryption root. */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Identity root. */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type. */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Device address. */ + __IM uint32_t OVERRIDEEN; /*!< (@ 0x000000AC) Radio calibration override enable. */ + __IM uint32_t NRF_1MBIT[5]; /*!< (@ 0x000000B0) Override values for the OVERRIDEn registers in + RADIO for NRF_1Mbit mode. */ + __IM uint32_t RESERVED5[10]; + __IM uint32_t BLE_1MBIT[5]; /*!< (@ 0x000000EC) Override values for the OVERRIDEn registers in + RADIO for BLE_1Mbit mode. */ +} NRF_FICR_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User Information Configuration. (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IOM uint32_t CLENR0; /*!< (@ 0x00000000) Length of code region 0. */ + __IOM uint32_t RBPCONF; /*!< (@ 0x00000004) Readback protection configuration. */ + __IOM uint32_t XTALFREQ; /*!< (@ 0x00000008) Reset value for CLOCK XTALFREQ register. */ + __IM uint32_t RESERVED; + __IM uint32_t FWID; /*!< (@ 0x00000010) Firmware ID. */ + + union { + __IOM uint32_t BOOTLOADERADDR; /*!< (@ 0x00000014) Bootloader start address. */ + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Reserved for Nordic firmware design. */ + }; + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Reserved for Nordic hardware design. */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Reserved for customer. */ +} NRF_UICR_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General purpose input and output. (GPIO) + */ + +typedef struct { /*!< (@ 0x50000000) GPIO Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port. */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port. */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port. */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port. */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins. */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register. */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register. */ + __IM uint32_t RESERVED1[120]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Configuration of GPIO pins. */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_MPU_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_ADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI_BASE 0x40014000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_GPIO_BASE 0x50000000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_MPU ((NRF_MPU_Type*) NRF_MPU_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_ADC ((NRF_ADC_Type*) NRF_ADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) +#define NRF_SWI ((NRF_SWI_Type*) NRF_SWI_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_GPIO ((NRF_GPIO_Type*) NRF_GPIO_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF51_H */ + + +/** @} */ /* End of group nrf51 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51422_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51422_peripherals.h new file mode 100755 index 0000000..6c9b692 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51422_peripherals.h @@ -0,0 +1,156 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +/* This file is deprecated */ +#ifndef _NRF51422_PERIPHERALS_H +#define _NRF51422_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAMON_REGISTERS_PRESENT + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 64 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 8 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 16 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 4 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 16 +#define TIMER2_MAX_SIZE 16 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Slave with DMA */ +#define SPIS_PRESENT +#define SPIS_COUNT 1 + +#define SPIS1_EASYDMA_MAXCNT_SIZE 8 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Analog to Digital Converter */ +#define ADC_PRESENT +#define ADC_COUNT 1 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 4 + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 8 + + +#endif // _NRF51422_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51801_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51801_peripherals.h new file mode 100755 index 0000000..7be6e53 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51801_peripherals.h @@ -0,0 +1,156 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +/* This file is deprecated */ +#ifndef _NRF51801_PERIPHERALS_H +#define _NRF51801_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAMON_REGISTERS_PRESENT + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 64 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 8 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 16 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 4 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 16 +#define TIMER2_MAX_SIZE 16 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Slave with DMA */ +#define SPIS_PRESENT +#define SPIS_COUNT 1 + +#define SPIS1_EASYDMA_MAXCNT_SIZE 8 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Analog to Digital Converter */ +#define ADC_PRESENT +#define ADC_COUNT 1 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 4 + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 8 + + +#endif // _NRF51801_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51802_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51802_peripherals.h new file mode 100755 index 0000000..182d31f --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51802_peripherals.h @@ -0,0 +1,156 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +/* This file is deprecated */ +#ifndef _NRF51802_PERIPHERALS_H +#define _NRF51802_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAMON_REGISTERS_PRESENT + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 64 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 8 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 16 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 4 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 16 +#define TIMER2_MAX_SIZE 16 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Slave with DMA */ +#define SPIS_PRESENT +#define SPIS_COUNT 1 + +#define SPIS1_EASYDMA_MAXCNT_SIZE 8 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Analog to Digital Converter */ +#define ADC_PRESENT +#define ADC_COUNT 1 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 4 + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 8 + + +#endif // _NRF51802_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51822_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51822_peripherals.h new file mode 100755 index 0000000..2762e17 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51822_peripherals.h @@ -0,0 +1,157 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + + +/* This file is deprecated */ +#ifndef _NRF51822_PERIPHERALS_H +#define _NRF51822_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAMON_REGISTERS_PRESENT + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 64 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 8 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 16 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 4 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 16 +#define TIMER2_MAX_SIZE 16 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Slave with DMA */ +#define SPIS_PRESENT +#define SPIS_COUNT 1 + +#define SPIS1_EASYDMA_MAXCNT_SIZE 8 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Analog to Digital Converter */ +#define ADC_PRESENT +#define ADC_COUNT 1 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 4 + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 8 + + +#endif // _NRF51822_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51824_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51824_peripherals.h new file mode 100755 index 0000000..5a29c8d --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51824_peripherals.h @@ -0,0 +1,157 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + + +/* This file is deprecated */ +#ifndef _NRF51824_PERIPHERALS_H +#define _NRF51824_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAMON_REGISTERS_PRESENT + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 64 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 8 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 16 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 4 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 16 +#define TIMER2_MAX_SIZE 16 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Slave with DMA */ +#define SPIS_PRESENT +#define SPIS_COUNT 1 + +#define SPIS1_EASYDMA_MAXCNT_SIZE 8 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Analog to Digital Converter */ +#define ADC_PRESENT +#define ADC_COUNT 1 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 4 + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 8 + + +#endif // _NRF51824_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_bitfields.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_bitfields.h new file mode 100755 index 0000000..7a98d12 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_bitfields.h @@ -0,0 +1,6131 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF51_BITS_H +#define __NRF51_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver. */ + +/* Register: AAR_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on NOTRESOLVED event. */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on RESOLVED event. */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on END event. */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: AAR_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on NOTRESOLVED event. */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on RESOLVED event. */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDKSGEN event. */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status. */ + +/* Bits 3..0 : The IRK used last time an address was resolved. */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR. */ + +/* Bits 1..0 : Enable AAR. */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ +#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ + +/* Register: AAR_NIRK */ +/* Description: Number of Identity root Keys in the IRK data structure. */ + +/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: ADC */ +/* Description: Analog to digital converter. */ + +/* Register: ADC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on END event. */ +#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: ADC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on END event. */ +#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: ADC_BUSY */ +/* Description: ADC busy register. */ + +/* Bit 0 : ADC busy register. */ +#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ +#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ +#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ +#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ + +/* Register: ADC_ENABLE */ +/* Description: ADC enable. */ + +/* Bits 1..0 : ADC enable. */ +#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ +#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ + +/* Register: ADC_CONFIG */ +/* Description: ADC configuration register. */ + +/* Bits 17..16 : ADC external reference pin selection. */ +#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ +#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ +#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ +#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ + +/* Bits 15..8 : ADC analog pin selection. */ +#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ +#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ +#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ + +/* Bits 6..5 : ADC reference selection. */ +#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ +#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ +#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ +#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ +#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ + +/* Bits 4..2 : ADC input selection. */ +#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ +#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ +#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ +#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ + +/* Bits 1..0 : ADC resolution. */ +#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ +#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ +#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ +#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ +#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ + +/* Register: ADC_RESULT */ +/* Description: Result of ADC conversion. */ + +/* Bits 9..0 : Result of ADC conversion. */ +#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ + +/* Register: ADC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption. */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcuts for the CCM. */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: CCM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on ERROR event. */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on ENDCRYPT event. */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on ENDKSGEN event. */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: CCM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on ERROR event. */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on ENDCRYPT event. */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDKSGEN event. */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: CCM_MICSTATUS */ +/* Description: CCM RX MIC check result. */ + +/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ + +/* Register: CCM_ENABLE */ +/* Description: CCM enable. */ + +/* Bits 1..0 : CCM enable. */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ +#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ + +/* Register: CCM_MODE */ +/* Description: Operation mode. */ + +/* Bit 0 : CCM mode operation. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ + +/* Register: CCM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control. */ + +/* Register: CLOCK_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 4 : Enable interrupt on CTTO event. */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on DONE event. */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 4 : Disable interrupt on CTTO event. */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on DONE event. */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Task HFCLKSTART trigger status. */ + +/* Bit 0 : Task HFCLKSTART trigger status. */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: High frequency clock status. */ + +/* Bit 16 : State for the HFCLK. */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ + +/* Bit 0 : Active clock source for the HF clock. */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Task LFCLKSTART triggered status. */ + +/* Bit 0 : Task LFCLKSTART triggered status. */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: Low frequency clock status. */ + +/* Bit 16 : State for the LF clock. */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ + +/* Bits 1..0 : Active clock source for the LF clock. */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ + +/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK clock. */ + +/* Bits 1..0 : Clock source. */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval. */ + +/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_XTALFREQ */ +/* Description: Crystal frequency. */ + +/* Bits 7..0 : External Xtal frequency selection. */ +#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ +#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ +#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ +#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption. */ + +/* Register: ECB_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 1 : Enable interrupt on ERRORECB event. */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on ENDECB event. */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: ECB_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 1 : Disable interrupt on ERRORECB event. */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on ENDECB event. */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: ECB_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration. */ + +/* Register: FICR_PPFC */ +/* Description: Pre-programmed factory code present. */ + +/* Bits 7..0 : Pre-programmed factory code present. */ +#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ +#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ +#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ +#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ + +/* Register: FICR_CONFIGID */ +/* Description: Configuration identifier. */ + +/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ +#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ +#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ + +/* Bits 15..0 : Hardware Identification Number. */ +#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ +#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type. */ + +/* Bit 0 : Device address type. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ + +/* Register: FICR_OVERRIDEEN */ +/* Description: Radio calibration override enable. */ + +/* Bit 3 : Override default values for BLE_1Mbit mode. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ +#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ + +/* Bit 0 : Override default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ +#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ + + +/* Peripheral: GPIO */ +/* Description: General purpose input and output. */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins. */ + +/* Bit 31 : Pin 31. */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ + +/* Bit 30 : Pin 30. */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ + +/* Bit 29 : Pin 29. */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ + +/* Bit 28 : Pin 28. */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ + +/* Bit 27 : Pin 27. */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ + +/* Bit 26 : Pin 26. */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ + +/* Bit 25 : Pin 25. */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ + +/* Bit 24 : Pin 24. */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ + +/* Bit 23 : Pin 23. */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ + +/* Bit 22 : Pin 22. */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ + +/* Bit 21 : Pin 21. */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ + +/* Bit 20 : Pin 20. */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ + +/* Bit 19 : Pin 19. */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ + +/* Bit 18 : Pin 18. */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ + +/* Bit 17 : Pin 17. */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ + +/* Bit 16 : Pin 16. */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ + +/* Bit 15 : Pin 15. */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ + +/* Bit 14 : Pin 14. */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ + +/* Bit 13 : Pin 13. */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ + +/* Bit 12 : Pin 12. */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ + +/* Bit 11 : Pin 11. */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ + +/* Bit 10 : Pin 10. */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ + +/* Bit 9 : Pin 9. */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ + +/* Bit 8 : Pin 8. */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ + +/* Bit 7 : Pin 7. */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ + +/* Bit 6 : Pin 6. */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ + +/* Bit 5 : Pin 5. */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ + +/* Bit 4 : Pin 4. */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ + +/* Bit 3 : Pin 3. */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ + +/* Bit 2 : Pin 2. */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ + +/* Bit 1 : Pin 1. */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ + +/* Bit 0 : Pin 0. */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register. */ + +/* Bit 31 : Set as output pin 31. */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ + +/* Bit 30 : Set as output pin 30. */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ + +/* Bit 29 : Set as output pin 29. */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ + +/* Bit 28 : Set as output pin 28. */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ + +/* Bit 27 : Set as output pin 27. */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ + +/* Bit 26 : Set as output pin 26. */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ + +/* Bit 25 : Set as output pin 25. */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ + +/* Bit 24 : Set as output pin 24. */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ + +/* Bit 23 : Set as output pin 23. */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ + +/* Bit 22 : Set as output pin 22. */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ + +/* Bit 21 : Set as output pin 21. */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ + +/* Bit 20 : Set as output pin 20. */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ + +/* Bit 19 : Set as output pin 19. */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ + +/* Bit 18 : Set as output pin 18. */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ + +/* Bit 17 : Set as output pin 17. */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ + +/* Bit 16 : Set as output pin 16. */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ + +/* Bit 15 : Set as output pin 15. */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ + +/* Bit 14 : Set as output pin 14. */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ + +/* Bit 13 : Set as output pin 13. */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ + +/* Bit 12 : Set as output pin 12. */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ + +/* Bit 11 : Set as output pin 11. */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ + +/* Bit 10 : Set as output pin 10. */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ + +/* Bit 9 : Set as output pin 9. */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ + +/* Bit 8 : Set as output pin 8. */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ + +/* Bit 7 : Set as output pin 7. */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ + +/* Bit 6 : Set as output pin 6. */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ + +/* Bit 5 : Set as output pin 5. */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ + +/* Bit 4 : Set as output pin 4. */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ + +/* Bit 3 : Set as output pin 3. */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ + +/* Bit 2 : Set as output pin 2. */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ + +/* Bit 1 : Set as output pin 1. */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ + +/* Bit 0 : Set as output pin 0. */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register. */ + +/* Bit 31 : Set as input pin 31. */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 30 : Set as input pin 30. */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 29 : Set as input pin 29. */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 28 : Set as input pin 28. */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 27 : Set as input pin 27. */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 26 : Set as input pin 26. */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 25 : Set as input pin 25. */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 24 : Set as input pin 24. */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 23 : Set as input pin 23. */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 22 : Set as input pin 22. */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 21 : Set as input pin 21. */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 20 : Set as input pin 20. */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 19 : Set as input pin 19. */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 18 : Set as input pin 18. */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 17 : Set as input pin 17. */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 16 : Set as input pin 16. */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 15 : Set as input pin 15. */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 14 : Set as input pin 14. */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 13 : Set as input pin 13. */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 12 : Set as input pin 12. */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 11 : Set as input pin 11. */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 10 : Set as input pin 10. */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 9 : Set as input pin 9. */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 8 : Set as input pin 8. */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 7 : Set as input pin 7. */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 6 : Set as input pin 6. */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 5 : Set as input pin 5. */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 4 : Set as input pin 4. */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 3 : Set as input pin 3. */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 2 : Set as input pin 2. */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 1 : Set as input pin 1. */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ + +/* Bit 0 : Set as input pin 0. */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Configuration of GPIO pins. */ + +/* Bits 17..16 : Pin sensing mechanism. */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ +#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ +#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ + +/* Bits 10..8 : Drive configuration. */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ + +/* Bits 3..2 : Pull-up or -down configuration. */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ +#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ +#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ + +/* Bit 1 : Connect or disconnect input path. */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ + +/* Bit 0 : Pin direction. */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO tasks and events. */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 31 : Enable interrupt on PORT event. */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on IN[3] event. */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on IN[2] event. */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on IN[1] event. */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on IN[0] event. */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 31 : Disable interrupt on PORT event. */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on IN[3] event. */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on IN[2] event. */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on IN[1] event. */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on IN[0] event. */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Channel configuration registers. */ + +/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ + +/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ + +/* Bits 12..8 : Pin select. */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ +#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ +#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ + +/* Register: GPIOTE_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low power comparator. */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcuts for the LPCOMP. */ + +/* Bit 4 : Shortcut between CROSS event and STOP task. */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between UP event and STOP task. */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between DOWN event and STOP task. */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between RADY event and STOP task. */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 3 : Enable interrupt on CROSS event. */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on UP event. */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on DOWN event. */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on READY event. */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 3 : Disable interrupt on CROSS event. */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on UP event. */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on DOWN event. */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on READY event. */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: LPCOMP_RESULT */ +/* Description: Result of last compare. */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is bellow the reference threshold. */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable the LPCOMP. */ + +/* Bits 1..0 : Enable or disable LPCOMP. */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ +#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select. */ + +/* Bits 2..0 : Analog input pin select. */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select. */ + +/* Bits 2..0 : Reference select. */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select. */ + +/* Bit 0 : External analog reference pin selection. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration. */ + +/* Bits 1..0 : Analog detect configuration. */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ + +/* Register: LPCOMP_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: MPU */ +/* Description: Memory Protection Unit. */ + +/* Register: MPU_PERR0 */ +/* Description: Configuration of peripherals in mpu regions. */ + +/* Bit 31 : PPI region configuration. */ +#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ +#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ +#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 30 : NVMC region configuration. */ +#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ +#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ +#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 19 : LPCOMP region configuration. */ +#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 18 : QDEC region configuration. */ +#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ +#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ +#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 17 : RTC1 region configuration. */ +#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ +#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ +#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 16 : WDT region configuration. */ +#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ +#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ +#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 15 : CCM and AAR region configuration. */ +#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ +#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ +#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 14 : ECB region configuration. */ +#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ +#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ +#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 13 : RNG region configuration. */ +#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ +#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ +#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 12 : TEMP region configuration. */ +#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ +#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ +#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 11 : RTC0 region configuration. */ +#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ +#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ +#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 10 : TIMER2 region configuration. */ +#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ +#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ +#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 9 : TIMER1 region configuration. */ +#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ +#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ +#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 8 : TIMER0 region configuration. */ +#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ +#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ +#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 7 : ADC region configuration. */ +#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ +#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ +#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 6 : GPIOTE region configuration. */ +#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ +#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ +#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 4 : SPI1 and TWI1 region configuration. */ +#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ +#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ +#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 3 : SPI0 and TWI0 region configuration. */ +#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ +#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ +#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 2 : UART0 region configuration. */ +#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ +#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ +#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 1 : RADIO region configuration. */ +#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ +#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ +#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Bit 0 : POWER_CLOCK region configuration. */ +#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ +#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ +#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ +#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ + +/* Register: MPU_PROTENSET0 */ +/* Description: Erase and write protection bit enable set register. */ + +/* Bit 31 : Protection enable for region 31. */ +#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ +#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ +#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 30 : Protection enable for region 30. */ +#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ +#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ +#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 29 : Protection enable for region 29. */ +#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ +#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ +#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 28 : Protection enable for region 28. */ +#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ +#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ +#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 27 : Protection enable for region 27. */ +#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ +#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ +#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 26 : Protection enable for region 26. */ +#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ +#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ +#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 25 : Protection enable for region 25. */ +#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ +#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ +#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 24 : Protection enable for region 24. */ +#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ +#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ +#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 23 : Protection enable for region 23. */ +#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ +#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ +#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 22 : Protection enable for region 22. */ +#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ +#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ +#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 21 : Protection enable for region 21. */ +#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ +#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ +#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 20 : Protection enable for region 20. */ +#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ +#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ +#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 19 : Protection enable for region 19. */ +#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ +#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ +#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 18 : Protection enable for region 18. */ +#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ +#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ +#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 17 : Protection enable for region 17. */ +#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ +#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ +#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 16 : Protection enable for region 16. */ +#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ +#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ +#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 15 : Protection enable for region 15. */ +#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ +#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ +#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 14 : Protection enable for region 14. */ +#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ +#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ +#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 13 : Protection enable for region 13. */ +#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ +#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ +#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 12 : Protection enable for region 12. */ +#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ +#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ +#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 11 : Protection enable for region 11. */ +#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ +#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ +#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 10 : Protection enable for region 10. */ +#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ +#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ +#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 9 : Protection enable for region 9. */ +#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ +#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ +#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 8 : Protection enable for region 8. */ +#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ +#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ +#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 7 : Protection enable for region 7. */ +#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ +#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ +#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 6 : Protection enable for region 6. */ +#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ +#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ +#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 5 : Protection enable for region 5. */ +#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ +#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ +#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 4 : Protection enable for region 4. */ +#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ +#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ +#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 3 : Protection enable for region 3. */ +#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ +#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ +#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 2 : Protection enable for region 2. */ +#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ +#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ +#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 1 : Protection enable for region 1. */ +#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ +#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ +#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 0 : Protection enable for region 0. */ +#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ +#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ +#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ + +/* Register: MPU_PROTENSET1 */ +/* Description: Erase and write protection bit enable set register. */ + +/* Bit 31 : Protection enable for region 63. */ +#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ +#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ +#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 30 : Protection enable for region 62. */ +#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ +#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ +#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 29 : Protection enable for region 61. */ +#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ +#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ +#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 28 : Protection enable for region 60. */ +#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ +#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ +#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 27 : Protection enable for region 59. */ +#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ +#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ +#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 26 : Protection enable for region 58. */ +#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ +#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ +#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 25 : Protection enable for region 57. */ +#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ +#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ +#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 24 : Protection enable for region 56. */ +#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ +#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ +#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 23 : Protection enable for region 55. */ +#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ +#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ +#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 22 : Protection enable for region 54. */ +#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ +#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ +#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 21 : Protection enable for region 53. */ +#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ +#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ +#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 20 : Protection enable for region 52. */ +#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ +#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ +#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 19 : Protection enable for region 51. */ +#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ +#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ +#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 18 : Protection enable for region 50. */ +#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ +#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ +#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 17 : Protection enable for region 49. */ +#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ +#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ +#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 16 : Protection enable for region 48. */ +#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ +#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ +#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 15 : Protection enable for region 47. */ +#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ +#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ +#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 14 : Protection enable for region 46. */ +#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ +#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ +#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 13 : Protection enable for region 45. */ +#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ +#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ +#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 12 : Protection enable for region 44. */ +#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ +#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ +#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 11 : Protection enable for region 43. */ +#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ +#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ +#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 10 : Protection enable for region 42. */ +#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ +#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ +#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 9 : Protection enable for region 41. */ +#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ +#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ +#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 8 : Protection enable for region 40. */ +#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ +#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ +#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 7 : Protection enable for region 39. */ +#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ +#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ +#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 6 : Protection enable for region 38. */ +#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ +#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ +#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 5 : Protection enable for region 37. */ +#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ +#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ +#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 4 : Protection enable for region 36. */ +#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ +#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ +#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 3 : Protection enable for region 35. */ +#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ +#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ +#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 2 : Protection enable for region 34. */ +#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ +#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ +#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 1 : Protection enable for region 33. */ +#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ +#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ +#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ + +/* Bit 0 : Protection enable for region 32. */ +#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ +#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ +#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ +#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ +#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ + +/* Register: MPU_DISABLEINDEBUG */ +/* Description: Disable erase and write protection mechanism in debug mode. */ + +/* Bit 0 : Disable protection mechanism in debug mode. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ + +/* Register: MPU_PROTBLOCKSIZE */ +/* Description: Erase and write protection block size. */ + +/* Bits 1..0 : Erase and write protection block size. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ +#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller. */ + +/* Register: NVMC_READY */ +/* Description: Ready flag. */ + +/* Bit 0 : NVMC ready. */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register. */ + +/* Bits 1..0 : Program write enable. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ +#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ +#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory. */ + +/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for start erasing User Information Congfiguration Registers. */ + +/* Bit 0 : It can only be used when all contents of code region 1 are erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ + + +/* Peripheral: POWER */ +/* Description: Power Control. */ + +/* Register: POWER_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on POFWARN event. */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: POWER_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on POFWARN event. */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason. */ + +/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */ + +/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */ + +/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */ + +/* Bit 3 : Reset from CPU lock-up detected. */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */ + +/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */ + +/* Bit 1 : Reset from watchdog detected. */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */ + +/* Bit 0 : Reset from pin-reset detected. */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Ram status register. */ + +/* Bit 3 : RAM block 3 status. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ + +/* Bit 2 : RAM block 2 status. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ + +/* Bit 1 : RAM block 1 status. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ + +/* Bit 0 : RAM block 0 status. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System off register. */ + +/* Bit 0 : Enter system off mode. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ + +/* Register: POWER_POFCON */ +/* Description: Power failure configuration. */ + +/* Bits 2..1 : Set threshold level. */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ +#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ +#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ +#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ + +/* Bit 0 : Power failure comparator enable. */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register. This register is a retained register. */ + +/* Bits 7..0 : General purpose retention register. */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_RAMON */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 1 behaviour in OFF mode. */ +#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ +#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ + +/* Bit 16 : RAM block 0 behaviour in OFF mode. */ +#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ +#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ + +/* Bit 1 : RAM block 1 behaviour in ON mode. */ +#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ +#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ + +/* Bit 0 : RAM block 0 behaviour in ON mode. */ +#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ +#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ + +/* Register: POWER_RESET */ +/* Description: Pin reset functionality configuration register. This register is a retained register. */ + +/* Bit 0 : Enable or disable pin reset in debug interface mode. */ +#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ +#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ +#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ +#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ + +/* Register: POWER_RAMONB */ +/* Description: Ram on/off. */ + +/* Bit 17 : RAM block 3 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ + +/* Bit 16 : RAM block 2 behaviour in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ + +/* Bit 1 : RAM block 3 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ + +/* Bit 0 : RAM block 2 behaviour in ON mode. */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ + +/* Register: POWER_DCDCEN */ +/* Description: DCDC converter enable configuration register. */ + +/* Bit 0 : Enable DCDC converter. */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ + +/* Register: POWER_DCDCFORCE */ +/* Description: DCDC power-up force register. */ + +/* Bit 1 : DCDC power-up force on. */ +#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ +#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ + +/* Bit 0 : DCDC power-up force off. */ +#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ +#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ +#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ + + +/* Peripheral: PPI */ +/* Description: PPI controller. */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable. */ + +/* Bit 31 : Enable PPI channel 31. */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 30 : Enable PPI channel 30. */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 29 : Enable PPI channel 29. */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 28 : Enable PPI channel 28. */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 27 : Enable PPI channel 27. */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 26 : Enable PPI channel 26. */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 25 : Enable PPI channel 25. */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 24 : Enable PPI channel 24. */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 23 : Enable PPI channel 23. */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 22 : Enable PPI channel 22. */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 21 : Enable PPI channel 21. */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 20 : Enable PPI channel 20. */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 15 : Enable PPI channel 15. */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 14 : Enable PPI channel 14. */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 13 : Enable PPI channel 13. */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 12 : Enable PPI channel 12. */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 11 : Enable PPI channel 11. */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 10 : Enable PPI channel 10. */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 9 : Enable PPI channel 9. */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 8 : Enable PPI channel 8. */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 7 : Enable PPI channel 7. */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 6 : Enable PPI channel 6. */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 5 : Enable PPI channel 5. */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 4 : Enable PPI channel 4. */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 3 : Enable PPI channel 3. */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ + +/* Bit 2 : Enable PPI channel 2. */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 1 : Enable PPI channel 1. */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ + +/* Bit 0 : Enable PPI channel 0. */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set. */ + +/* Bit 31 : Enable PPI channel 31. */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 30 : Enable PPI channel 30. */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 29 : Enable PPI channel 29. */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 28 : Enable PPI channel 28. */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 27 : Enable PPI channel 27. */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 26 : Enable PPI channel 26. */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 25 : Enable PPI channel 25. */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 24 : Enable PPI channel 24. */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 23 : Enable PPI channel 23. */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 22 : Enable PPI channel 22. */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 21 : Enable PPI channel 21. */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 20 : Enable PPI channel 20. */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 15 : Enable PPI channel 15. */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 14 : Enable PPI channel 14. */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 13 : Enable PPI channel 13. */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 12 : Enable PPI channel 12. */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 11 : Enable PPI channel 11. */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 10 : Enable PPI channel 10. */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 9 : Enable PPI channel 9. */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 8 : Enable PPI channel 8. */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 7 : Enable PPI channel 7. */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 6 : Enable PPI channel 6. */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 5 : Enable PPI channel 5. */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 4 : Enable PPI channel 4. */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 3 : Enable PPI channel 3. */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 2 : Enable PPI channel 2. */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 1 : Enable PPI channel 1. */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ + +/* Bit 0 : Enable PPI channel 0. */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear. */ + +/* Bit 31 : Disable PPI channel 31. */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 30 : Disable PPI channel 30. */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 29 : Disable PPI channel 29. */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 28 : Disable PPI channel 28. */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 27 : Disable PPI channel 27. */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 26 : Disable PPI channel 26. */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 25 : Disable PPI channel 25. */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 24 : Disable PPI channel 24. */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 23 : Disable PPI channel 23. */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 22 : Disable PPI channel 22. */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 21 : Disable PPI channel 21. */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 20 : Disable PPI channel 20. */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 15 : Disable PPI channel 15. */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 14 : Disable PPI channel 14. */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 13 : Disable PPI channel 13. */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 12 : Disable PPI channel 12. */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 11 : Disable PPI channel 11. */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 10 : Disable PPI channel 10. */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 9 : Disable PPI channel 9. */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 8 : Disable PPI channel 8. */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 7 : Disable PPI channel 7. */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 6 : Disable PPI channel 6. */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 5 : Disable PPI channel 5. */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 4 : Disable PPI channel 4. */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 3 : Disable PPI channel 3. */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 2 : Disable PPI channel 2. */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 1 : Disable PPI channel 1. */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ + +/* Bit 0 : Disable PPI channel 0. */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ + +/* Register: PPI_CHG */ +/* Description: Channel group configuration. */ + +/* Bit 31 : Include CH31 in channel group. */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ + +/* Bit 30 : Include CH30 in channel group. */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ + +/* Bit 29 : Include CH29 in channel group. */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ + +/* Bit 28 : Include CH28 in channel group. */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ + +/* Bit 27 : Include CH27 in channel group. */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ + +/* Bit 26 : Include CH26 in channel group. */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ + +/* Bit 25 : Include CH25 in channel group. */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ + +/* Bit 24 : Include CH24 in channel group. */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ + +/* Bit 23 : Include CH23 in channel group. */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ + +/* Bit 22 : Include CH22 in channel group. */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ + +/* Bit 21 : Include CH21 in channel group. */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ + +/* Bit 20 : Include CH20 in channel group. */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ + +/* Bit 15 : Include CH15 in channel group. */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ + +/* Bit 14 : Include CH14 in channel group. */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ + +/* Bit 13 : Include CH13 in channel group. */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ + +/* Bit 12 : Include CH12 in channel group. */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ + +/* Bit 11 : Include CH11 in channel group. */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ + +/* Bit 10 : Include CH10 in channel group. */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ + +/* Bit 9 : Include CH9 in channel group. */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ + +/* Bit 8 : Include CH8 in channel group. */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ + +/* Bit 7 : Include CH7 in channel group. */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ + +/* Bit 6 : Include CH6 in channel group. */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ + +/* Bit 5 : Include CH5 in channel group. */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ + +/* Bit 4 : Include CH4 in channel group. */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ + +/* Bit 3 : Include CH3 in channel group. */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ + +/* Bit 2 : Include CH2 in channel group. */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ + +/* Bit 1 : Include CH1 in channel group. */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ + +/* Bit 0 : Include CH0 in channel group. */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ +#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ + + +/* Peripheral: QDEC */ +/* Description: Rotary decoder. */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcuts for the QDEC. */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: QDEC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on ACCOF event. */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on REPORTRDY event. */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on SAMPLERDY event. */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: QDEC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on ACCOF event. */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on REPORTRDY event. */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on SAMPLERDY event. */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the QDEC. */ + +/* Bit 0 : Enable or disable QDEC. */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity. */ + +/* Bit 0 : LED output pin polarity. */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period. */ + +/* Bits 2..0 : Sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value. */ + +/* Bits 31..0 : Last sample taken in compliment to 2. */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to generate an EVENT_REPORTRDY. */ + +/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable debouncer input filters. */ + +/* Bit 0 : Enable debounce input filters. */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time LED is switched ON before the sample. */ + +/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Accumulated double (error) transitions register. */ + +/* Bits 3..0 : Accumulated double (error) transitions. */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ + +/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + +/* Register: QDEC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RADIO */ +/* Description: The radio. */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcuts for the radio. */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 5 : Shortcut between END event and START task. */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task. */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task. */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between END event and DISABLE task. */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between READY event and START task. */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: RADIO_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 10 : Enable interrupt on BCMATCH event. */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on RSSIEND event. */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 6 : Enable interrupt on DEVMISS event. */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 5 : Enable interrupt on DEVMATCH event. */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on DISABLED event. */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 3 : Enable interrupt on END event. */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on PAYLOAD event. */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on ADDRESS event. */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on READY event. */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RADIO_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 10 : Disable interrupt on BCMATCH event. */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on RSSIEND event. */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 6 : Disable interrupt on DEVMISS event. */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 5 : Disable interrupt on DEVMATCH event. */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on DISABLED event. */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 3 : Disable interrupt on END event. */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on PAYLOAD event. */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on ADDRESS event. */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on READY event. */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status of received packet. */ + +/* Bit 0 : CRC status of received packet. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address. */ + +/* Bits 2..0 : Logical address in which previous packet was received. */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: Received CRC. */ + +/* Bits 23..0 : CRC field of previously received packet. */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index. */ + +/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency. */ + +/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power. */ + +/* Bits 7..0 : Radio output power. Decision point: TXEN task. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation. */ + +/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ +#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration 0. */ + +/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration 1. */ + +/* Bit 25 : Packet whitening enable. */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ + +/* Bit 24 : On air endianness of packet length field. Decision point: START task. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload in number of bytes. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0 to 3. */ + +/* Bits 31..24 : Address prefix 3. Decision point: START task. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. Decision point: START task. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. Decision point: START task. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. Decision point: START task. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4 to 7. */ + +/* Bits 31..24 : Address prefix 7. Decision point: START task. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. Decision point: START task. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. Decision point: START task. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. Decision point: START task. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select. */ + +/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select. */ + +/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ + +/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration. */ + +/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ + +/* Bits 1..0 : CRC length. Decision point: START task. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial. */ + +/* Bits 23..0 : CRC polynomial. Decision point: START task. */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value. */ + +/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TEST */ +/* Description: Test features enable register. */ + +/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ +#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ +#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ +#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ + +/* Bit 0 : Constant carrier. Decision point: TXEN task. */ +#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ +#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ +#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in microseconds. */ + +/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample. */ + +/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state. */ + +/* Bits 3..0 : Current radio state. */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ +#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ +#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ +#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ +#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ +#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ +#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ +#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ +#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value. */ + +/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_DAP */ +/* Description: Device address prefix. */ + +/* Bits 15..0 : Device address prefix. */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration. */ + +/* Bit 15 : TxAdd for device address 7. */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6. */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5. */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4. */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3. */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2. */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1. */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0. */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7. */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ + +/* Bit 6 : Enable or disable device address matching using device address 6. */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ + +/* Bit 5 : Enable or disable device address matching using device address 5. */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ + +/* Bit 4 : Enable or disable device address matching using device address 4. */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ + +/* Bit 3 : Enable or disable device address matching using device address 3. */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ + +/* Bit 2 : Enable or disable device address matching using device address 2. */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ + +/* Bit 1 : Enable or disable device address matching using device address 1. */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ + +/* Bit 0 : Enable or disable device address matching using device address 0. */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ + +/* Register: RADIO_OVERRIDE0 */ +/* Description: Trim value override register 0. */ + +/* Bits 31..0 : Trim value override 0. */ +#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ +#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ + +/* Register: RADIO_OVERRIDE1 */ +/* Description: Trim value override register 1. */ + +/* Bits 31..0 : Trim value override 1. */ +#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ +#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ + +/* Register: RADIO_OVERRIDE2 */ +/* Description: Trim value override register 2. */ + +/* Bits 31..0 : Trim value override 2. */ +#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ +#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ + +/* Register: RADIO_OVERRIDE3 */ +/* Description: Trim value override register 3. */ + +/* Bits 31..0 : Trim value override 3. */ +#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ +#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ + +/* Register: RADIO_OVERRIDE4 */ +/* Description: Trim value override register 4. */ + +/* Bit 31 : Enable or disable override of default trim values. */ +#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ +#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ +#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ + +/* Bits 27..0 : Trim value override 4. */ +#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ +#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator. */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcuts for the RNG. */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task. */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: RNG_INTENSET */ +/* Description: Interrupt enable set register */ + +/* Bit 0 : Enable interrupt on VALRDY event. */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RNG_INTENCLR */ +/* Description: Interrupt enable clear register */ + +/* Bit 0 : Disable interrupt on VALRDY event. */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 0 : Digital error correction enable. */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ + +/* Register: RNG_VALUE */ +/* Description: RNG random number. */ + +/* Bits 7..0 : Generated random number. */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + +/* Register: RNG_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0. */ + +/* Register: RTC_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on COMPARE[3] event. */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 18 : Enable interrupt on COMPARE[2] event. */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 17 : Enable interrupt on COMPARE[1] event. */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 16 : Enable interrupt on COMPARE[0] event. */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on OVRFLW event. */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on TICK event. */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: RTC_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on COMPARE[3] event. */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 18 : Disable interrupt on COMPARE[2] event. */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 17 : Disable interrupt on COMPARE[1] event. */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 16 : Disable interrupt on COMPARE[0] event. */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on OVRFLW event. */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on TICK event. */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: RTC_EVTEN */ +/* Description: Configures event enable routing to PPI for each RTC event. */ + +/* Bit 19 : COMPARE[3] event enable. */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 18 : COMPARE[2] event enable. */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 17 : COMPARE[1] event enable. */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 16 : COMPARE[0] event enable. */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 1 : OVRFLW event enable. */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ + +/* Bit 0 : TICK event enable. */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ + +/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ + +/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ + +/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ + +/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ + +/* Bit 1 : Enable routing to PPI of OVRFLW event. */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ + +/* Bit 0 : Enable routing to PPI of TICK event. */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ + +/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 1 : Disable routing to PPI of OVRFLW event. */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ + +/* Bit 0 : Disable routing to PPI of TICK event. */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value. */ + +/* Bits 23..0 : Counter value. */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ + +/* Bits 11..0 : RTC PRESCALER value. */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Capture/compare registers. */ + +/* Bits 23..0 : Compare value. */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + +/* Register: RTC_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: SPI */ +/* Description: SPI master 0. */ + +/* Register: SPI_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 2 : Enable interrupt on READY event. */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPI_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 2 : Disable interrupt on READY event. */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI. */ + +/* Bits 2..0 : Enable or disable SPI. */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ +#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ + +/* Register: SPI_RXD */ +/* Description: RX data. */ + +/* Bits 7..0 : RX data from last transfer. */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TX data. */ + +/* Bits 7..0 : TX data for next transfer. */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI data rate. */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPI_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: SPIS */ +/* Description: SPI slave 1. */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcuts for SPIS. */ + +/* Bit 2 : Shortcut between END event and the ACQUIRE task. */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: SPIS_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 10 : Enable interrupt on ACQUIRED event. */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : enable interrupt on ENDRX event. */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on END event. */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIS_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 10 : Disable interrupt on ACQUIRED event. */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on ENDRX event. */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on END event. */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status. */ + +/* Bits 1..0 : Semaphore status. */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction. */ + +/* Bit 1 : RX buffer overflow detected, and prevented. */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ + +/* Bit 0 : TX buffer overread detected, and prevented. */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPIS. */ + +/* Bits 2..0 : Enable or disable SPIS. */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ +#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ + +/* Register: SPIS_MAXRX */ +/* Description: Maximum number of bytes in the receive buffer. */ + +/* Bits 7..0 : Maximum number of bytes in the receive buffer. */ +#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ +#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ + +/* Register: SPIS_AMOUNTRX */ +/* Description: Number of bytes received in last granted transaction. */ + +/* Bits 7..0 : Number of bytes received in last granted transaction. */ +#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ +#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ + +/* Register: SPIS_MAXTX */ +/* Description: Maximum number of bytes in the transmit buffer. */ + +/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ +#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ +#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ + +/* Register: SPIS_AMOUNTTX */ +/* Description: Number of bytes transmitted in last granted transaction. */ + +/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ +#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ +#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIS_DEF */ +/* Description: Default character. */ + +/* Bits 7..0 : Default character. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIS_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor. */ + +/* Register: TEMP_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on DATARDY event. */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TEMP_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on DATARDY event. */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TEMP_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TIMER */ +/* Description: Timer 0. */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcuts for Timer. */ + +/* Bit 11 : Shortcut between CC[3] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 10 : Shortcut between CC[2] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 9 : Shortcut between CC[1] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 8 : Shortcut between CC[0] event and the STOP task. */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: TIMER_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on COMPARE[3] */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 18 : Enable interrupt on COMPARE[2] */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 17 : Enable interrupt on COMPARE[1] */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 16 : Enable interrupt on COMPARE[0] */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TIMER_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on COMPARE[3] */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 18 : Disable interrupt on COMPARE[2] */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 17 : Disable interrupt on COMPARE[1] */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 16 : Disable interrupt on COMPARE[0] */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TIMER_MODE */ +/* Description: Timer Mode selection. */ + +/* Bit 0 : Select Normal or Counter mode. */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ + +/* Register: TIMER_BITMODE */ +/* Description: Sets timer behaviour. */ + +/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ +#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ + +/* Register: TIMER_PRESCALER */ +/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ + +/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: TWI */ +/* Description: Two-wire interface master 0. */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcuts for TWI. */ + +/* Bit 1 : Shortcut between BB event and the STOP task. */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 0 : Shortcut between BB event and the SUSPEND task. */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: TWI_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 18 : Enable interrupt on SUSPENDED event. */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 14 : Enable interrupt on BB event. */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 9 : Enable interrupt on ERROR event. */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on TXDSENT event. */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on READY event. */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: TWI_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 18 : Disable interrupt on SUSPENDED event. */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 14 : Disable interrupt on BB event. */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 9 : Disable interrupt on ERROR event. */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on TXDSENT event. */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on RXDREADY event. */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: TWI_ERRORSRC */ +/* Description: Two-wire error source. Write error field to 1 to clear error. */ + +/* Bit 2 : NACK received after sending a data byte. */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 1 : NACK received after sending the address. */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ + +/* Register: TWI_ENABLE */ +/* Description: Enable two-wire master. */ + +/* Bits 2..0 : Enable or disable W2M */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ +#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ + +/* Register: TWI_RXD */ +/* Description: RX data register. */ + +/* Bits 7..0 : RX data from last transfer. */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TX data register. */ + +/* Bits 7..0 : TX data for next transfer. */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: Two-wire frequency. */ + +/* Bits 31..0 : Two-wire master clock frequency. */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps). */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the two-wire transfer. */ + +/* Bits 6..0 : Two-wire address. */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWI_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter. */ + +/* Register: UART_SHORTS */ +/* Description: Shortcuts for UART. */ + +/* Bit 4 : Shortcut between NCTS event and STOPRX task. */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Bit 3 : Shortcut between CTS event and STARTRX task. */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ + +/* Register: UART_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 17 : Enable interrupt on RXTO event. */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 9 : Enable interrupt on ERROR event. */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 7 : Enable interrupt on TXRDY event. */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 2 : Enable interrupt on RXRDY event. */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on NCTS event. */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 0 : Enable interrupt on CTS event. */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: UART_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 17 : Disable interrupt on RXTO event. */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 9 : Disable interrupt on ERROR event. */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 7 : Disable interrupt on TXRDY event. */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 2 : Disable interrupt on RXRDY event. */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on NCTS event. */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 0 : Disable interrupt on CTS event. */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source. Write error field to 1 to clear error. */ + +/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ + +/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ +#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART and acquire IOs. */ + +/* Bits 2..0 : Enable or disable UART and acquire IOs. */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ +#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ + +/* Register: UART_RXD */ +/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ + +/* Bits 7..0 : RX data from previous transfer. Double buffered. */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register. */ + +/* Bits 7..0 : TX data for transfer. */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: UART Baudrate. */ + +/* Bits 31..0 : UART baudrate. */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control register. */ + +/* Bits 3..1 : Include parity bit. */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ +#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ + +/* Bit 0 : Hardware flow control. */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ + +/* Register: UART_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/* Peripheral: UICR */ +/* Description: User Information Configuration. */ + +/* Register: UICR_RBPCONF */ +/* Description: Readback protection configuration. */ + +/* Bits 15..8 : Readback protect all code in the device. */ +#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ +#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ +#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ + +/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ +#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ +#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ +#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ +#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ + +/* Register: UICR_XTALFREQ */ +/* Description: Reset value for CLOCK XTALFREQ register. */ + +/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ +#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ +#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ +#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ +#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ + +/* Register: UICR_FWID */ +/* Description: Firmware ID. */ + +/* Bits 15..0 : Identification number for the firmware loaded into the chip. */ +#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ +#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer. */ + +/* Register: WDT_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 0 : Enable interrupt on TIMEOUT event. */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: WDT_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 0 : Disable interrupt on TIMEOUT event. */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Watchdog running status. */ + +/* Bit 0 : Watchdog running status. */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status. */ + +/* Bit 7 : Request status for RR[7]. */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ + +/* Bit 6 : Request status for RR[6]. */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ + +/* Bit 5 : Request status for RR[5]. */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ + +/* Bit 4 : Request status for RR[4]. */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ + +/* Bit 3 : Request status for RR[3]. */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ + +/* Bit 2 : Request status for RR[2]. */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ + +/* Bit 1 : Request status for RR[1]. */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ + +/* Bit 0 : Request status for RR[0]. */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ + +/* Register: WDT_RREN */ +/* Description: Reload request enable. */ + +/* Bit 7 : Enable or disable RR[7] register. */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ + +/* Bit 6 : Enable or disable RR[6] register. */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ + +/* Bit 5 : Enable or disable RR[5] register. */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ + +/* Bit 4 : Enable or disable RR[4] register. */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ + +/* Bit 3 : Enable or disable RR[3] register. */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ + +/* Bit 2 : Enable or disable RR[2] register. */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ + +/* Bit 1 : Enable or disable RR[1] register. */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ + +/* Bit 0 : Enable or disable RR[0] register. */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ + +/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ + +/* Register: WDT_RR */ +/* Description: Reload requests registers. */ + +/* Bits 31..0 : Reload register. */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ + +/* Register: WDT_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_deprecated.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_deprecated.h new file mode 100755 index 0000000..19370d4 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_deprecated.h @@ -0,0 +1,446 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_DEPRECATED_H +#define NRF51_DEPRECATED_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and + * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. + */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* LPCOMP */ +/* The interrupt ISR was renamed. Adding old name to the macros. */ +#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn LPCOMP_IRQn +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + + +/* MPU */ +/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ +#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos +#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk +#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 +#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 + + +/* POWER */ +/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_OFFRAM3_Pos (19UL) +#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) +#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) +#define POWER_RAMON_OFFRAM3_RAM3On (1UL) +/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_OFFRAM2_Pos (18UL) +#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) +#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) +#define POWER_RAMON_OFFRAM2_RAM2On (1UL) +/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_ONRAM3_Pos (3UL) +#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) +#define POWER_RAMON_ONRAM3_RAM3Off (0UL) +#define POWER_RAMON_ONRAM3_RAM3On (1UL) +/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ +#define POWER_RAMON_ONRAM2_Pos (2UL) +#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) +#define POWER_RAMON_ONRAM2_RAM2Off (0UL) +#define POWER_RAMON_ONRAM2_RAM2On (1UL) + + +/* RADIO */ +/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ +#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos +#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk +#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled +#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled +/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ +#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos +#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk +#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled +#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled + + +/* FICR */ +/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ +#define SIZERAMBLOCK0 SIZERAMBLOCKS +#define SIZERAMBLOCK1 SIZERAMBLOCKS +#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ +#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + +/* SPIS */ +/* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */ +#define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_DEPRECATED_H */ + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_peripherals.h new file mode 100755 index 0000000..fd89248 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_peripherals.h @@ -0,0 +1,155 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF51_PERIPHERALS_H +#define _NRF51_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAMON_REGISTERS_PRESENT + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 64 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 8 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 16 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 4 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 16 +#define TIMER2_MAX_SIZE 16 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Slave with DMA */ +#define SPIS_PRESENT +#define SPIS_COUNT 1 + +#define SPIS1_EASYDMA_MAXCNT_SIZE 8 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Analog to Digital Converter */ +#define ADC_PRESENT +#define ADC_COUNT 1 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 4 + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 8 + + +#endif // _NRF51_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52.h new file mode 100755 index 0000000..9cdae0c --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52.h @@ -0,0 +1,954 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_TO_NRF52_H +#define NRF51_TO_NRF52_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#define UART0_IRQHandler UARTE0_UART0_IRQHandler +#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define ADC_IRQHandler SAADC_IRQHandler +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#define SWI5_IRQHandler SWI5_EGU5_IRQHandler + +#define UART0_IRQn UARTE0_UART0_IRQn +#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#define ADC_IRQn SAADC_IRQn +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define SWI0_IRQn SWI0_EGU0_IRQn +#define SWI1_IRQn SWI1_EGU1_IRQn +#define SWI2_IRQn SWI2_EGU2_IRQn +#define SWI3_IRQn SWI3_EGU3_IRQn +#define SWI4_IRQn SWI4_EGU4_IRQn +#define SWI5_IRQn SWI5_EGU5_IRQn + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#define RBPCONF APPROTECT + +#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled + + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#define NRF_GPIO NRF_P0 +#define NRF_GPIO_BASE NRF_P0_BASE + + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#define PSELLED PSEL.LED +#define PSELA PSEL.A +#define PSELB PSEL.B + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#define PSELSCK PSEL.SCK +#define PSELMISO PSEL.MISO +#define PSELMOSI PSEL.MOSI +#define PSELCSN PSEL.CSN + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#define RXDPTR RXD.PTR +#define MAXRX RXD.MAXCNT +#define AMOUNTRX RXD.AMOUNT + +#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#define TXDPTR TXD.PTR +#define MAXTX TXD.MAXCNT +#define AMOUNTTX TXD.AMOUNT + +#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk + + +/* MPU */ +/* Part of MPU module was renamed BPROT, while the rest was eliminated. */ +#define NRF_MPU NRF_BPROT + +/* Register DISABLEINDEBUG macros were affected. */ +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled + +/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ +#define PROTENSET0 CONFIG0 +#define PROTENSET1 CONFIG1 + +#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos +#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk +#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled +#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled +#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled + +#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos +#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk +#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled +#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled +#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled + +#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos +#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk +#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled +#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled +#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled + +#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos +#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk +#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled +#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled +#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled + +#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos +#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk +#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled +#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled +#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled + +#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos +#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk +#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled +#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled +#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled + +#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos +#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk +#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled +#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled +#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled + +#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos +#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk +#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled +#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled +#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled + +#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos +#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk +#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled +#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled +#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled + +#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos +#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk +#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled +#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled +#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled + +#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos +#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk +#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled +#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled +#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled + +#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos +#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk +#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled +#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled +#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled + +#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos +#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk +#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled +#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled +#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled + +#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos +#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk +#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled +#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled +#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled + +#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos +#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk +#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled +#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled +#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled + +#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos +#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk +#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled +#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled +#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled + +#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos +#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk +#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled +#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled +#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled + +#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos +#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk +#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled +#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled +#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled + +#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos +#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk +#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled +#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled +#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled + +#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos +#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk +#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled +#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled +#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled + +#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos +#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk +#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled +#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled +#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled + +#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos +#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk +#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled +#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled +#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled + +#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos +#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk +#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled +#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled +#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled + +#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos +#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk +#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled +#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled +#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled + +#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos +#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk +#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled +#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled +#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled + +#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos +#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk +#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled +#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled +#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled + +#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos +#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk +#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled +#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled +#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled + +#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos +#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk +#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled +#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled +#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled + +#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos +#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk +#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled +#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled +#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled + +#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos +#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk +#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled +#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled +#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled + +#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos +#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk +#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled +#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled +#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled + +#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos +#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk +#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled +#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled +#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled + +#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos +#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk +#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled +#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled +#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled + +#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos +#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk +#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled +#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled +#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled + +#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos +#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk +#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled +#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled +#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled + +#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos +#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk +#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled +#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled +#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled + +#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos +#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk +#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled +#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled +#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled + +#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos +#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk +#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled +#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled +#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled + +#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos +#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk +#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled +#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled +#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled + +#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos +#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk +#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled +#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled +#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled + +#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos +#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk +#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled +#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled +#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled + +#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos +#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk +#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled +#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled +#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled + +#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos +#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk +#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled +#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled +#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled + +#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos +#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk +#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled +#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled +#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled + +#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos +#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk +#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled +#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled +#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled + +#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos +#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk +#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled +#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled +#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled + +#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos +#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk +#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled +#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled +#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled + +#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos +#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk +#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled +#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled +#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled + +#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos +#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk +#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled +#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled +#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled + +#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos +#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk +#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled +#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled +#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled + +#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos +#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk +#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled +#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled +#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled + +#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos +#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk +#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled +#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled +#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled + +#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos +#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk +#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled +#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled +#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled + +#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos +#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk +#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled +#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled +#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled + +#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos +#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk +#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled +#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled +#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled + +#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos +#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk +#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled +#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled +#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled + +#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos +#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk +#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled +#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled +#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled + +#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos +#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk +#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled +#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled +#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled + +#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos +#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk +#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled +#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled +#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled + +#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos +#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk +#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled +#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled +#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled + +#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos +#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk +#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled +#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled +#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled + +#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos +#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk +#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled +#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled +#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled + +#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos +#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk +#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled +#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled +#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled + +#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos +#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk +#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled +#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled +#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52 headers. */ +#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn + + +/* REFSEL register redefined enumerated values and added some more. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd + + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52_H */ + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52810.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52810.h new file mode 100755 index 0000000..ff521ab --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52810.h @@ -0,0 +1,523 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_TO_NRF52810_H +#define NRF51_TO_NRF52810_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + + /* Differences between latest nRF51 headers and nRF52810 headers. */ + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#define SWI1_IRQHandler SWI1_EGU1_IRQHandler + +#define SWI0_IRQn SWI0_EGU0_IRQn +#define SWI1_IRQn SWI1_EGU1_IRQn + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#define RBPCONF APPROTECT + +#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled + + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#define NRF_GPIO NRF_P0 +#define NRF_GPIO_BASE NRF_P0_BASE + + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#define PSELLED PSEL.LED +#define PSELA PSEL.A +#define PSELB PSEL.B + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#define PSELSCK PSEL.SCK +#define PSELMISO PSEL.MISO +#define PSELMOSI PSEL.MOSI +#define PSELCSN PSEL.CSN + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#define RXDPTR RXD.PTR +#define MAXRX RXD.MAXCNT +#define AMOUNTRX RXD.AMOUNT + +#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#define TXDPTR TXD.PTR +#define MAXTX TXD.MAXCNT +#define AMOUNTTX TXD.AMOUNT + +#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk + + +/* From nrf51_deprecated.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52810_H */ + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52840.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52840.h new file mode 100755 index 0000000..d0a4421 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf51_to_nrf52840.h @@ -0,0 +1,569 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF51_TO_NRF52840_H +#define NRF51_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. + * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf51_deprecated.h file. */ + + +/* IRQ */ +/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ +#define UART0_IRQHandler UARTE0_UART0_IRQHandler +#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define ADC_IRQHandler SAADC_IRQHandler +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#define SWI5_IRQHandler SWI5_EGU5_IRQHandler + +#define UART0_IRQn UARTE0_UART0_IRQn +#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#define ADC_IRQn SAADC_IRQn +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define SWI0_IRQn SWI0_EGU0_IRQn +#define SWI1_IRQn SWI1_EGU1_IRQn +#define SWI2_IRQn SWI2_EGU2_IRQn +#define SWI3_IRQn SWI3_EGU3_IRQn +#define SWI4_IRQn SWI4_EGU4_IRQn +#define SWI5_IRQn SWI5_EGU5_IRQn + + +/* UICR */ +/* Register RBPCONF was renamed to APPROTECT. */ +#define RBPCONF APPROTECT + +#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled + + +/* GPIO */ +/* GPIO port was renamed to P0. */ +#define NRF_GPIO NRF_P0 +#define NRF_GPIO_BASE NRF_P0_BASE + + +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#define PSELLED PSEL.LED +#define PSELA PSEL.A +#define PSELB PSEL.B + + +/* SPIS */ +/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ +#define PSELSCK PSEL.SCK +#define PSELMISO PSEL.MISO +#define PSELMOSI PSEL.MOSI +#define PSELCSN PSEL.CSN + +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#define RXDPTR RXD.PTR +#define MAXRX RXD.MAXCNT +#define AMOUNTRX RXD.AMOUNT + +#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk + +/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ +#define TXDPTR TXD.PTR +#define MAXTX TXD.MAXCNT +#define AMOUNTTX TXD.AMOUNT + +#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk + + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#define PSELRTS PSEL.RTS +#define PSELTXD PSEL.TXD +#define PSELCTS PSEL.CTS +#define PSELRXD PSEL.RXD + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#define PSELSCL PSEL.SCL +#define PSELSDA PSEL.SDA + + + +/* From nrf51_deprecated.h */ + +/* NVMC */ +/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ +#define ERASEPROTECTEDPAGE ERASEPCR0 + + +/* IRQ */ +/* COMP module was eliminated. Adapted to nrf52840 headers. */ +#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn + + +/* REFSEL register redefined enumerated values and added some more. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd + + +/* RADIO */ +/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip + + +/* FICR */ +/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] + +/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] + +/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] + +/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] + + +/* PPI */ +/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS + +/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP + +/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] + +/* All bitfield macros for the CHGx registers therefore changed name. */ +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + + + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52.h new file mode 100755 index 0000000..05a921b --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52.h @@ -0,0 +1,2441 @@ +/* + * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 06. June 2018 + * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:38 + * from File 'nrf52.svd', + * last modified on Wednesday, 06.06.2018 13:21:34 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52 + * @{ + */ + + +#ifndef NRF52_H +#define NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== nrf52 Specific Interrupt Numbers ============================================ */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38 /*!< 38 FPU */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_nrf52.h" /*!< nrf52 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production + configuration */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ + __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */ +} FICR_INFO_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */ + __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */ + __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */ + __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */ + __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */ + __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */ + __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief FICR_NFC [NFC] (Unspecified) + */ +typedef struct { + __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set + register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) + */ +typedef struct { + __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */ +} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief NFCT_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ + __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ +} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief NFCT_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ +} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal + or above CH[0].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal + or below CH[0].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection + for CH[0] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection + for CH[0] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for + CH[0] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event + monitoring a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last + START */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in + Data RAM of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty + cycles) in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional + PWM periods between samples loaded into + compare register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the + sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select + for PWM channel 0 */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group + 0 */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group + 0 */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region + 0 detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region + 0 detected */ +} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral + region 0 detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral + region 0 detected */ +} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_PERREGION [PERREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt + in region 0, write access detected while + corresponding subregion was enabled for + watching */ + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt + in region 0, read access detected while + corresponding subregion was enabled for + watching */ +} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_REGION [REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region + 0 */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region + 0 */ + __IM uint32_t RESERVED[2]; +} MWU_REGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief MWU_PREGION [PREGION] (Unspecified) + */ +typedef struct { + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region + 0 */ + __IM uint32_t RESERVED; +} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief I2S_CONFIG [CONFIG] (Unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ +} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + + +/** + * @brief I2S_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ +} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_RXTXD [RXTXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ +} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory Information Configuration Registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word + 0 */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word + 0 */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */ + __IM uint32_t RESERVED3[21]; + __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[185]; + __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ + __IM uint32_t RESERVED5[2]; + __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ +} NRF_FICR_Type; /*!< Size = 1120 (0x460) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User Information Configuration Registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ + __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ + __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ + __IM uint32_t RESERVED; + __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic + firmware design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic + hardware design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ + __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: + NFC antenna or GPIO */ +} NRF_UICR_Type; /*!< Size = 528 (0x210) */ + + + +/* =========================================================================================================================== */ +/* ================ BPROT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Block Protect (BPROT) + */ + +typedef struct { /*!< (@ 0x40000000) BPROT Structure */ + __IM uint32_t RESERVED[384]; + __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ + __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ + __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface + mode */ + __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ + __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */ + __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */ +} NRF_BPROT_Type; /*!< Size = 1560 (0x618) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IM uint32_t RESERVED3[122]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ + __IM uint32_t RESERVED6[53]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ + __IM uint32_t RESERVED8[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this + register is retained) */ + __IM uint32_t RESERVED9[11]; + __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this + register is retained) */ + __IM uint32_t RESERVED10[8]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ + __IM uint32_t RESERVED11[225]; + __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2432 (0x980) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[124]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED4; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED6[7]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ + __IM uint32_t RESERVED7[8]; + __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */ +} NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz Radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength. */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __IM uint32_t RESERVED[55]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IM uint32_t RESERVED3[50]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED4[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED6; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t RESERVED7[60]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED8; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED10[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base + segment 0 */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix + 0 */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IM uint32_t RESERVED11[3]; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED12[618]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */ + __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */ + __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */ + __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED10; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED11[4]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED12[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in + case and over-read of the TXD buffer. */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IM uint32_t RESERVED11; + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IM uint32_t RESERVED12; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED14[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND + task has been issued, TWI traffic is now + suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED13; + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[14]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address + 0 */ + __IM uint32_t RESERVED15; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED16[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI0) + */ + +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */ + __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ NFCT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< (@ 0x40005000) NFCT Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing + frames, change state to activated */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */ + __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to + sense mode */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change + state to transmit */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ + __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send + frames */ + __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ + __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ + __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted + frame */ + __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air + symbol of a frame */ + __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received + frame */ + __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity) + and transferred to RAM, and EasyDMA has + ended accessing the RX buffer */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register + contains details on the source of the error. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX + register contains details on the source + of the error. */ + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) + in Data RAM full. */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA + has ended accessing the TX buffer */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */ + __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ + __IM uint32_t RESERVED6[43]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[62]; + __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ + __IM uint32_t RESERVED9; + __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ + __IM uint32_t RESERVED10[8]; + __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */ + __IM uint32_t RESERVED11[2]; + __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ + __IM uint32_t RESERVED12[49]; + __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ + __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ + __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in + Data RAM */ + __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage + buffer in Data RAM */ + __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ + __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ + __IM uint32_t RESERVED14; + __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ + __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is configured in CONFIG[0].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to + pin specified in CONFIG[0].PSEL. Action + on pin is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from + pin specified in CONFIG[0].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for + OUT[n], SET[n] and CLR[n] tasks and IN[n] + event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog to Digital Converter (SAADC) + */ + +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in + RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels + are sampled */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the mode, multiple conversions might + be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should + not be combined with SCAN. The RESOLUTION + is applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value + to CC[0] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register + 0 */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu + t be written when RTC is stopped */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_CCM_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ + __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ +} NRF_COMP_Type; /*!< Size = 1344 (0x540) */ + + + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low Power Comparator (LPCOMP) + */ + +typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event Generator Unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering + the corresponding TRIGGERED[0] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated + by triggering the corresponding TRIGGER[0] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Width Modulation Unit 0 (PWM0) + */ + +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM + value on all enabled channels from sequence + 0, and starts playing that sequence at the + rate defined in SEQ[0]REFRESH and/or DECODER.MODE. + Causes PWM generation to start it was not + running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start it + was not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started + on sequence 0 */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of + every sequence 0, when last value from RAM + has been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IM uint32_t RESERVED4[8]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */ + __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in Code area. Equivalent to ERASEPAGE. */ + }; + __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in Code area. Equivalent to ERASEPAGE. */ + __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration + Registers */ + __IM uint32_t RESERVED2[10]; + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */ + __IM uint32_t RESERVED3; + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */ +} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ MWU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< (@ 0x40020000) MWU Structure */ + __IM uint32_t RESERVED[64]; + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ + __IM uint32_t RESERVED1[16]; + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ + __IM uint32_t RESERVED2[100]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ + __IM uint32_t RESERVED4[53]; + __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ + __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ + __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ + __IM uint32_t RESERVED6[57]; + __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ + __IM uint32_t RESERVED7[32]; + __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ +} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< (@ 0x40025000) I2S Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. + Triggering this task will cause the {event:STOPPED} + event to be generated. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started + and RX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started + and TX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __IM uint32_t RESERVED2[122]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ + __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ + __IM uint32_t RESERVED4[3]; + __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ + __IM uint32_t RESERVED5; + __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED6[3]; + __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ + __IM uint32_t RESERVED7[3]; + __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ FPU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< (@ 0x40026000) FPU Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_FPU_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_BPROT_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_P0_BASE 0x50000000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52_H */ + + +/** @} */ /* End of group nrf52 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810.h new file mode 100755 index 0000000..168c040 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810.h @@ -0,0 +1,1846 @@ +/* + * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52810.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 06. June 2018 + * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:39 + * from File 'nrf52810.svd', + * last modified on Wednesday, 06.06.2018 13:21:35 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52810 + * @{ + */ + + +#ifndef NRF52810_H +#define NRF52810_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== nrf52810 Specific Interrupt Numbers ========================================== */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_IRQn = 2, /*!< 2 UARTE0 */ + TWIM0_TWIS0_IRQn = 3, /*!< 3 TWIM0_TWIS0 */ + SPIM0_SPIS0_IRQn = 4, /*!< 4 SPIM0_SPIS0 */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_IRQn = 19, /*!< 19 COMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_IRQn = 22, /*!< 22 SWI2 */ + SWI3_IRQn = 23, /*!< 23 SWI3 */ + SWI4_IRQn = 24, /*!< 24 SWI4 */ + SWI5_IRQn = 25, /*!< 25 SWI5 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29 /*!< 29 PDM */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_nrf52810.h" /*!< nrf52810 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production + configuration */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ + __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ +} FICR_INFO_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ + __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ + __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ + __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ + __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ + __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ + __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register. + The RAM size will vary depending on product + variant, and the RAMn register will only + be present if the corresponding RAM AHB + slave is present on the device. */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set + register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last results is equal + or above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last results is equal + or below CH[n].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection + for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection + for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for + CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event + monitoring a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last + START */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in + RAM of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty + cycles) in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional + PWM periods between samples loaded into + compare register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the + sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select + for PWM channel n */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group + n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group + n */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory information configuration registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word + n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity root, word + n */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ + __IM uint32_t RESERVED3[21]; + __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[185]; + __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ +} NRF_FICR_Type; /*!< Size = 1096 (0x448) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User information configuration registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ + __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ + __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ + __IM uint32_t RESERVED; + __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic + firmware design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic + hardware design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ +} NRF_UICR_Type; /*!< Size = 524 (0x20c) */ + + + +/* =========================================================================================================================== */ +/* ================ BPROT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Block Protect (BPROT) + */ + +typedef struct { /*!< (@ 0x40000000) BPROT Structure */ + __IM uint32_t RESERVED[384]; + __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ + __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ + __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ + __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ +} NRF_BPROT_Type; /*!< Size = 1552 (0x610) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[124]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED4; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED6[7]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ +} NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IM uint32_t RESERVED3[122]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[63]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ + __IM uint32_t RESERVED7[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IM uint32_t RESERVED8[21]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ + __IM uint32_t RESERVED9[225]; + __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2432 (0x980) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz Radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength. */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __IM uint32_t RESERVED[55]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IM uint32_t RESERVED3[50]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED4[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED6; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t RESERVED7[60]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED8; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED10[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base + segment n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix + n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IM uint32_t RESERVED11[3]; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED12[618]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write + one to clear. */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND + task has been issued, TWI traffic is now + suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED13; + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[14]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address + n */ + __IM uint32_t RESERVED15; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED16[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0) + */ + +typedef struct { /*!< (@ 0x40004000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED10; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED11[4]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED12[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in + case and over-read of the TXD buffer. */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave (SPIS0) + */ + +typedef struct { /*!< (@ 0x40004000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IM uint32_t RESERVED11; + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IM uint32_t RESERVED12; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED14[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to + pin specified in CONFIG[n].PSEL. Action + on pin is configured in CONFIG[n].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to + pin specified in CONFIG[n].PSEL. Action + on pin is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to + pin specified in CONFIG[n].PSEL. Action + on pin is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from + pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for + OUT[n], SET[n] and CLR[n] tasks and IN[n] + event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog to Digital Converter (SAADC) + */ + +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in + RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels + are sampled */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the mode, multiple conversions might + be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should + not be combined with SCAN. The RESOLUTION + is applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value + to CC[n] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register + n */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu + t be written when RTC is stopped */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with + the contents of the RATEOVERRIDE register + for any ongoing encryption/decryption */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + = Extended. */ + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ +} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event Generator Unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering + the corresponding TRIGGERED[n] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated + by triggering the corresponding TRIGGER[n] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse width modulation unit (PWM0) + */ + +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM + value on all enabled channels from sequence + n, and starts playing that sequence at the + rate defined in SEQ[n]REFRESH and/or DECODER.MODE. + Causes PWM generation to start if not running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start if + not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started + on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of + every sequence n, when last value from RAM + has been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IM uint32_t RESERVED4[8]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non-volatile memory controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area. Equivalent to ERASEPAGE. */ + }; + __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area. Equivalent to ERASEPAGE. */ + __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + registers */ + __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + area */ + __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ +} NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_BPROT_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPIM0_BASE 0x40004000UL +#define NRF_SPIS0_BASE 0x40004000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_P0_BASE 0x50000000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52810_H */ + + +/** @} */ /* End of group nrf52810 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810_bitfields.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810_bitfields.h new file mode 100755 index 0000000..fa1980b --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810_bitfields.h @@ -0,0 +1,10263 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF52810_BITS_H +#define __NRF52810_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_TASKS_START */ +/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ + +/* Bit 0 : */ +#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: AAR_TASKS_STOP */ +/* Description: Stop resolving addresses */ + +/* Bit 0 : */ +#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: AAR_EVENTS_END */ +/* Description: Address resolution procedure complete */ + +/* Bit 0 : */ +#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: AAR_EVENTS_RESOLVED */ +/* Description: Address resolved */ + +/* Bit 0 : */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ + +/* Register: AAR_EVENTS_NOTRESOLVED */ +/* Description: Address not resolved */ + +/* Bit 0 : */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for RESOLVED event */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for END event */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for RESOLVED event */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for END event */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: BPROT */ +/* Description: Block Protect */ + +/* Register: BPROT_CONFIG0 */ +/* Description: Block protect configuration register 0 */ + +/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_CONFIG1 */ +/* Description: Block protect configuration register 1 */ + +/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_DISABLEINDEBUG */ +/* Description: Disable protection mechanism in debug mode */ + +/* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enabled in debug */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disabled in debug */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_TASKS_KSGEN */ +/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ + +/* Bit 0 : */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ + +/* Register: CCM_TASKS_CRYPT */ +/* Description: Start encryption/decryption. This operation will stop by itself when completed. */ + +/* Bit 0 : */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ + +/* Register: CCM_TASKS_STOP */ +/* Description: Stop encryption/decryption */ + +/* Bit 0 : */ +#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: CCM_TASKS_RATEOVERRIDE */ +/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ + +/* Bit 0 : */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ + +/* Register: CCM_EVENTS_ENDKSGEN */ +/* Description: Key-stream generation complete */ + +/* Bit 0 : */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ + +/* Register: CCM_EVENTS_ENDCRYPT */ +/* Description: Encrypt/decrypt complete */ + +/* Bit 0 : */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ + +/* Register: CCM_EVENTS_ERROR */ +/* Description: Deprecated register - CCM error event */ + +/* Bit 0 : */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for ERROR event */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for ERROR event */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ + +/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ + +/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + +/* Register: CCM_MAXPACKETSIZE */ +/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ + +/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ + +/* Register: CCM_RATEOVERRIDE */ +/* Description: Data rate override setting. */ + +/* Bits 1..0 : Data rate override setting. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_TASKS_HFCLKSTART */ +/* Description: Start HFCLK crystal oscillator */ + +/* Bit 0 : */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ + +/* Register: CLOCK_TASKS_HFCLKSTOP */ +/* Description: Stop HFCLK crystal oscillator */ + +/* Bit 0 : */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ + +/* Register: CLOCK_TASKS_LFCLKSTART */ +/* Description: Start LFCLK source */ + +/* Bit 0 : */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ + +/* Register: CLOCK_TASKS_LFCLKSTOP */ +/* Description: Stop LFCLK source */ + +/* Bit 0 : */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ + +/* Register: CLOCK_TASKS_CAL */ +/* Description: Start calibration of LFRC oscillator */ + +/* Bit 0 : */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ + +/* Register: CLOCK_TASKS_CTSTART */ +/* Description: Start calibration timer */ + +/* Bit 0 : */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ + +/* Register: CLOCK_TASKS_CTSTOP */ +/* Description: Stop calibration timer */ + +/* Bit 0 : */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ + +/* Register: CLOCK_EVENTS_HFCLKSTARTED */ +/* Description: HFCLK oscillator started */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ + +/* Register: CLOCK_EVENTS_LFCLKSTARTED */ +/* Description: LFCLK started */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ + +/* Register: CLOCK_EVENTS_DONE */ +/* Description: Calibration of LFCLK RC oscillator complete event */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ + +/* Register: CLOCK_EVENTS_CTTO */ +/* Description: Calibration timer timeout */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to enable interrupt for CTTO event */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for DONE event */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to disable interrupt for CTTO event */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for DONE event */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_TASKS_START */ +/* Description: Start comparator */ + +/* Bit 0 : */ +#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: COMP_TASKS_STOP */ +/* Description: Stop comparator */ + +/* Bit 0 : */ +#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: COMP_TASKS_SAMPLE */ +/* Description: Sample comparator value */ + +/* Bit 0 : */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ + +/* Register: COMP_EVENTS_READY */ +/* Description: COMP is ready and output is valid */ + +/* Bit 0 : */ +#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ + +/* Register: COMP_EVENTS_DOWN */ +/* Description: Downward crossing */ + +/* Bit 0 : */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ + +/* Register: COMP_EVENTS_UP */ +/* Description: Upward crossing */ + +/* Bit 0 : */ +#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ + +/* Register: COMP_EVENTS_CROSS */ +/* Description: Downward or upward crossing */ + +/* Bit 0 : */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for CROSS event */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for UP event */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for DOWN event */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for UP event */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for READY event */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for UP event */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for READY event */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_VddDiv2 (7UL) /*!< VDD/2 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select for single-ended mode */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bits 2..0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation modes */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power modes */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_TASKS_STARTECB */ +/* Description: Start ECB block encrypt */ + +/* Bit 0 : */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ + +/* Register: ECB_TASKS_STOPECB */ +/* Description: Abort a possible executing ECB operation */ + +/* Bit 0 : */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ + +/* Register: ECB_EVENTS_ENDECB */ +/* Description: ECB block encrypt complete */ + +/* Bit 0 : */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ + +/* Register: ECB_EVENTS_ERRORECB */ +/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ + +/* Bit 0 : */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to enable interrupt for ERRORECB event */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for ENDECB event */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to disable interrupt for ERRORECB event */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for ENDECB event */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_TASKS_TRIGGER */ +/* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event */ + +/* Bit 0 : */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ + +/* Register: EGU_EVENTS_TRIGGERED */ +/* Description: Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task */ + +/* Bit 0 : */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory information configuration registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection[n]: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection[n]: Encryption root, word n */ + +/* Bits 31..0 : Encryption root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection[n]: Identity root, word n */ + +/* Bits 31..0 : Identity root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection[n]: Device address n */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52810 (0x52810UL) /*!< nRF52810 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part variant, hardware version and production configuration */ + +/* Bits 31..0 : Part variant, hardware version and production configuration, encoded as ASCII */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ +#define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ +#define FICR_INFO_VARIANT_VARIANT_AACB (0x41414342UL) /*!< AACB */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_QC (0x2003UL) /*!< QCxx - 32-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K24 (0x18UL) /*!< 24 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K192 (0xC0UL) /*!< 192 kByte flash */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: Y-intercept B0 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: Y-intercept B1 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: Y-intercept B2 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: Y-intercept B3 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: Y-intercept B4 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: Y-intercept B5 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_TASKS_OUT */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + +/* Bit 0 : */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ + +/* Register: GPIOTE_TASKS_SET */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + +/* Bit 0 : */ +#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ + +/* Register: GPIOTE_TASKS_CLR */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + +/* Bit 0 : */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ + +/* Register: GPIOTE_EVENTS_IN */ +/* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */ + +/* Bit 0 : */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ + +/* Register: GPIOTE_EVENTS_PORT */ +/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ + +/* Bit 0 : */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to enable interrupt for PORT event */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for IN[7] event */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for IN[6] event */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for IN[5] event */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for IN[4] event */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for IN[3] event */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for IN[2] event */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for IN[1] event */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for IN[0] event */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to disable interrupt for PORT event */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for IN[7] event */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for IN[6] event */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for IN[5] event */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for IN[4] event */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for IN[3] event */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for IN[2] event */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for IN[1] event */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for IN[0] event */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: NVMC */ +/* Description: Non-volatile memory controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in code area */ + +/* Bits 31..0 : Register for starting erase of a page in code area. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start erase of chip */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing user information configuration registers */ + +/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ERASEPAGEPARTIAL */ +/* Description: Register for partial erase of a page in code area */ + +/* Bits 31..0 : Register for starting partial erase of a page in code area */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */ + +/* Register: NVMC_ERASEPAGEPARTIALCFG */ +/* Description: Register for partial erase configuration */ + +/* Bits 6..0 : Duration of the partial erase in milliseconds */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection[n]: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_TASKS_START */ +/* Description: Starts continuous PDM transfer */ + +/* Bit 0 : */ +#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: PDM_TASKS_STOP */ +/* Description: Stops PDM transfer */ + +/* Bit 0 : */ +#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: PDM_EVENTS_STARTED */ +/* Description: PDM transfer has started */ + +/* Bit 0 : */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ + +/* Register: PDM_EVENTS_STOPPED */ +/* Description: PDM transfer has finished */ + +/* Bit 0 : */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: PDM_EVENTS_END */ +/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ + +/* Bit 0 : */ +#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for END event */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for END event */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for END event */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_TASKS_CONSTLAT */ +/* Description: Enable constant latency mode */ + +/* Bit 0 : */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ + +/* Register: POWER_TASKS_LOWPWR */ +/* Description: Enable low power mode (variable latency) */ + +/* Bit 0 : */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ + +/* Register: POWER_EVENTS_POFWARN */ +/* Description: Power failure warning */ + +/* Bit 0 : */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ + +/* Register: POWER_EVENTS_SLEEPENTER */ +/* Description: CPU entered WFI/WFE sleep */ + +/* Bit 0 : */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ + +/* Register: POWER_EVENTS_SLEEPEXIT */ +/* Description: CPU exited WFI/WFE sleep */ + +/* Bit 0 : */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for POFWARN event */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for POFWARN event */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power failure comparator configuration */ + +/* Bits 4..1 : Power failure comparator threshold setting */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure comparator */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_DCDCEN */ +/* Description: DC/DC enable register */ + +/* Bit 0 : Enable or disable DC/DC converter */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster[n]: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster[n]: RAMn power control set register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster[n]: RAMn power control clear register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_TASKS_CHG_EN */ +/* Description: Description cluster[n]: Enable channel group n */ + +/* Bit 0 : */ +#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ + +/* Register: PPI_TASKS_CHG_DIS */ +/* Description: Description cluster[n]: Disable channel group n */ + +/* Bit 0 : */ +#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster[n]: Channel n event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster[n]: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection[n]: Channel group n */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster[n]: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse width modulation unit */ + +/* Register: PWM_TASKS_STOP */ +/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ + +/* Bit 0 : */ +#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: PWM_TASKS_SEQSTART */ +/* Description: Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ + +/* Bit 0 : */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ + +/* Register: PWM_TASKS_NEXTSTEP */ +/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ + +/* Bit 0 : */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ + +/* Register: PWM_EVENTS_STOPPED */ +/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ + +/* Bit 0 : */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: PWM_EVENTS_SEQSTARTED */ +/* Description: Description collection[n]: First PWM period started on sequence n */ + +/* Bit 0 : */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ + +/* Register: PWM_EVENTS_SEQEND */ +/* Description: Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + +/* Bit 0 : */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ + +/* Register: PWM_EVENTS_PWMPERIODEND */ +/* Description: Emitted at the end of each PWM period */ + +/* Bit 0 : */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ + +/* Register: PWM_EVENTS_LOOPSDONE */ +/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + +/* Bit 0 : */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up mode or up-and-down mode for the counter */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Prescaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Number of playbacks of a loop */ + +/* Bits 15..0 : Number of playbacks of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster[n]: Beginning address in RAM of this sequence */ + +/* Bits 31..0 : Beginning address in RAM of this sequence */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */ + +/* Bits 14..0 : Number of values (duty cycles) in this sequence */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ + +/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster[n]: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection[n]: Output pin select for PWM channel n */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_TASKS_START */ +/* Description: Task starting the quadrature decoder */ + +/* Bit 0 : */ +#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: QDEC_TASKS_STOP */ +/* Description: Task stopping the quadrature decoder */ + +/* Bit 0 : */ +#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: QDEC_TASKS_READCLRACC */ +/* Description: Read and clear ACC and ACCDBL */ + +/* Bit 0 : */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ + +/* Register: QDEC_TASKS_RDCLRACC */ +/* Description: Read and clear ACC */ + +/* Bit 0 : */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ + +/* Register: QDEC_TASKS_RDCLRDBL */ +/* Description: Read and clear ACCDBL */ + +/* Bit 0 : */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ + +/* Register: QDEC_EVENTS_SAMPLERDY */ +/* Description: Event being generated for every new sample value written to the SAMPLE register */ + +/* Bit 0 : */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ + +/* Register: QDEC_EVENTS_REPORTRDY */ +/* Description: Non-null report ready */ + +/* Bit 0 : */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ + +/* Register: QDEC_EVENTS_ACCOF */ +/* Description: ACC or ACCDBL register overflow */ + +/* Bit 0 : */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ + +/* Register: QDEC_EVENTS_DBLRDY */ +/* Description: Double displacement(s) detected */ + +/* Bit 0 : */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ + +/* Register: QDEC_EVENTS_STOPPED */ +/* Description: QDEC has been stopped */ + +/* Bit 0 : */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to enable interrupt for STOPPED event */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for DBLRDY event */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for ACCOF event */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to disable interrupt for STOPPED event */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for DBLRDY event */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for ACCOF event */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz Radio */ + +/* Register: RADIO_TASKS_TXEN */ +/* Description: Enable RADIO in TX mode */ + +/* Bit 0 : */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ + +/* Register: RADIO_TASKS_RXEN */ +/* Description: Enable RADIO in RX mode */ + +/* Bit 0 : */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ + +/* Register: RADIO_TASKS_START */ +/* Description: Start RADIO */ + +/* Bit 0 : */ +#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: RADIO_TASKS_STOP */ +/* Description: Stop RADIO */ + +/* Bit 0 : */ +#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: RADIO_TASKS_DISABLE */ +/* Description: Disable RADIO */ + +/* Bit 0 : */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ + +/* Register: RADIO_TASKS_RSSISTART */ +/* Description: Start the RSSI and take one single sample of the receive signal strength. */ + +/* Bit 0 : */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ + +/* Register: RADIO_TASKS_RSSISTOP */ +/* Description: Stop the RSSI measurement */ + +/* Bit 0 : */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ + +/* Register: RADIO_TASKS_BCSTART */ +/* Description: Start the bit counter */ + +/* Bit 0 : */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ + +/* Register: RADIO_TASKS_BCSTOP */ +/* Description: Stop the bit counter */ + +/* Bit 0 : */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ + +/* Register: RADIO_EVENTS_READY */ +/* Description: RADIO has ramped up and is ready to be started */ + +/* Bit 0 : */ +#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ + +/* Register: RADIO_EVENTS_ADDRESS */ +/* Description: Address sent or received */ + +/* Bit 0 : */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ + +/* Register: RADIO_EVENTS_PAYLOAD */ +/* Description: Packet payload sent or received */ + +/* Bit 0 : */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ + +/* Register: RADIO_EVENTS_END */ +/* Description: Packet sent or received */ + +/* Bit 0 : */ +#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: RADIO_EVENTS_DISABLED */ +/* Description: RADIO has been disabled */ + +/* Bit 0 : */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ + +/* Register: RADIO_EVENTS_DEVMATCH */ +/* Description: A device address match occurred on the last received packet */ + +/* Bit 0 : */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ + +/* Register: RADIO_EVENTS_DEVMISS */ +/* Description: No device address match occurred on the last received packet */ + +/* Bit 0 : */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ + +/* Register: RADIO_EVENTS_RSSIEND */ +/* Description: Sampling of receive signal strength complete. */ + +/* Bit 0 : */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ + +/* Register: RADIO_EVENTS_BCMATCH */ +/* Description: Bit counter reached bit count value. */ + +/* Bit 0 : */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ + +/* Register: RADIO_EVENTS_CRCOK */ +/* Description: Packet received with CRC ok */ + +/* Bit 0 : */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ + +/* Register: RADIO_EVENTS_CRCERROR */ +/* Description: Packet received with CRC error */ + +/* Bit 0 : */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between END event and START task */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between END event and DISABLE task */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and START task */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 13 : Write '1' to enable interrupt for CRCERROR event */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for CRCOK event */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for BCMATCH event */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for RSSIEND event */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for DEVMISS event */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for DISABLED event */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for END event */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for ADDRESS event */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for READY event */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 13 : Write '1' to disable interrupt for CRCERROR event */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for CRCOK event */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for BCMATCH event */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for RSSIEND event */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for DEVMISS event */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for DISABLED event */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for END event */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for ADDRESS event */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for READY event */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bit 8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in us */ + +/* Bits 7..0 : Inter Frame Spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection[n]: Device address base segment n */ + +/* Bits 31..0 : Device address base segment n */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection[n]: Device address prefix n */ + +/* Bits 15..0 : Device address prefix n */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_TASKS_START */ +/* Description: Task starting the random number generator */ + +/* Bit 0 : */ +#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: RNG_TASKS_STOP */ +/* Description: Task stopping the random number generator */ + +/* Bit 0 : */ +#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: RNG_EVENTS_VALRDY */ +/* Description: Event being generated for every new random number written to the VALUE register */ + +/* Bit 0 : */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for VALRDY event */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for VALRDY event */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_TASKS_START */ +/* Description: Start RTC COUNTER */ + +/* Bit 0 : */ +#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: RTC_TASKS_STOP */ +/* Description: Stop RTC COUNTER */ + +/* Bit 0 : */ +#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: RTC_TASKS_CLEAR */ +/* Description: Clear RTC COUNTER */ + +/* Bit 0 : */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ + +/* Register: RTC_TASKS_TRIGOVRFLW */ +/* Description: Set COUNTER to 0xFFFFF0 */ + +/* Bit 0 : */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ + +/* Register: RTC_EVENTS_TICK */ +/* Description: Event on COUNTER increment */ + +/* Bit 0 : */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ + +/* Register: RTC_EVENTS_OVRFLW */ +/* Description: Event on COUNTER overflow */ + +/* Bit 0 : */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ + +/* Register: RTC_EVENTS_COMPARE */ +/* Description: Description collection[n]: Compare event on CC[n] match */ + +/* Bit 0 : */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for OVRFLW event */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for TICK event */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for OVRFLW event */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for TICK event */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable event routing for OVRFLW event */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable event routing for TICK event */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable event routing for OVRFLW event */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable event routing for TICK event */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable event routing for OVRFLW event */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable event routing for TICK event */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection[n]: Compare register n */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Analog to Digital Converter */ + +/* Register: SAADC_TASKS_START */ +/* Description: Start the ADC and prepare the result buffer in RAM */ + +/* Bit 0 : */ +#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: SAADC_TASKS_SAMPLE */ +/* Description: Take one ADC sample, if scan is enabled all channels are sampled */ + +/* Bit 0 : */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ + +/* Register: SAADC_TASKS_STOP */ +/* Description: Stop the ADC and terminate any on-going conversion */ + +/* Bit 0 : */ +#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: SAADC_TASKS_CALIBRATEOFFSET */ +/* Description: Starts offset auto-calibration */ + +/* Bit 0 : */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ + +/* Register: SAADC_EVENTS_STARTED */ +/* Description: The ADC has started */ + +/* Bit 0 : */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ + +/* Register: SAADC_EVENTS_END */ +/* Description: The ADC has filled up the Result buffer */ + +/* Bit 0 : */ +#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: SAADC_EVENTS_DONE */ +/* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ + +/* Bit 0 : */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ + +/* Register: SAADC_EVENTS_RESULTDONE */ +/* Description: A result is ready to get transferred to RAM. */ + +/* Bit 0 : */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ + +/* Register: SAADC_EVENTS_CALIBRATEDONE */ +/* Description: Calibration is complete */ + +/* Bit 0 : */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ + +/* Register: SAADC_EVENTS_STOPPED */ +/* Description: The ADC has stopped */ + +/* Bit 0 : */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: SAADC_EVENTS_CH_LIMITH */ +/* Description: Description cluster[n]: Last results is equal or above CH[n].LIMIT.HIGH */ + +/* Bit 0 : */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ + +/* Register: SAADC_EVENTS_CH_LIMITL */ +/* Description: Description cluster[n]: Last results is equal or below CH[n].LIMIT.LOW */ + +/* Bit 0 : */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for STOPPED event */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for DONE event */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for END event */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for STOPPED event */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for DONE event */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for END event */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for STOPPED event */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for DONE event */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for END event */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable ADC */ + +/* Bit 0 : Enable or disable ADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster[n]: Input positive pin selection for CH[n] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster[n]: Input negative pin selection for CH[n] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster[n]: Input configuration for CH[n] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster[n]: High/low limits for event monitoring a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 14..0 : Maximum number of buffer words to transfer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of buffer words transferred since last START */ + +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA */ + +/* Register: SPIM_TASKS_START */ +/* Description: Start SPI transaction */ + +/* Bit 0 : */ +#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: SPIM_TASKS_STOP */ +/* Description: Stop SPI transaction */ + +/* Bit 0 : */ +#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: SPIM_TASKS_SUSPEND */ +/* Description: Suspend SPI transaction */ + +/* Bit 0 : */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ + +/* Register: SPIM_TASKS_RESUME */ +/* Description: Resume SPI transaction */ + +/* Bit 0 : */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ + +/* Register: SPIM_EVENTS_STOPPED */ +/* Description: SPI transaction has stopped */ + +/* Bit 0 : */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: SPIM_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ + +/* Register: SPIM_EVENTS_END */ +/* Description: End of RXD buffer and TXD buffer reached */ + +/* Bit 0 : */ +#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: SPIM_EVENTS_ENDTX */ +/* Description: End of TXD buffer reached */ + +/* Bit 0 : */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ + +/* Register: SPIM_EVENTS_STARTED */ +/* Description: Transaction started */ + +/* Bit 0 : */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 17 : Shortcut between END event and START task */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for STARTED event */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for END event */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for STARTED event */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for END event */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 9..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 9..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ + +/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave */ + +/* Register: SPIS_TASKS_ACQUIRE */ +/* Description: Acquire SPI semaphore */ + +/* Bit 0 : */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ + +/* Register: SPIS_TASKS_RELEASE */ +/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ + +/* Bit 0 : */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ + +/* Register: SPIS_EVENTS_END */ +/* Description: Granted transaction completed */ + +/* Bit 0 : */ +#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: SPIS_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ + +/* Register: SPIS_EVENTS_ACQUIRED */ +/* Description: Semaphore acquired */ + +/* Bit 0 : */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 2 : Shortcut between END event and ACQUIRE task */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for END event */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for END event */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 9..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 9..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 9..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 9..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_TASKS_START */ +/* Description: Start temperature measurement */ + +/* Bit 0 : */ +#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: TEMP_TASKS_STOP */ +/* Description: Stop temperature measurement */ + +/* Bit 0 : */ +#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TEMP_EVENTS_DATARDY */ +/* Description: Temperature measurement complete, data ready */ + +/* Bit 0 : */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for DATARDY event */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for DATARDY event */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_TASKS_START */ +/* Description: Start Timer */ + +/* Bit 0 : */ +#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: TIMER_TASKS_STOP */ +/* Description: Stop Timer */ + +/* Bit 0 : */ +#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TIMER_TASKS_COUNT */ +/* Description: Increment Timer (Counter mode only) */ + +/* Bit 0 : */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ + +/* Register: TIMER_TASKS_CLEAR */ +/* Description: Clear time */ + +/* Bit 0 : */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ + +/* Register: TIMER_TASKS_SHUTDOWN */ +/* Description: Deprecated register - Shut down timer */ + +/* Bit 0 : */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ + +/* Register: TIMER_TASKS_CAPTURE */ +/* Description: Description collection[n]: Capture Timer value to CC[n] register */ + +/* Bit 0 : */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ + +/* Register: TIMER_EVENTS_COMPARE */ +/* Description: Description collection[n]: Compare event on CC[n] match */ + +/* Bit 0 : */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection[n]: Capture/Compare register n */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA */ + +/* Register: TWIM_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ + +/* Register: TWIM_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ + +/* Register: TWIM_TASKS_STOP */ +/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + +/* Bit 0 : */ +#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TWIM_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ + +/* Register: TWIM_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ + +/* Register: TWIM_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: TWIM_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: TWIM_EVENTS_SUSPENDED */ +/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ + +/* Bit 0 : */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ + +/* Register: TWIM_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ + +/* Register: TWIM_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ + +/* Register: TWIM_EVENTS_LASTRX */ +/* Description: Byte boundary, starting to receive the last byte */ + +/* Bit 0 : */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ + +/* Register: TWIM_EVENTS_LASTTX */ +/* Description: Byte boundary, starting to transmit the last byte */ + +/* Bit 0 : */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 12 : Shortcut between LASTRX event and STOP task */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between LASTRX event and SUSPEND task */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between LASTTX event and STOP task */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for LASTTX event */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for LASTRX event */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for LASTTX event */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for LASTRX event */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for LASTTX event */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for LASTRX event */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 9..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 9..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA */ + +/* Register: TWIS_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : */ +#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TWIS_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ + +/* Register: TWIS_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ + +/* Register: TWIS_TASKS_PREPARERX */ +/* Description: Prepare the TWI slave to respond to a write command */ + +/* Bit 0 : */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ + +/* Register: TWIS_TASKS_PREPARETX */ +/* Description: Prepare the TWI slave to respond to a read command */ + +/* Bit 0 : */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ + +/* Register: TWIS_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: TWIS_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: TWIS_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ + +/* Register: TWIS_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ + +/* Register: TWIS_EVENTS_WRITE */ +/* Description: Write command received */ + +/* Bit 0 : */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ + +/* Register: TWIS_EVENTS_READ */ +/* Description: Read command received */ + +/* Bit 0 : */ +#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 14 : Shortcut between READ event and SUSPEND task */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for READ event */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for WRITE event */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to enable interrupt for READ event */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for WRITE event */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to disable interrupt for READ event */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for WRITE event */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 9..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 9..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection[n]: TWI slave address n */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA */ + +/* Register: UARTE_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ + +/* Register: UARTE_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ + +/* Register: UARTE_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ + +/* Register: UARTE_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ + +/* Register: UARTE_TASKS_FLUSHRX */ +/* Description: Flush RX FIFO into RX buffer */ + +/* Bit 0 : */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ + +/* Register: UARTE_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ + +/* Register: UARTE_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ + +/* Register: UARTE_EVENTS_RXDRDY */ +/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ + +/* Bit 0 : */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ + +/* Register: UARTE_EVENTS_ENDRX */ +/* Description: Receive buffer is filled up */ + +/* Bit 0 : */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ + +/* Register: UARTE_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ + +/* Register: UARTE_EVENTS_ENDTX */ +/* Description: Last TX byte transmitted */ + +/* Bit 0 : */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ + +/* Register: UARTE_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: UARTE_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ + +/* Register: UARTE_EVENTS_RXSTARTED */ +/* Description: UART receiver has started */ + +/* Bit 0 : */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ + +/* Register: UARTE_EVENTS_TXSTARTED */ +/* Description: UART transmitter has started */ + +/* Bit 0 : */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ + +/* Register: UARTE_EVENTS_TXSTOPPED */ +/* Description: Transmitter stopped */ + +/* Bit 0 : */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for RXTO event */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDTX event */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDRX event */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for NCTS event */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for CTS event */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for CTS event */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for CTS event */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source Note : this register is read / write one to clear. */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 9..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 9..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User information configuration registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection[n]: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection[n]: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection[n]: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection[n]: Mapping of the nRESET function (see POWER chapter for details) */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 5..0 : GPIO number P0.n onto which reset is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access port protection */ + +/* Bits 7..0 : Enable or disable access port protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_TASKS_START */ +/* Description: Start the watchdog */ + +/* Bit 0 : */ +#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: WDT_EVENTS_TIMEOUT */ +/* Description: Watchdog timeout */ + +/* Bit 0 : */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection[n]: Reload request n */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810_peripherals.h new file mode 100755 index 0000000..2c31ccf --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52810_peripherals.h @@ -0,0 +1,209 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF52810_PERIPHERALS_H +#define _NRF52810_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAM_REGISTERS_PRESENT +#define POWER_FEATURE_RAM_REGISTERS_COUNT 3 + +/* Systick timer */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 48 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +#define RADIO_EASYDMA_MAXCNT_SIZE 8 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 16 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 20 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 6 +#define PPI_FEATURE_FORKS_PRESENT + +/* Event Generator Unit */ +#define EGU_PRESENT +#define EGU_COUNT 2 + +#define EGU0_CH_NUM 16 +#define EGU1_CH_NUM 16 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 32 +#define TIMER2_MAX_SIZE 32 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master with DMA */ +#define SPIM_PRESENT +#define SPIM_COUNT 1 + +#define SPIM0_MAX_DATARATE 8 + +#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 + +#define SPIM0_FEATURE_DCX_PRESENT 0 + +#define SPIM0_FEATURE_RXDELAY_PRESENT 0 + +#define SPIM0_EASYDMA_MAXCNT_SIZE 10 + +/* Serial Peripheral Interface Slave with DMA*/ +#define SPIS_PRESENT +#define SPIS_COUNT 1 + +#define SPIS0_EASYDMA_MAXCNT_SIZE 10 + +/* Two Wire Interface Master with DMA */ +#define TWIM_PRESENT +#define TWIM_COUNT 1 + +#define TWIM0_EASYDMA_MAXCNT_SIZE 10 + +/* Two Wire Interface Slave with DMA */ +#define TWIS_PRESENT +#define TWIS_COUNT 1 + +#define TWIS0_EASYDMA_MAXCNT_SIZE 10 + +/* Universal Asynchronous Receiver-Transmitter with DMA */ +#define UARTE_PRESENT +#define UARTE_COUNT 1 + +#define UARTE0_EASYDMA_MAXCNT_SIZE 10 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Successive Approximation Analog to Digital Converter */ +#define SAADC_PRESENT +#define SAADC_COUNT 1 + +#define SAADC_EASYDMA_MAXCNT_SIZE 15 + +#define SAADC_CH_NUM 8 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 8 + +#define GPIOTE_FEATURE_SET_PRESENT +#define GPIOTE_FEATURE_CLR_PRESENT + +/* Comparator */ +#define COMP_PRESENT +#define COMP_COUNT 1 + +/* Pulse Width Modulator */ +#define PWM_PRESENT +#define PWM_COUNT 1 + +#define PWM0_CH_NUM 4 + +#define PWM0_EASYDMA_MAXCNT_SIZE 15 + +/* Pulse Density Modulator */ +#define PDM_PRESENT +#define PDM_COUNT 1 + +#define PDM_EASYDMA_MAXCNT_SIZE 15 + + +#endif // _NRF52810_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52832_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52832_peripherals.h new file mode 100755 index 0000000..af81b05 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52832_peripherals.h @@ -0,0 +1,276 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF52832_PERIPHERALS_H +#define _NRF52832_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAM_REGISTERS_PRESENT +#define POWER_FEATURE_RAM_REGISTERS_COUNT 8 + +/* Floating Point Unit */ +#define FPU_PRESENT +#define FPU_COUNT 1 + +/* Systick timer */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* Memory Watch Unit */ +#define MWU_PRESENT +#define MWU_COUNT 1 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 128 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +#define RADIO_EASYDMA_MAXCNT_SIZE 8 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 16 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* NFC Tag */ +#define NFCT_PRESENT +#define NFCT_COUNT 1 + +#define NFCT_EASYDMA_MAXCNT_SIZE 9 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 20 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 6 +#define PPI_FEATURE_FORKS_PRESENT + +/* Event Generator Unit */ +#define EGU_PRESENT +#define EGU_COUNT 6 + +#define EGU0_CH_NUM 16 +#define EGU1_CH_NUM 16 +#define EGU2_CH_NUM 16 +#define EGU3_CH_NUM 16 +#define EGU4_CH_NUM 16 +#define EGU5_CH_NUM 16 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 5 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 32 +#define TIMER2_MAX_SIZE 32 +#define TIMER3_MAX_SIZE 32 +#define TIMER4_MAX_SIZE 32 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 +#define TIMER3_CC_NUM 6 +#define TIMER4_CC_NUM 6 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 3 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 +#define RTC2_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 3 + +/* Serial Peripheral Interface Master with DMA */ +#define SPIM_PRESENT +#define SPIM_COUNT 3 + +#define SPIM0_MAX_DATARATE 8 +#define SPIM1_MAX_DATARATE 8 +#define SPIM2_MAX_DATARATE 8 + +#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0 + +#define SPIM0_FEATURE_DCX_PRESENT 0 +#define SPIM1_FEATURE_DCX_PRESENT 0 +#define SPIM2_FEATURE_DCX_PRESENT 0 + +#define SPIM0_FEATURE_RXDELAY_PRESENT 0 +#define SPIM1_FEATURE_RXDELAY_PRESENT 0 +#define SPIM2_FEATURE_RXDELAY_PRESENT 0 + +#define SPIM0_EASYDMA_MAXCNT_SIZE 8 +#define SPIM1_EASYDMA_MAXCNT_SIZE 8 +#define SPIM2_EASYDMA_MAXCNT_SIZE 8 + +/* Serial Peripheral Interface Slave with DMA*/ +#define SPIS_PRESENT +#define SPIS_COUNT 3 + +#define SPIS0_EASYDMA_MAXCNT_SIZE 8 +#define SPIS1_EASYDMA_MAXCNT_SIZE 8 +#define SPIS2_EASYDMA_MAXCNT_SIZE 8 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Two Wire Interface Master with DMA */ +#define TWIM_PRESENT +#define TWIM_COUNT 2 + +#define TWIM0_EASYDMA_MAXCNT_SIZE 8 +#define TWIM1_EASYDMA_MAXCNT_SIZE 8 + +/* Two Wire Interface Slave with DMA */ +#define TWIS_PRESENT +#define TWIS_COUNT 2 + +#define TWIS0_EASYDMA_MAXCNT_SIZE 8 +#define TWIS1_EASYDMA_MAXCNT_SIZE 8 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Universal Asynchronous Receiver-Transmitter with DMA */ +#define UARTE_PRESENT +#define UARTE_COUNT 1 + +#define UARTE0_EASYDMA_MAXCNT_SIZE 8 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Successive Approximation Analog to Digital Converter */ +#define SAADC_PRESENT +#define SAADC_COUNT 1 + +#define SAADC_EASYDMA_MAXCNT_SIZE 15 + +#define SAADC_CH_NUM 8 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 8 + +#define GPIOTE_FEATURE_SET_PRESENT +#define GPIOTE_FEATURE_CLR_PRESENT + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 16 + +#define LPCOMP_FEATURE_HYST_PRESENT + +/* Comparator */ +#define COMP_PRESENT +#define COMP_COUNT 1 + +/* Pulse Width Modulator */ +#define PWM_PRESENT +#define PWM_COUNT 3 + +#define PWM0_CH_NUM 4 +#define PWM1_CH_NUM 4 +#define PWM2_CH_NUM 4 + +#define PWM0_EASYDMA_MAXCNT_SIZE 15 +#define PWM1_EASYDMA_MAXCNT_SIZE 15 +#define PWM2_EASYDMA_MAXCNT_SIZE 15 + +/* Pulse Density Modulator */ +#define PDM_PRESENT +#define PDM_COUNT 1 + +#define PDM_EASYDMA_MAXCNT_SIZE 15 + +/* Inter-IC Sound Interface */ +#define I2S_PRESENT +#define I2S_COUNT 1 + +#define I2S_EASYDMA_MAXCNT_SIZE 14 + + +#endif // _NRF52832_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840.h new file mode 100755 index 0000000..4d6287e --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840.h @@ -0,0 +1,2937 @@ +/* + * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52840.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 06. June 2018 + * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:39 + * from File 'nrf52840.svd', + * last modified on Wednesday, 06.06.2018 13:21:35 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52840 + * @{ + */ + + +#ifndef NRF52840_H +#define NRF52840_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38, /*!< 38 FPU */ + USBD_IRQn = 39, /*!< 39 USBD */ + UARTE1_IRQn = 40, /*!< 40 UARTE1 */ + QSPI_IRQn = 41, /*!< 41 QSPI */ + CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ + PWM3_IRQn = 45, /*!< 45 PWM3 */ + SPIM3_IRQn = 47 /*!< 47 SPIM3 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_nrf52840.h" /*!< nrf52840 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ + __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ +} FICR_INFO_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ + __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ + __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ + __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ + __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ + __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ + __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief FICR_NFC [NFC] (Unspecified) + */ +typedef struct { + __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ + __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) + */ +typedef struct { + __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ + __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ + __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ + __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ + __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ + __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ + __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ + __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ +} FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set + register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UART_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ +} UART_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ +} SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) + */ +typedef struct { + __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ + __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge + of SCK and minimum duration CSN must stay + high between transactions */ +} SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief TWI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ +} TWI_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) + */ +typedef struct { + __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ +} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief NFCT_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ + __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ +} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief NFCT_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ +} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last result is equal + or above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last result is equal + or below CH[n].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection + for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection + for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for + CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event + monitoring of a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written + to output RAM buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM + buffer since the previous START task */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in + RAM of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty + cycles) in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional + PWM periods between samples loaded into + compare register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the + sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select + for PWM channel n */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief ACL_ACL [ACL] (Unspecified) + */ +typedef struct { + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster[n]: Configure the word-aligned + start address of region n to protect */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster[n]: Size of region to protect + counting from address ACL[n].ADDR. Write + '0' as no effect. */ + __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster[n]: Access permissions for + region n as defined by start address ACL[n].ADDR + and size ACL[n].SIZE */ + __IOM uint32_t UNUSED0; /*!< (@ 0x0000000C) Unspecified */ +} ACL_ACL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group + n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group + n */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to region + n detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to region + n detected */ +} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to peripheral + region n detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to peripheral + region n detected */ +} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_PERREGION [PERREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[n]: Source of event/interrupt + in region n, write access detected while + corresponding subregion was enabled for + watching */ + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[n]: Source of event/interrupt + in region n, read access detected while + corresponding subregion was enabled for + watching */ +} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_REGION [REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Start address for region + n */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: End address of region + n */ + __IM uint32_t RESERVED[2]; +} MWU_REGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief MWU_PREGION [PREGION] (Unspecified) + */ +typedef struct { + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[n]: Subregions of region + n */ + __IM uint32_t RESERVED; +} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief I2S_CONFIG [CONFIG] (Unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ +} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + + +/** + * @brief I2S_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ +} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_RXTXD [RXTXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ +} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_HALTED [HALTED] (Unspecified) + */ +typedef struct { + __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection[n]: IN endpoint halted + status. Can be used as is as response to + a GetStatus() request to endpoint. */ + __IM uint32_t RESERVED; + __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection[n]: OUT endpoint halted + status. Can be used as is as response to + a GetStatus() request to endpoint. */ +} USBD_HALTED_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief USBD_SIZE [SIZE] (Unspecified) + */ +typedef struct { + __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection[n]: Number of bytes received + last in the data stage of this OUT endpoint */ + __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT + data endpoint */ +} USBD_SIZE_Type; /*!< Size = 36 (0x24) */ + + +/** + * @brief USBD_EPIN [EPIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPIN_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOIN [ISOIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief USBD_EPOUT [EPOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOOUT [ISOOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_READ [READ] (Unspecified) + */ +typedef struct { + __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ + __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ +} QSPI_READ_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_WRITE [WRITE] (Unspecified) + */ +typedef struct { + __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ + __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ +} QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_ERASE [ERASE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ + __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ +} QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief QSPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ + __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ + __IM uint32_t RESERVED; + __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ + __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ + __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ + __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ +} QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory information configuration registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word + n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity Root, word + n */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ + __IM uint32_t RESERVED3[21]; + __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[140]; + __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection[n]: Production test signature + n */ + __IM uint32_t RESERVED5[42]; + __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ + __IM uint32_t RESERVED6[2]; + __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ + __IM uint32_t RESERVED7[488]; + __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ +} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User information configuration registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ + __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ + __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ + __IM uint32_t RESERVED; + __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic + firmware design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic + hardware design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET + function */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ + __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: + NFC antenna or GPIO */ + __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ + __IM uint32_t RESERVED2[60]; + __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply + voltage in high voltage mode */ +} NRF_UICR_Type; /*!< Size = 776 (0x308) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready + to process new tasks */ + __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready + to process new tasks */ + __IM uint32_t RESERVED3[117]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED5; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED6[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering + the TASKS_HFCLKSTART task. */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ + __IM uint32_t RESERVED9[8]; + __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ +} NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ + __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ + __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ + __IM uint32_t RESERVED3[119]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ + __IM uint32_t RESERVED6[3]; + __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ + __IM uint32_t RESERVED7[49]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage. */ + __IM uint32_t RESERVED11; + __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage. */ + __IM uint32_t RESERVED12[47]; + __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ + __IM uint32_t RESERVED13[175]; + __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ + __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ + __IM uint32_t RESERVED[51]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ + __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new + ED sample is ready for readout from the + RADIO.EDSAMPLE register. */ + __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ + __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ + __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ + __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ + __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed + from Ble_LR125Kbit to Ble_LR500Kbit. */ + __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started + TX path */ + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started + RX path */ + __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and + BleIeee802154_250Kbit modes when last bit + is sent on air. */ + __IM uint32_t RESERVED4[36]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED7; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ + __IM uint32_t RESERVED8[59]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IM uint32_t RESERVED9; + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED10; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED12[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base + segment n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix + n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ + __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ + __IM uint32_t RESERVED13; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED14[3]; + __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ + __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ + __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ + __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ + __IM uint32_t RESERVED15[611]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA 0 (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write + one to clear. */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI0) + */ + +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[61]; + __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields + in this register is set to STALL by hardware + whenever a stall occurres and can be cleared + (set to NOSTALL) by the CPU. */ + __IM uint32_t RESERVED10[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED11; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED14[2]; + __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ + __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ + __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ + __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ + __IM uint32_t RESERVED15[19]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have + been transmitted in the case when RXD.MAXCNT + is greater than TXD.MAXCNT */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IM uint32_t RESERVED11; + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IM uint32_t RESERVED12; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED14[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND + task has been issued, TWI traffic is now + suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED13; + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[14]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address + n */ + __IM uint32_t RESERVED15; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED16[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ NFCT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< (@ 0x40005000) NFCT Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing + frames, change state to activated */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ + __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to + sense mode */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change + state to transmit */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ + __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send + frames */ + __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ + __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ + __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted + frame */ + __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air + symbol of a frame */ + __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received + frame */ + __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) + and transferred to RAM, and EasyDMA has + ended accessing the RX buffer */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register + contains details on the source of the error. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX + register contains details on the source + of the error. */ + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) + in Data RAM full. */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA + has ended accessing the TX buffer */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ + __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ + __IM uint32_t RESERVED6[43]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[62]; + __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ + __IM uint32_t RESERVED9; + __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ + __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ + __IM uint32_t RESERVED10[3]; + __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ + __IM uint32_t RESERVED11[6]; + __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ + __IM uint32_t RESERVED12[49]; + __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ + __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ + __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in + Data RAM */ + __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD + data storage each */ + __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ + __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ + __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. + This setting must be done before the NFCT + peripheral is enabled. */ + __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ + __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to + pin specified in CONFIG[n].PSEL. Action + on pin is configured in CONFIG[n].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to + pin specified in CONFIG[n].PSEL. Action + on pin is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to + pin specified in CONFIG[n].PSEL. Action + on pin is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from + pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for + OUT[n], SET[n] and CLR[n] tasks and IN[n] + event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) + */ + +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer + in RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the configuration, multiple conversions + might be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is + applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value + to CC[n] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register + n */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu + t be written when RTC is stopped */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with + the contents of the RATEOVERRIDE register + for any ongoing encryption/decryption */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + = Extended. */ + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ +} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low Power Comparator (LPCOMP) + */ + +typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event Generator Unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering + the corresponding TRIGGERED[n] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated + by triggering the corresponding TRIGGER[n] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse width modulation unit 0 (PWM0) + */ + +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM + value on all enabled channels from sequence + n, and starts playing that sequence at the + rate defined in SEQ[n]REFRESH and/or DECODER.MODE. + Causes PWM generation to start if not running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start if + not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started + on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of + every sequence n, when last value from RAM + has been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output + sample rate. Change PDMCLKCTRL accordingly. */ + __IM uint32_t RESERVED4[7]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ ACL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access control lists (ACL) + */ + +typedef struct { /*!< (@ 0x4001E000) ACL Structure */ + __IM uint32_t RESERVED[512]; + __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ +} NRF_ACL_Type; /*!< Size = 2176 (0x880) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1; + __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ + __IM uint32_t RESERVED2[62]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area. Equivalent to ERASEPAGE. */ + }; + __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area. Equivalent to ERASEPAGE. */ + __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + registers */ + __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + area */ + __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ + __IM uint32_t RESERVED3[8]; + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register. */ + __IM uint32_t RESERVED4; + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter. */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter. */ +} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ MWU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< (@ 0x40020000) MWU Structure */ + __IM uint32_t RESERVED[64]; + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ + __IM uint32_t RESERVED1[16]; + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ + __IM uint32_t RESERVED2[100]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ + __IM uint32_t RESERVED4[53]; + __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ + __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ + __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ + __IM uint32_t RESERVED6[57]; + __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ + __IM uint32_t RESERVED7[32]; + __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ +} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< (@ 0x40025000) I2S Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. + Triggering this task will cause the {event:STOPPED} + event to be generated. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started + and RX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started + and TX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __IM uint32_t RESERVED2[122]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ + __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ + __IM uint32_t RESERVED4[3]; + __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ + __IM uint32_t RESERVED5; + __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED6[3]; + __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ + __IM uint32_t RESERVED7[3]; + __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ FPU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< (@ 0x40026000) FPU Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_FPU_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ USBD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal serial bus device (USBD) + */ + +typedef struct { /*!< (@ 0x40027000) USBD Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection[n]: Captures the EPIN[n].PTR + and EPIN[n].MAXCNT registers values, and + enables endpoint IN n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers + values, and enables sending data on ISO + endpoint */ + __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection[n]: Captures the EPOUT[n].PTR + and EPOUT[n].MAXCNT registers values, and + enables endpoint n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers + values, and enables receiving of data on + ISO endpoint */ + __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint + 0 */ + __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined + in the DPDMVALUE register */ + __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state + (USB engine takes control) */ + __IM uint32_t RESERVED1[40]; + __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected + on USB lines */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, + or EPOUT[n].PTR and EPOUT[n].MAXCNT registers + have been captured on all endpoints reported + in the EPSTATUS register */ + __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection[n]: The whole EPIN[n] + buffer has been consumed. The RAM buffer + can be accessed safely by software. */ + __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place + on the control endpoint */ + __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The + RAM buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection[n]: The whole EPOUT[n] + buffer has been consumed. The RAM buffer + can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The + RAM buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition + has been detected on USB lines */ + __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific + events has occurred. Check EVENTCAUSE register + to find the cause. */ + __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) + on the control endpoint */ + __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, + indicated by the EPDATASTATUS register */ + __IM uint32_t RESERVED2[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ + __IM uint32_t RESERVED5[7]; + __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ + __IM uint32_t RESERVED6; + __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA + registers have been captured */ + __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an + acknowledged data transfer has occurred + (EPDATA event) */ + __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ + __IM uint32_t RESERVED7[3]; + __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ + __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ + __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ + __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ + __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ + __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ + __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ + __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ + __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ + __IM uint32_t RESERVED8[15]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ + __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ + __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by + the DPDMDRIVE task. The DPDMNODRIVE task + reverts the control of the lines to MAC + IP (no forcing). */ + __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ + __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ + __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ + __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ + __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ + __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame + counter */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during + USB suspend */ + __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint + to an IN token when no data is ready to + be sent */ + __IM uint32_t RESERVED10[51]; + __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ + __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ + __IM uint32_t RESERVED11[21]; + __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ + __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ +} NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ + + + +/* =========================================================================================================================== */ +/* ================ QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External flash interface (QSPI) + */ + +typedef struct { /*!< (@ 0x40029000) QSPI Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ + __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to + internal RAM */ + __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external + flash memory */ + __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ + __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be + generated as a response to any QSPI task. */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected + in PSELn registers */ + __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ + __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ + __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ + __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ + __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute + in Place operation. */ + __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ + __IM uint32_t RESERVED3[46]; + __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ + __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep + power-down mode (DPM). */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ + __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ + __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ + __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ +} NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + +/* =========================================================================================================================== */ +/* ================ CC_HOST_RGF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) + */ + +typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ + __IM uint32_t RESERVED[1678]; + __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. + When this register is set, K_PRTL can not + be used and a zeroed key will be used instead. + The value of this register is saved in the + CRYPTOCELL AO power domain. */ + __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. Reading from this address + returns the K_DR valid status indicating + if K_DR is successfully retained. */ + __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The + value of this register is saved in the CRYPTOCELL + AO power domain. */ + __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL + subsystem */ +} NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ + + + +/* =========================================================================================================================== */ +/* ================ CRYPTOCELL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) + */ + +typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ + __IM uint32_t RESERVED[320]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ +} NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_ACL_BASE 0x4001E000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_USBD_BASE 0x40027000UL +#define NRF_UARTE1_BASE 0x40028000UL +#define NRF_QSPI_BASE 0x40029000UL +#define NRF_PWM3_BASE 0x4002D000UL +#define NRF_SPIM3_BASE 0x4002F000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_P1_BASE 0x50000300UL +#define NRF_CC_HOST_RGF_BASE 0x5002A000UL +#define NRF_CRYPTOCELL_BASE 0x5002A000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) +#define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) +#define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) +#define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) +#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) +#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) +#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) +#define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) +#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52840_H */ + + +/** @} */ /* End of group nrf52840 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840_bitfields.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840_bitfields.h new file mode 100755 index 0000000..6d1990b --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840_bitfields.h @@ -0,0 +1,16906 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF52840_BITS_H +#define __NRF52840_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_TASKS_START */ +/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ + +/* Bit 0 : */ +#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: AAR_TASKS_STOP */ +/* Description: Stop resolving addresses */ + +/* Bit 0 : */ +#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: AAR_EVENTS_END */ +/* Description: Address resolution procedure complete */ + +/* Bit 0 : */ +#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: AAR_EVENTS_RESOLVED */ +/* Description: Address resolved */ + +/* Bit 0 : */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ + +/* Register: AAR_EVENTS_NOTRESOLVED */ +/* Description: Address not resolved */ + +/* Bit 0 : */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for RESOLVED event */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for END event */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for RESOLVED event */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for END event */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: ACL */ +/* Description: Access control lists */ + +/* Register: ACL_ACL_ADDR */ +/* Description: Description cluster[n]: Configure the word-aligned start address of region n to protect */ + +/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ +#define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ +#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* Register: ACL_ACL_SIZE */ +/* Description: Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ + +/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. */ +#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: ACL_ACL_PERM */ +/* Description: Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ + +/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ +#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ +#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ + +/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ +#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ +#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_TASKS_KSGEN */ +/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ + +/* Bit 0 : */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ + +/* Register: CCM_TASKS_CRYPT */ +/* Description: Start encryption/decryption. This operation will stop by itself when completed. */ + +/* Bit 0 : */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ + +/* Register: CCM_TASKS_STOP */ +/* Description: Stop encryption/decryption */ + +/* Bit 0 : */ +#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: CCM_TASKS_RATEOVERRIDE */ +/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ + +/* Bit 0 : */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ + +/* Register: CCM_EVENTS_ENDKSGEN */ +/* Description: Key-stream generation complete */ + +/* Bit 0 : */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ + +/* Register: CCM_EVENTS_ENDCRYPT */ +/* Description: Encrypt/decrypt complete */ + +/* Bit 0 : */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ + +/* Register: CCM_EVENTS_ERROR */ +/* Description: Deprecated register - CCM error event */ + +/* Bit 0 : */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for ERROR event */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for ERROR event */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ + +/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ + +/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + +/* Register: CCM_MAXPACKETSIZE */ +/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ + +/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ + +/* Register: CCM_RATEOVERRIDE */ +/* Description: Data rate override setting. */ + +/* Bits 1..0 : Data rate override setting. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ + + +/* Peripheral: CC_HOST_RGF */ +/* Description: CRYPTOCELL HOST_RGF interface */ + +/* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */ +/* Description: AES hardware key select */ + +/* Bits 1..0 : Select the source of the HW key that is used by the AES engine */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ + +/* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ +/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ +/* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ + +/* Bits 31..0 : Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR1 */ +/* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 63:32 */ +#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR2 */ +/* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 95:64 */ +#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_KDR3 */ +/* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ + +/* Bits 31..0 : K_DR bits 127:96 */ +#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */ +#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */ + +/* Register: CC_HOST_RGF_HOST_IOT_LCS */ +/* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ + +/* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< A valid LCS is not yet retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< A valid LCS is successfully retained in the CRYPTOCELL AO power domain */ + +/* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_TASKS_HFCLKSTART */ +/* Description: Start HFXO crystal oscillator */ + +/* Bit 0 : */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ + +/* Register: CLOCK_TASKS_HFCLKSTOP */ +/* Description: Stop HFXO crystal oscillator */ + +/* Bit 0 : */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ + +/* Register: CLOCK_TASKS_LFCLKSTART */ +/* Description: Start LFCLK */ + +/* Bit 0 : */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ + +/* Register: CLOCK_TASKS_LFCLKSTOP */ +/* Description: Stop LFCLK */ + +/* Bit 0 : */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ + +/* Register: CLOCK_TASKS_CAL */ +/* Description: Start calibration of LFRC */ + +/* Bit 0 : */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ + +/* Register: CLOCK_TASKS_CTSTART */ +/* Description: Start calibration timer */ + +/* Bit 0 : */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ + +/* Register: CLOCK_TASKS_CTSTOP */ +/* Description: Stop calibration timer */ + +/* Bit 0 : */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ + +/* Register: CLOCK_EVENTS_HFCLKSTARTED */ +/* Description: HFXO crystal oscillator started */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ + +/* Register: CLOCK_EVENTS_LFCLKSTARTED */ +/* Description: LFCLK started */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ + +/* Register: CLOCK_EVENTS_DONE */ +/* Description: Calibration of LFRC completed */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ + +/* Register: CLOCK_EVENTS_CTTO */ +/* Description: Calibration timer timeout */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ + +/* Register: CLOCK_EVENTS_CTSTARTED */ +/* Description: Calibration timer has been started and is ready to process new tasks */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */ + +/* Register: CLOCK_EVENTS_CTSTOPPED */ +/* Description: Calibration timer has been stopped and is ready to process new tasks */ + +/* Bit 0 : */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 11 : Write '1' to enable interrupt for CTSTOPPED event */ +#define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ +#define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ +#define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for CTSTARTED event */ +#define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ +#define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ +#define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for CTTO event */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for DONE event */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 11 : Write '1' to disable interrupt for CTSTOPPED event */ +#define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ +#define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ +#define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for CTSTARTED event */ +#define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ +#define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ +#define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for CTTO event */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for DONE event */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ + +/* Register: CLOCK_HFXODEBOUNCE */ +/* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */ + +/* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. */ +#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_TRACECONFIG */ +/* Description: Clocking options for the trace port debug interface */ + +/* Bits 17..16 : Pin multiplexing of trace signals. See pin assignment chapter for more details. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< No trace signals routed to pins. All pins can be used as regular GPIOs. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. */ + +/* Bits 1..0 : Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz trace port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz trace port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) */ + +/* Register: CLOCK_LFRCMODE */ +/* Description: LFRC mode configuration */ + +/* Bit 16 : Active LFRC mode. This field is read only. */ +#define CLOCK_LFRCMODE_STATUS_Pos (16UL) /*!< Position of STATUS field. */ +#define CLOCK_LFRCMODE_STATUS_Msk (0x1UL << CLOCK_LFRCMODE_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFRCMODE_STATUS_Normal (0UL) /*!< Normal mode */ +#define CLOCK_LFRCMODE_STATUS_ULP (1UL) /*!< Ultra-low power mode (ULP) */ + +/* Bit 0 : Set LFRC mode */ +#define CLOCK_LFRCMODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CLOCK_LFRCMODE_MODE_Msk (0x1UL << CLOCK_LFRCMODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CLOCK_LFRCMODE_MODE_Normal (0UL) /*!< Normal mode */ +#define CLOCK_LFRCMODE_MODE_ULP (1UL) /*!< Ultra-low power mode (ULP) */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_TASKS_START */ +/* Description: Start comparator */ + +/* Bit 0 : */ +#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: COMP_TASKS_STOP */ +/* Description: Stop comparator */ + +/* Bit 0 : */ +#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: COMP_TASKS_SAMPLE */ +/* Description: Sample comparator value */ + +/* Bit 0 : */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ + +/* Register: COMP_EVENTS_READY */ +/* Description: COMP is ready and output is valid */ + +/* Bit 0 : */ +#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ + +/* Register: COMP_EVENTS_DOWN */ +/* Description: Downward crossing */ + +/* Bit 0 : */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ + +/* Register: COMP_EVENTS_UP */ +/* Description: Upward crossing */ + +/* Bit 0 : */ +#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ + +/* Register: COMP_EVENTS_CROSS */ +/* Description: Downward or upward crossing */ + +/* Bit 0 : */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for CROSS event */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for UP event */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for DOWN event */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for UP event */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for READY event */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for UP event */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for READY event */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select for single-ended mode */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bits 2..0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation modes */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power modes */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + + +/* Peripheral: CRYPTOCELL */ +/* Description: ARM TrustZone CryptoCell register interface */ + +/* Register: CRYPTOCELL_ENABLE */ +/* Description: Enable CRYPTOCELL subsystem */ + +/* Bit 0 : Enable or disable the CRYPTOCELL subsystem */ +#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_TASKS_STARTECB */ +/* Description: Start ECB block encrypt */ + +/* Bit 0 : */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ + +/* Register: ECB_TASKS_STOPECB */ +/* Description: Abort a possible executing ECB operation */ + +/* Bit 0 : */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ + +/* Register: ECB_EVENTS_ENDECB */ +/* Description: ECB block encrypt complete */ + +/* Bit 0 : */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ + +/* Register: ECB_EVENTS_ERRORECB */ +/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ + +/* Bit 0 : */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to enable interrupt for ERRORECB event */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for ENDECB event */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to disable interrupt for ERRORECB event */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for ENDECB event */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_TASKS_TRIGGER */ +/* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event */ + +/* Bit 0 : */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ + +/* Register: EGU_EVENTS_TRIGGERED */ +/* Description: Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task */ + +/* Bit 0 : */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory information configuration registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection[n]: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection[n]: Encryption root, word n */ + +/* Bits 31..0 : Encryption root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection[n]: Identity Root, word n */ + +/* Bits 31..0 : Identity Root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection[n]: Device address n */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Build code (hardware version and production configuration) */ + +/* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ +#define FICR_INFO_VARIANT_VARIANT_BAAA (0x42414141UL) /*!< BAAA */ +#define FICR_INFO_VARIANT_VARIANT_CAAA (0x43414141UL) /*!< CAAA */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ +#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */ +#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_PRODTEST */ +/* Description: Description collection[n]: Production test signature n */ + +/* Bits 31..0 : Production test signature n */ +#define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */ +#define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */ +#define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */ +#define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5 */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: Y-intercept B0 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: Y-intercept B1 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: Y-intercept B2 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: Y-intercept B3 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: Y-intercept B4 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: Y-intercept B5 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_NFC_TAGHEADER0 */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 3 */ +#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ +#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ + +/* Bits 23..16 : Unique identifier byte 2 */ +#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ +#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ + +/* Bits 15..8 : Unique identifier byte 1 */ +#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ +#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ + +/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ +#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ +#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ + +/* Register: FICR_NFC_TAGHEADER1 */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 7 */ +#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ +#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ + +/* Bits 23..16 : Unique identifier byte 6 */ +#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ +#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ + +/* Bits 15..8 : Unique identifier byte 5 */ +#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ +#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ + +/* Bits 7..0 : Unique identifier byte 4 */ +#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ +#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ + +/* Register: FICR_NFC_TAGHEADER2 */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 11 */ +#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ +#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ + +/* Bits 23..16 : Unique identifier byte 10 */ +#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ +#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ + +/* Bits 15..8 : Unique identifier byte 9 */ +#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ +#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ + +/* Bits 7..0 : Unique identifier byte 8 */ +#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ +#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ + +/* Register: FICR_NFC_TAGHEADER3 */ +/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 15 */ +#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ +#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ + +/* Bits 23..16 : Unique identifier byte 14 */ +#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ +#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ + +/* Bits 15..8 : Unique identifier byte 13 */ +#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ +#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ + +/* Bits 7..0 : Unique identifier byte 12 */ +#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ +#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ + +/* Register: FICR_TRNG90B_BYTES */ +/* Description: Amount of bytes for the required entropy bits */ + +/* Bits 31..0 : Amount of bytes for the required entropy bits */ +#define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */ +#define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */ + +/* Register: FICR_TRNG90B_RCCUTOFF */ +/* Description: Repetition counter cutoff */ + +/* Bits 31..0 : Repetition counter cutoff */ +#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */ +#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */ + +/* Register: FICR_TRNG90B_APCUTOFF */ +/* Description: Adaptive proportion cutoff */ + +/* Bits 31..0 : Adaptive proportion cutoff */ +#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */ +#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */ + +/* Register: FICR_TRNG90B_STARTUP */ +/* Description: Amount of bytes for the startup tests */ + +/* Bits 31..0 : Amount of bytes for the startup tests */ +#define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */ +#define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */ + +/* Register: FICR_TRNG90B_ROSC1 */ +/* Description: Sample count for ring oscillator 1 */ + +/* Bits 31..0 : Sample count for ring oscillator 1 */ +#define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */ +#define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */ + +/* Register: FICR_TRNG90B_ROSC2 */ +/* Description: Sample count for ring oscillator 2 */ + +/* Bits 31..0 : Sample count for ring oscillator 2 */ +#define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */ +#define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */ + +/* Register: FICR_TRNG90B_ROSC3 */ +/* Description: Sample count for ring oscillator 3 */ + +/* Bits 31..0 : Sample count for ring oscillator 3 */ +#define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */ +#define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */ + +/* Register: FICR_TRNG90B_ROSC4 */ +/* Description: Sample count for ring oscillator 4 */ + +/* Bits 31..0 : Sample count for ring oscillator 4 */ +#define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */ +#define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_TASKS_OUT */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + +/* Bit 0 : */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ + +/* Register: GPIOTE_TASKS_SET */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + +/* Bit 0 : */ +#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ + +/* Register: GPIOTE_TASKS_CLR */ +/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + +/* Bit 0 : */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ + +/* Register: GPIOTE_EVENTS_IN */ +/* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */ + +/* Bit 0 : */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ + +/* Register: GPIOTE_EVENTS_PORT */ +/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ + +/* Bit 0 : */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to enable interrupt for PORT event */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for IN[7] event */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for IN[6] event */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for IN[5] event */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for IN[4] event */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for IN[3] event */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for IN[2] event */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for IN[1] event */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for IN[0] event */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to disable interrupt for PORT event */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for IN[7] event */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for IN[6] event */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for IN[5] event */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for IN[4] event */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for IN[3] event */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for IN[2] event */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for IN[1] event */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for IN[0] event */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bit 13 : Port number */ +#define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */ +#define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: I2S */ +/* Description: Inter-IC Sound */ + +/* Register: I2S_TASKS_START */ +/* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ + +/* Bit 0 : */ +#define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: I2S_TASKS_STOP */ +/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. */ + +/* Bit 0 : */ +#define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: I2S_EVENTS_RXPTRUPD */ +/* Description: The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ + +/* Bit 0 : */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ + +/* Register: I2S_EVENTS_STOPPED */ +/* Description: I2S transfer stopped. */ + +/* Bit 0 : */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: I2S_EVENTS_TXPTRUPD */ +/* Description: The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ + +/* Bit 0 : */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ + +/* Register: I2S_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for STOPPED event */ +#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 5 : Write '1' to enable interrupt for TXPTRUPD event */ +#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for STOPPED event */ +#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for RXPTRUPD event */ +#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ + +/* Register: I2S_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 5 : Write '1' to disable interrupt for TXPTRUPD event */ +#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for STOPPED event */ +#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for RXPTRUPD event */ +#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Register: I2S_ENABLE */ +/* Description: Enable I2S module. */ + +/* Bit 0 : Enable I2S module. */ +#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_CONFIG_MODE */ +/* Description: I2S mode. */ + +/* Bit 0 : I2S mode. */ +#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ + +/* Register: I2S_CONFIG_RXEN */ +/* Description: Reception (RX) enable. */ + +/* Bit 0 : Reception (RX) enable. */ +#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: I2S_CONFIG_TXEN */ +/* Description: Transmission (TX) enable. */ + +/* Bit 0 : Transmission (TX) enable. */ +#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ + +/* Register: I2S_CONFIG_MCKEN */ +/* Description: Master clock generator enable. */ + +/* Bit 0 : Master clock generator enable. */ +#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + +/* Register: I2S_CONFIG_MCKFREQ */ +/* Description: Master clock generator frequency. */ + +/* Bits 31..0 : Master clock generator frequency. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ + +/* Register: I2S_CONFIG_RATIO */ +/* Description: MCK / LRCK ratio. */ + +/* Bits 3..0 : MCK / LRCK ratio. */ +#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ + +/* Register: I2S_CONFIG_SWIDTH */ +/* Description: Sample width. */ + +/* Bits 1..0 : Sample width. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ + +/* Register: I2S_CONFIG_ALIGN */ +/* Description: Alignment of sample within a frame. */ + +/* Bit 0 : Alignment of sample within a frame. */ +#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ + +/* Register: I2S_CONFIG_FORMAT */ +/* Description: Frame format. */ + +/* Bit 0 : Frame format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ + +/* Register: I2S_CONFIG_CHANNELS */ +/* Description: Enable channels. */ + +/* Bits 1..0 : Enable channels. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ + +/* Register: I2S_RXD_PTR */ +/* Description: Receive buffer RAM start address. */ + +/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ +#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_TXD_PTR */ +/* Description: Transmit buffer RAM start address. */ + +/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ +#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_RXTXD_MAXCNT */ +/* Description: Size of RXD and TXD buffers. */ + +/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: I2S_PSEL_MCK */ +/* Description: Pin select for MCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SCK */ +/* Description: Pin select for SCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_LRCK */ +/* Description: Pin select for LRCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDIN */ +/* Description: Pin select for SDIN signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDOUT */ +/* Description: Pin select for SDOUT signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low Power Comparator */ + +/* Register: LPCOMP_TASKS_START */ +/* Description: Start comparator */ + +/* Bit 0 : */ +#define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: LPCOMP_TASKS_STOP */ +/* Description: Stop comparator */ + +/* Bit 0 : */ +#define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: LPCOMP_TASKS_SAMPLE */ +/* Description: Sample comparator value */ + +/* Bit 0 : */ +#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ + +/* Register: LPCOMP_EVENTS_READY */ +/* Description: LPCOMP is ready and output is valid */ + +/* Bit 0 : */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ + +/* Register: LPCOMP_EVENTS_DOWN */ +/* Description: Downward crossing */ + +/* Bit 0 : */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ + +/* Register: LPCOMP_EVENTS_UP */ +/* Description: Upward crossing */ + +/* Bit 0 : */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ + +/* Register: LPCOMP_EVENTS_CROSS */ +/* Description: Downward or upward crossing */ + +/* Bit 0 : */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for UP event */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for READY event */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for UP event */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for READY event */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: LPCOMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable LPCOMP */ + +/* Bits 1..0 : Enable or disable LPCOMP */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select */ + +/* Bits 2..0 : Analog pin select */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select */ + +/* Bits 3..0 : Reference select */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ +#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration */ + +/* Bits 1..0 : Analog detect configuration */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ + +/* Register: LPCOMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis enable */ +#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */ +#define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */ + + +/* Peripheral: MWU */ +/* Description: Memory Watch Unit */ + +/* Register: MWU_EVENTS_REGION_WA */ +/* Description: Description cluster[n]: Write access to region n detected */ + +/* Bit 0 : */ +#define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ +#define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */ + +/* Register: MWU_EVENTS_REGION_RA */ +/* Description: Description cluster[n]: Read access to region n detected */ + +/* Bit 0 : */ +#define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ +#define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */ + +/* Register: MWU_EVENTS_PREGION_WA */ +/* Description: Description cluster[n]: Write access to peripheral region n detected */ + +/* Bit 0 : */ +#define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ +#define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */ + +/* Register: MWU_EVENTS_PREGION_RA */ +/* Description: Description cluster[n]: Read access to peripheral region n detected */ + +/* Bit 0 : */ +#define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ +#define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */ + +/* Register: MWU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to enable interrupt for PREGION[1].RA event */ +#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to enable interrupt for PREGION[1].WA event */ +#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for PREGION[0].RA event */ +#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to enable interrupt for PREGION[0].WA event */ +#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for REGION[3].RA event */ +#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for REGION[3].WA event */ +#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for REGION[2].RA event */ +#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for REGION[2].WA event */ +#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for REGION[1].RA event */ +#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for REGION[1].WA event */ +#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for REGION[0].RA event */ +#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for REGION[0].WA event */ +#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to disable interrupt for PREGION[1].RA event */ +#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to disable interrupt for PREGION[1].WA event */ +#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for PREGION[0].RA event */ +#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to disable interrupt for PREGION[0].WA event */ +#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for REGION[3].RA event */ +#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for REGION[3].WA event */ +#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for REGION[2].RA event */ +#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for REGION[2].WA event */ +#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for REGION[1].RA event */ +#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for REGION[1].WA event */ +#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for REGION[0].RA event */ +#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for REGION[0].WA event */ +#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_NMIEN */ +/* Description: Enable or disable non-maskable interrupt */ + +/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_NMIENSET */ +/* Description: Enable non-maskable interrupt */ + +/* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_NMIENCLR */ +/* Description: Disable non-maskable interrupt */ + +/* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_PERREGION_SUBSTATWA */ +/* Description: Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Register: MWU_PERREGION_SUBSTATRA */ +/* Description: Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region n (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Register: MWU_REGIONEN */ +/* Description: Enable/disable regions watch */ + +/* Bit 27 : Enable/disable read access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable/disable write access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable/disable read access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable/disable write access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable/disable read access watch in region[3] */ +#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable/disable write access watch in region[3] */ +#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable/disable read access watch in region[2] */ +#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable/disable write access watch in region[2] */ +#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable/disable read access watch in region[1] */ +#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable/disable write access watch in region[1] */ +#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable/disable read access watch in region[0] */ +#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable/disable write access watch in region[0] */ +#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENSET */ +/* Description: Enable regions watch */ + +/* Bit 27 : Enable read access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable write access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable read access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable write access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable read access watch in region[3] */ +#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable write access watch in region[3] */ +#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable read access watch in region[2] */ +#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable write access watch in region[2] */ +#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable read access watch in region[1] */ +#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable write access watch in region[1] */ +#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable read access watch in region[0] */ +#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable write access watch in region[0] */ +#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENCLR */ +/* Description: Disable regions watch */ + +/* Bit 27 : Disable read access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 26 : Disable write access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 25 : Disable read access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 24 : Disable write access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 7 : Disable read access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 6 : Disable write access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 5 : Disable read access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 4 : Disable write access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 3 : Disable read access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 2 : Disable write access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 1 : Disable read access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 0 : Disable write access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Register: MWU_REGION_START */ +/* Description: Description cluster[n]: Start address for region n */ + +/* Bits 31..0 : Start address for region */ +#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_REGION_END */ +/* Description: Description cluster[n]: End address of region n */ + +/* Bits 31..0 : End address of region. */ +#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_START */ +/* Description: Description cluster[n]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_PREGION_END */ +/* Description: Description cluster[n]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_SUBS */ +/* Description: Description cluster[n]: Subregions of region n */ + +/* Bit 31 : Include or exclude subregion 31 in region */ +#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude subregion 30 in region */ +#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude subregion 29 in region */ +#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude subregion 28 in region */ +#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude subregion 27 in region */ +#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude subregion 26 in region */ +#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude subregion 25 in region */ +#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude subregion 24 in region */ +#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude subregion 23 in region */ +#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude subregion 22 in region */ +#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude subregion 21 in region */ +#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude subregion 20 in region */ +#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude subregion 19 in region */ +#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude subregion 18 in region */ +#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude subregion 17 in region */ +#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude subregion 16 in region */ +#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude subregion 15 in region */ +#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude subregion 14 in region */ +#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude subregion 13 in region */ +#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude subregion 12 in region */ +#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude subregion 11 in region */ +#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude subregion 10 in region */ +#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude subregion 9 in region */ +#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude subregion 8 in region */ +#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude subregion 7 in region */ +#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude subregion 6 in region */ +#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude subregion 5 in region */ +#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude subregion 4 in region */ +#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude subregion 3 in region */ +#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude subregion 2 in region */ +#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude subregion 1 in region */ +#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude subregion 0 in region */ +#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ + + +/* Peripheral: NFCT */ +/* Description: NFC-A compatible radio */ + +/* Register: NFCT_TASKS_ACTIVATE */ +/* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ + +/* Bit 0 : */ +#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ +#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ + +/* Register: NFCT_TASKS_DISABLE */ +/* Description: Disable NFCT peripheral */ + +/* Bit 0 : */ +#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ +#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ + +/* Register: NFCT_TASKS_SENSE */ +/* Description: Enable NFC sense field mode, change state to sense mode */ + +/* Bit 0 : */ +#define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */ +#define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */ + +/* Register: NFCT_TASKS_STARTTX */ +/* Description: Start transmission of an outgoing frame, change state to transmit */ + +/* Bit 0 : */ +#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ + +/* Register: NFCT_TASKS_ENABLERXDATA */ +/* Description: Initializes the EasyDMA for receive. */ + +/* Bit 0 : */ +#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */ +#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */ + +/* Register: NFCT_TASKS_GOIDLE */ +/* Description: Force state machine to IDLE state */ + +/* Bit 0 : */ +#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */ +#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */ + +/* Register: NFCT_TASKS_GOSLEEP */ +/* Description: Force state machine to SLEEP_A state */ + +/* Bit 0 : */ +#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */ +#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */ + +/* Register: NFCT_EVENTS_READY */ +/* Description: The NFCT peripheral is ready to receive and send frames */ + +/* Bit 0 : */ +#define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ + +/* Register: NFCT_EVENTS_FIELDDETECTED */ +/* Description: Remote NFC field detected */ + +/* Bit 0 : */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */ + +/* Register: NFCT_EVENTS_FIELDLOST */ +/* Description: Remote NFC field lost */ + +/* Bit 0 : */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */ + +/* Register: NFCT_EVENTS_TXFRAMESTART */ +/* Description: Marks the start of the first symbol of a transmitted frame */ + +/* Bit 0 : */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */ + +/* Register: NFCT_EVENTS_TXFRAMEEND */ +/* Description: Marks the end of the last transmitted on-air symbol of a frame */ + +/* Bit 0 : */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */ + +/* Register: NFCT_EVENTS_RXFRAMESTART */ +/* Description: Marks the end of the first symbol of a received frame */ + +/* Bit 0 : */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */ + +/* Register: NFCT_EVENTS_RXFRAMEEND */ +/* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ + +/* Bit 0 : */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */ + +/* Register: NFCT_EVENTS_ERROR */ +/* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ + +/* Bit 0 : */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: NFCT_EVENTS_RXERROR */ +/* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ + +/* Bit 0 : */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */ + +/* Register: NFCT_EVENTS_ENDRX */ +/* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + +/* Bit 0 : */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ + +/* Register: NFCT_EVENTS_ENDTX */ +/* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ + +/* Bit 0 : */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ + +/* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */ +/* Description: Auto collision resolution process has started */ + +/* Bit 0 : */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */ + +/* Register: NFCT_EVENTS_COLLISION */ +/* Description: NFC auto collision resolution error reported. */ + +/* Bit 0 : */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */ + +/* Register: NFCT_EVENTS_SELECTED */ +/* Description: NFC auto collision resolution successfully completed */ + +/* Bit 0 : */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */ + +/* Register: NFCT_EVENTS_STARTED */ +/* Description: EasyDMA is ready to receive or send frames. */ + +/* Bit 0 : */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ + +/* Register: NFCT_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 5 : Shortcut between TXFRAMEEND event and ENABLERXDATA task */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: NFCT_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 20 : Enable or disable interrupt for STARTED event */ +#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for SELECTED event */ +#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for COLLISION event */ +#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for ENDTX event */ +#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for ENDRX event */ +#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for RXERROR event */ +#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for ERROR event */ +#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: NFCT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 20 : Write '1' to enable interrupt for STARTED event */ +#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for SELECTED event */ +#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for COLLISION event */ +#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for ENDTX event */ +#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for ENDRX event */ +#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for RXERROR event */ +#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for ERROR event */ +#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for RXFRAMEEND event */ +#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for RXFRAMESTART event */ +#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for TXFRAMEEND event */ +#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for TXFRAMESTART event */ +#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for FIELDLOST event */ +#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for FIELDDETECTED event */ +#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for READY event */ +#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: NFCT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 20 : Write '1' to disable interrupt for STARTED event */ +#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for SELECTED event */ +#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for COLLISION event */ +#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for ENDTX event */ +#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for ENDRX event */ +#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for RXERROR event */ +#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for ERROR event */ +#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for RXFRAMEEND event */ +#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for RXFRAMESTART event */ +#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for TXFRAMEEND event */ +#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for TXFRAMESTART event */ +#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for FIELDLOST event */ +#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for FIELDDETECTED event */ +#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for READY event */ +#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: NFCT_ERRORSTATUS */ +/* Description: NFC Error Status register */ + +/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ + +/* Register: NFCT_FRAMESTATUS_RX */ +/* Description: Result of last incoming frame */ + +/* Bit 3 : Overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ + +/* Bit 2 : Parity status of received frame */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ + +/* Bit 0 : No valid end of frame (EoF) detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ + +/* Register: NFCT_NFCTAGSTATE */ +/* Description: NfcTag state register */ + +/* Bits 2..0 : NfcTag state */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */ +#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */ + +/* Register: NFCT_SLEEPSTATE */ +/* Description: Sleep state during automatic collision resolution */ + +/* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. */ +#define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */ +#define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */ +#define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL) /*!< State is IDLE. */ +#define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (1UL) /*!< State is SLEEP_A. */ + +/* Register: NFCT_FIELDPRESENT */ +/* Description: Indicates the presence or not of a valid field */ + +/* Bit 1 : Indicates if the low level has locked to the field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ + +/* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ + +/* Register: NFCT_FRAMEDELAYMIN */ +/* Description: Minimum frame delay */ + +/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ + +/* Register: NFCT_FRAMEDELAYMAX */ +/* Description: Maximum frame delay */ + +/* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ + +/* Register: NFCT_FRAMEDELAYMODE */ +/* Description: Configuration register for the Frame Delay Timer */ + +/* Bits 1..0 : Configuration register for the Frame Delay Timer */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ + +/* Register: NFCT_PACKETPTR */ +/* Description: Packet pointer for TXD and RXD data storage in Data RAM */ + +/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */ +#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: NFCT_MAXLEN */ +/* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */ + +/* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */ +#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: NFCT_TXD_FRAMECONFIG */ +/* Description: Configuration of outgoing frames */ + +/* Bit 4 : CRC mode for outgoing frames */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ + +/* Bit 2 : Adding SoF or not in TX frames */ +#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */ +#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */ + +/* Bit 1 : Discarding unused bits at start or end of a frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */ + +/* Bit 0 : Indicates if parity is added to the frame */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */ + +/* Register: NFCT_TXD_AMOUNT */ +/* Description: Size of outgoing frame */ + +/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ + +/* Register: NFCT_RXD_FRAMECONFIG */ +/* Description: Configuration of incoming frames */ + +/* Bit 4 : CRC mode for incoming frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ + +/* Bit 2 : SoF expected or not in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */ + +/* Bit 0 : Indicates if parity expected in RX frame */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ + +/* Register: NFCT_RXD_AMOUNT */ +/* Description: Size of last incoming frame */ + +/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ + +/* Register: NFCT_NFCID1_LAST */ +/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ + +/* Bits 31..24 : NFCID1 byte W */ +#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ +#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ + +/* Bits 23..16 : NFCID1 byte X */ +#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ +#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ + +/* Bits 15..8 : NFCID1 byte Y */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ + +/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ + +/* Register: NFCT_NFCID1_2ND_LAST */ +/* Description: Second last NFCID1 part (7 or 10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte T */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ + +/* Bits 15..8 : NFCID1 byte U */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ + +/* Bits 7..0 : NFCID1 byte V */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ + +/* Register: NFCT_NFCID1_3RD_LAST */ +/* Description: Third last NFCID1 part (10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte Q */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ + +/* Bits 15..8 : NFCID1 byte R */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ + +/* Bits 7..0 : NFCID1 byte S */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ + +/* Register: NFCT_AUTOCOLRESCONFIG */ +/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. */ + +/* Bit 0 : Enables/disables auto collision resolution */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */ +#define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */ + +/* Register: NFCT_SENSRES */ +/* Description: NFC-A SENS_RES auto-response settings */ + +/* Bits 15..12 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ +#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ + +/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ +#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ + +/* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */ +#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ + +/* Bit 5 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ +#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ + +/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ + +/* Register: NFCT_SELRES */ +/* Description: NFC-A SEL_RES auto-response settings */ + +/* Bit 7 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ +#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ + +/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ +#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + +/* Bits 4..3 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ +#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ + +/* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */ +#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ + +/* Bits 1..0 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ +#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_READYNEXT */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC can accept a new write operation */ +#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ +#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ +#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ +#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in code area */ + +/* Bits 31..0 : Register for starting erase of a page in code area */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing user information configuration registers */ + +/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ERASEPAGEPARTIAL */ +/* Description: Register for partial erase of a page in code area */ + +/* Bits 31..0 : Register for starting partial erase of a page in code area */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */ + +/* Register: NVMC_ERASEPAGEPARTIALCFG */ +/* Description: Register for partial erase configuration */ + +/* Bits 6..0 : Duration of the partial erase in milliseconds */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ + +/* Register: NVMC_ICACHECNF */ +/* Description: I-code cache configuration register. */ + +/* Bit 8 : Cache profiling enable */ +#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ + +/* Bit 0 : Cache enable */ +#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ + +/* Register: NVMC_IHIT */ +/* Description: I-code cache hit counter. */ + +/* Bits 31..0 : Number of cache hits */ +#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ +#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ + +/* Register: NVMC_IMISS */ +/* Description: I-code cache miss counter. */ + +/* Bits 31..0 : Number of cache misses */ +#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ +#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 1 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection[n]: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_TASKS_START */ +/* Description: Starts continuous PDM transfer */ + +/* Bit 0 : */ +#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: PDM_TASKS_STOP */ +/* Description: Stops PDM transfer */ + +/* Bit 0 : */ +#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: PDM_EVENTS_STARTED */ +/* Description: PDM transfer has started */ + +/* Bit 0 : */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ + +/* Register: PDM_EVENTS_STOPPED */ +/* Description: PDM transfer has finished */ + +/* Bit 0 : */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: PDM_EVENTS_END */ +/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ + +/* Bit 0 : */ +#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for END event */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for END event */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for END event */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */ +#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_RATIO */ +/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ + +/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */ +#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */ +#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_TASKS_CONSTLAT */ +/* Description: Enable constant latency mode */ + +/* Bit 0 : */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ + +/* Register: POWER_TASKS_LOWPWR */ +/* Description: Enable low power mode (variable latency) */ + +/* Bit 0 : */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ + +/* Register: POWER_EVENTS_POFWARN */ +/* Description: Power failure warning */ + +/* Bit 0 : */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ + +/* Register: POWER_EVENTS_SLEEPENTER */ +/* Description: CPU entered WFI/WFE sleep */ + +/* Bit 0 : */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ + +/* Register: POWER_EVENTS_SLEEPEXIT */ +/* Description: CPU exited WFI/WFE sleep */ + +/* Bit 0 : */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ + +/* Register: POWER_EVENTS_USBDETECTED */ +/* Description: Voltage supply detected on VBUS */ + +/* Bit 0 : */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */ + +/* Register: POWER_EVENTS_USBREMOVED */ +/* Description: Voltage supply removed from VBUS */ + +/* Bit 0 : */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */ + +/* Register: POWER_EVENTS_USBPWRRDY */ +/* Description: USB 3.3 V supply ready */ + +/* Bit 0 : */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 9 : Write '1' to enable interrupt for USBPWRRDY event */ +#define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ +#define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ +#define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for USBREMOVED event */ +#define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ +#define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ +#define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for USBDETECTED event */ +#define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ +#define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ +#define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for POFWARN event */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 9 : Write '1' to disable interrupt for USBPWRRDY event */ +#define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ +#define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ +#define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for USBREMOVED event */ +#define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ +#define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ +#define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for USBDETECTED event */ +#define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ +#define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ +#define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for POFWARN event */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */ +#define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */ +#define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */ +#define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */ + +/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ +#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ +#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ +#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Deprecated register - RAM status register */ + +/* Bit 3 : RAM block 3 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ + +/* Bit 2 : RAM block 2 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ + +/* Bit 1 : RAM block 1 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ + +/* Bit 0 : RAM block 0 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ + +/* Register: POWER_USBREGSTATUS */ +/* Description: USB supply status */ + +/* Bit 1 : USB supply output settling time elapsed */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */ +#define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */ +#define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */ + +/* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */ +#define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */ +#define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */ +#define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */ +#define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power-fail comparator configuration */ + +/* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */ +#define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */ +#define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */ +#define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */ +#define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */ +#define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */ +#define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */ +#define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */ +#define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */ +#define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */ +#define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */ +#define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */ +#define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */ +#define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */ +#define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */ +#define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */ +#define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */ +#define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */ + +/* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure warning */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_DCDCEN */ +/* Description: Enable DC/DC converter for REG1 stage. */ + +/* Bit 0 : Enable DC/DC converter for REG1 stage. */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_DCDCEN0 */ +/* Description: Enable DC/DC converter for REG0 stage. */ + +/* Bit 0 : Enable DC/DC converter for REG0 stage. */ +#define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN0_DCDCEN_Msk (0x1UL << POWER_DCDCEN0_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN0_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN0_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_MAINREGSTATUS */ +/* Description: Main supply status */ + +/* Bit 0 : Main supply status */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */ +#define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster[n]: RAMn power control register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is off */ +#define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is off */ +#define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is off */ +#define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is off */ +#define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is off */ +#define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is off */ +#define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is off */ +#define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is off */ +#define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is off */ +#define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is off */ +#define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is off */ +#define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is off */ +#define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is off */ +#define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is off */ +#define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is off */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is off */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 15 : Keep RAM section S15 on or off in System ON mode. */ +#define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */ + +/* Bit 14 : Keep RAM section S14 on or off in System ON mode. */ +#define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */ + +/* Bit 13 : Keep RAM section S13 on or off in System ON mode. */ +#define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */ + +/* Bit 12 : Keep RAM section S12 on or off in System ON mode. */ +#define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */ + +/* Bit 11 : Keep RAM section S11 on or off in System ON mode. */ +#define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */ + +/* Bit 10 : Keep RAM section S10 on or off in System ON mode. */ +#define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */ + +/* Bit 9 : Keep RAM section S9 on or off in System ON mode. */ +#define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */ + +/* Bit 8 : Keep RAM section S8 on or off in System ON mode. */ +#define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */ + +/* Bit 7 : Keep RAM section S7 on or off in System ON mode. */ +#define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */ + +/* Bit 6 : Keep RAM section S6 on or off in System ON mode. */ +#define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */ + +/* Bit 5 : Keep RAM section S5 on or off in System ON mode. */ +#define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */ + +/* Bit 4 : Keep RAM section S4 on or off in System ON mode. */ +#define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */ + +/* Bit 3 : Keep RAM section S3 on or off in System ON mode. */ +#define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */ + +/* Bit 2 : Keep RAM section S2 on or off in System ON mode. */ +#define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 on or off in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 on or off in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster[n]: RAMn power control set register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */ + +/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */ + +/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */ + +/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */ + +/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */ + +/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */ + +/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */ + +/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */ + +/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */ + +/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */ + +/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */ + +/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */ + +/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */ + +/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster[n]: RAMn power control clear register */ + +/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ +#define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ +#define POWER_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */ + +/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ +#define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ +#define POWER_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */ + +/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ +#define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ +#define POWER_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */ + +/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ +#define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ +#define POWER_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */ + +/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ +#define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ +#define POWER_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */ + +/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ +#define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ +#define POWER_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */ + +/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ +#define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ +#define POWER_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */ + +/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ +#define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ +#define POWER_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */ + +/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ +#define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ +#define POWER_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */ + +/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ +#define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ +#define POWER_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */ + +/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ +#define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ +#define POWER_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */ + +/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ +#define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ +#define POWER_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */ + +/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ +#define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ +#define POWER_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */ + +/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ +#define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ +#define POWER_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ +#define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ +#define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */ + +/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ +#define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ +#define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */ + +/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ +#define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ +#define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */ + +/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ +#define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ +#define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */ + +/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ +#define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ +#define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */ + +/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ +#define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ +#define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */ + +/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ +#define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ +#define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */ + +/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ +#define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ +#define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */ + +/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ +#define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ +#define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */ + +/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ +#define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ +#define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */ + +/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ +#define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ +#define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */ + +/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ +#define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ +#define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */ + +/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ +#define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ +#define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */ + +/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ +#define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ +#define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_TASKS_CHG_EN */ +/* Description: Description cluster[n]: Enable channel group n */ + +/* Bit 0 : */ +#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ + +/* Register: PPI_TASKS_CHG_DIS */ +/* Description: Description cluster[n]: Disable channel group n */ + +/* Bit 0 : */ +#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster[n]: Channel n event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster[n]: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection[n]: Channel group n */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster[n]: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse width modulation unit 0 */ + +/* Register: PWM_TASKS_STOP */ +/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ + +/* Bit 0 : */ +#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: PWM_TASKS_SEQSTART */ +/* Description: Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ + +/* Bit 0 : */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ + +/* Register: PWM_TASKS_NEXTSTEP */ +/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ + +/* Bit 0 : */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ + +/* Register: PWM_EVENTS_STOPPED */ +/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ + +/* Bit 0 : */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: PWM_EVENTS_SEQSTARTED */ +/* Description: Description collection[n]: First PWM period started on sequence n */ + +/* Bit 0 : */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ + +/* Register: PWM_EVENTS_SEQEND */ +/* Description: Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + +/* Bit 0 : */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ + +/* Register: PWM_EVENTS_PWMPERIODEND */ +/* Description: Emitted at the end of each PWM period */ + +/* Bit 0 : */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ + +/* Register: PWM_EVENTS_LOOPSDONE */ +/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + +/* Bit 0 : */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up mode or up-and-down mode for the counter */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Prescaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Number of playbacks of a loop */ + +/* Bits 15..0 : Number of playbacks of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster[n]: Beginning address in RAM of this sequence */ + +/* Bits 31..0 : Beginning address in RAM of this sequence */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */ + +/* Bits 14..0 : Number of values (duty cycles) in this sequence */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ + +/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster[n]: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection[n]: Output pin select for PWM channel n */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_TASKS_START */ +/* Description: Task starting the quadrature decoder */ + +/* Bit 0 : */ +#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: QDEC_TASKS_STOP */ +/* Description: Task stopping the quadrature decoder */ + +/* Bit 0 : */ +#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: QDEC_TASKS_READCLRACC */ +/* Description: Read and clear ACC and ACCDBL */ + +/* Bit 0 : */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ + +/* Register: QDEC_TASKS_RDCLRACC */ +/* Description: Read and clear ACC */ + +/* Bit 0 : */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ + +/* Register: QDEC_TASKS_RDCLRDBL */ +/* Description: Read and clear ACCDBL */ + +/* Bit 0 : */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ + +/* Register: QDEC_EVENTS_SAMPLERDY */ +/* Description: Event being generated for every new sample value written to the SAMPLE register */ + +/* Bit 0 : */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ + +/* Register: QDEC_EVENTS_REPORTRDY */ +/* Description: Non-null report ready */ + +/* Bit 0 : */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ + +/* Register: QDEC_EVENTS_ACCOF */ +/* Description: ACC or ACCDBL register overflow */ + +/* Bit 0 : */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ + +/* Register: QDEC_EVENTS_DBLRDY */ +/* Description: Double displacement(s) detected */ + +/* Bit 0 : */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ + +/* Register: QDEC_EVENTS_STOPPED */ +/* Description: QDEC has been stopped */ + +/* Bit 0 : */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to enable interrupt for STOPPED event */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for DBLRDY event */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for ACCOF event */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to disable interrupt for STOPPED event */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for DBLRDY event */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for ACCOF event */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: QSPI */ +/* Description: External flash interface */ + +/* Register: QSPI_TASKS_ACTIVATE */ +/* Description: Activate QSPI interface */ + +/* Bit 0 : */ +#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ +#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ + +/* Register: QSPI_TASKS_READSTART */ +/* Description: Start transfer from external flash memory to internal RAM */ + +/* Bit 0 : */ +#define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */ +#define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */ + +/* Register: QSPI_TASKS_WRITESTART */ +/* Description: Start transfer from internal RAM to external flash memory */ + +/* Bit 0 : */ +#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */ +#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */ + +/* Register: QSPI_TASKS_ERASESTART */ +/* Description: Start external flash memory erase operation */ + +/* Bit 0 : */ +#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */ +#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */ + +/* Register: QSPI_TASKS_DEACTIVATE */ +/* Description: Deactivate QSPI interface */ + +/* Bit 0 : */ +#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */ +#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */ + +/* Register: QSPI_EVENTS_READY */ +/* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ + +/* Bit 0 : */ +#define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ + +/* Register: QSPI_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define QSPI_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: QSPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for READY event */ +#define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define QSPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: QSPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for READY event */ +#define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define QSPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: QSPI_ENABLE */ +/* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */ + +/* Bit 0 : Enable or disable QSPI */ +#define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QSPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable QSPI */ +#define QSPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QSPI */ + +/* Register: QSPI_READ_SRC */ +/* Description: Flash memory source address */ + +/* Bits 31..0 : Word-aligned flash memory source address. */ +#define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + +/* Register: QSPI_READ_DST */ +/* Description: RAM destination address */ + +/* Bits 31..0 : Word-aligned RAM destination address. */ +#define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */ +#define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */ + +/* Register: QSPI_READ_CNT */ +/* Description: Read transfer length */ + +/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +#define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: QSPI_WRITE_DST */ +/* Description: Flash destination address */ + +/* Bits 31..0 : Word-aligned flash destination address. */ +#define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */ +#define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */ + +/* Register: QSPI_WRITE_SRC */ +/* Description: RAM source address */ + +/* Bits 31..0 : Word-aligned RAM source address. */ +#define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */ + +/* Register: QSPI_WRITE_CNT */ +/* Description: Write transfer length */ + +/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +#define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: QSPI_ERASE_PTR */ +/* Description: Start address of flash block to be erased */ + +/* Bits 31..0 : Word-aligned start address of block to be erased. */ +#define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: QSPI_ERASE_LEN */ +/* Description: Size of block to be erased. */ + +/* Bits 1..0 : LEN */ +#define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */ +#define QSPI_ERASE_LEN_LEN_4KB (0UL) /*!< Erase 4 kB block (flash command 0x20) */ +#define QSPI_ERASE_LEN_LEN_64KB (1UL) /*!< Erase 64 kB block (flash command 0xD8) */ +#define QSPI_ERASE_LEN_LEN_All (2UL) /*!< Erase all (flash command 0xC7) */ + +/* Register: QSPI_PSEL_SCK */ +/* Description: Pin select for serial clock SCK */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_SCK_PORT_Msk (0x1UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_CSN */ +/* Description: Pin select for chip select signal CSN. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_CSN_PORT_Msk (0x1UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO0 */ +/* Description: Pin select for serial data MOSI/IO0. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO0_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO0_PORT_Msk (0x1UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO1 */ +/* Description: Pin select for serial data MISO/IO1. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO1_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO1_PORT_Msk (0x1UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO2 */ +/* Description: Pin select for serial data IO2. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO2_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO2_PORT_Msk (0x1UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_PSEL_IO3 */ +/* Description: Pin select for serial data IO3. */ + +/* Bit 31 : Connection */ +#define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QSPI_PSEL_IO3_CONNECT_Connected (0UL) /*!< Connect */ +#define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define QSPI_PSEL_IO3_PORT_Msk (0x1UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QSPI_XIPOFFSET */ +/* Description: Address offset into the external memory for Execute in Place operation. */ + +/* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */ +#define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */ +#define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */ + +/* Register: QSPI_IFCONFIG0 */ +/* Description: Interface configuration. */ + +/* Bit 12 : Page size for commands PP, PP2O, PP4O and PP4IO. */ +#define QSPI_IFCONFIG0_PPSIZE_Pos (12UL) /*!< Position of PPSIZE field. */ +#define QSPI_IFCONFIG0_PPSIZE_Msk (0x1UL << QSPI_IFCONFIG0_PPSIZE_Pos) /*!< Bit mask of PPSIZE field. */ +#define QSPI_IFCONFIG0_PPSIZE_256Bytes (0UL) /*!< 256 bytes. */ +#define QSPI_IFCONFIG0_PPSIZE_512Bytes (1UL) /*!< 512 bytes. */ + +/* Bit 7 : Enable deep power-down mode (DPM) feature. */ +#define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */ +#define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */ +#define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL) /*!< Disable DPM feature. */ +#define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL) /*!< Enable DPM feature. */ + +/* Bit 6 : Addressing mode. */ +#define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */ +#define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */ +#define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */ +#define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */ + +/* Bits 5..3 : Configure number of data lines and opcode used for writing. */ +#define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */ +#define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */ +#define QSPI_IFCONFIG0_WRITEOC_PP (0UL) /*!< Single data line SPI. PP (opcode 0x02). */ +#define QSPI_IFCONFIG0_WRITEOC_PP2O (1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */ +#define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */ +#define QSPI_IFCONFIG0_WRITEOC_PP4IO (3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */ + +/* Bits 2..0 : Configure number of data lines and opcode used for reading. */ +#define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */ +#define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */ +#define QSPI_IFCONFIG0_READOC_FASTREAD (0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */ +#define QSPI_IFCONFIG0_READOC_READ2O (1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */ +#define QSPI_IFCONFIG0_READOC_READ2IO (2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */ +#define QSPI_IFCONFIG0_READOC_READ4O (3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */ +#define QSPI_IFCONFIG0_READOC_READ4IO (4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */ + +/* Register: QSPI_IFCONFIG1 */ +/* Description: Interface configuration. */ + +/* Bits 31..28 : SCK frequency is given as 32 MHz / (SCKFREQ + 1). */ +#define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */ +#define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */ + +/* Bit 25 : Select SPI mode. */ +#define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */ +#define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */ +#define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */ +#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */ + +/* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */ +#define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */ +#define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */ +#define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */ +#define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */ + +/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */ +#define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */ +#define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */ + +/* Register: QSPI_STATUS */ +/* Description: Status register. */ + +/* Bits 31..24 : Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */ +#define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */ +#define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */ + +/* Bit 3 : Ready status. */ +#define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */ +#define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */ +#define QSPI_STATUS_READY_BUSY (0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */ +#define QSPI_STATUS_READY_READY (1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */ + +/* Bit 2 : Deep power-down mode (DPM) status of external flash. */ +#define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */ +#define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */ +#define QSPI_STATUS_DPM_Disabled (0UL) /*!< External flash is not in DPM. */ +#define QSPI_STATUS_DPM_Enabled (1UL) /*!< External flash is in DPM. */ + +/* Register: QSPI_DPMDUR */ +/* Description: Set the duration required to enter/exit deep power-down mode (DPM). */ + +/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */ +#define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */ +#define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */ + +/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */ +#define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */ +#define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */ + +/* Register: QSPI_ADDRCONF */ +/* Description: Extended address configuration. */ + +/* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */ +#define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */ +#define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */ +#define QSPI_ADDRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */ +#define QSPI_ADDRCONF_WREN_Enable (1UL) /*!< Send WREN. */ + +/* Bit 26 : Wait for write complete before sending command. */ +#define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */ +#define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */ +#define QSPI_ADDRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */ +#define QSPI_ADDRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */ + +/* Bits 25..24 : Extended addressing mode. */ +#define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */ +#define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */ +#define QSPI_ADDRCONF_MODE_NoInstr (0UL) /*!< Do not send any instruction. */ +#define QSPI_ADDRCONF_MODE_Opcode (1UL) /*!< Send opcode. */ +#define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, byte0. */ +#define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, byte0, byte1. */ + +/* Bits 23..16 : Byte 1 following byte 0. */ +#define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */ +#define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */ + +/* Bits 15..8 : Byte 0 following opcode. */ +#define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */ +#define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */ + +/* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */ +#define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */ +#define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */ + +/* Register: QSPI_CINSTRCONF */ +/* Description: Custom instruction configuration register. */ + +/* Bit 17 : Stop (finalize) long frame transaction */ +#define QSPI_CINSTRCONF_LFSTOP_Pos (17UL) /*!< Position of LFSTOP field. */ +#define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos) /*!< Bit mask of LFSTOP field. */ +#define QSPI_CINSTRCONF_LFSTOP_Stop (1UL) /*!< Stop */ + +/* Bit 16 : Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */ +#define QSPI_CINSTRCONF_LFEN_Pos (16UL) /*!< Position of LFEN field. */ +#define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos) /*!< Bit mask of LFEN field. */ +#define QSPI_CINSTRCONF_LFEN_Disable (0UL) /*!< Long frame mode disabled */ +#define QSPI_CINSTRCONF_LFEN_Enable (1UL) /*!< Long frame mode enabled */ + +/* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */ +#define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */ +#define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */ +#define QSPI_CINSTRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */ +#define QSPI_CINSTRCONF_WREN_Enable (1UL) /*!< Send WREN. */ + +/* Bit 14 : Wait for write complete before sending command. */ +#define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */ +#define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */ +#define QSPI_CINSTRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */ +#define QSPI_CINSTRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */ + +/* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */ +#define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */ +#define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */ + +/* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */ +#define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */ +#define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */ + +/* Bits 11..8 : Length of custom instruction in number of bytes. */ +#define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */ +#define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define QSPI_CINSTRCONF_LENGTH_1B (1UL) /*!< Send opcode only. */ +#define QSPI_CINSTRCONF_LENGTH_2B (2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */ +#define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */ +#define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */ +#define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */ +#define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */ +#define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */ +#define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */ +#define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */ + +/* Bits 7..0 : Opcode of Custom instruction. */ +#define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */ +#define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */ + +/* Register: QSPI_CINSTRDAT0 */ +/* Description: Custom instruction data register 0. */ + +/* Bits 31..24 : Data byte 3 */ +#define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */ +#define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */ + +/* Bits 23..16 : Data byte 2 */ +#define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */ +#define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */ + +/* Bits 15..8 : Data byte 1 */ +#define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */ +#define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */ + +/* Bits 7..0 : Data byte 0 */ +#define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */ +#define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */ + +/* Register: QSPI_CINSTRDAT1 */ +/* Description: Custom instruction data register 1. */ + +/* Bits 31..24 : Data byte 7 */ +#define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */ +#define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */ + +/* Bits 23..16 : Data byte 6 */ +#define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */ +#define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */ + +/* Bits 15..8 : Data byte 5 */ +#define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */ +#define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */ + +/* Bits 7..0 : Data byte 4 */ +#define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */ +#define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */ + +/* Register: QSPI_IFTIMING */ +/* Description: SPI interface timing. */ + +/* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. */ +#define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */ +#define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz radio */ + +/* Register: RADIO_TASKS_TXEN */ +/* Description: Enable RADIO in TX mode */ + +/* Bit 0 : */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ + +/* Register: RADIO_TASKS_RXEN */ +/* Description: Enable RADIO in RX mode */ + +/* Bit 0 : */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ + +/* Register: RADIO_TASKS_START */ +/* Description: Start RADIO */ + +/* Bit 0 : */ +#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: RADIO_TASKS_STOP */ +/* Description: Stop RADIO */ + +/* Bit 0 : */ +#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: RADIO_TASKS_DISABLE */ +/* Description: Disable RADIO */ + +/* Bit 0 : */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ + +/* Register: RADIO_TASKS_RSSISTART */ +/* Description: Start the RSSI and take one single sample of the receive signal strength */ + +/* Bit 0 : */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ + +/* Register: RADIO_TASKS_RSSISTOP */ +/* Description: Stop the RSSI measurement */ + +/* Bit 0 : */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ + +/* Register: RADIO_TASKS_BCSTART */ +/* Description: Start the bit counter */ + +/* Bit 0 : */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ + +/* Register: RADIO_TASKS_BCSTOP */ +/* Description: Stop the bit counter */ + +/* Bit 0 : */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ + +/* Register: RADIO_TASKS_EDSTART */ +/* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ + +/* Bit 0 : */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ + +/* Register: RADIO_TASKS_EDSTOP */ +/* Description: Stop the energy detect measurement */ + +/* Bit 0 : */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ + +/* Register: RADIO_TASKS_CCASTART */ +/* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ + +/* Bit 0 : */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ + +/* Register: RADIO_TASKS_CCASTOP */ +/* Description: Stop the clear channel assessment */ + +/* Bit 0 : */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ + +/* Register: RADIO_EVENTS_READY */ +/* Description: RADIO has ramped up and is ready to be started */ + +/* Bit 0 : */ +#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ + +/* Register: RADIO_EVENTS_ADDRESS */ +/* Description: Address sent or received */ + +/* Bit 0 : */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ + +/* Register: RADIO_EVENTS_PAYLOAD */ +/* Description: Packet payload sent or received */ + +/* Bit 0 : */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ + +/* Register: RADIO_EVENTS_END */ +/* Description: Packet sent or received */ + +/* Bit 0 : */ +#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: RADIO_EVENTS_DISABLED */ +/* Description: RADIO has been disabled */ + +/* Bit 0 : */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ + +/* Register: RADIO_EVENTS_DEVMATCH */ +/* Description: A device address match occurred on the last received packet */ + +/* Bit 0 : */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ + +/* Register: RADIO_EVENTS_DEVMISS */ +/* Description: No device address match occurred on the last received packet */ + +/* Bit 0 : */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ + +/* Register: RADIO_EVENTS_RSSIEND */ +/* Description: Sampling of receive signal strength complete */ + +/* Bit 0 : */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ + +/* Register: RADIO_EVENTS_BCMATCH */ +/* Description: Bit counter reached bit count value */ + +/* Bit 0 : */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ + +/* Register: RADIO_EVENTS_CRCOK */ +/* Description: Packet received with CRC ok */ + +/* Bit 0 : */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ + +/* Register: RADIO_EVENTS_CRCERROR */ +/* Description: Packet received with CRC error */ + +/* Bit 0 : */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ + +/* Register: RADIO_EVENTS_FRAMESTART */ +/* Description: IEEE 802.15.4 length field received */ + +/* Bit 0 : */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ + +/* Register: RADIO_EVENTS_EDEND */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ + +/* Bit 0 : */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ + +/* Register: RADIO_EVENTS_EDSTOPPED */ +/* Description: The sampling of energy detection has stopped */ + +/* Bit 0 : */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ + +/* Register: RADIO_EVENTS_CCAIDLE */ +/* Description: Wireless medium in idle - clear to send */ + +/* Bit 0 : */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ + +/* Register: RADIO_EVENTS_CCABUSY */ +/* Description: Wireless medium busy - do not send */ + +/* Bit 0 : */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ + +/* Register: RADIO_EVENTS_CCASTOPPED */ +/* Description: The CCA has stopped */ + +/* Bit 0 : */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ + +/* Register: RADIO_EVENTS_RATEBOOST */ +/* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ + +/* Bit 0 : */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ + +/* Register: RADIO_EVENTS_TXREADY */ +/* Description: RADIO has ramped up and is ready to be started TX path */ + +/* Bit 0 : */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ + +/* Register: RADIO_EVENTS_RXREADY */ +/* Description: RADIO has ramped up and is ready to be started RX path */ + +/* Bit 0 : */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ + +/* Register: RADIO_EVENTS_MHRMATCH */ +/* Description: MAC header match found */ + +/* Bit 0 : */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ + +/* Register: RADIO_EVENTS_PHYEND */ +/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air. */ + +/* Bit 0 : */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 21 : Shortcut between PHYEND event and START task */ +#define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ +#define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ +#define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 20 : Shortcut between PHYEND event and DISABLE task */ +#define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ +#define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ +#define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 19 : Shortcut between RXREADY event and START task */ +#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 18 : Shortcut between TXREADY event and START task */ +#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 17 : Shortcut between CCAIDLE event and STOP task */ +#define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 16 : Shortcut between EDEND event and DISABLE task */ +#define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 15 : Shortcut between READY event and EDSTART task */ +#define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 14 : Shortcut between FRAMESTART event and BCSTART task */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between CCABUSY event and DISABLE task */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between CCAIDLE event and TXEN task */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between RXREADY event and CCASTART task */ +#define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between END event and START task */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between END event and DISABLE task */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and START task */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to enable interrupt for PHYEND event */ +#define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ +#define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ +#define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for MHRMATCH event */ +#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to enable interrupt for RXREADY event */ +#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to enable interrupt for TXREADY event */ +#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for RATEBOOST event */ +#define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for CCASTOPPED event */ +#define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for CCABUSY event */ +#define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for CCAIDLE event */ +#define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for EDSTOPPED event */ +#define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for EDEND event */ +#define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for FRAMESTART event */ +#define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for CRCERROR event */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for CRCOK event */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for BCMATCH event */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for RSSIEND event */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for DEVMISS event */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for DISABLED event */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for END event */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for ADDRESS event */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for READY event */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to disable interrupt for PHYEND event */ +#define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ +#define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ +#define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for MHRMATCH event */ +#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to disable interrupt for RXREADY event */ +#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to disable interrupt for TXREADY event */ +#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for RATEBOOST event */ +#define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for CCASTOPPED event */ +#define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for CCABUSY event */ +#define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for CCAIDLE event */ +#define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for EDSTOPPED event */ +#define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for EDEND event */ +#define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for FRAMESTART event */ +#define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for CRCERROR event */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for CRCOK event */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for BCMATCH event */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for RSSIEND event */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for DEVMISS event */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for DISABLED event */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for END event */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for ADDRESS event */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for READY event */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PDUSTAT */ +/* Description: Payload status */ + +/* Bits 2..1 : Status on what rate packet is received with in Long Range */ +#define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ +#define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ +#define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125kbps */ +#define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500kbps */ + +/* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ +#define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ +#define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s BLE */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s BLE */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bits 30..29 : Length of TERM field in Long Range operation */ +#define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ +#define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ + +/* Bit 26 : Indicates if LENGTH field contains CRC or not */ +#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */ +#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */ + +/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ +#define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */ + +/* Bits 23..22 : Length of code indicator - long range */ +#define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ +#define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ +#define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Interframe spacing in us */ + +/* Bits 9..0 : Interframe spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection[n]: Device address base segment n */ + +/* Bits 31..0 : Device address base segment n */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection[n]: Device address prefix n */ + +/* Bits 15..0 : Device address prefix n */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_SFD */ +/* Description: IEEE 802.15.4 start of frame delimiter */ + +/* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */ +#define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ +#define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ + +/* Register: RADIO_EDCNT */ +/* Description: IEEE 802.15.4 energy detect loop count */ + +/* Bits 20..0 : IEEE 802.15.4 energy detect loop count */ +#define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ +#define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ + +/* Register: RADIO_EDSAMPLE */ +/* Description: IEEE 802.15.4 energy detect level */ + +/* Bits 7..0 : IEEE 802.15.4 energy detect level */ +#define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ +#define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ + +/* Register: RADIO_CCACTRL */ +/* Description: IEEE 802.15.4 clear channel assessment control */ + +/* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ +#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ +#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ + +/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */ +#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ +#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ + +/* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ +#define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ +#define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ + +/* Bits 2..0 : CCA mode of operation */ +#define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */ +#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ +#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_TASKS_START */ +/* Description: Task starting the random number generator */ + +/* Bit 0 : */ +#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: RNG_TASKS_STOP */ +/* Description: Task stopping the random number generator */ + +/* Bit 0 : */ +#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: RNG_EVENTS_VALRDY */ +/* Description: Event being generated for every new random number written to the VALUE register */ + +/* Bit 0 : */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for VALRDY event */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for VALRDY event */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_TASKS_START */ +/* Description: Start RTC COUNTER */ + +/* Bit 0 : */ +#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: RTC_TASKS_STOP */ +/* Description: Stop RTC COUNTER */ + +/* Bit 0 : */ +#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: RTC_TASKS_CLEAR */ +/* Description: Clear RTC COUNTER */ + +/* Bit 0 : */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ + +/* Register: RTC_TASKS_TRIGOVRFLW */ +/* Description: Set COUNTER to 0xFFFFF0 */ + +/* Bit 0 : */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ + +/* Register: RTC_EVENTS_TICK */ +/* Description: Event on COUNTER increment */ + +/* Bit 0 : */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ + +/* Register: RTC_EVENTS_OVRFLW */ +/* Description: Event on COUNTER overflow */ + +/* Bit 0 : */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ + +/* Register: RTC_EVENTS_COMPARE */ +/* Description: Description collection[n]: Compare event on CC[n] match */ + +/* Bit 0 : */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for OVRFLW event */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for TICK event */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for OVRFLW event */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for TICK event */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable event routing for OVRFLW event */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable event routing for TICK event */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable event routing for OVRFLW event */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable event routing for TICK event */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable event routing for OVRFLW event */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable event routing for TICK event */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection[n]: Compare register n */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Successive approximation register (SAR) analog-to-digital converter */ + +/* Register: SAADC_TASKS_START */ +/* Description: Starts the SAADC and prepares the result buffer in RAM */ + +/* Bit 0 : */ +#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: SAADC_TASKS_SAMPLE */ +/* Description: Takes one SAADC sample */ + +/* Bit 0 : */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ + +/* Register: SAADC_TASKS_STOP */ +/* Description: Stops the SAADC and terminates all on-going conversions */ + +/* Bit 0 : */ +#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: SAADC_TASKS_CALIBRATEOFFSET */ +/* Description: Starts offset auto-calibration */ + +/* Bit 0 : */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ + +/* Register: SAADC_EVENTS_STARTED */ +/* Description: The SAADC has started */ + +/* Bit 0 : */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ + +/* Register: SAADC_EVENTS_END */ +/* Description: The SAADC has filled up the result buffer */ + +/* Bit 0 : */ +#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: SAADC_EVENTS_DONE */ +/* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ + +/* Bit 0 : */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ + +/* Register: SAADC_EVENTS_RESULTDONE */ +/* Description: Result ready for transfer to RAM */ + +/* Bit 0 : */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ + +/* Register: SAADC_EVENTS_CALIBRATEDONE */ +/* Description: Calibration is complete */ + +/* Bit 0 : */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ + +/* Register: SAADC_EVENTS_STOPPED */ +/* Description: The SAADC has stopped */ + +/* Bit 0 : */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: SAADC_EVENTS_CH_LIMITH */ +/* Description: Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */ + +/* Bit 0 : */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ + +/* Register: SAADC_EVENTS_CH_LIMITL */ +/* Description: Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW */ + +/* Bit 0 : */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for STOPPED event */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for DONE event */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for END event */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for STOPPED event */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for DONE event */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for END event */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for STOPPED event */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for DONE event */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for END event */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< SAADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable SAADC */ + +/* Bit 0 : Enable or disable SAADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SAADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster[n]: Input positive pin selection for CH[n] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ +#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster[n]: Input negative pin selection for CH[n] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ +#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster[n]: Input configuration for CH[n] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the SAADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster[n]: High/low limits for event monitoring of a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bits */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bits */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bits */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bits */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of 16-bit samples to be written to output RAM buffer */ + +/* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of 16-bit samples written to output RAM buffer since the previous START task */ + +/* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_EVENTS_READY */ +/* Description: TXD byte sent and RXD byte received */ + +/* Bit 0 : */ +#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for READY event */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for READY event */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_SCK_PORT_Msk (0x1UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_MOSI_PORT_Msk (0x1UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPI_PSEL_MISO_PORT_Msk (0x1UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_TASKS_START */ +/* Description: Start SPI transaction */ + +/* Bit 0 : */ +#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: SPIM_TASKS_STOP */ +/* Description: Stop SPI transaction */ + +/* Bit 0 : */ +#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: SPIM_TASKS_SUSPEND */ +/* Description: Suspend SPI transaction */ + +/* Bit 0 : */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ + +/* Register: SPIM_TASKS_RESUME */ +/* Description: Resume SPI transaction */ + +/* Bit 0 : */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ + +/* Register: SPIM_EVENTS_STOPPED */ +/* Description: SPI transaction has stopped */ + +/* Bit 0 : */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: SPIM_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ + +/* Register: SPIM_EVENTS_END */ +/* Description: End of RXD buffer and TXD buffer reached */ + +/* Bit 0 : */ +#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: SPIM_EVENTS_ENDTX */ +/* Description: End of TXD buffer reached */ + +/* Bit 0 : */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ + +/* Register: SPIM_EVENTS_STARTED */ +/* Description: Transaction started */ + +/* Bit 0 : */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 17 : Shortcut between END event and START task */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for STARTED event */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for END event */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for STARTED event */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for END event */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_STALLSTAT */ +/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ + +/* Bit 1 : Stall status for EasyDMA RAM writes */ +#define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */ +#define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */ +#define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */ +#define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */ + +/* Bit 0 : Stall status for EasyDMA RAM reads */ +#define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */ +#define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */ +#define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */ +#define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_CSN */ +/* Description: Pin select for CSN */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_IFTIMING_RXDELAY */ +/* Description: Sample delay for input serial data on MISO */ + +/* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */ +#define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */ +#define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + +/* Register: SPIM_IFTIMING_CSNDUR */ +/* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */ + +/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */ +#define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */ +#define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */ + +/* Register: SPIM_CSNPOL */ +/* Description: Polarity of CSN output */ + +/* Bit 0 : Polarity of CSN output */ +#define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */ +#define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */ +#define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */ +#define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */ + +/* Register: SPIM_PSELDCX */ +/* Description: Pin select for DCX signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_DCXCNT */ +/* Description: DCX configuration */ + +/* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */ +#define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */ +#define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */ + +/* Register: SPIM_ORC */ +/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */ + +/* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_TASKS_ACQUIRE */ +/* Description: Acquire SPI semaphore */ + +/* Bit 0 : */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ + +/* Register: SPIS_TASKS_RELEASE */ +/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ + +/* Bit 0 : */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ + +/* Register: SPIS_EVENTS_END */ +/* Description: Granted transaction completed */ + +/* Bit 0 : */ +#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ + +/* Register: SPIS_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ + +/* Register: SPIS_EVENTS_ACQUIRED */ +/* Description: Semaphore acquired */ + +/* Bit 0 : */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 2 : Shortcut between END event and ACQUIRE task */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for END event */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for END event */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 15..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 15..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_TASKS_START */ +/* Description: Start temperature measurement */ + +/* Bit 0 : */ +#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: TEMP_TASKS_STOP */ +/* Description: Stop temperature measurement */ + +/* Bit 0 : */ +#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TEMP_EVENTS_DATARDY */ +/* Description: Temperature measurement complete, data ready */ + +/* Bit 0 : */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for DATARDY event */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for DATARDY event */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_TASKS_START */ +/* Description: Start Timer */ + +/* Bit 0 : */ +#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: TIMER_TASKS_STOP */ +/* Description: Stop Timer */ + +/* Bit 0 : */ +#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TIMER_TASKS_COUNT */ +/* Description: Increment Timer (Counter mode only) */ + +/* Bit 0 : */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ + +/* Register: TIMER_TASKS_CLEAR */ +/* Description: Clear time */ + +/* Bit 0 : */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ + +/* Register: TIMER_TASKS_SHUTDOWN */ +/* Description: Deprecated register - Shut down timer */ + +/* Bit 0 : */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ + +/* Register: TIMER_TASKS_CAPTURE */ +/* Description: Description collection[n]: Capture Timer value to CC[n] register */ + +/* Bit 0 : */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ + +/* Register: TIMER_EVENTS_COMPARE */ +/* Description: Description collection[n]: Compare event on CC[n] match */ + +/* Bit 0 : */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection[n]: Capture/Compare register n */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface 0 */ + +/* Register: TWI_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ + +/* Register: TWI_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ + +/* Register: TWI_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : */ +#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TWI_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ + +/* Register: TWI_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ + +/* Register: TWI_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: TWI_EVENTS_RXDREADY */ +/* Description: TWI RXD byte received */ + +/* Bit 0 : */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ + +/* Register: TWI_EVENTS_TXDSENT */ +/* Description: TWI TXD byte sent */ + +/* Bit 0 : */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ + +/* Register: TWI_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: TWI_EVENTS_BB */ +/* Description: TWI byte boundary, generated before each byte that is sent or received */ + +/* Bit 0 : */ +#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ + +/* Register: TWI_EVENTS_SUSPENDED */ +/* Description: TWI entered the suspended state */ + +/* Bit 0 : */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between BB event and STOP task */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between BB event and SUSPEND task */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for BB event */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for TXDSENT event */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for RXDREADY event */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for BB event */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for TXDSENT event */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for RXDREADY event */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSEL_SCL */ +/* Description: Pin select for SCL */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWI_PSEL_SCL_PORT_Msk (0x1UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_PSEL_SDA */ +/* Description: Pin select for SDA */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWI_PSEL_SDA_PORT_Msk (0x1UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ + +/* Register: TWIM_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ + +/* Register: TWIM_TASKS_STOP */ +/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + +/* Bit 0 : */ +#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TWIM_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ + +/* Register: TWIM_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ + +/* Register: TWIM_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: TWIM_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: TWIM_EVENTS_SUSPENDED */ +/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ + +/* Bit 0 : */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ + +/* Register: TWIM_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ + +/* Register: TWIM_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ + +/* Register: TWIM_EVENTS_LASTRX */ +/* Description: Byte boundary, starting to receive the last byte */ + +/* Bit 0 : */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ + +/* Register: TWIM_EVENTS_LASTTX */ +/* Description: Byte boundary, starting to transmit the last byte */ + +/* Bit 0 : */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 12 : Shortcut between LASTRX event and STOP task */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between LASTRX event and SUSPEND task */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between LASTTX event and STOP task */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for LASTTX event */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for LASTRX event */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for LASTTX event */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for LASTRX event */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for LASTTX event */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for LASTRX event */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : */ +#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ + +/* Register: TWIS_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ + +/* Register: TWIS_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ + +/* Register: TWIS_TASKS_PREPARERX */ +/* Description: Prepare the TWI slave to respond to a write command */ + +/* Bit 0 : */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ + +/* Register: TWIS_TASKS_PREPARETX */ +/* Description: Prepare the TWI slave to respond to a read command */ + +/* Bit 0 : */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ + +/* Register: TWIS_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ + +/* Register: TWIS_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: TWIS_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ + +/* Register: TWIS_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ + +/* Register: TWIS_EVENTS_WRITE */ +/* Description: Write command received */ + +/* Bit 0 : */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ + +/* Register: TWIS_EVENTS_READ */ +/* Description: Read command received */ + +/* Bit 0 : */ +#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 14 : Shortcut between READ event and SUSPEND task */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for READ event */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for WRITE event */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to enable interrupt for READ event */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for WRITE event */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to disable interrupt for READ event */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for WRITE event */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 15..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 15..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection[n]: TWI slave address n */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ + +/* Register: UART_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ + +/* Register: UART_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ + +/* Register: UART_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ + +/* Register: UART_TASKS_SUSPEND */ +/* Description: Suspend UART */ + +/* Bit 0 : */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ + +/* Register: UART_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : */ +#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ + +/* Register: UART_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ + +/* Register: UART_EVENTS_RXDRDY */ +/* Description: Data received in RXD */ + +/* Bit 0 : */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ + +/* Register: UART_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ + +/* Register: UART_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: UART_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ + +/* Register: UART_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between CTS event and STARTRX task */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for CTS event */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for CTS event */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSEL_RTS */ +/* Description: Pin select for RTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_TXD */ +/* Description: Pin select for TXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_CTS */ +/* Description: Pin select for CTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_RXD */ +/* Description: Pin select for RXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA 0 */ + +/* Register: UARTE_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ + +/* Register: UARTE_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ + +/* Register: UARTE_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ + +/* Register: UARTE_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ + +/* Register: UARTE_TASKS_FLUSHRX */ +/* Description: Flush RX FIFO into RX buffer */ + +/* Bit 0 : */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ + +/* Register: UARTE_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ + +/* Register: UARTE_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ + +/* Register: UARTE_EVENTS_RXDRDY */ +/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ + +/* Bit 0 : */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ + +/* Register: UARTE_EVENTS_ENDRX */ +/* Description: Receive buffer is filled up */ + +/* Bit 0 : */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ + +/* Register: UARTE_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ + +/* Register: UARTE_EVENTS_ENDTX */ +/* Description: Last TX byte transmitted */ + +/* Bit 0 : */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ + +/* Register: UARTE_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ + +/* Register: UARTE_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ + +/* Register: UARTE_EVENTS_RXSTARTED */ +/* Description: UART receiver has started */ + +/* Bit 0 : */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ + +/* Register: UARTE_EVENTS_TXSTARTED */ +/* Description: UART transmitter has started */ + +/* Bit 0 : */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ + +/* Register: UARTE_EVENTS_TXSTOPPED */ +/* Description: Transmitter stopped */ + +/* Bit 0 : */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for RXTO event */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDTX event */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDRX event */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for NCTS event */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for CTS event */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for CTS event */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for CTS event */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source Note : this register is read / write one to clear. */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number */ +#define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 15..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 15..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User information configuration registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection[n]: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection[n]: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection[n]: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection[n]: Mapping of the nRESET function */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bit 5 : Port number onto which nRESET is exposed */ +#define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */ +#define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */ + +/* Bits 4..0 : Pin number of PORT onto which nRESET is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access port protection */ + +/* Bits 7..0 : Enable or disable access port protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + +/* Register: UICR_NFCPINS */ +/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ + +/* Bit 0 : Setting of pins dedicated to NFC functionality */ +#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ + +/* Register: UICR_DEBUGCTRL */ +/* Description: Processor debug control */ + +/* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */ +#define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */ +#define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */ + +/* Bits 7..0 : Configure CPU non-intrusive debug features */ +#define UICR_DEBUGCTRL_CPUNIDEN_Pos (0UL) /*!< Position of CPUNIDEN field. */ +#define UICR_DEBUGCTRL_CPUNIDEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUNIDEN_Pos) /*!< Bit mask of CPUNIDEN field. */ +#define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */ +#define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ + +/* Register: UICR_REGOUT0 */ +/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */ + +/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ +#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ +#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */ +#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */ +#define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */ +#define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */ +#define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */ +#define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */ +#define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */ +#define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */ + + +/* Peripheral: USBD */ +/* Description: Universal serial bus device */ + +/* Register: USBD_TASKS_STARTEPIN */ +/* Description: Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ + +/* Bit 0 : */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */ + +/* Register: USBD_TASKS_STARTISOIN */ +/* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ + +/* Bit 0 : */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */ + +/* Register: USBD_TASKS_STARTEPOUT */ +/* Description: Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ + +/* Bit 0 : */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */ + +/* Register: USBD_TASKS_STARTISOOUT */ +/* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ + +/* Bit 0 : */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */ + +/* Register: USBD_TASKS_EP0RCVOUT */ +/* Description: Allows OUT data stage on control endpoint 0 */ + +/* Bit 0 : */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */ + +/* Register: USBD_TASKS_EP0STATUS */ +/* Description: Allows status stage on control endpoint 0 */ + +/* Bit 0 : */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */ + +/* Register: USBD_TASKS_EP0STALL */ +/* Description: Stalls data and status stage on control endpoint 0 */ + +/* Bit 0 : */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */ + +/* Register: USBD_TASKS_DPDMDRIVE */ +/* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */ + +/* Bit 0 : */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */ + +/* Register: USBD_TASKS_DPDMNODRIVE */ +/* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */ + +/* Bit 0 : */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */ + +/* Register: USBD_EVENTS_USBRESET */ +/* Description: Signals that a USB reset condition has been detected on USB lines */ + +/* Bit 0 : */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */ + +/* Register: USBD_EVENTS_STARTED */ +/* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ + +/* Bit 0 : */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ + +/* Register: USBD_EVENTS_ENDEPIN */ +/* Description: Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + +/* Bit 0 : */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ + +/* Register: USBD_EVENTS_EP0DATADONE */ +/* Description: An acknowledged data transfer has taken place on the control endpoint */ + +/* Bit 0 : */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */ + +/* Register: USBD_EVENTS_ENDISOIN */ +/* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ + +/* Bit 0 : */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ + +/* Register: USBD_EVENTS_ENDEPOUT */ +/* Description: Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ + +/* Bit 0 : */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ + +/* Register: USBD_EVENTS_ENDISOOUT */ +/* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ + +/* Bit 0 : */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ + +/* Register: USBD_EVENTS_SOF */ +/* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */ + +/* Bit 0 : */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */ + +/* Register: USBD_EVENTS_USBEVENT */ +/* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ + +/* Bit 0 : */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */ + +/* Register: USBD_EVENTS_EP0SETUP */ +/* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */ + +/* Bit 0 : */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */ + +/* Register: USBD_EVENTS_EPDATA */ +/* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ + +/* Bit 0 : */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */ + +/* Register: USBD_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between ENDEPOUT[0] event and EP0STATUS task */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between EP0DATADONE event and STARTEPOUT[0] task */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between EP0DATADONE event and STARTEPIN[0] task */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */ +#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: USBD_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for EPDATA event */ +#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for EP0SETUP event */ +#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */ + +/* Bit 22 : Enable or disable interrupt for USBEVENT event */ +#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */ + +/* Bit 21 : Enable or disable interrupt for SOF event */ +#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for ENDISOOUT event */ +#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */ +#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */ +#define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */ +#define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */ +#define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */ +#define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */ +#define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */ +#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */ +#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for ENDISOIN event */ +#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for EP0DATADONE event */ +#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */ +#define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */ +#define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */ +#define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */ +#define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */ +#define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */ +#define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */ +#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */ +#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STARTED event */ +#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for USBRESET event */ +#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */ + +/* Register: USBD_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for EPDATA event */ +#define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for EP0SETUP event */ +#define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to enable interrupt for USBEVENT event */ +#define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to enable interrupt for SOF event */ +#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for ENDISOOUT event */ +#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for ENDEPOUT[7] event */ +#define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for ENDEPOUT[6] event */ +#define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for ENDEPOUT[5] event */ +#define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for ENDEPOUT[4] event */ +#define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for ENDEPOUT[3] event */ +#define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for ENDEPOUT[2] event */ +#define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for ENDEPOUT[1] event */ +#define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for ENDEPOUT[0] event */ +#define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for ENDISOIN event */ +#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for EP0DATADONE event */ +#define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for ENDEPIN[7] event */ +#define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for ENDEPIN[6] event */ +#define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for ENDEPIN[5] event */ +#define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for ENDEPIN[4] event */ +#define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for ENDEPIN[3] event */ +#define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for ENDEPIN[2] event */ +#define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for ENDEPIN[1] event */ +#define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for ENDEPIN[0] event */ +#define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for STARTED event */ +#define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for USBRESET event */ +#define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */ + +/* Register: USBD_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for EPDATA event */ +#define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ +#define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ +#define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for EP0SETUP event */ +#define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ +#define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ +#define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to disable interrupt for USBEVENT event */ +#define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ +#define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ +#define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to disable interrupt for SOF event */ +#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ +#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ +#define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for ENDISOOUT event */ +#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ +#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ +#define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for ENDEPOUT[7] event */ +#define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ +#define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ +#define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for ENDEPOUT[6] event */ +#define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ +#define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ +#define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for ENDEPOUT[5] event */ +#define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ +#define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ +#define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for ENDEPOUT[4] event */ +#define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ +#define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ +#define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for ENDEPOUT[3] event */ +#define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ +#define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ +#define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for ENDEPOUT[2] event */ +#define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ +#define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ +#define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for ENDEPOUT[1] event */ +#define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ +#define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ +#define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for ENDEPOUT[0] event */ +#define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ +#define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ +#define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for ENDISOIN event */ +#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ +#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ +#define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for EP0DATADONE event */ +#define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ +#define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ +#define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for ENDEPIN[7] event */ +#define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ +#define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ +#define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for ENDEPIN[6] event */ +#define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ +#define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ +#define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for ENDEPIN[5] event */ +#define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ +#define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ +#define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for ENDEPIN[4] event */ +#define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ +#define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ +#define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for ENDEPIN[3] event */ +#define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ +#define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ +#define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for ENDEPIN[2] event */ +#define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ +#define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ +#define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for ENDEPIN[1] event */ +#define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ +#define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ +#define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for ENDEPIN[0] event */ +#define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ +#define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ +#define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for STARTED event */ +#define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ +#define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for USBRESET event */ +#define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ +#define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ +#define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */ + +/* Register: USBD_EVENTCAUSE */ +/* Description: Details on what caused the USBEVENT event */ + +/* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */ +#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */ +#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */ +#define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */ +#define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */ + +/* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */ +#define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */ +#define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */ + +/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */ +#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */ +#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */ +#define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */ +#define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */ + +/* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */ +#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */ +#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */ +#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */ +#define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */ + +/* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */ +#define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */ +#define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ + +/* Register: USBD_HALTED_EPIN */ +/* Description: Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ + +/* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +#define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ +#define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */ +#define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */ +#define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ + +/* Register: USBD_HALTED_EPOUT */ +/* Description: Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ + +/* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +#define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ +#define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */ +#define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */ +#define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ + +/* Register: USBD_EPSTATUS */ +/* Description: Provides information on which endpoint's EasyDMA registers have been captured */ + +/* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */ +#define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */ +#define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ +#define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ +#define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ +#define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ +#define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ +#define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ +#define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ +#define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ +#define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ +#define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ +#define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ +#define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ +#define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ +#define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ +#define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */ +#define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */ +#define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */ +#define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */ +#define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ +#define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ +#define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ +#define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ +#define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ +#define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ +#define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ +#define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ +#define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ +#define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ +#define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ +#define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ +#define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ +#define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ +#define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +#define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */ +#define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */ +#define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ +#define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ + +/* Register: USBD_EPDATASTATUS */ +/* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */ + +/* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ +#define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ +#define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ +#define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ +#define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ +#define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ +#define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ +#define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ +#define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ +#define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ +#define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ +#define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ +#define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ +#define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ +#define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ +#define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ +#define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ +#define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ +#define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ +#define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ +#define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ +#define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ +#define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ +#define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ +#define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ +#define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ +#define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */ +#define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ +#define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ +#define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */ +#define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */ + +/* Register: USBD_USBADDR */ +/* Description: Device USB address */ + +/* Bits 6..0 : Device USB address */ +#define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ +#define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ + +/* Register: USBD_BMREQUESTTYPE */ +/* Description: SETUP data, byte 0, bmRequestType */ + +/* Bit 7 : Data transfer direction */ +#define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */ +#define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */ +#define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */ +#define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */ + +/* Bits 6..5 : Data transfer type */ +#define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */ +#define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */ +#define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */ +#define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */ +#define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */ + +/* Bits 4..0 : Data transfer type */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */ +#define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */ + +/* Register: USBD_BREQUEST */ +/* Description: SETUP data, byte 1, bRequest */ + +/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */ +#define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */ +#define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */ +#define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */ +#define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */ +#define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */ +#define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */ +#define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */ +#define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */ +#define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */ +#define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */ +#define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */ + +/* Register: USBD_WVALUEL */ +/* Description: SETUP data, byte 2, LSB of wValue */ + +/* Bits 7..0 : SETUP data, byte 2, LSB of wValue */ +#define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */ +#define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */ + +/* Register: USBD_WVALUEH */ +/* Description: SETUP data, byte 3, MSB of wValue */ + +/* Bits 7..0 : SETUP data, byte 3, MSB of wValue */ +#define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */ +#define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */ + +/* Register: USBD_WINDEXL */ +/* Description: SETUP data, byte 4, LSB of wIndex */ + +/* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */ +#define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */ +#define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */ + +/* Register: USBD_WINDEXH */ +/* Description: SETUP data, byte 5, MSB of wIndex */ + +/* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */ +#define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */ +#define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */ + +/* Register: USBD_WLENGTHL */ +/* Description: SETUP data, byte 6, LSB of wLength */ + +/* Bits 7..0 : SETUP data, byte 6, LSB of wLength */ +#define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */ +#define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */ + +/* Register: USBD_WLENGTHH */ +/* Description: SETUP data, byte 7, MSB of wLength */ + +/* Bits 7..0 : SETUP data, byte 7, MSB of wLength */ +#define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */ +#define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ + +/* Register: USBD_SIZE_EPOUT */ +/* Description: Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint */ + +/* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */ +#define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: USBD_SIZE_ISOOUT */ +/* Description: Number of bytes received last on this ISO OUT data endpoint */ + +/* Bit 16 : Zero-length data packet received */ +#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */ +#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */ +#define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */ +#define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */ + +/* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */ +#define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ +#define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ + +/* Register: USBD_ENABLE */ +/* Description: Enable USB */ + +/* Bit 0 : Enable USB */ +#define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */ +#define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */ + +/* Register: USBD_USBPULLUP */ +/* Description: Control of the USB pull-up */ + +/* Bit 0 : Control of the USB pull-up on the D+ line */ +#define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */ +#define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */ +#define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */ + +/* Register: USBD_DPDMVALUE */ +/* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */ + +/* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */ +#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */ +#define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */ +#define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */ + +/* Register: USBD_DTOGGLE */ +/* Description: Data toggle control and status */ + +/* Bits 9..8 : Data toggle value */ +#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */ +#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */ +#define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */ +#define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */ +#define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */ + +/* Bit 7 : Selects IN or OUT endpoint */ +#define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */ +#define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */ +#define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */ +#define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */ + +/* Bits 2..0 : Select bulk endpoint number */ +#define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */ +#define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */ + +/* Register: USBD_EPINEN */ +/* Description: Endpoint IN enable */ + +/* Bit 8 : Enable ISO IN endpoint */ +#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */ +#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */ +#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */ +#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */ + +/* Bit 7 : Enable IN endpoint 7 */ +#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */ +#define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */ + +/* Bit 6 : Enable IN endpoint 6 */ +#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */ +#define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */ + +/* Bit 5 : Enable IN endpoint 5 */ +#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */ +#define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */ + +/* Bit 4 : Enable IN endpoint 4 */ +#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */ +#define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */ + +/* Bit 3 : Enable IN endpoint 3 */ +#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */ +#define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */ + +/* Bit 2 : Enable IN endpoint 2 */ +#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */ +#define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */ + +/* Bit 1 : Enable IN endpoint 1 */ +#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */ +#define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */ + +/* Bit 0 : Enable IN endpoint 0 */ +#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */ +#define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */ + +/* Register: USBD_EPOUTEN */ +/* Description: Endpoint OUT enable */ + +/* Bit 8 : Enable ISO OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */ +#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */ +#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */ + +/* Bit 7 : Enable OUT endpoint 7 */ +#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ +#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */ +#define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */ + +/* Bit 6 : Enable OUT endpoint 6 */ +#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */ +#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */ +#define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */ + +/* Bit 5 : Enable OUT endpoint 5 */ +#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */ +#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */ +#define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */ + +/* Bit 4 : Enable OUT endpoint 4 */ +#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */ +#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */ +#define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */ + +/* Bit 3 : Enable OUT endpoint 3 */ +#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */ +#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */ +#define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */ + +/* Bit 2 : Enable OUT endpoint 2 */ +#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */ +#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */ +#define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */ + +/* Bit 1 : Enable OUT endpoint 1 */ +#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */ +#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */ +#define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */ + +/* Bit 0 : Enable OUT endpoint 0 */ +#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */ +#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */ +#define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */ +#define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */ + +/* Register: USBD_EPSTALL */ +/* Description: STALL endpoints */ + +/* Bit 8 : Stall selected endpoint */ +#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */ +#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */ +#define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */ +#define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */ + +/* Bit 7 : Selects IN or OUT endpoint */ +#define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */ +#define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */ +#define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */ +#define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */ + +/* Bits 2..0 : Select endpoint number */ +#define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */ +#define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */ + +/* Register: USBD_ISOSPLIT */ +/* Description: Controls the split of ISO buffers */ + +/* Bits 15..0 : Controls the split of ISO buffers */ +#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ +#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ + +/* Register: USBD_FRAMECNTR */ +/* Description: Returns the current value of the start of frame counter */ + +/* Bits 10..0 : Returns the current value of the start of frame counter */ +#define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */ +#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */ + +/* Register: USBD_LOWPOWER */ +/* Description: Controls USBD peripheral low power mode during USB suspend */ + +/* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */ +#define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */ +#define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */ +#define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */ +#define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */ + +/* Register: USBD_ISOINCONFIG */ +/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ + +/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ +#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */ +#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */ +#define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */ +#define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ + +/* Register: USBD_EPIN_PTR */ +/* Description: Description cluster[n]: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_EPIN_MAXCNT */ +/* Description: Description cluster[n]: Maximum number of bytes to transfer */ + +/* Bits 6..0 : Maximum number of bytes to transfer */ +#define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_EPIN_AMOUNT */ +/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ + +/* Bits 6..0 : Number of bytes transferred in the last transaction */ +#define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_ISOIN_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_ISOIN_MAXCNT */ +/* Description: Maximum number of bytes to transfer */ + +/* Bits 9..0 : Maximum number of bytes to transfer */ +#define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_ISOIN_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_EPOUT_PTR */ +/* Description: Description cluster[n]: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_EPOUT_MAXCNT */ +/* Description: Description cluster[n]: Maximum number of bytes to transfer */ + +/* Bits 6..0 : Maximum number of bytes to transfer */ +#define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_EPOUT_AMOUNT */ +/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ + +/* Bits 6..0 : Number of bytes transferred in the last transaction */ +#define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: USBD_ISOOUT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: USBD_ISOOUT_MAXCNT */ +/* Description: Maximum number of bytes to transfer */ + +/* Bits 9..0 : Maximum number of bytes to transfer */ +#define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: USBD_ISOOUT_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_TASKS_START */ +/* Description: Start the watchdog */ + +/* Bit 0 : */ +#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + +/* Register: WDT_EVENTS_TIMEOUT */ +/* Description: Watchdog timeout */ + +/* Bit 0 : */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection[n]: Reload request n */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840_peripherals.h new file mode 100755 index 0000000..99120c0 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52840_peripherals.h @@ -0,0 +1,301 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF52840_PERIPHERALS_H +#define _NRF52840_PERIPHERALS_H + + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAM_REGISTERS_PRESENT +#define POWER_FEATURE_RAM_REGISTERS_COUNT 9 + +#define POWER_FEATURE_VDDH_PRESENT + +/* Floating Point Unit */ +#define FPU_PRESENT +#define FPU_COUNT 1 + +/* Systick timer */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* Memory Watch Unit */ +#define MWU_PRESENT +#define MWU_COUNT 1 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 2 + +#define P0_PIN_NUM 32 +#define P1_PIN_NUM 16 + +/* ACL */ +#define ACL_PRESENT + +#define ACL_REGIONS_COUNT 8 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +#define RADIO_EASYDMA_MAXCNT_SIZE 8 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 16 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* NFC Tag */ +#define NFCT_PRESENT +#define NFCT_COUNT 1 + +#define NFCT_EASYDMA_MAXCNT_SIZE 9 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 20 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 6 +#define PPI_FEATURE_FORKS_PRESENT + +/* Event Generator Unit */ +#define EGU_PRESENT +#define EGU_COUNT 6 + +#define EGU0_CH_NUM 16 +#define EGU1_CH_NUM 16 +#define EGU2_CH_NUM 16 +#define EGU3_CH_NUM 16 +#define EGU4_CH_NUM 16 +#define EGU5_CH_NUM 16 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 5 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 32 +#define TIMER2_MAX_SIZE 32 +#define TIMER3_MAX_SIZE 32 +#define TIMER4_MAX_SIZE 32 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 +#define TIMER3_CC_NUM 6 +#define TIMER4_CC_NUM 6 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 3 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 +#define RTC2_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 3 + +/* Serial Peripheral Interface Master with DMA */ +#define SPIM_PRESENT +#define SPIM_COUNT 4 + +#define SPIM0_MAX_DATARATE 8 +#define SPIM1_MAX_DATARATE 8 +#define SPIM2_MAX_DATARATE 8 +#define SPIM3_MAX_DATARATE 32 + +#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1 + +#define SPIM0_FEATURE_DCX_PRESENT 0 +#define SPIM1_FEATURE_DCX_PRESENT 0 +#define SPIM2_FEATURE_DCX_PRESENT 0 +#define SPIM3_FEATURE_DCX_PRESENT 1 + +#define SPIM0_FEATURE_RXDELAY_PRESENT 0 +#define SPIM1_FEATURE_RXDELAY_PRESENT 0 +#define SPIM2_FEATURE_RXDELAY_PRESENT 0 +#define SPIM3_FEATURE_RXDELAY_PRESENT 1 + +#define SPIM0_EASYDMA_MAXCNT_SIZE 16 +#define SPIM1_EASYDMA_MAXCNT_SIZE 16 +#define SPIM2_EASYDMA_MAXCNT_SIZE 16 +#define SPIM3_EASYDMA_MAXCNT_SIZE 16 + +/* Serial Peripheral Interface Slave with DMA*/ +#define SPIS_PRESENT +#define SPIS_COUNT 3 + +#define SPIS0_EASYDMA_MAXCNT_SIZE 16 +#define SPIS1_EASYDMA_MAXCNT_SIZE 16 +#define SPIS2_EASYDMA_MAXCNT_SIZE 16 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 2 + +/* Two Wire Interface Master with DMA */ +#define TWIM_PRESENT +#define TWIM_COUNT 2 + +#define TWIM0_EASYDMA_MAXCNT_SIZE 16 +#define TWIM1_EASYDMA_MAXCNT_SIZE 16 + +/* Two Wire Interface Slave with DMA */ +#define TWIS_PRESENT +#define TWIS_COUNT 2 + +#define TWIS0_EASYDMA_MAXCNT_SIZE 16 +#define TWIS1_EASYDMA_MAXCNT_SIZE 16 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Universal Asynchronous Receiver-Transmitter with DMA */ +#define UARTE_PRESENT +#define UARTE_COUNT 2 + +#define UARTE0_EASYDMA_MAXCNT_SIZE 16 +#define UARTE1_EASYDMA_MAXCNT_SIZE 16 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Successive Approximation Analog to Digital Converter */ +#define SAADC_PRESENT +#define SAADC_COUNT 1 + +#define SAADC_EASYDMA_MAXCNT_SIZE 15 + +#define SAADC_CH_NUM 8 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 8 + +#define GPIOTE_FEATURE_SET_PRESENT +#define GPIOTE_FEATURE_CLR_PRESENT + +/* Low Power Comparator */ +#define LPCOMP_PRESENT +#define LPCOMP_COUNT 1 + +#define LPCOMP_REFSEL_RESOLUTION 16 + +#define LPCOMP_FEATURE_HYST_PRESENT + +/* Comparator */ +#define COMP_PRESENT +#define COMP_COUNT 1 + +/* Pulse Width Modulator */ +#define PWM_PRESENT +#define PWM_COUNT 4 + +#define PWM0_CH_NUM 4 +#define PWM1_CH_NUM 4 +#define PWM2_CH_NUM 4 +#define PWM3_CH_NUM 4 + +#define PWM0_EASYDMA_MAXCNT_SIZE 15 +#define PWM1_EASYDMA_MAXCNT_SIZE 15 +#define PWM2_EASYDMA_MAXCNT_SIZE 15 +#define PWM3_EASYDMA_MAXCNT_SIZE 15 + +/* Pulse Density Modulator */ +#define PDM_PRESENT +#define PDM_COUNT 1 + +#define PDM_EASYDMA_MAXCNT_SIZE 15 + +/* Inter-IC Sound Interface */ +#define I2S_PRESENT +#define I2S_COUNT 1 + +#define I2S_EASYDMA_MAXCNT_SIZE 14 + +/* Universal Serial Bus Device */ +#define USBD_PRESENT +#define USBD_COUNT 1 + +#define USBD_EASYDMA_MAXCNT_SIZE 7 + +/* ARM TrustZone Cryptocell 310 */ +#define CRYPTOCELL_PRESENT +#define CRYPTOCELL_COUNT 1 + +/* Quad SPI */ +#define QSPI_PRESENT +#define QSPI_COUNT 1 + +#define QSPI_EASYDMA_MAXCNT_SIZE 20 + +#endif // _NRF52840_PERIPHERALS_H diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_bitfields.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_bitfields.h new file mode 100755 index 0000000..2b4aa81 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_bitfields.h @@ -0,0 +1,12654 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF52_BITS_H +#define __NRF52_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for END event */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for END event */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: BPROT */ +/* Description: Block Protect */ + +/* Register: BPROT_CONFIG0 */ +/* Description: Block protect configuration register 0 */ + +/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */ + +/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */ + +/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */ + +/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */ + +/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */ + +/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */ + +/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */ + +/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */ + +/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */ + +/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */ + +/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */ + +/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */ + +/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */ + +/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */ + +/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */ + +/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */ + +/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */ + +/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */ + +/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */ + +/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */ + +/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */ + +/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */ + +/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */ + +/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */ + +/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */ + +/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */ + +/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */ + +/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */ + +/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */ + +/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */ + +/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */ + +/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */ + +/* Register: BPROT_CONFIG1 */ +/* Description: Block protect configuration register 1 */ + +/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */ +#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */ +#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */ +#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */ +#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */ +#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */ +#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */ +#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */ +#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */ +#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */ +#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */ +#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */ +#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */ +#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */ +#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */ +#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */ +#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */ +#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */ +#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */ +#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */ +#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */ +#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */ +#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */ +#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */ +#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */ +#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */ +#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */ +#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */ +#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */ +#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */ +#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */ +#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */ +#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_DISABLEINDEBUG */ +/* Description: Disable protection mechanism in debug interface mode */ + +/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */ + +/* Register: BPROT_CONFIG2 */ +/* Description: Block protect configuration register 2 */ + +/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */ +#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */ +#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */ +#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */ +#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */ +#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */ +#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */ +#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */ +#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */ +#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */ +#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */ +#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */ +#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */ +#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */ +#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */ +#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */ +#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */ +#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */ +#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */ +#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */ +#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */ +#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */ +#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */ +#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */ +#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */ +#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */ +#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */ +#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */ +#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */ +#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */ +#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */ +#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */ +#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */ +#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */ +#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */ +#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */ +#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */ +#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */ +#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */ +#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */ +#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */ +#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */ +#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */ +#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */ +#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */ +#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */ +#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */ +#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */ +#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */ +#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */ +#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */ +#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */ +#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */ +#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */ +#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */ +#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */ +#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */ +#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */ +#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */ +#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */ +#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */ +#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */ +#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */ +#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */ +#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */ +#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_CONFIG3 */ +/* Description: Block protect configuration register 3 */ + +/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */ +#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */ +#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */ +#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */ +#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */ +#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */ +#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */ +#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */ +#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */ +#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */ +#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */ +#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */ +#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */ +#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */ +#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */ +#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */ +#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */ +#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */ +#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */ +#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */ +#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */ +#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */ +#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */ +#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */ +#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */ +#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */ +#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */ +#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */ +#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */ +#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */ +#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */ +#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */ +#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */ +#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */ +#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */ +#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */ +#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */ +#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */ +#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */ +#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */ +#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */ +#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */ +#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */ +#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */ +#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */ +#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */ +#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */ +#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */ +#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */ +#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */ +#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */ +#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */ +#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */ +#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */ +#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */ +#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */ +#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */ +#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */ +#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */ +#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */ +#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */ +#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */ +#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */ +#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */ +#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */ +#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for ERROR event */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for ERROR event */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */ + +/* Bit 16 : Data rate that the CCM shall run in synch with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */ + +/* Bit 0 : The mode of operation to be used */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for CTTO event */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DONE event */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for CTTO event */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DONE event */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + +/* Register: CLOCK_TRACECONFIG */ +/* Description: Clocking options for the Trace Port debug interface */ + +/* Bits 17..16 : Pin multiplexing of trace signals. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ +#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */ + +/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for CROSS event */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for UP event */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for DOWN event */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select for single-ended mode */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bits 2..0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation modes */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power modes */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + +/* Register: COMP_ISOURCE */ +/* Description: Current source select on analog input */ + +/* Bits 1..0 : Comparator hysteresis */ +#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */ +#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory Information Configuration Registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection[0]: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection[0]: Encryption Root, word 0 */ + +/* Bits 31..0 : Encryption Root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection[0]: Identity Root, word 0 */ + +/* Bits 31..0 : Identity Root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection[0]: Device address 0 */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part Variant, Hardware version and Production configuration */ + +/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ +#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ +#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5. */ + +/* Bits 11..0 : A (slope definition) register. */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: y-intercept B0. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: y-intercept B1. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: y-intercept B2. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: y-intercept B3. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: y-intercept B4. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: y-intercept B5. */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4. */ + +/* Bits 7..0 : T (segment end)register. */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_NFC_TAGHEADER0 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 3 */ +#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ +#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ + +/* Bits 23..16 : Unique identifier byte 2 */ +#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ +#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ + +/* Bits 15..8 : Unique identifier byte 1 */ +#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ +#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ + +/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ +#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ +#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ + +/* Register: FICR_NFC_TAGHEADER1 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 7 */ +#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ +#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ + +/* Bits 23..16 : Unique identifier byte 6 */ +#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ +#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ + +/* Bits 15..8 : Unique identifier byte 5 */ +#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ +#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ + +/* Bits 7..0 : Unique identifier byte 4 */ +#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ +#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ + +/* Register: FICR_NFC_TAGHEADER2 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 11 */ +#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ +#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ + +/* Bits 23..16 : Unique identifier byte 10 */ +#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ +#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ + +/* Bits 15..8 : Unique identifier byte 9 */ +#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ +#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ + +/* Bits 7..0 : Unique identifier byte 8 */ +#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ +#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ + +/* Register: FICR_NFC_TAGHEADER3 */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + +/* Bits 31..24 : Unique identifier byte 15 */ +#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ +#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ + +/* Bits 23..16 : Unique identifier byte 14 */ +#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ +#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ + +/* Bits 15..8 : Unique identifier byte 13 */ +#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ +#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ + +/* Bits 7..0 : Unique identifier byte 12 */ +#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ +#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to Enable interrupt for PORT event */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to Disable interrupt for PORT event */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: I2S */ +/* Description: Inter-IC Sound */ + +/* Register: I2S_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for STOPPED event */ +#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ +#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ +#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ +#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ + +/* Register: I2S_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ +#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ +#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ +#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ + +/* Register: I2S_ENABLE */ +/* Description: Enable I2S module. */ + +/* Bit 0 : Enable I2S module. */ +#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: I2S_CONFIG_MODE */ +/* Description: I2S mode. */ + +/* Bit 0 : I2S mode. */ +#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ + +/* Register: I2S_CONFIG_RXEN */ +/* Description: Reception (RX) enable. */ + +/* Bit 0 : Reception (RX) enable. */ +#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ + +/* Register: I2S_CONFIG_TXEN */ +/* Description: Transmission (TX) enable. */ + +/* Bit 0 : Transmission (TX) enable. */ +#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ + +/* Register: I2S_CONFIG_MCKEN */ +/* Description: Master clock generator enable. */ + +/* Bit 0 : Master clock generator enable. */ +#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ + +/* Register: I2S_CONFIG_MCKFREQ */ +/* Description: Master clock generator frequency. */ + +/* Bits 31..0 : Master clock generator frequency. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ + +/* Register: I2S_CONFIG_RATIO */ +/* Description: MCK / LRCK ratio. */ + +/* Bits 3..0 : MCK / LRCK ratio. */ +#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ +#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ + +/* Register: I2S_CONFIG_SWIDTH */ +/* Description: Sample width. */ + +/* Bits 1..0 : Sample width. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ + +/* Register: I2S_CONFIG_ALIGN */ +/* Description: Alignment of sample within a frame. */ + +/* Bit 0 : Alignment of sample within a frame. */ +#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ + +/* Register: I2S_CONFIG_FORMAT */ +/* Description: Frame format. */ + +/* Bit 0 : Frame format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ + +/* Register: I2S_CONFIG_CHANNELS */ +/* Description: Enable channels. */ + +/* Bits 1..0 : Enable channels. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ + +/* Register: I2S_RXD_PTR */ +/* Description: Receive buffer RAM start address. */ + +/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ +#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_TXD_PTR */ +/* Description: Transmit buffer RAM start address. */ + +/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ +#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: I2S_RXTXD_MAXCNT */ +/* Description: Size of RXD and TXD buffers. */ + +/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: I2S_PSEL_MCK */ +/* Description: Pin select for MCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SCK */ +/* Description: Pin select for SCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_LRCK */ +/* Description: Pin select for LRCK signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDIN */ +/* Description: Pin select for SDIN signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: I2S_PSEL_SDOUT */ +/* Description: Pin select for SDOUT signal. */ + +/* Bit 31 : Connection */ +#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: LPCOMP */ +/* Description: Low Power Comparator */ + +/* Register: LPCOMP_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between CROSS event and STOP task */ +#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between UP event and STOP task */ +#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DOWN event and STOP task */ +#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between READY event and STOP task */ +#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and SAMPLE task */ +#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: LPCOMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ +#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for UP event */ +#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ +#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: LPCOMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ +#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for UP event */ +#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ +#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: LPCOMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ + +/* Register: LPCOMP_ENABLE */ +/* Description: Enable LPCOMP */ + +/* Bits 1..0 : Enable or disable LPCOMP */ +#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: LPCOMP_PSEL */ +/* Description: Input pin select */ + +/* Bits 2..0 : Analog pin select */ +#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ + +/* Register: LPCOMP_REFSEL */ +/* Description: Reference select */ + +/* Bits 3..0 : Reference select */ +#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ +#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ +#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ + +/* Register: LPCOMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bit 0 : External analog reference select */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ + +/* Register: LPCOMP_ANADETECT */ +/* Description: Analog detect configuration */ + +/* Bits 1..0 : Analog detect configuration */ +#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ +#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ +#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ +#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ + +/* Register: LPCOMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis enable */ +#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */ + + +/* Peripheral: MWU */ +/* Description: Memory Watch Unit */ + +/* Register: MWU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ +#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ +#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ +#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ +#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ +#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ +#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ +#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ +#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ +#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ +#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ +#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ +#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ +#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ +#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ +#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ +#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ +#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ +#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ +#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ +#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ +#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ +#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ +#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ +#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_NMIEN */ +/* Description: Enable or disable non-maskable interrupt */ + +/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ +#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ + +/* Register: MWU_NMIENSET */ +/* Description: Enable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ + +/* Register: MWU_NMIENCLR */ +/* Description: Disable non-maskable interrupt */ + +/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ +#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ +#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ +#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ +#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ +#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ +#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ +#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ +#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ +#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ +#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ +#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ +#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ +#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ +#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ +#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ +#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ +#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ +#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ +#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ +#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ +#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ +#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ +#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ +#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ +#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ +#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ + +/* Register: MWU_PERREGION_SUBSTATWA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ + +/* Register: MWU_PERREGION_SUBSTATRA */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ + +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ +#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ +#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ + +/* Register: MWU_REGIONEN */ +/* Description: Enable/disable regions watch */ + +/* Bit 27 : Enable/disable read access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable/disable write access watch in PREGION[1] */ +#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable/disable read access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable/disable write access watch in PREGION[0] */ +#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ +#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable/disable read access watch in region[3] */ +#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable/disable write access watch in region[3] */ +#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable/disable read access watch in region[2] */ +#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable/disable write access watch in region[2] */ +#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable/disable read access watch in region[1] */ +#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable/disable write access watch in region[1] */ +#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable/disable read access watch in region[0] */ +#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ +#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable/disable write access watch in region[0] */ +#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ +#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENSET */ +/* Description: Enable regions watch */ + +/* Bit 27 : Enable read access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 26 : Enable write access watch in PREGION[1] */ +#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 25 : Enable read access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ + +/* Bit 24 : Enable write access watch in PREGION[0] */ +#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ + +/* Bit 7 : Enable read access watch in region[3] */ +#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 6 : Enable write access watch in region[3] */ +#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 5 : Enable read access watch in region[2] */ +#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 4 : Enable write access watch in region[2] */ +#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 3 : Enable read access watch in region[1] */ +#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 2 : Enable write access watch in region[1] */ +#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Bit 1 : Enable read access watch in region[0] */ +#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ + +/* Bit 0 : Enable write access watch in region[0] */ +#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ + +/* Register: MWU_REGIONENCLR */ +/* Description: Disable regions watch */ + +/* Bit 27 : Disable read access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ +#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 26 : Disable write access watch in PREGION[1] */ +#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ +#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 25 : Disable read access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ +#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ + +/* Bit 24 : Disable write access watch in PREGION[0] */ +#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ +#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ +#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ +#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ + +/* Bit 7 : Disable read access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ +#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 6 : Disable write access watch in region[3] */ +#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ +#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 5 : Disable read access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ +#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 4 : Disable write access watch in region[2] */ +#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ +#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 3 : Disable read access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ +#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 2 : Disable write access watch in region[1] */ +#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ +#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Bit 1 : Disable read access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ +#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ + +/* Bit 0 : Disable write access watch in region[0] */ +#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ +#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ +#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ +#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ + +/* Register: MWU_REGION_START */ +/* Description: Description cluster[0]: Start address for region 0 */ + +/* Bits 31..0 : Start address for region */ +#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_REGION_END */ +/* Description: Description cluster[0]: End address of region 0 */ + +/* Bits 31..0 : End address of region. */ +#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_START */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ +#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ + +/* Register: MWU_PREGION_END */ +/* Description: Description cluster[0]: Reserved for future use */ + +/* Bits 31..0 : Reserved for future use */ +#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ +#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ + +/* Register: MWU_PREGION_SUBS */ +/* Description: Description cluster[0]: Subregions of region 0 */ + +/* Bit 31 : Include or exclude subregion 31 in region */ +#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ +#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude subregion 30 in region */ +#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ +#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude subregion 29 in region */ +#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ +#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude subregion 28 in region */ +#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ +#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude subregion 27 in region */ +#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ +#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude subregion 26 in region */ +#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ +#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude subregion 25 in region */ +#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ +#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude subregion 24 in region */ +#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ +#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude subregion 23 in region */ +#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ +#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude subregion 22 in region */ +#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ +#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude subregion 21 in region */ +#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ +#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude subregion 20 in region */ +#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ +#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude subregion 19 in region */ +#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ +#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude subregion 18 in region */ +#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ +#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude subregion 17 in region */ +#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ +#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude subregion 16 in region */ +#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ +#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude subregion 15 in region */ +#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ +#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude subregion 14 in region */ +#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ +#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude subregion 13 in region */ +#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ +#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude subregion 12 in region */ +#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ +#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude subregion 11 in region */ +#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ +#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude subregion 10 in region */ +#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ +#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude subregion 9 in region */ +#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ +#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude subregion 8 in region */ +#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ +#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude subregion 7 in region */ +#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ +#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude subregion 6 in region */ +#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ +#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude subregion 5 in region */ +#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ +#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude subregion 4 in region */ +#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ +#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude subregion 3 in region */ +#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ +#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude subregion 2 in region */ +#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ +#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude subregion 1 in region */ +#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ +#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude subregion 0 in region */ +#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ +#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ +#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ + + +/* Peripheral: NFCT */ +/* Description: NFC-A compatible radio */ + +/* Register: NFCT_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ +#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: NFCT_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 20 : Enable or disable interrupt for STARTED event */ +#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for SELECTED event */ +#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for COLLISION event */ +#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for ENDTX event */ +#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for ENDRX event */ +#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for RXERROR event */ +#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for ERROR event */ +#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for READY event */ +#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: NFCT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 20 : Write '1' to Enable interrupt for STARTED event */ +#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ +#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ +#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ +#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ +#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ +#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for ERROR event */ +#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ +#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ +#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ +#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ +#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ +#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ +#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: NFCT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 20 : Write '1' to Disable interrupt for STARTED event */ +#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ +#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ +#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ +#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ +#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ +#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ +#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ +#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ +#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for ERROR event */ +#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ +#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ +#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ +#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ +#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ +#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ +#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ +#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ +#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ +#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ +#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ +#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ +#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: NFCT_ERRORSTATUS */ +/* Description: NFC Error Status register */ + +/* Bit 3 : Field level is too low at min load resistance */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */ + +/* Bit 2 : Field level is too high at max load resistance */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */ +#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */ + +/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ +#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ + +/* Register: NFCT_FRAMESTATUS_RX */ +/* Description: Result of last incoming frames */ + +/* Bit 3 : Overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ +#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ + +/* Bit 2 : Parity status of received frame */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ +#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ + +/* Bit 0 : No valid End of Frame detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ +#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ + +/* Register: NFCT_CURRENTLOADCTRL */ +/* Description: Current value driven to the NFC Load Control */ + +/* Bits 5..0 : Current value driven to the NFC Load Control */ +#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */ +#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */ + +/* Register: NFCT_FIELDPRESENT */ +/* Description: Indicates the presence or not of a valid field */ + +/* Bit 1 : Indicates if the low level has locked to the field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ +#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ +#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ + +/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ +#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ + +/* Register: NFCT_FRAMEDELAYMIN */ +/* Description: Minimum frame delay */ + +/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ +#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ + +/* Register: NFCT_FRAMEDELAYMAX */ +/* Description: Maximum frame delay */ + +/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ + +/* Register: NFCT_FRAMEDELAYMODE */ +/* Description: Configuration register for the Frame Delay Timer */ + +/* Bits 1..0 : Configuration register for the Frame Delay Timer */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ +#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ + +/* Register: NFCT_PACKETPTR */ +/* Description: Packet pointer for TXD and RXD data storage in Data RAM */ + +/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */ +#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: NFCT_MAXLEN */ +/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */ + +/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */ +#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: NFCT_TXD_FRAMECONFIG */ +/* Description: Configuration of outgoing frames */ + +/* Bit 4 : CRC mode for outgoing frames */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ +#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ + +/* Bit 2 : Adding SoF or not in TX frames */ +#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */ +#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */ + +/* Bit 1 : Discarding unused bits in start or at end of a Frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */ +#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */ + +/* Bit 0 : Adding parity or not in the frame */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */ +#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */ + +/* Register: NFCT_TXD_AMOUNT */ +/* Description: Size of outgoing frame */ + +/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ +#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ +#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ + +/* Register: NFCT_RXD_FRAMECONFIG */ +/* Description: Configuration of incoming frames */ + +/* Bit 4 : CRC mode for incoming frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ + +/* Bit 2 : SoF expected or not in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ +#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */ + +/* Bit 0 : Parity expected or not in RX frame */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ +#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ + +/* Register: NFCT_RXD_AMOUNT */ +/* Description: Size of last incoming frame */ + +/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ +#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ + +/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ +#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ + +/* Register: NFCT_NFCID1_LAST */ +/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ + +/* Bits 31..24 : NFCID1 byte W */ +#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ +#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ + +/* Bits 23..16 : NFCID1 byte X */ +#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ +#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ + +/* Bits 15..8 : NFCID1 byte Y */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ +#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ + +/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ +#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ + +/* Register: NFCT_NFCID1_2ND_LAST */ +/* Description: Second last NFCID1 part (7 or 10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte T */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ + +/* Bits 15..8 : NFCID1 byte U */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ + +/* Bits 7..0 : NFCID1 byte V */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ +#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ + +/* Register: NFCT_NFCID1_3RD_LAST */ +/* Description: Third last NFCID1 part (10 bytes ID) */ + +/* Bits 23..16 : NFCID1 byte Q */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ + +/* Bits 15..8 : NFCID1 byte R */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ + +/* Bits 7..0 : NFCID1 byte S */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ +#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ + +/* Register: NFCT_SENSRES */ +/* Description: NFC-A SENS_RES auto-response settings */ + +/* Bits 15..12 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ +#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ + +/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ +#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ + +/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */ +#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ +#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ + +/* Bit 5 : Reserved for future use. Shall be 0. */ +#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ +#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ + +/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ +#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ + +/* Register: NFCT_SELRES */ +/* Description: NFC-A SEL_RES auto-response settings */ + +/* Bit 7 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ +#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ + +/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ +#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ + +/* Bits 4..3 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ +#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ + +/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */ +#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ +#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */ +#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */ + +/* Bits 1..0 : Reserved for future use. Shall be 0. */ +#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ +#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ + + +/* Peripheral: NVMC */ +/* Description: Non Volatile Memory Controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in Code area */ + +/* Bits 31..0 : Register for starting erase of a page in Code area */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing User Information Configuration Registers */ + +/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ICACHECNF */ +/* Description: I-Code cache configuration register. */ + +/* Bit 8 : Cache profiling enable */ +#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ + +/* Bit 0 : Cache enable */ +#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ + +/* Register: NVMC_IHIT */ +/* Description: I-Code cache hit counter. */ + +/* Bits 31..0 : Number of cache hits */ +#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ +#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ + +/* Register: NVMC_IMISS */ +/* Description: I-Code cache miss counter. */ + +/* Bits 31..0 : Number of cache misses */ +#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ +#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port 1 */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection[0]: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for END event */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for END event */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for END event */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ +#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ +#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ +#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ +#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ +#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_RAMSTATUS */ +/* Description: Deprecated register - RAM status register */ + +/* Bit 3 : RAM block 3 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ +#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ + +/* Bit 2 : RAM block 2 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ +#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ + +/* Bit 1 : RAM block 1 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ +#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ + +/* Bit 0 : RAM block 0 is on or off/powering up */ +#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ +#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ +#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power failure comparator configuration */ + +/* Bits 4..1 : Power failure comparator threshold setting */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure comparator */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_RAMON */ +/* Description: Deprecated register - RAM on/off register (this register is retained) */ + +/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */ +#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ +#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */ +#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */ +#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ +#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */ +#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */ +#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ +#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */ +#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */ +#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ +#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */ +#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */ + +/* Register: POWER_RAMONB */ +/* Description: Deprecated register - RAM on/off register (this register is retained) */ + +/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */ +#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ +#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */ +#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */ +#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ +#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */ +#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */ +#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ +#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */ +#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */ +#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ +#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */ +#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */ + +/* Register: POWER_DCDCEN */ +/* Description: DC/DC enable register */ + +/* Bit 0 : Enable or disable DC/DC converter */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster[0]: RAM0 power control register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster[0]: RAM0 power control set register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster[0]: RAM0 power control clear register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster[0]: Channel 0 event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection[0]: Channel group 0 */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster[0]: Channel 0 task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse Width Modulation Unit 0 */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up or up and down as wave counter mode */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Pre-scaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Amount of playback of a loop */ + +/* Bits 15..0 : Amount of playback of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */ + +/* Bits 31..0 : Beginning address in Data RAM of this sequence */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */ + +/* Bits 14..0 : Amount of values (duty cycles) in this sequence */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */ + +/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster[0]: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection[0]: Output pin select for PWM channel 0 */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz Radio */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between END event and START task */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between END event and DISABLE task */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between READY event and START task */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for END event */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for READY event */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for END event */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for READY event */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power. */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bit 8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Inter Frame Spacing in us */ + +/* Bits 7..0 : Inter Frame Spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection[0]: Device address base segment 0 */ + +/* Bits 31..0 : Device address base segment 0 */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection[0]: Device address prefix 0 */ + +/* Bits 15..0 : Device address prefix 0 */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 0 : Shortcut between VALRDY event and STOP task */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for TICK event */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for TICK event */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable event routing for OVRFLW event */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable event routing for TICK event */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable event routing for TICK event */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable event routing for TICK event */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection[0]: Compare register 0 */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Analog to Digital Converter */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for STOPPED event */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for DONE event */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for END event */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for STARTED event */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for DONE event */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for DONE event */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable ADC */ + +/* Bit 0 : Enable or disable ADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster[0]: Input positive pin selection for CH[0] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster[0]: Input negative pin selection for CH[0] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster[0]: Input configuration for CH[0] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster[0]: High/low limits for event monitoring a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 14..0 : Maximum number of buffer words to transfer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of buffer words transferred since last START */ + +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for READY event */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to Disable interrupt for READY event */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bits 31..0 : Pin number configuration for SPI SCK signal */ +#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */ +#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */ +#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI */ + +/* Bits 31..0 : Pin number configuration for SPI MOSI signal */ +#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */ +#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */ +#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO */ + +/* Bits 31..0 : Pin number configuration for SPI MISO signal */ +#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */ +#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */ +#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 17 : Shortcut between END event and START task */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to Enable interrupt for STARTED event */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to Enable interrupt for END event */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to Disable interrupt for STARTED event */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to Disable interrupt for END event */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ + +/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 2 : Shortcut between END event and ACQUIRE task */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for END event */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for END event */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 7..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 7..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection[0]: Capture/Compare register 0 */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface 0 */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 1 : Shortcut between BB event and STOP task */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between BB event and SUSPEND task */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to Enable interrupt for BB event */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to Disable interrupt for BB event */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSELSCL */ +/* Description: Pin select for SCL */ + +/* Bits 31..0 : Pin number configuration for TWI SCL signal */ +#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */ +#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */ +#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: TWI_PSELSDA */ +/* Description: Pin select for SDA */ + +/* Bits 31..0 : Pin number configuration for TWI SDA signal */ +#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */ +#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */ +#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 12 : Shortcut between LASTRX event and STOP task */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between LASTTX event and STOP task */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for LASTTX event */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for LASTRX event */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 14 : Shortcut between READ event and SUSPEND task */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for READ event */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for WRITE event */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for STOPPED event */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to Enable interrupt for READ event */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to Enable interrupt for WRITE event */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to Disable interrupt for READ event */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to Disable interrupt for WRITE event */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 7..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection[0]: TWI slave address 0 */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between CTS event and STARTRX task */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSELRTS */ +/* Description: Pin select for RTS */ + +/* Bits 31..0 : Pin number configuration for UART RTS signal */ +#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */ +#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */ +#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELTXD */ +/* Description: Pin select for TXD */ + +/* Bits 31..0 : Pin number configuration for UART TXD signal */ +#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */ +#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */ +#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELCTS */ +/* Description: Pin select for CTS */ + +/* Bits 31..0 : Pin number configuration for UART CTS signal */ +#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */ +#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */ +#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_PSELRXD */ +/* Description: Pin select for RXD */ + +/* Bits 31..0 : Pin number configuration for UART RXD signal */ +#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */ +#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */ +#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcut register */ + +/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for RXTO event */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for ERROR event */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for ENDTX event */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for ENDRX event */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for NCTS event */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for CTS event */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 7..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 7..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User Information Configuration Registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection[0]: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection[0]: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection[0]: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 5..0 : GPIO number P0.n onto which Reset is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access Port protection */ + +/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + +/* Register: UICR_NFCPINS */ +/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ + +/* Bit 0 : Setting of pins dedicated to NFC functionality */ +#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection[0]: Reload request 0 */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_name_change.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_name_change.h new file mode 100755 index 0000000..3631d24 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_name_change.h @@ -0,0 +1,72 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_NAME_CHANGE_H +#define NRF52_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and + * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead. + */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + +/*lint --flb "Leave library region" */ + +#endif /* NRF52_NAME_CHANGE_H */ + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_to_nrf52810.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_to_nrf52810.h new file mode 100755 index 0000000..e702e87 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_to_nrf52810.h @@ -0,0 +1,96 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_TO_NRF52810_H +#define NRF52_TO_NRF52810_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52810 devices. + * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf52_namechange.h file. */ + +/* Differences between latest nRF52 headers and nRF52810 headers. */ + +/* Interrupt service routines handlers. Note that handlers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler and + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler are not redefined since functionality is not equivalent. */ +#define UARTE0_UART0_IRQHandler UARTE0_IRQHandler +#define COMP_LPCOMP_IRQHandler COMP_IRQHandler +#define SWI2_EGU2_IRQHandler SWI2_IRQHandler +#define SWI3_EGU3_IRQHandler SWI3_IRQHandler +#define SWI4_EGU4_IRQHandler SWI4_IRQHandler +#define SWI5_EGU5_IRQHandler SWI5_IRQHandler + +/* Interrupt service routines index. Note that indexes SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn and + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn are not redefined since functionality is not equivalent. */ +#define UARTE0_UART0_IRQn UARTE0_IRQn +#define COMP_LPCOMP_IRQn COMP_IRQn +#define SWI2_EGU2_IRQn SWI2_IRQn +#define SWI3_EGU3_IRQn SWI3_IRQn +#define SWI4_EGU4_IRQn SWI4_IRQn +#define SWI5_EGU5_IRQn SWI5_IRQn + + +/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52810_H */ + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_to_nrf52840.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_to_nrf52840.h new file mode 100755 index 0000000..67345cc --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf52_to_nrf52840.h @@ -0,0 +1,96 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52_TO_NRF52840_H +#define NRF52_TO_NRF52840_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices. + * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * from the nrf52_namechange.h file. */ + +/* Differences between latest nRF52 headers and nRF52840 headers. */ + +/* UART */ +/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ +#define PSELRTS PSEL.RTS +#define PSELTXD PSEL.TXD +#define PSELCTS PSEL.CTS +#define PSELRXD PSEL.RXD + +/* TWI */ +/* The registers PSELSCL, PSELSDA were restructured into a struct. */ +#define PSELSCL PSEL.SCL +#define PSELSDA PSEL.SDA + + +/* LPCOMP */ +/* The hysteresis control enumerated values has changed name for nRF52840 devices. */ +#define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled +#define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled + + +/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ + +/* I2S */ +/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right + +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below + + +/*lint --flb "Leave library region" */ + +#endif /* NRF51_TO_NRF52840_H */ + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/nrf_peripherals.h b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf_peripherals.h new file mode 100755 index 0000000..352b41c --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/nrf_peripherals.h @@ -0,0 +1,63 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_PERIPHERALS_H__ +#define NRF_PERIPHERALS_H__ + +/*lint ++flb "Enter library region */ + +#if defined(_WIN32) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__unix) + /* Do not include nrf specific files when building for PC host */ +#elif defined(__APPLE__) + /* Do not include nrf specific files when building for PC host */ +#else + + #if defined(NRF51) + #include "nrf51_peripherals.h" + + #elif defined(NRF52810_XXAA) + #include "nrf52810_peripherals.h" + #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) + #include "nrf52832_peripherals.h" + #elif defined(NRF52840_XXAA) + #include "nrf52840_peripherals.h" + + #else + #error "Device must be defined. See nrf.h." + #endif +#endif + +/*lint --flb "Leave library region" */ + +#endif // NRF_PERIPHERALS_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/startup_config.h b/arduino/cores/nRF5/nordic/nrfx/mdk/startup_config.h new file mode 100755 index 0000000..b9e9ae3 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/startup_config.h @@ -0,0 +1,51 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +/* Configure stack size, stack alignement and heap size with a header file instead of project settings or modification of Nordic provided assembler files. Modify this file as needed. */ + +/* In order to make use this file, + 1. For Keil uVision IDE, in the Options for Target -> Asm tab, define symbol __STARTUP_CONFIG and use the additional assembler option --cpreproc in Misc Control text box. + 2. For GCC compiling, add extra assembly option -D__STARTUP_CONFIG. + 3. For IAR Embedded Workbench define symbol __STARTUP_CONFIG in the Assembler options and define symbol __STARTUP_CONFIG=1 in the linker options. +*/ + +/* This file is a template and should be copied to the project directory. */ + +/* Define size of stack. Size must be multiple of 4. */ +#define __STARTUP_CONFIG_STACK_SIZE 0x1000 + +/* Define alignement of stack. Alignment will be 2 to the power of __STARTUP_CONFIG_STACK_ALIGNEMENT. Since calling convention requires that the stack is aligned to 8-bytes when a function is called, the minimum __STARTUP_CONFIG_STACK_ALIGNEMENT is therefore 3. */ +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + +/* Define size of heap. Size must be multiple of 4. */ +#define __STARTUP_CONFIG_HEAP_SIZE 0x1000 + diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52.c b/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52.c new file mode 100755 index 0000000..c2d7066 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52.c @@ -0,0 +1,377 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifdef NRF52832_XXAA + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include <stdint.h> +#include <stdbool.h> +#include "nrf.h" +#include "system_nrf52.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_64M (64000000UL) + +static bool errata_12(void); +static bool errata_16(void); +static bool errata_31(void); +static bool errata_32(void); +static bool errata_36(void); +static bool errata_37(void); +static bool errata_57(void); +static bool errata_66(void); +static bool errata_108(void); +static bool errata_136(void); +static bool errata_182(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_12()){ + *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; + } + + /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_16()){ + *(volatile uint32_t *)0x4007C074 = 3131961357ul; + } + + /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_31()){ + *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; + } + + /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_32()){ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } + + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_37()){ + *(volatile uint32_t *)0x400005A0 = 0x3; + } + + /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_57()){ + *(volatile uint32_t *)0x40005610 = 0x00000005; + *(volatile uint32_t *)0x40005688 = 0x00000001; + *(volatile uint32_t *)0x40005618 = 0x00000000; + *(volatile uint32_t *)0x40005614 = 0x0000003F; + } + + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + + /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_108()){ + *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; + } + + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_136()){ + if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ + NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; + } + } + + /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_182()){ + *(volatile uint32_t *) 0x4000173C |= (0x1 << 10); + } + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + SystemCoreClockUpdate(); +} + + +static bool errata_12(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + +static bool errata_16(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + } + + return false; +} + +static bool errata_31(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + +static bool errata_32(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + } + + return false; +} + +static bool errata_36(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + +static bool errata_37(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + } + + return false; +} + +static bool errata_57(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + } + + return false; +} + +static bool errata_66(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + + +static bool errata_108(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + + +static bool errata_136(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)){ + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40){ + return true; + } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50){ + return true; + } + } + + return false; +} + + +static bool errata_182(void) +{ + if (*(uint32_t *)0x10000130ul == 0x6ul){ + if (*(uint32_t *)0x10000134ul == 0x6ul){ + return true; + } + } + + return false; +} + + +/*lint --flb "Leave library region" */ + +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52.h b/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52.h new file mode 100755 index 0000000..d05316c --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52_H +#define SYSTEM_NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52_H */ diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52840.c b/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52840.c new file mode 100755 index 0000000..51322cd --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52840.c @@ -0,0 +1,292 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifdef NRF52840_XXAA + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include <stdint.h> +#include <stdbool.h> +#include "nrf.h" +#include "system_nrf52840.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_64M (64000000UL) + +static bool errata_36(void); +static bool errata_66(void); +static bool errata_98(void); +static bool errata_103(void); +static bool errata_115(void); +static bool errata_120(void); +static bool errata_136(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product + Specification to see which one). */ + #if defined (ENABLE_SWO) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product + Specification to see which ones). */ + #if defined (ENABLE_TRACE) + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; + NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + #endif + + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + + /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_98()){ + *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; + } + + /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_103()){ + NRF_CCM->MAXPACKETSIZE = 0xFBul; + } + + /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_115()){ + *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); + } + + /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_120()){ + *(volatile uint32_t *)0x40029640ul = 0x200ul; + } + + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_136()){ + if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ + NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; + } + } + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 18; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 18; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + SystemCoreClockUpdate(); +} + + +static bool errata_36(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + } + + return true; +} + + +static bool errata_66(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + } + + return true; +} + + +static bool errata_98(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; +} + + +static bool errata_103(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; +} + + +static bool errata_115(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; +} + + +static bool errata_120(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + } + + return false; +} + + +static bool errata_136(void) +{ + if (*(uint32_t *)0x10000130ul == 0x8ul){ + if (*(uint32_t *)0x10000134ul == 0x0ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x1ul){ + return true; + } + if (*(uint32_t *)0x10000134ul == 0x2ul){ + return true; + } + } + + return true; +} + +/*lint --flb "Leave library region" */ + +#endif diff --git a/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52840.h b/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52840.h new file mode 100755 index 0000000..28b3151 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/mdk/system_nrf52840.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52840_H +#define SYSTEM_NRF52840_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52840_H */ diff --git a/arduino/cores/nRF5/nordic/nrfx/nrfx.h b/arduino/cores/nRF5/nordic/nrfx/nrfx.h new file mode 100755 index 0000000..1f1f40d --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/nrfx.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_H__ +#define NRFX_H__ + +#include <nrfx_config.h> +#include <drivers/nrfx_common.h> +#include <nrfx_glue.h> +#include <drivers/nrfx_errors.h> + +#endif // NRFX_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_coredep.h b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_coredep.h new file mode 100755 index 0000000..0ba8489 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_coredep.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_COREDEP_H__ +#define NRFX_COREDEP_H__ + +/** + * @defgroup nrfx_coredep Core-dependent functionality + * @{ + * @ingroup nrfx + * @brief Module containing functions with core-dependent implementation, like delay. + */ + +#if defined(__NRFX_DOXYGEN__) + +/** @brief Core frequency (in MHz). */ +#define NRFX_DELAY_CPU_FREQ_MHZ +/** @brief Availability of DWT unit in the given SoC. */ +#define NRFX_DELAY_DWT_PRESENT + +#elif defined(NRF51) + #define NRFX_DELAY_CPU_FREQ_MHZ 16 + #define NRFX_DELAY_DWT_PRESENT 0 +#elif defined(NRF52810_XXAA) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 0 +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 1 +#elif defined(NRF52840_XXAA) + #define NRFX_DELAY_CPU_FREQ_MHZ 64 + #define NRFX_DELAY_DWT_PRESENT 1 +#else + #error "Unknown device." +#endif + +/** + * @brief Function for delaying execution for a number of microseconds. + * + * The value of @p time_us is multiplied by the frequency in MHz. Therefore, the delay is limited to + * maximum uint32_t capacity divided by frequency. For example: + * - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds) + * - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds) + * + * @param time_us Number of microseconds to wait. + */ +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us); + +/** @} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +#if NRFX_CHECK(NRFX_DELAY_DWT_BASED) + +#if !NRFX_DELAY_DWT_PRESENT +#error "DWT unit not present in the SoC that is used." +#endif + +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) +{ + if (time_us == 0) + { + return; + } + uint32_t time_cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; + + // Save the current state of the DEMCR register to be able to restore it before exiting + // this function. Enable the trace and debug blocks (DWT is one of them). + uint32_t core_debug = CoreDebug->DEMCR; + CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk; + + // Save the current state of the CTRL register in DWT block. Make sure + // that cycle counter is enabled. + uint32_t dwt_ctrl = DWT->CTRL; + DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk; + + // Store start value of cycle counter. + uint32_t cyccnt_initial = DWT->CYCCNT; + + // Delay required time. + while ((DWT->CYCCNT - cyccnt_initial) < time_cycles) + {} + + // Restore preserved registers. + DWT->CTRL = dwt_ctrl; + CoreDebug->DEMCR = core_debug; +} +#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED) + + +__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) +{ + if (time_us == 0) + { + return; + } + + #if defined(NRF51) + // The loop takes 4 cycles: 1 for SUBS and 3 for BHI. + static const uint16_t delay_bytecode[] = { + 0x3804, // SUBS r0, #4 + 0xd8fd, // BHI .-2 + 0x4770 // BX LR + }; + #elif defined(NRF52810_XXAA) + // The loop takes 7 cycles: 1 for SUBS and 2 for BHI and 2 for flash wait states. + static const uint16_t delay_bytecode[] = { + 0x3807, // SUBS r0, #7 + 0xd8fd, // BHI .-2 + 0x4770 // BX LR + }; + #elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) || defined(NRF52840_XXAA) + // The loop takes 3 cycles: 1 for SUBS and 2 for BHI. + // Make sure that code will be cached properly, so that no extra wait states appear. + __ALIGN(16) + static const uint16_t delay_bytecode[] = { + 0x3803, // SUBS r0, #3 + 0xd8fd, // BHI .-2 + 0x4770 // BX LR + }; + #endif + + typedef void (* delay_func_t)(uint32_t); + // Set LSB to 1 to execute code in Thumb mode. + const delay_func_t delay_cycles = (delay_func_t)((((uint32_t)delay_bytecode) | 1)); + uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ; + delay_cycles(cycles); +} + +#endif // !NRFX_CHECK(NRFX_DELAY_DWT_BASED_DELAY) + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +#endif // NRFX_COREDEP_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs.h b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs.h new file mode 100755 index 0000000..cddf399 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_IRQS_H__ +#define NRFX_IRQS_H__ + +#if defined(NRF51) + #include <soc/nrfx_irqs_nrf51.h> +#elif defined(NRF52810_XXAA) + #include <soc/nrfx_irqs_nrf52810.h> +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) + #include <soc/nrfx_irqs_nrf52832.h> +#elif defined(NRF52840_XXAA) + #include <soc/nrfx_irqs_nrf52840.h> +#else + #error "Unknown device." +#endif + +#endif // NRFX_IRQS_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf51.h b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf51.h new file mode 100755 index 0000000..3c6aeda --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf51.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_IRQS_NRF51_H__ +#define NRFX_IRQS_NRF51_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UART0_IRQn +#define nrfx_uart_0_irq_handler UART0_IRQHandler + +// SPI0_TWI0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler SPI0_TWI0_IRQHandler +#else +#define nrfx_spi_0_irq_handler SPI0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler SPI0_TWI0_IRQHandler +#endif + +// SPI1_TWI1_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPI1_TWI1_IRQHandler +#else +#define nrfx_spi_1_irq_handler SPI1_TWI1_IRQHandler +#define nrfx_spis_1_irq_handler SPI1_TWI1_IRQHandler +#define nrfx_twi_1_irq_handler SPI1_TWI1_IRQHandler +#endif + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// ADC_IRQn +#define nrfx_adc_irq_handler ADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// LPCOMP_IRQn +#define nrfx_lpcomp_irq_handler LPCOMP_IRQHandler + +// SWI0_IRQn +#define nrfx_swi_0_irq_handler SWI0_IRQHandler + +// SWI1_IRQn +#define nrfx_swi_1_irq_handler SWI1_IRQHandler + +// SWI2_IRQn +#define nrfx_swi_2_irq_handler SWI2_IRQHandler + +// SWI3_IRQn +#define nrfx_swi_3_irq_handler SWI3_IRQHandler + +// SWI4_IRQn +#define nrfx_swi_4_irq_handler SWI4_IRQHandler + +// SWI5_IRQn +#define nrfx_swi_5_irq_handler SWI5_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF51_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52810.h b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52810.h new file mode 100755 index 0000000..9ce92e4 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52810.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_IRQS_NRF52832_H__ +#define NRFX_IRQS_NRF52832_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_IRQn +#define nrfx_uarte_0_irq_handler UARTE0_IRQHandler + +// TWIM0_TWIS0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_IRQHandler +#else +#define nrfx_twim_0_irq_handler TWIM0_TWIS0_IRQHandler +#define nrfx_twis_0_irq_handler TWIM0_TWIS0_IRQHandler +#endif + +// SPIM0_SPIS0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM0_SPIS0_IRQHandler +#else +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_IRQHandler +#endif + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// COMP_IRQn +#define nrfx_comp_irq_handler COMP_IRQHandler + +// SWI0_EGU0_IRQn +#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_IRQn +#define nrfx_swi_2_irq_handler SWI2_IRQHandler + +// SWI3_IRQn +#define nrfx_swi_3_irq_handler SWI3_IRQHandler + +// SWI4_IRQn +#define nrfx_swi_4_irq_handler SWI4_IRQHandler + +// SWI5_IRQn +#define nrfx_swi_5_irq_handler SWI5_IRQHandler + +// PWM0_IRQn +#define nrfx_pwm_0_irq_handler PWM0_IRQHandler + +// PDM_IRQn +#define nrfx_pdm_irq_handler PDM_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52832_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52832.h b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52832.h new file mode 100755 index 0000000..0ad4b68 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52832.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_IRQS_NRF52832_H__ +#define NRFX_IRQS_NRF52832_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_UART0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) +#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler +#else +#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler +#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler +#endif + +// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#else +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif + +// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#else +#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif + +// NFCT_IRQn +#define nrfx_nfct_irq_handler NFCT_IRQHandler + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// COMP_LPCOMP_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) +#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler +#else +#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler +#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler +#endif + +// SWI0_EGU0_IRQn +#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_EGU2_IRQn +#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler + +// SWI3_EGU3_IRQn +#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler + +// SWI4_EGU4_IRQn +#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler + +// SWI5_EGU5_IRQn +#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler + +// TIMER3_IRQn +#define nrfx_timer_3_irq_handler TIMER3_IRQHandler + +// TIMER4_IRQn +#define nrfx_timer_4_irq_handler TIMER4_IRQHandler + +// PWM0_IRQn +#define nrfx_pwm_0_irq_handler PWM0_IRQHandler + +// PDM_IRQn +#define nrfx_pdm_irq_handler PDM_IRQHandler + +// MWU_IRQn + +// PWM1_IRQn +#define nrfx_pwm_1_irq_handler PWM1_IRQHandler + +// PWM2_IRQn +#define nrfx_pwm_2_irq_handler PWM2_IRQHandler + +// SPIM2_SPIS2_SPI2_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#else +#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#endif + +// RTC2_IRQn +#define nrfx_rtc_2_irq_handler RTC2_IRQHandler + +// I2S_IRQn +#define nrfx_i2s_irq_handler I2S_IRQHandler + +// FPU_IRQn + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52832_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52840.h b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52840.h new file mode 100755 index 0000000..37dc39d --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx/soc/nrfx_irqs_nrf52840.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_IRQS_NRF52840_H__ +#define NRFX_IRQS_NRF52840_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_UART0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED) +#define nrfx_prs_box_4_irq_handler UARTE0_UART0_IRQHandler +#else +#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler +#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler +#endif + +// SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#else +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_spi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif + +// SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#else +#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_spi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define nrfx_twi_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif + +// NFCT_IRQn +#define nrfx_nfct_irq_handler NFCT_IRQHandler + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// COMP_LPCOMP_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) +#define nrfx_prs_box_3_irq_handler COMP_LPCOMP_IRQHandler +#else +#define nrfx_comp_irq_handler COMP_LPCOMP_IRQHandler +#define nrfx_lpcomp_irq_handler COMP_LPCOMP_IRQHandler +#endif + +// SWI0_EGU0_IRQn +#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_EGU2_IRQn +#define nrfx_swi_2_irq_handler SWI2_EGU2_IRQHandler + +// SWI3_EGU3_IRQn +#define nrfx_swi_3_irq_handler SWI3_EGU3_IRQHandler + +// SWI4_EGU4_IRQn +#define nrfx_swi_4_irq_handler SWI4_EGU4_IRQHandler + +// SWI5_EGU5_IRQn +#define nrfx_swi_5_irq_handler SWI5_EGU5_IRQHandler + +// TIMER3_IRQn +#define nrfx_timer_3_irq_handler TIMER3_IRQHandler + +// TIMER4_IRQn +#define nrfx_timer_4_irq_handler TIMER4_IRQHandler + +// PWM0_IRQn +#define nrfx_pwm_0_irq_handler PWM0_IRQHandler + +// PDM_IRQn +#define nrfx_pdm_irq_handler PDM_IRQHandler + +// MWU_IRQn + +// PWM1_IRQn +#define nrfx_pwm_1_irq_handler PWM1_IRQHandler + +// PWM2_IRQn +#define nrfx_pwm_2_irq_handler PWM2_IRQHandler + +// SPIM2_SPIS2_SPI2_IRQn +#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#else +#define nrfx_spim_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spis_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#define nrfx_spi_2_irq_handler SPIM2_SPIS2_SPI2_IRQHandler +#endif + +// RTC2_IRQn +#define nrfx_rtc_2_irq_handler RTC2_IRQHandler + +// I2S_IRQn +#define nrfx_i2s_irq_handler I2S_IRQHandler + +// FPU_IRQn + +// USBD_IRQn +#define nrfx_usbd_irq_handler USBD_IRQHandler + +// UARTE1_IRQn +#define nrfx_uarte_1_irq_handler UARTE1_IRQHandler + +// QSPI_IRQn +#define nrfx_qspi_irq_handler QSPI_IRQHandler + +// CRYPTOCELL_IRQn + +// PWM3_IRQn +#define nrfx_pwm_3_irq_handler PWM3_IRQHandler + +// SPIM3_IRQn +#define nrfx_spim_3_irq_handler SPIM3_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52840_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx_config.h b/arduino/cores/nRF5/nordic/nrfx_config.h new file mode 100755 index 0000000..4405f44 --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx_config.h @@ -0,0 +1,15 @@ +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +#define NRFX_POWER_ENABLED 1 +#define NRFX_POWER_CONFIG_IRQ_PRIORITY 7 + +//#define NRFX_CLOCK_ENABLED 0 + +#ifdef NRF52840_XXAA +#define NRFX_QSPI_ENABLED 1 +#else +#define NRFX_QSPI_ENABLED 0 +#endif + +#endif // NRFX_CONFIG_H__ diff --git a/arduino/cores/nRF5/nordic/nrfx_glue.h b/arduino/cores/nRF5/nordic/nrfx_glue.h new file mode 100755 index 0000000..2aa3adf --- /dev/null +++ b/arduino/cores/nRF5/nordic/nrfx_glue.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +// Uncomment this line to use the standard MDK way of binding IRQ handlers +// at linking time. +#include <soc/nrfx_irqs.h> + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to evaluate. + */ +#define NRFX_ASSERT(expression) + +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to evaluate. + */ +#define NRFX_STATIC_ASSERT(expression) + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority) +static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, + uint8_t priority) +{ + NRFX_ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); + NVIC_SetPriority(irq_number, priority); +} + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) +static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); + NVIC_EnableIRQ(irq_number); +} + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) +static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) +{ + return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); +} + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) +static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) +{ + NVIC_DisableIRQ(irq_number); +} + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) +static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) +{ + NVIC_SetPendingIRQ(irq_number); +} + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) +static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); +} + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) +static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) +{ + return (NVIC_GetPendingIRQ(irq_number) == 1); +} + +/** + * @brief Macro for entering into a critical section. + */ +#define NRFX_CRITICAL_SECTION_ENTER() + +/** + * @brief Macro for exiting from a critical section. + */ +#define NRFX_CRITICAL_SECTION_EXIT() + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +/** + * @brief Macro for delaying the code execution for at least the specified time. + * + * @param us_time Number of microseconds to wait. + */ +#include <soc/nrfx_coredep.h> +#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined + * in a customized way and the default definitions from @c <nrfx_error.h> + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 0 + +//------------------------------------------------------------------------------ + +/** + * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. + */ +#define NRFX_PPI_CHANNELS_USED 0 + +/** + * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. + */ +#define NRFX_PPI_GROUPS_USED 0 + +/** + * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. + */ +#define NRFX_SWI_USED 0 + +/** + * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. + */ +#define NRFX_TIMERS_USED 0 + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble.h new file mode 100755 index 0000000..76a432b --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble.h @@ -0,0 +1,685 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON BLE SoftDevice Common + @{ + @defgroup ble_api Events, type definitions and API calls + @{ + + @brief Module independent events, type definitions and API calls for the BLE SoftDevice. + + */ + +#ifndef BLE_H__ +#define BLE_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_err.h" +#include "ble_gap.h" +#include "ble_l2cap.h" +#include "ble_gatt.h" +#include "ble_gattc.h" +#include "ble_gatts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations + * @{ */ + +/** + * @brief Common API SVC numbers. + */ +enum BLE_COMMON_SVCS +{ + SD_BLE_ENABLE = BLE_SVC_BASE, /**< Enable and initialize the BLE stack */ + SD_BLE_EVT_GET, /**< Get an event from the pending events queue. */ + SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific base UUID. */ + SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */ + SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */ + SD_BLE_VERSION_GET, /**< Get the local version information (company ID, Link Layer Version, Link Layer Subversion). */ + SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */ + SD_BLE_OPT_SET, /**< Set a BLE option. */ + SD_BLE_OPT_GET, /**< Get a BLE option. */ + SD_BLE_CFG_SET, /**< Add a configuration to the BLE stack. */ + SD_BLE_UUID_VS_REMOVE, /**< Remove a Vendor Specific base UUID. */ +}; + +/** + * @brief BLE Module Independent Event IDs. + */ +enum BLE_COMMON_EVTS +{ + BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. @ref ble_evt_user_mem_request_t */ + BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1, /**< User Memory release. @ref ble_evt_user_mem_release_t */ +}; + +/**@brief BLE Connection Configuration IDs. + * + * IDs that uniquely identify a connection configuration. + */ +enum BLE_CONN_CFGS +{ + BLE_CONN_CFG_GAP = BLE_CONN_CFG_BASE + 0, /**< BLE GAP specific connection configuration. */ + BLE_CONN_CFG_GATTC = BLE_CONN_CFG_BASE + 1, /**< BLE GATTC specific connection configuration. */ + BLE_CONN_CFG_GATTS = BLE_CONN_CFG_BASE + 2, /**< BLE GATTS specific connection configuration. */ + BLE_CONN_CFG_GATT = BLE_CONN_CFG_BASE + 3, /**< BLE GATT specific connection configuration. */ + BLE_CONN_CFG_L2CAP = BLE_CONN_CFG_BASE + 4, /**< BLE L2CAP specific connection configuration. */ +}; + +/**@brief BLE Common Configuration IDs. + * + * IDs that uniquely identify a common configuration. + */ +enum BLE_COMMON_CFGS +{ + BLE_COMMON_CFG_VS_UUID = BLE_CFG_BASE, /**< Vendor specific base UUID configuration */ +}; + +/**@brief Common Option IDs. + * IDs that uniquely identify a common option. + */ +enum BLE_COMMON_OPTS +{ + BLE_COMMON_OPT_PA_LNA = BLE_OPT_BASE + 0, /**< PA and LNA options */ + BLE_COMMON_OPT_CONN_EVT_EXT = BLE_OPT_BASE + 1, /**< Extended connection events option */ + BLE_COMMON_OPT_EXTENDED_RC_CAL = BLE_OPT_BASE + 2, /**< Extended RC calibration option */ + BLE_COMMON_OPT_ADV_SCHED_CFG = BLE_OPT_BASE + 3, /**< Advertiser role scheduling configuration option */ +}; + +/** @} */ + +/** @addtogroup BLE_COMMON_DEFINES Defines + * @{ */ + +/** @brief Required pointer alignment for BLE Events. +*/ +#define BLE_EVT_PTR_ALIGNMENT 4 + +/** @brief Leaves the maximum of the two arguments. +*/ +#define BLE_MAX(a, b) ((a) < (b) ? (b) : (a)) + +/** @brief Maximum possible length for BLE Events. + * @note The highest value used for @ref ble_gatt_conn_cfg_t::att_mtu in any connection configuration shall be used as a parameter. + * If that value has not been configured for any connections then @ref BLE_GATT_ATT_MTU_DEFAULT must be used instead. +*/ +#define BLE_EVT_LEN_MAX(ATT_MTU) ( \ + offsetof(ble_evt_t, evt.gattc_evt.params.prim_srvc_disc_rsp.services) + ((ATT_MTU) - 1) / 4 * sizeof(ble_gattc_service_t) \ +) + +/** @defgroup ADV_SCHED_CFG Advertiser Role Scheduling Configuration + * @{ */ +#define ADV_SCHED_CFG_DEFAULT 0 /**< Default advertiser role scheduling configuration. */ +#define ADV_SCHED_CFG_IMPROVED 1 /**< Improved advertiser role scheduling configuration in which the housekeeping time is reduced. */ +/** @} */ + +/** @defgroup BLE_USER_MEM_TYPES User Memory Types + * @{ */ +#define BLE_USER_MEM_TYPE_INVALID 0x00 /**< Invalid User Memory Types. */ +#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES 0x01 /**< User Memory for GATTS queued writes. */ +/** @} */ + +/** @defgroup BLE_UUID_VS_COUNTS Vendor Specific base UUID counts + * @{ + */ +#define BLE_UUID_VS_COUNT_DEFAULT 10 /**< Default VS UUID count. */ +#define BLE_UUID_VS_COUNT_MAX 254 /**< Maximum VS UUID count. */ +/** @} */ + +/** @defgroup BLE_COMMON_CFG_DEFAULTS Configuration defaults. + * @{ + */ +#define BLE_CONN_CFG_TAG_DEFAULT 0 /**< Default configuration tag, SoftDevice default connection configuration. */ + +/** @} */ + +/** @} */ + +/** @addtogroup BLE_COMMON_STRUCTURES Structures + * @{ */ + +/**@brief User Memory Block. */ +typedef struct +{ + uint8_t *p_mem; /**< Pointer to the start of the user memory block. */ + uint16_t len; /**< Length in bytes of the user memory block. */ +} ble_user_mem_block_t; + +/**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */ +typedef struct +{ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ +} ble_evt_user_mem_request_t; + +/**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */ +typedef struct +{ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ + ble_user_mem_block_t mem_block; /**< User memory block */ +} ble_evt_user_mem_release_t; + +/**@brief Event structure for events not associated with a specific function module. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which this event occurred. */ + union + { + ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */ + ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */ + } params; /**< Event parameter union. */ +} ble_common_evt_t; + +/**@brief BLE Event header. */ +typedef struct +{ + uint16_t evt_id; /**< Value from a BLE_<module>_EVT series. */ + uint16_t evt_len; /**< Length in octets including this header. */ +} ble_evt_hdr_t; + +/**@brief Common BLE Event type, wrapping the module specific event reports. */ +typedef struct +{ + ble_evt_hdr_t header; /**< Event header. */ + union + { + ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ + ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ + ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ + ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ + ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ + } evt; /**< Event union. */ +} ble_evt_t; + + +/** + * @brief Version Information. + */ +typedef struct +{ + uint8_t version_number; /**< Link Layer Version number. See https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer for assigned values. */ + uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ + uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ +} ble_version_t; + +/** + * @brief Configuration parameters for the PA and LNA. + */ +typedef struct +{ + uint8_t enable :1; /**< Enable toggling for this amplifier */ + uint8_t active_high :1; /**< Set the pin to be active high */ + uint8_t gpio_pin :6; /**< The GPIO pin to toggle for this amplifier */ +} ble_pa_lna_cfg_t; + +/** + * @brief PA & LNA GPIO toggle configuration + * + * This option configures the SoftDevice to toggle pins when the radio is active for use with a power amplifier and/or + * a low noise amplifier. + * + * Toggling the pins is achieved by using two PPI channels and a GPIOTE channel. The hardware channel IDs are provided + * by the application and should be regarded as reserved as long as any PA/LNA toggling is enabled. + * + * @note @ref sd_ble_opt_get is not supported for this option. + * @note Setting this option while the radio is in use (i.e. any of the roles are active) may have undefined consequences + * and must be avoided by the application. + */ +typedef struct +{ + ble_pa_lna_cfg_t pa_cfg; /**< Power Amplifier configuration */ + ble_pa_lna_cfg_t lna_cfg; /**< Low Noise Amplifier configuration */ + + uint8_t ppi_ch_id_set; /**< PPI channel used for radio pin setting */ + uint8_t ppi_ch_id_clr; /**< PPI channel used for radio pin clearing */ + uint8_t gpiote_ch_id; /**< GPIOTE channel used for radio pin toggling */ +} ble_common_opt_pa_lna_t; + +/** + * @brief Configuration of extended BLE connection events. + * + * When enabled the SoftDevice will dynamically extend the connection event when possible. + * + * The connection event length is controlled by the connection configuration as set by @ref ble_gap_conn_cfg_t::event_length. + * The connection event can be extended if there is time to send another packet pair before the start of the next connection interval, + * and if there are no conflicts with other BLE roles requesting radio time. + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */ +} ble_common_opt_conn_evt_ext_t; + +/** + * @brief Enable/disable extended RC calibration. + * + * If extended RC calibration is enabled and the internal RC oscillator (@ref NRF_CLOCK_LF_SRC_RC) is used as the SoftDevice + * LFCLK source, the SoftDevice as a peripheral will by default try to increase the receive window if two consecutive packets + * are not received. If it turns out that the packets were not received due to clock drift, the RC calibration is started. + * This calibration comes in addition to the periodic calibration that is configured by @ref sd_softdevice_enable(). When + * using only peripheral connections, the periodic calibration can therefore be configured with a much longer interval as the + * peripheral will be able to detect and adjust automatically to clock drift, and calibrate on demand. + * + * If extended RC calibration is disabled and the internal RC oscillator is used as the SoftDevice LFCLK source, the + * RC oscillator is calibrated periodically as configured by @ref sd_softdevice_enable(). + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable extended RC calibration, enabled by default. */ +} ble_common_opt_extended_rc_cal_t; + +/** + * @brief Configuration of BLE advertiser role scheduling. + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t sched_cfg; /**< See @ref ADV_SCHED_CFG. */ +} ble_common_opt_adv_sched_cfg_t; + +/**@brief Option structure for common options. */ +typedef union +{ + ble_common_opt_pa_lna_t pa_lna; /**< Parameters for controlling PA and LNA pin toggling. */ + ble_common_opt_conn_evt_ext_t conn_evt_ext; /**< Parameters for enabling extended connection events. */ + ble_common_opt_extended_rc_cal_t extended_rc_cal; /**< Parameters for enabling extended RC calibration. */ + ble_common_opt_adv_sched_cfg_t adv_sched_cfg; /**< Parameters for configuring advertiser role scheduling. */ +} ble_common_opt_t; + +/**@brief Common BLE Option type, wrapping the module specific options. */ +typedef union +{ + ble_common_opt_t common_opt; /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */ + ble_gap_opt_t gap_opt; /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */ +} ble_opt_t; + +/**@brief BLE connection configuration type, wrapping the module specific configurations, set with + * @ref sd_ble_cfg_set. + * + * @note Connection configurations don't have to be set. + * In the case that no configurations has been set, or fewer connection configurations has been set than enabled connections, + * the default connection configuration will be automatically added for the remaining connections. + * When creating connections with the default configuration, @ref BLE_CONN_CFG_TAG_DEFAULT should be used in + * place of @ref ble_conn_cfg_t::conn_cfg_tag. + * + * @sa sd_ble_gap_adv_start() + * @sa sd_ble_gap_connect() + * + * @mscs + * @mmsc{@ref BLE_CONN_CFG} + * @endmscs + + */ +typedef struct +{ + uint8_t conn_cfg_tag; /**< The application chosen tag it can use with the + @ref sd_ble_gap_adv_start() and @ref sd_ble_gap_connect() calls + to select this configuration when creating a connection. + Must be different for all connection configurations added and not @ref BLE_CONN_CFG_TAG_DEFAULT. */ + union { + ble_gap_conn_cfg_t gap_conn_cfg; /**< GAP connection configuration, cfg_id is @ref BLE_CONN_CFG_GAP. */ + ble_gattc_conn_cfg_t gattc_conn_cfg; /**< GATTC connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTC. */ + ble_gatts_conn_cfg_t gatts_conn_cfg; /**< GATTS connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTS. */ + ble_gatt_conn_cfg_t gatt_conn_cfg; /**< GATT connection configuration, cfg_id is @ref BLE_CONN_CFG_GATT. */ + ble_l2cap_conn_cfg_t l2cap_conn_cfg; /**< L2CAP connection configuration, cfg_id is @ref BLE_CONN_CFG_L2CAP. */ + } params; /**< Connection configuration union. */ +} ble_conn_cfg_t; + +/** + * @brief Configuration of Vendor Specific base UUIDs, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_PARAM Too many UUIDs configured. + */ +typedef struct +{ + uint8_t vs_uuid_count; /**< Number of 128-bit Vendor Specific base UUID bases to allocate memory for. + Default value is @ref BLE_UUID_VS_COUNT_DEFAULT. Maximum value is + @ref BLE_UUID_VS_COUNT_MAX. */ +} ble_common_cfg_vs_uuid_t; + +/**@brief Common BLE Configuration type, wrapping the common configurations. */ +typedef union +{ + ble_common_cfg_vs_uuid_t vs_uuid_cfg; /**< Vendor Specific base UUID configuration, cfg_id is @ref BLE_COMMON_CFG_VS_UUID. */ +} ble_common_cfg_t; + +/**@brief BLE Configuration type, wrapping the module specific configurations. */ +typedef union +{ + ble_conn_cfg_t conn_cfg; /**< Connection specific configurations, cfg_id in @ref BLE_CONN_CFGS series. */ + ble_common_cfg_t common_cfg; /**< Global common configurations, cfg_id in @ref BLE_COMMON_CFGS series. */ + ble_gap_cfg_t gap_cfg; /**< Global GAP configurations, cfg_id in @ref BLE_GAP_CFGS series. */ + ble_gatts_cfg_t gatts_cfg; /**< Global GATTS configuration, cfg_id in @ref BLE_GATTS_CFGS series. */ +} ble_cfg_t; + +/** @} */ + +/** @addtogroup BLE_COMMON_FUNCTIONS Functions + * @{ */ + +/**@brief Enable the BLE stack + * + * @param[in, out] p_app_ram_base Pointer to a variable containing the start address of the + * application RAM region (APP_RAM_BASE). On return, this will + * contain the minimum start address of the application RAM region + * required by the SoftDevice for this configuration. + * + * @note The memory requirement for a specific configuration will not increase between SoftDevices + * with the same major version number. + * + * @note At runtime the IC's RAM is split into 2 regions: The SoftDevice RAM region is located + * between 0x20000000 and APP_RAM_BASE-1 and the application's RAM region is located between + * APP_RAM_BASE and the start of the call stack. + * + * @details This call initializes the BLE stack, no BLE related function other than @ref + * sd_ble_cfg_set can be called before this one. + * + * @mscs + * @mmsc{@ref BLE_COMMON_ENABLE} + * @endmscs + * + * @retval ::NRF_SUCCESS The BLE stack has been initialized successfully. + * @retval ::NRF_ERROR_INVALID_STATE The BLE stack had already been initialized and cannot be reinitialized. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_NO_MEM One or more of the following is true: + * - The amount of memory assigned to the SoftDevice by *p_app_ram_base is not + * large enough to fit this configuration's memory requirement. Check *p_app_ram_base + * and set the start address of the application RAM region accordingly. + * - Dynamic part of the SoftDevice RAM region is larger then 64 kB which + * is currently not supported. + * @retval ::NRF_ERROR_RESOURCES The total number of L2CAP Channels configured using @ref sd_ble_cfg_set is too large. + */ +SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(uint32_t * p_app_ram_base)); + +/**@brief Add configurations for the BLE stack + * + * @param[in] cfg_id Config ID, see @ref BLE_CONN_CFGS, @ref BLE_COMMON_CFGS, @ref + * BLE_GAP_CFGS or @ref BLE_GATTS_CFGS. + * @param[in] p_cfg Pointer to a ble_cfg_t structure containing the configuration value. + * @param[in] app_ram_base The start address of the application RAM region (APP_RAM_BASE). + * See @ref sd_ble_enable for details about APP_RAM_BASE. + * + * @note The memory requirement for a specific configuration will not increase between SoftDevices + * with the same major version number. + * + * @note If a configuration is set more than once, the last one set is the one that takes effect on + * @ref sd_ble_enable. + * + * @note Any part of the BLE stack that is NOT configured with @ref sd_ble_cfg_set will have default + * configuration. + * + * @note @ref sd_ble_cfg_set may be called at any time when the SoftDevice is enabled (see @ref + * sd_softdevice_enable) while the BLE part of the SoftDevice is not enabled (see @ref + * sd_ble_enable). + * + * @note Error codes for the configurations are described in the configuration structs. + * + * @mscs + * @mmsc{@ref BLE_COMMON_ENABLE} + * @endmscs + * + * @retval ::NRF_SUCCESS The configuration has been added successfully. + * @retval ::NRF_ERROR_INVALID_STATE The BLE stack had already been initialized. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid cfg_id supplied. + * @retval ::NRF_ERROR_NO_MEM The amount of memory assigned to the SoftDevice by app_ram_base is not + * large enough to fit this configuration's memory requirement. + */ +SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * p_cfg, uint32_t app_ram_base)); + +/**@brief Get an event from the pending events queue. + * + * @param[out] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length. + * This buffer <b>must be aligned to the extend defined by @ref BLE_EVT_PTR_ALIGNMENT</b>. + * The buffer should be interpreted as a @ref ble_evt_t struct. + * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length. + * + * @details This call allows the application to pull a BLE event from the BLE stack. The application is signaled that + * an event is available from the BLE stack by the triggering of the SD_EVT_IRQn interrupt. + * The application is free to choose whether to call this function from thread mode (main context) or directly from the + * Interrupt Service Routine that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher + * priority than the application, this function should be called in a loop (until @ref NRF_ERROR_NOT_FOUND is returned) + * every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the BLE stack. Failure to do so + * could potentially leave events in the internal queue without the application being aware of this fact. + * + * Sizing the p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to + * be copied into application memory. If the buffer provided is not large enough to fit the entire contents of the event, + * @ref NRF_ERROR_DATA_SIZE will be returned and the application can then call again with a larger buffer size. + * The maximum possible event length is defined by @ref BLE_EVT_LEN_MAX. The application may also "peek" the event length + * by providing p_dest as a NULL pointer and inspecting the value of *p_len upon return: + * + * \code + * uint16_t len; + * errcode = sd_ble_evt_get(NULL, &len); + * \endcode + * + * @mscs + * @mmsc{@ref BLE_COMMON_IRQ_EVT_MSC} + * @mmsc{@ref BLE_COMMON_THREAD_EVT_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled. + * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer. + */ +SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len)); + + +/**@brief Add a Vendor Specific base UUID. + * + * @details This call enables the application to add a Vendor Specific base UUID to the BLE stack's table, for later + * use with all other modules and APIs. This then allows the application to use the shorter, 24-bit @ref ble_uuid_t + * format when dealing with both 16-bit and 128-bit UUIDs without having to check for lengths and having split code + * paths. This is accomplished by extending the grouping mechanism that the Bluetooth SIG standard base UUID uses + * for all other 128-bit UUIDs. The type field in the @ref ble_uuid_t structure is an index (relative to + * @ref BLE_UUID_TYPE_VENDOR_BEGIN) to the table populated by multiple calls to this function, and the UUID field + * in the same structure contains the 2 bytes at indexes 12 and 13. The number of possible 128-bit UUIDs available to + * the application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536, + * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array. + * + * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by + * the 16-bit uuid field in @ref ble_uuid_t. + * + * @note If a UUID is already present in the BLE stack's internal table, the corresponding index will be returned in + * p_uuid_type along with an @ref NRF_SUCCESS error code. + * + * @param[in] p_vs_uuid Pointer to a 16-octet (128-bit) little endian Vendor Specific base UUID disregarding + * bytes 12 and 13. + * @param[out] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponding to this UUID will be stored. + * + * @retval ::NRF_SUCCESS Successfully added the Vendor Specific base UUID. + * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid. + * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs. + */ +SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type)); + + +/**@brief Remove a Vendor Specific base UUID. + * + * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows + * the application to reuse memory allocated for Vendor Specific base UUIDs. + * + * @note Currently this function can only be called with a p_uuid_type set to @ref BLE_UUID_TYPE_UNKNOWN or the last added UUID type. + * + * @param[in] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t::type corresponds to the UUID type that + * shall be removed. If the type is set to @ref BLE_UUID_TYPE_UNKNOWN, or the pointer is NULL, the last + * Vendor Specific base UUID will be removed. + * @param[out] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponds to the UUID type that was + * removed. If function returns with a failure, it contains the last type that is in use by the ATT Server. + * + * @retval ::NRF_SUCCESS Successfully removed the Vendor Specific base UUID. + * @retval ::NRF_ERROR_INVALID_ADDR If p_uuid_type is invalid. + * @retval ::NRF_ERROR_INVALID_PARAM If p_uuid_type points to a non-valid UUID type. + * @retval ::NRF_ERROR_FORBIDDEN If the Vendor Specific base UUID is in use by the ATT Server. + */ + +SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t *p_uuid_type)); + + +/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure. + * + * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared + * to the corresponding ones in each entry of the table of Vendor Specific base UUIDs populated with @ref sd_ble_uuid_vs_add + * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index + * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type. + * + * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE. + * + * @param[in] uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes). + * @param[in] p_uuid_le Pointer pointing to little endian raw UUID bytes. + * @param[out] p_uuid Pointer to a @ref ble_uuid_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length. + * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs. + */ +SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid)); + + +/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit). + * + * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed. + * + * @param[in] p_uuid Pointer to a @ref ble_uuid_t structure that will be encoded into bytes. + * @param[out] p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes). + * @param[out] p_uuid_le Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored. + * + * @retval ::NRF_SUCCESS Successfully encoded into the buffer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type. + */ +SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le)); + + +/**@brief Get Version Information. + * + * @details This call allows the application to get the BLE stack version information. + * + * @param[out] p_version Pointer to a ble_version_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Version information stored successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure). + */ +SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version)); + + +/**@brief Provide a user memory block. + * + * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application. + * + * @param[in] conn_handle Connection handle. + * @param[in] p_block Pointer to a user memory block structure or NULL if memory is managed by the application. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_PEER_CANCEL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully queued a response to the peer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid user memory block length supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection state or no user memory request pending. + */ +SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block)); + +/**@brief Set a BLE option. + * + * @details This call allows the application to set the value of an option. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC} + * @endmscs + * + * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS. + * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value. + * + * @retval ::NRF_SUCCESS Option set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed. + */ +SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt)); + + +/**@brief Get a BLE option. + * + * @details This call allows the application to retrieve the value of an option. + * + * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS. + * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Option retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed. + * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported. + * + */ +SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt)); + +/** @} */ +#ifdef __cplusplus +} +#endif +#endif /* BLE_H__ */ + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_err.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_err.h new file mode 100755 index 0000000..1b4820d --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_err.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @addtogroup nrf_error + @{ + @ingroup BLE_COMMON + @} + + @defgroup ble_err General error codes + @{ + + @brief General error code definitions for the BLE API. + + @ingroup BLE_COMMON +*/ +#ifndef NRF_BLE_ERR_H__ +#define NRF_BLE_ERR_H__ + +#include "nrf_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* @defgroup BLE_ERRORS Error Codes + * @{ */ +#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */ +#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */ +#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */ +#define BLE_ERROR_INVALID_ADV_HANDLE (NRF_ERROR_STK_BASE_NUM+0x004) /**< Invalid advertising handle. */ +#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */ +#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM+0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */ +/** @} */ + + +/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges + * @brief Assignment of subranges for module specific error codes. + * @note For specific error codes, see ble_<module>.h or ble_error_<module>.h. + * @{ */ +#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */ +#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */ +#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */ +#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */ +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif + + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gap.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gap.h new file mode 100755 index 0000000..fe9365f --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gap.h @@ -0,0 +1,2681 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GAP Generic Access Profile (GAP) + @{ + @brief Definitions and prototypes for the GAP interface. + */ + +#ifndef BLE_GAP_H__ +#define BLE_GAP_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations + * @{ */ + +/**@brief GAP API SVC numbers. + */ +enum BLE_GAP_SVCS +{ + SD_BLE_GAP_ADDR_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ + SD_BLE_GAP_ADDR_GET = BLE_GAP_SVC_BASE + 1, /**< Get own Bluetooth Address. */ + SD_BLE_GAP_WHITELIST_SET = BLE_GAP_SVC_BASE + 2, /**< Set active whitelist. */ + SD_BLE_GAP_DEVICE_IDENTITIES_SET = BLE_GAP_SVC_BASE + 3, /**< Set device identity list. */ + SD_BLE_GAP_PRIVACY_SET = BLE_GAP_SVC_BASE + 4, /**< Set Privacy settings*/ + SD_BLE_GAP_PRIVACY_GET = BLE_GAP_SVC_BASE + 5, /**< Get Privacy settings*/ + SD_BLE_GAP_ADV_SET_CONFIGURE = BLE_GAP_SVC_BASE + 6, /**< Configure an advertising set. */ + SD_BLE_GAP_ADV_START = BLE_GAP_SVC_BASE + 7, /**< Start Advertising. */ + SD_BLE_GAP_ADV_STOP = BLE_GAP_SVC_BASE + 8, /**< Stop Advertising. */ + SD_BLE_GAP_CONN_PARAM_UPDATE = BLE_GAP_SVC_BASE + 9, /**< Connection Parameter Update. */ + SD_BLE_GAP_DISCONNECT = BLE_GAP_SVC_BASE + 10, /**< Disconnect. */ + SD_BLE_GAP_TX_POWER_SET = BLE_GAP_SVC_BASE + 11, /**< Set TX Power. */ + SD_BLE_GAP_APPEARANCE_SET = BLE_GAP_SVC_BASE + 12, /**< Set Appearance. */ + SD_BLE_GAP_APPEARANCE_GET = BLE_GAP_SVC_BASE + 13, /**< Get Appearance. */ + SD_BLE_GAP_PPCP_SET = BLE_GAP_SVC_BASE + 14, /**< Set PPCP. */ + SD_BLE_GAP_PPCP_GET = BLE_GAP_SVC_BASE + 15, /**< Get PPCP. */ + SD_BLE_GAP_DEVICE_NAME_SET = BLE_GAP_SVC_BASE + 16, /**< Set Device Name. */ + SD_BLE_GAP_DEVICE_NAME_GET = BLE_GAP_SVC_BASE + 17, /**< Get Device Name. */ + SD_BLE_GAP_AUTHENTICATE = BLE_GAP_SVC_BASE + 18, /**< Initiate Pairing/Bonding. */ + SD_BLE_GAP_SEC_PARAMS_REPLY = BLE_GAP_SVC_BASE + 19, /**< Reply with Security Parameters. */ + SD_BLE_GAP_AUTH_KEY_REPLY = BLE_GAP_SVC_BASE + 20, /**< Reply with an authentication key. */ + SD_BLE_GAP_LESC_DHKEY_REPLY = BLE_GAP_SVC_BASE + 21, /**< Reply with an LE Secure Connections DHKey. */ + SD_BLE_GAP_KEYPRESS_NOTIFY = BLE_GAP_SVC_BASE + 22, /**< Notify of a keypress during an authentication procedure. */ + SD_BLE_GAP_LESC_OOB_DATA_GET = BLE_GAP_SVC_BASE + 23, /**< Get the local LE Secure Connections OOB data. */ + SD_BLE_GAP_LESC_OOB_DATA_SET = BLE_GAP_SVC_BASE + 24, /**< Set the remote LE Secure Connections OOB data. */ + SD_BLE_GAP_ENCRYPT = BLE_GAP_SVC_BASE + 25, /**< Initiate encryption procedure. */ + SD_BLE_GAP_SEC_INFO_REPLY = BLE_GAP_SVC_BASE + 26, /**< Reply with Security Information. */ + SD_BLE_GAP_CONN_SEC_GET = BLE_GAP_SVC_BASE + 27, /**< Obtain connection security level. */ + SD_BLE_GAP_RSSI_START = BLE_GAP_SVC_BASE + 28, /**< Start reporting of changes in RSSI. */ + SD_BLE_GAP_RSSI_STOP = BLE_GAP_SVC_BASE + 29, /**< Stop reporting of changes in RSSI. */ + SD_BLE_GAP_SCAN_START = BLE_GAP_SVC_BASE + 30, /**< Start Scanning. */ + SD_BLE_GAP_SCAN_STOP = BLE_GAP_SVC_BASE + 31, /**< Stop Scanning. */ + SD_BLE_GAP_CONNECT = BLE_GAP_SVC_BASE + 32, /**< Connect. */ + SD_BLE_GAP_CONNECT_CANCEL = BLE_GAP_SVC_BASE + 33, /**< Cancel ongoing connection procedure. */ + SD_BLE_GAP_RSSI_GET = BLE_GAP_SVC_BASE + 34, /**< Get the last RSSI sample. */ + SD_BLE_GAP_PHY_UPDATE = BLE_GAP_SVC_BASE + 35, /**< Initiate or respond to a PHY Update Procedure. */ + SD_BLE_GAP_DATA_LENGTH_UPDATE = BLE_GAP_SVC_BASE + 36, /**< Initiate or respond to a Data Length Update Procedure. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_START = BLE_GAP_SVC_BASE + 37, /**< Start Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP = BLE_GAP_SVC_BASE + 38, /**< Stop Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_ADV_ADDR_GET = BLE_GAP_SVC_BASE + 39, /**< Get the Address used on air while Advertising. */ +}; + +/**@brief GAP Event IDs. + * IDs that uniquely identify an event coming from the stack to the application. + */ +enum BLE_GAP_EVTS +{ + BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connected to peer. \n See @ref ble_gap_evt_connected_t */ + BLE_GAP_EVT_DISCONNECTED = BLE_GAP_EVT_BASE + 1, /**< Disconnected from peer. \n See @ref ble_gap_evt_disconnected_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE = BLE_GAP_EVT_BASE + 2, /**< Connection Parameters updated. \n See @ref ble_gap_evt_conn_param_update_t. */ + BLE_GAP_EVT_SEC_PARAMS_REQUEST = BLE_GAP_EVT_BASE + 3, /**< Request to provide security parameters. \n Reply with @ref sd_ble_gap_sec_params_reply. \n See @ref ble_gap_evt_sec_params_request_t. */ + BLE_GAP_EVT_SEC_INFO_REQUEST = BLE_GAP_EVT_BASE + 4, /**< Request to provide security information. \n Reply with @ref sd_ble_gap_sec_info_reply. \n See @ref ble_gap_evt_sec_info_request_t. */ + BLE_GAP_EVT_PASSKEY_DISPLAY = BLE_GAP_EVT_BASE + 5, /**< Request to display a passkey to the user. \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */ + BLE_GAP_EVT_KEY_PRESSED = BLE_GAP_EVT_BASE + 6, /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t */ + BLE_GAP_EVT_AUTH_KEY_REQUEST = BLE_GAP_EVT_BASE + 7, /**< Request to provide an authentication key. \n Reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_auth_key_request_t. */ + BLE_GAP_EVT_LESC_DHKEY_REQUEST = BLE_GAP_EVT_BASE + 8, /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply. \n See @ref ble_gap_evt_lesc_dhkey_request_t */ + BLE_GAP_EVT_AUTH_STATUS = BLE_GAP_EVT_BASE + 9, /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t. */ + BLE_GAP_EVT_CONN_SEC_UPDATE = BLE_GAP_EVT_BASE + 10, /**< Connection security updated. \n See @ref ble_gap_evt_conn_sec_update_t. */ + BLE_GAP_EVT_TIMEOUT = BLE_GAP_EVT_BASE + 11, /**< Timeout expired. \n See @ref ble_gap_evt_timeout_t. */ + BLE_GAP_EVT_RSSI_CHANGED = BLE_GAP_EVT_BASE + 12, /**< RSSI report. \n See @ref ble_gap_evt_rssi_changed_t. */ + BLE_GAP_EVT_ADV_REPORT = BLE_GAP_EVT_BASE + 13, /**< Advertising report. \n See @ref ble_gap_evt_adv_report_t. */ + BLE_GAP_EVT_SEC_REQUEST = BLE_GAP_EVT_BASE + 14, /**< Security Request. \n See @ref ble_gap_evt_sec_request_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 15, /**< Connection Parameter Update Request. \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */ + BLE_GAP_EVT_SCAN_REQ_REPORT = BLE_GAP_EVT_BASE + 16, /**< Scan request report. \n See @ref ble_gap_evt_scan_req_report_t. */ + BLE_GAP_EVT_PHY_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 17, /**< PHY Update Request. \n Reply with @ref sd_ble_gap_phy_update. \n See @ref ble_gap_evt_phy_update_request_t. */ + BLE_GAP_EVT_PHY_UPDATE = BLE_GAP_EVT_BASE + 18, /**< PHY Update Procedure is complete. \n See @ref ble_gap_evt_phy_update_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 19, /**< Data Length Update Request. \n Reply with @ref sd_ble_gap_data_length_update.\n See @ref ble_gap_evt_data_length_update_request_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE = BLE_GAP_EVT_BASE + 20, /**< LL Data Channel PDU payload length updated. \n See @ref ble_gap_evt_data_length_update_t. */ + BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT = BLE_GAP_EVT_BASE + 21, /**< Channel survey report. \n See @ref ble_gap_evt_qos_channel_survey_report_t. */ + BLE_GAP_EVT_ADV_SET_TERMINATED = BLE_GAP_EVT_BASE + 22, /**< Advertising set terminated. \n See @ref ble_gap_evt_adv_set_terminated_t. */ +}; + +/**@brief GAP Option IDs. + * IDs that uniquely identify a GAP option. + */ +enum BLE_GAP_OPTS +{ + BLE_GAP_OPT_CH_MAP = BLE_GAP_OPT_BASE, /**< Channel Map. @ref ble_gap_opt_ch_map_t */ + BLE_GAP_OPT_LOCAL_CONN_LATENCY = BLE_GAP_OPT_BASE + 1, /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */ + BLE_GAP_OPT_PASSKEY = BLE_GAP_OPT_BASE + 2, /**< Set passkey. @ref ble_gap_opt_passkey_t */ + BLE_GAP_OPT_COMPAT_MODE_1 = BLE_GAP_OPT_BASE + 3, /**< Compatibility mode. @ref ble_gap_opt_compat_mode_1_t */ + BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT = BLE_GAP_OPT_BASE + 4, /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */ + BLE_GAP_OPT_SLAVE_LATENCY_DISABLE = BLE_GAP_OPT_BASE + 5, /**< Disable slave latency. @ref ble_gap_opt_slave_latency_disable_t */ +}; + +/**@brief GAP Configuration IDs. + * + * IDs that uniquely identify a GAP configuration. + */ +enum BLE_GAP_CFGS +{ + BLE_GAP_CFG_ROLE_COUNT = BLE_GAP_CFG_BASE, /**< Role count configuration. */ + BLE_GAP_CFG_DEVICE_NAME = BLE_GAP_CFG_BASE + 1, /**< Device name configuration. */ +}; + +/**@brief GAP TX Power roles. + */ +enum BLE_GAP_TX_POWER_ROLES +{ + BLE_GAP_TX_POWER_ROLE_ADV = 1, /**< Advertiser role. */ + BLE_GAP_TX_POWER_ROLE_SCAN_INIT = 2, /**< Scanner and initiator role. */ + BLE_GAP_TX_POWER_ROLE_CONN = 3, /**< Connection role. */ +}; + +/** @} */ + +/**@addtogroup BLE_GAP_DEFINES Defines + * @{ */ + +/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP + * @{ */ +#define BLE_ERROR_GAP_UUID_LIST_MISMATCH (NRF_GAP_ERR_BASE + 0x000) /**< UUID list does not contain an integral number of UUIDs. */ +#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST (NRF_GAP_ERR_BASE + 0x001) /**< Use of Whitelist not permitted with discoverable advertising. */ +#define BLE_ERROR_GAP_INVALID_BLE_ADDR (NRF_GAP_ERR_BASE + 0x002) /**< The upper two bits of the address do not correspond to the specified address type. */ +#define BLE_ERROR_GAP_WHITELIST_IN_USE (NRF_GAP_ERR_BASE + 0x003) /**< Attempt to modify the whitelist while already in use by another operation. */ +#define BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE (NRF_GAP_ERR_BASE + 0x004) /**< Attempt to modify the device identity list while already in use by another operation. */ +#define BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE (NRF_GAP_ERR_BASE + 0x005) /**< The device identity list contains entries with duplicate identity addresses. */ +/**@} */ + + +/**@defgroup BLE_GAP_ROLES GAP Roles + * @{ */ +#define BLE_GAP_ROLE_INVALID 0x0 /**< Invalid Role. */ +#define BLE_GAP_ROLE_PERIPH 0x1 /**< Peripheral Role. */ +#define BLE_GAP_ROLE_CENTRAL 0x2 /**< Central Role. */ +/**@} */ + + +/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources + * @{ */ +#define BLE_GAP_TIMEOUT_SRC_SCAN 0x01 /**< Scanning timeout. */ +#define BLE_GAP_TIMEOUT_SRC_CONN 0x02 /**< Connection timeout. */ +#define BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD 0x03 /**< Authenticated payload timeout. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types + * @{ */ +#define BLE_GAP_ADDR_TYPE_PUBLIC 0x00 /**< Public (identity) address.*/ +#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC 0x01 /**< Random static (identity) address. */ +#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE 0x02 /**< Random private resolvable address. */ +#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Random private non-resolvable address. */ +#define BLE_GAP_ADDR_TYPE_ANONYMOUS 0x7F /**< An advertiser may advertise without its address. + This type of advertising is called anonymous. */ +/**@} */ + + +/**@brief The default interval in seconds at which a private address is refreshed. */ +#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (900) /* 15 minutes. */ +/**@brief The maximum interval in seconds at which a private address can be refreshed. */ +#define BLE_GAP_MAX_PRIVATE_ADDR_CYCLE_INTERVAL_S (41400) /* 11 hours 30 minutes. */ + + +/** @brief BLE address length. */ +#define BLE_GAP_ADDR_LEN (6) + +/**@defgroup BLE_GAP_PRIVACY_MODES Privacy modes + * @{ */ +#define BLE_GAP_PRIVACY_MODE_OFF 0x00 /**< Device will send and accept its identity address for its own address. */ +#define BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY 0x01 /**< Device will send and accept only private addresses for its own address. */ +#define BLE_GAP_PRIVACY_MODE_NETWORK_PRIVACY 0x02 /**< Device will send and accept only private addresses for its own address, + and will not accept a peer using identity address as sender address when + the peer IRK is exchanged, non-zero and added to the identity list. */ +/**@} */ + +/** @brief Invalid power level. */ +#define BLE_GAP_POWER_LEVEL_INVALID 127 + +/** @brief Advertising set handle not set. */ +#define BLE_GAP_ADV_SET_HANDLE_NOT_SET (0xFF) + +/** @brief The default number of advertising sets. */ +#define BLE_GAP_ADV_SET_COUNT_DEFAULT (1) + +/** @brief The maximum number of advertising sets supported by this SoftDevice. */ +#define BLE_GAP_ADV_SET_COUNT_MAX (1) + +/**@defgroup BLE_GAP_ADV_SET_DATA_SIZES Advertising data sizes. + * @{ */ +#define BLE_GAP_ADV_SET_DATA_SIZE_MAX (31) /**< Maximum data length for an advertising set. + If more advertising data is required, use extended advertising instead. */ +#define BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED (255) /**< Maximum supported data length for an extended advertising set. */ + +#define BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_CONNECTABLE_MAX_SUPPORTED (238) /**< Maximum supported data length for an extended connectable advertising set. */ +/**@}. */ + +/** @brief Set ID not available in advertising report. */ +#define BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE 0xFF + +/**@defgroup BLE_GAP_EVT_ADV_SET_TERMINATED_REASON GAP Advertising Set Terminated reasons + * @{ */ +#define BLE_GAP_EVT_ADV_SET_TERMINATED_REASON_TIMEOUT 0x01 /**< Timeout value reached. */ +#define BLE_GAP_EVT_ADV_SET_TERMINATED_REASON_LIMIT_REACHED 0x02 /**< @ref ble_gap_adv_params_t::max_adv_evts was reached. */ +/**@} */ + +/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format + * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm + * @{ */ +#define BLE_GAP_AD_TYPE_FLAGS 0x01 /**< Flags for discoverability. */ +#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE 0x02 /**< Partial list of 16 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE 0x03 /**< Complete list of 16 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE 0x04 /**< Partial list of 32 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE 0x05 /**< Complete list of 32 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE 0x06 /**< Partial list of 128 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE 0x07 /**< Complete list of 128 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME 0x08 /**< Short local device name. */ +#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME 0x09 /**< Complete local device name. */ +#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL 0x0A /**< Transmit power level. */ +#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE 0x0D /**< Class of device. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C 0x0E /**< Simple Pairing Hash C. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R 0x0F /**< Simple Pairing Randomizer R. */ +#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE 0x10 /**< Security Manager TK Value. */ +#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS 0x11 /**< Security Manager Out Of Band Flags. */ +#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 /**< Slave Connection Interval Range. */ +#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT 0x14 /**< List of 16-bit Service Solicitation UUIDs. */ +#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT 0x15 /**< List of 128-bit Service Solicitation UUIDs. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA 0x16 /**< Service Data - 16-bit UUID. */ +#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS 0x17 /**< Public Target Address. */ +#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS 0x18 /**< Random Target Address. */ +#define BLE_GAP_AD_TYPE_APPEARANCE 0x19 /**< Appearance. */ +#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL 0x1A /**< Advertising Interval. */ +#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B /**< LE Bluetooth Device Address. */ +#define BLE_GAP_AD_TYPE_LE_ROLE 0x1C /**< LE Role. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256 0x1D /**< Simple Pairing Hash C-256. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256 0x1E /**< Simple Pairing Randomizer R-256. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID 0x20 /**< Service Data - 32-bit UUID. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID 0x21 /**< Service Data - 128-bit UUID. */ +#define BLE_GAP_AD_TYPE_LESC_CONFIRMATION_VALUE 0x22 /**< LE Secure Connections Confirmation Value */ +#define BLE_GAP_AD_TYPE_LESC_RANDOM_VALUE 0x23 /**< LE Secure Connections Random Value */ +#define BLE_GAP_AD_TYPE_URI 0x24 /**< URI */ +#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA 0x3D /**< 3D Information Data. */ +#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA 0xFF /**< Manufacturer Specific Data. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags + * @{ */ +#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE (0x01) /**< LE Limited Discoverable Mode. */ +#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE (0x02) /**< LE General Discoverable Mode. */ +#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED (0x04) /**< BR/EDR not supported. */ +#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER (0x08) /**< Simultaneous LE and BR/EDR, Controller. */ +#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST (0x10) /**< Simultaneous LE and BR/EDR, Host. */ +#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE Limited Discoverable Mode, BR/EDR not supported. */ +#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE General Discoverable Mode, BR/EDR not supported. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min + * @{ */ +#define BLE_GAP_ADV_INTERVAL_MIN 0x000020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */ +#define BLE_GAP_ADV_INTERVAL_MAX 0x004000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */ + /**@} */ + + +/**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min + * @{ */ +#define BLE_GAP_SCAN_INTERVAL_MIN 0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */ +#define BLE_GAP_SCAN_INTERVAL_MAX 0xFFFF /**< Maximum Scan interval in 625 us units, i.e. 40,959.375 s. */ + /** @} */ + + +/**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min + * @{ */ +#define BLE_GAP_SCAN_WINDOW_MIN 0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */ +#define BLE_GAP_SCAN_WINDOW_MAX 0xFFFF /**< Maximum Scan window in 625 us units, i.e. 40,959.375 s. */ + /** @} */ + + +/**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min + * @{ */ +#define BLE_GAP_SCAN_TIMEOUT_MIN 0x0001 /**< Minimum Scan timeout in 10 ms units, i.e 10 ms. */ +#define BLE_GAP_SCAN_TIMEOUT_UNLIMITED 0x0000 /**< Continue to scan forever. */ + /** @} */ + +/**@defgroup BLE_GAP_SCAN_BUFFER_SIZE GAP Minimum scanner buffer size + * + * Scan buffers are used for storing advertising data received from an advertiser. + * If ble_gap_scan_params_t::extended is set to 0, @ref BLE_GAP_SCAN_BUFFER_MIN is the minimum scan buffer length. + * else the minimum scan buffer size is @ref BLE_GAP_SCAN_BUFFER_EXTENDED_MIN. + * @{ */ +#define BLE_GAP_SCAN_BUFFER_MIN (31) /**< Minimum data length for an + advertising set. */ +#define BLE_GAP_SCAN_BUFFER_MAX (31) /**< Maximum data length for an + advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MIN (255) /**< Minimum data length for an + extended advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MAX (1650) /**< Maximum data length for an + extended advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MAX_SUPPORTED (255) /**< Maximum supported data length for + an extended advertising set. */ +/** @} */ + +/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types + * + * Advertising types defined in Bluetooth Core Specification v5.0, Vol 6, Part B, Section 4.4.2. + * + * The maximum advertising data length is defined by @ref BLE_GAP_ADV_SET_DATA_SIZE_MAX. + * The maximum supported data length for an extended advertiser is defined by + * @ref BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED + * Note that some of the advertising types do not support advertising data. Non-scannable types do not support + * scan response data. + * + * @{ */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_SCANNABLE_UNDIRECTED 0x01 /**< Connectable and scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE 0x02 /**< Connectable non-scannable directed advertising + events. Advertising interval is less that 3.75 ms. + Use this type for fast reconnections. + @note Advertising data is not supported. */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED 0x03 /**< Connectable non-scannable directed advertising + events. + @note Advertising data is not supported. */ +#define BLE_GAP_ADV_TYPE_NONCONNECTABLE_SCANNABLE_UNDIRECTED 0x04 /**< Non-connectable scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED 0x05 /**< Non-connectable non-scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_CONNECTABLE_NONSCANNABLE_UNDIRECTED 0x06 /**< Connectable non-scannable undirected advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_CONNECTABLE_NONSCANNABLE_DIRECTED 0x07 /**< Connectable non-scannable directed advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_SCANNABLE_UNDIRECTED 0x08 /**< Non-connectable scannable undirected advertising + events using extended advertising PDUs. + @note Only scan response data is supported. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_SCANNABLE_DIRECTED 0x09 /**< Non-connectable scannable directed advertising + events using extended advertising PDUs. + @note Only scan response data is supported. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED 0x0A /**< Non-connectable non-scannable undirected advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED 0x0B /**< Non-connectable non-scannable directed advertising + events using extended advertising PDUs. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies + * @{ */ +#define BLE_GAP_ADV_FP_ANY 0x00 /**< Allow scan requests and connect requests from any device. */ +#define BLE_GAP_ADV_FP_FILTER_SCANREQ 0x01 /**< Filter scan requests with whitelist. */ +#define BLE_GAP_ADV_FP_FILTER_CONNREQ 0x02 /**< Filter connect requests with whitelist. */ +#define BLE_GAP_ADV_FP_FILTER_BOTH 0x03 /**< Filter both scan and connect requests with whitelist. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_DATA_STATUS GAP Advertising data status + * @{ */ +#define BLE_GAP_ADV_DATA_STATUS_COMPLETE 0x00 /**< All data in the advertising event have been received. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA 0x01 /**< More data to be received. + @note This value will only be used if + @ref ble_gap_scan_params_t::report_incomplete_evts and + @ref ble_gap_adv_report_type_t::extended_pdu are set to true. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_TRUNCATED 0x02 /**< Incomplete data. Buffer size insufficient to receive more. + @note This value will only be used if + @ref ble_gap_adv_report_type_t::extended_pdu is set to true. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MISSED 0x03 /**< Failed to receive the remaining data. + @note This value will only be used if + @ref ble_gap_adv_report_type_t::extended_pdu is set to true. */ +/**@} */ + +/**@defgroup BLE_GAP_SCAN_FILTER_POLICIES GAP Scanner filter policies + * @{ */ +#define BLE_GAP_SCAN_FP_ACCEPT_ALL 0x00 /**< Accept all advertising packets except directed advertising packets + not addressed to this device. */ +#define BLE_GAP_SCAN_FP_WHITELIST 0x01 /**< Accept advertising packets from devices in the whitelist except directed + packets not addressed to this device. */ +#define BLE_GAP_SCAN_FP_ALL_NOT_RESOLVED_DIRECTED 0x02 /**< Accept all advertising packets specified in @ref BLE_GAP_SCAN_FP_ACCEPT_ALL. + In addition, accept directed advertising packets, where the advertiser's + address is a resolvable private address that cannot be resolved. */ +#define BLE_GAP_SCAN_FP_WHITELIST_NOT_RESOLVED_DIRECTED 0x03 /**< Accept all advertising packets specified in @ref BLE_GAP_SCAN_FP_WHITELIST. + In addition, accept directed advertising packets, where the advertiser's + address is a resolvable private address that cannot be resolved. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values in 10 ms units + * @{ */ +#define BLE_GAP_ADV_TIMEOUT_HIGH_DUTY_MAX (128) /**< Maximum high duty advertising time in 10 ms units. Corresponds to 1.28 s. */ +#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX (18000) /**< Maximum advertising time in 10 ms units corresponding to TGAP(lim_adv_timeout) = 180 s in limited discoverable mode. */ +#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED (0) /**< Unlimited advertising in general discoverable mode. + For high duty cycle advertising, this corresponds to @ref BLE_GAP_ADV_TIMEOUT_HIGH_DUTY_MAX. */ +/**@} */ + + +/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes + * @{ */ +#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE 0x00 /**< Not discoverable discovery Mode. */ +#define BLE_GAP_DISC_MODE_LIMITED 0x01 /**< Limited Discovery Mode. */ +#define BLE_GAP_DISC_MODE_GENERAL 0x02 /**< General Discovery Mode. */ +/**@} */ + + +/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities + * @{ */ +#define BLE_GAP_IO_CAPS_DISPLAY_ONLY 0x00 /**< Display Only. */ +#define BLE_GAP_IO_CAPS_DISPLAY_YESNO 0x01 /**< Display and Yes/No entry. */ +#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY 0x02 /**< Keyboard Only. */ +#define BLE_GAP_IO_CAPS_NONE 0x03 /**< No I/O capabilities. */ +#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY 0x04 /**< Keyboard and Display. */ +/**@} */ + + +/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types + * @{ */ +#define BLE_GAP_AUTH_KEY_TYPE_NONE 0x00 /**< No key (may be used to reject). */ +#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY 0x01 /**< 6-digit Passkey. */ +#define BLE_GAP_AUTH_KEY_TYPE_OOB 0x02 /**< Out Of Band data. */ +/**@} */ + + +/**@defgroup BLE_GAP_KP_NOT_TYPES GAP Keypress Notification Types + * @{ */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_START 0x00 /**< Passkey entry started. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_IN 0x01 /**< Passkey digit entered. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_OUT 0x02 /**< Passkey digit erased. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_CLEAR 0x03 /**< Passkey cleared. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_END 0x04 /**< Passkey entry completed. */ +/**@} */ + + +/**@defgroup BLE_GAP_SEC_STATUS GAP Security status + * @{ */ +#define BLE_GAP_SEC_STATUS_SUCCESS 0x00 /**< Procedure completed with success. */ +#define BLE_GAP_SEC_STATUS_TIMEOUT 0x01 /**< Procedure timed out. */ +#define BLE_GAP_SEC_STATUS_PDU_INVALID 0x02 /**< Invalid PDU received. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE1_BEGIN 0x03 /**< Reserved for Future Use range #1 begin. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE1_END 0x80 /**< Reserved for Future Use range #1 end. */ +#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED 0x81 /**< Passkey entry failed (user canceled or other). */ +#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE 0x82 /**< Out of Band Key not available. */ +#define BLE_GAP_SEC_STATUS_AUTH_REQ 0x83 /**< Authentication requirements not met. */ +#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE 0x84 /**< Confirm value failed. */ +#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP 0x85 /**< Pairing not supported. */ +#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE 0x86 /**< Encryption key size. */ +#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED 0x87 /**< Unsupported SMP command. */ +#define BLE_GAP_SEC_STATUS_UNSPECIFIED 0x88 /**< Unspecified reason. */ +#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS 0x89 /**< Too little time elapsed since last attempt. */ +#define BLE_GAP_SEC_STATUS_INVALID_PARAMS 0x8A /**< Invalid parameters. */ +#define BLE_GAP_SEC_STATUS_DHKEY_FAILURE 0x8B /**< DHKey check failure. */ +#define BLE_GAP_SEC_STATUS_NUM_COMP_FAILURE 0x8C /**< Numeric Comparison failure. */ +#define BLE_GAP_SEC_STATUS_BR_EDR_IN_PROG 0x8D /**< BR/EDR pairing in progress. */ +#define BLE_GAP_SEC_STATUS_X_TRANS_KEY_DISALLOWED 0x8E /**< BR/EDR Link Key cannot be used for LE keys. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE2_BEGIN 0x8F /**< Reserved for Future Use range #2 begin. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE2_END 0xFF /**< Reserved for Future Use range #2 end. */ +/**@} */ + + +/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources + * @{ */ +#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL 0x00 /**< Local failure. */ +#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE 0x01 /**< Remote failure. */ +/**@} */ + + +/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits + * @{ */ +#define BLE_GAP_CP_MIN_CONN_INTVL_NONE 0xFFFF /**< No new minimum connection interval specified in connect parameters. */ +#define BLE_GAP_CP_MIN_CONN_INTVL_MIN 0x0006 /**< Lowest minimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ +#define BLE_GAP_CP_MIN_CONN_INTVL_MAX 0x0C80 /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_NONE 0xFFFF /**< No new maximum connection interval specified in connect parameters. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_MIN 0x0006 /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_MAX 0x0C80 /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ +#define BLE_GAP_CP_SLAVE_LATENCY_MAX 0x01F3 /**< Highest slave latency permitted, in connection events. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE 0xFFFF /**< No new supervision timeout specified in connect parameters. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN 0x000A /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX 0x0C80 /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */ +/**@} */ + + +/**@defgroup BLE_GAP_DEVNAME GAP device name defines. + * @{ */ +#define BLE_GAP_DEVNAME_DEFAULT "nRF5x" /**< Default device name value. */ +#define BLE_GAP_DEVNAME_DEFAULT_LEN 31 /**< Default number of octets in device name. */ +#define BLE_GAP_DEVNAME_MAX_LEN 248 /**< Maximum number of octets in device name. */ +/**@} */ + + +/**@brief Disable RSSI events for connections */ +#define BLE_GAP_RSSI_THRESHOLD_INVALID 0xFF + +/**@defgroup BLE_GAP_PHYS GAP PHYs + * @{ */ +#define BLE_GAP_PHY_AUTO 0x00 /**< Automatic PHY selection. Refer @ref sd_ble_gap_phy_update for more information.*/ +#define BLE_GAP_PHY_1MBPS 0x01 /**< 1 Mbps PHY. */ +#define BLE_GAP_PHY_2MBPS 0x02 /**< 2 Mbps PHY. */ +#define BLE_GAP_PHY_CODED 0x04 /**< Coded PHY. */ +#define BLE_GAP_PHY_NOT_SET 0xFF /**< PHY is not configured. */ + +/**@brief Supported PHYs in connections, for scanning, and for advertising. */ +#define BLE_GAP_PHYS_SUPPORTED (BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS) /**< All PHYs except @ref BLE_GAP_PHY_CODED are supported. */ + +/**@} */ + +/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters + * + * See @ref ble_gap_conn_sec_mode_t. + * @{ */ +/**@brief Set sec_mode pointed to by ptr to have no access rights.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0) +/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0) +/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0) +/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0) +/**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0) +/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0) +/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0) +/**@} */ + + +/**@brief GAP Security Random Number Length. */ +#define BLE_GAP_SEC_RAND_LEN 8 + + +/**@brief GAP Security Key Length. */ +#define BLE_GAP_SEC_KEY_LEN 16 + + +/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key Length. */ +#define BLE_GAP_LESC_P256_PK_LEN 64 + + +/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman DHKey Length. */ +#define BLE_GAP_LESC_DHKEY_LEN 32 + + +/**@brief GAP Passkey Length. */ +#define BLE_GAP_PASSKEY_LEN 6 + + +/**@brief Maximum amount of addresses in the whitelist. */ +#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8) + + +/**@brief Maximum amount of identities in the device identities list. */ +#define BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT (8) + + +/**@brief Default connection count for a configuration. */ +#define BLE_GAP_CONN_COUNT_DEFAULT (1) + + +/**@defgroup BLE_GAP_EVENT_LENGTH GAP event length defines. + * @{ */ +#define BLE_GAP_EVENT_LENGTH_MIN (2) /**< Minimum event length, in 1.25 ms units. */ +#define BLE_GAP_EVENT_LENGTH_DEFAULT (3) /**< Default event length, in 1.25 ms units. */ +/**@} */ + + +/**@defgroup BLE_GAP_ROLE_COUNT GAP concurrent connection count defines. + * @{ */ +#define BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT (1) /**< Default maximum number of connections concurrently acting as peripherals. */ +#define BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT (3) /**< Default maximum number of connections concurrently acting as centrals. */ +#define BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT (1) /**< Default number of SMP instances shared between all connections acting as centrals. */ +#define BLE_GAP_ROLE_COUNT_COMBINED_MAX (20) /**< Maximum supported number of concurrent connections in the peripheral and central roles combined. */ + +/**@} */ + +/**@brief Automatic data length parameter. */ +#define BLE_GAP_DATA_LENGTH_AUTO 0 + +/**@defgroup BLE_GAP_AUTH_PAYLOAD_TIMEOUT Authenticated payload timeout defines. + * @{ */ +#define BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MAX (48000) /**< Maximum authenticated payload timeout in 10 ms units, i.e. 8 minutes. */ +#define BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MIN (1) /**< Minimum authenticated payload timeout in 10 ms units, i.e. 10 ms. */ +/**@} */ + +/**@defgroup GAP_SEC_MODES GAP Security Modes + * @{ */ +#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */ +/**@} */ + +/**@brief The total number of channels in Bluetooth Low Energy. */ +#define BLE_GAP_CHANNEL_COUNT (40) + +/**@defgroup BLE_GAP_QOS_CHANNEL_SURVEY_INTERVALS Quality of Service (QoS) Channel survey interval defines + * @{ */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS (0) /**< Continuous channel survey. */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MIN_US (7500) /**< Minimum channel survey interval in microseconds (7.5 ms). */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MAX_US (4000000) /**< Maximum channel survey interval in microseconds (4 s). */ + /**@} */ + +/** @} */ + + +/**@addtogroup BLE_GAP_STRUCTURES Structures + * @{ */ + +/**@brief Advertising event properties. */ +typedef struct +{ + uint8_t type; /**< Advertising type. See @ref BLE_GAP_ADV_TYPES. */ + uint8_t anonymous : 1; /**< Omit advertiser's address from all PDUs. + @note Anonymous advertising is only available for + @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED and + @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED. */ + uint8_t include_tx_power : 1; /**< This feature is not supported on this SoftDevice. */ +} ble_gap_adv_properties_t; + + +/**@brief Advertising report type. */ +typedef struct +{ + uint16_t connectable : 1; /**< Connectable advertising event type. */ + uint16_t scannable : 1; /**< Scannable advertising event type. */ + uint16_t directed : 1; /**< Directed advertising event type. */ + uint16_t scan_response : 1; /**< Received a scan response. */ + uint16_t extended_pdu : 1; /**< Received an extended advertising set. */ + uint16_t status : 2; /**< Data status. See @ref BLE_GAP_ADV_DATA_STATUS. */ + uint16_t reserved : 9; /**< Reserved for future use. */ +} ble_gap_adv_report_type_t; + +/**@brief Advertising Auxiliary Pointer. */ +typedef struct +{ + uint16_t aux_offset; /**< Time offset from the beginning of advertising packet to the auxiliary packet in 100 us units. */ + uint8_t aux_phy; /**< Indicates the PHY on which the auxiliary advertising packet is sent. See @ref BLE_GAP_PHYS. */ +} ble_gap_aux_pointer_t; + +/**@brief Bluetooth Low Energy address. */ +typedef struct +{ + uint8_t addr_id_peer : 1; /**< Only valid for peer addresses. + This bit is set by the SoftDevice to indicate whether the address has been resolved from + a Resolvable Private Address (when the peer is using privacy). + If set to 1, @ref addr and @ref addr_type refer to the identity address of the resolved address. + + This bit is ignored when a variable of type @ref ble_gap_addr_t is used as input to API functions. */ + uint8_t addr_type : 7; /**< See @ref BLE_GAP_ADDR_TYPES. */ + uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. + @ref addr is not used if @ref addr_type is @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. */ +} ble_gap_addr_t; + + +/**@brief GAP connection parameters. + * + * @note When ble_conn_params_t is received in an event, both min_conn_interval and + * max_conn_interval will be equal to the connection interval set by the central. + * + * @note If both conn_sup_timeout and max_conn_interval are specified, then the following constraint applies: + * conn_sup_timeout * 4 > (1 + slave_latency) * max_conn_interval + * that corresponds to the following Bluetooth Spec requirement: + * The Supervision_Timeout in milliseconds shall be larger than + * (1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given in milliseconds. + */ +typedef struct +{ + uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ +} ble_gap_conn_params_t; + + +/**@brief GAP connection security modes. + * + * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n + * Security Mode 1 Level 1: No security is needed (aka open link).\n + * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n + * Security Mode 1 Level 3: MITM protected encrypted link required.\n + * Security Mode 1 Level 4: LESC MITM protected encrypted link using a 128-bit strength encryption key required.\n + * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n + * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n + */ +typedef struct +{ + uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ + uint8_t lv : 4; /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */ + +} ble_gap_conn_sec_mode_t; + + +/**@brief GAP connection security status.*/ +typedef struct +{ + ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ + uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ +} ble_gap_conn_sec_t; + +/**@brief Identity Resolving Key. */ +typedef struct +{ + uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ +} ble_gap_irk_t; + + +/**@brief Channel mask (40 bits). + * Every channel is represented with a bit positioned as per channel index defined in Bluetooth Core Specification v5.0, + * Vol 6, Part B, Section 1.4.1. The LSB contained in array element 0 represents channel index 0, and bit 39 represents + * channel index 39. If a bit is set to 1, the channel is not used. + */ +typedef uint8_t ble_gap_ch_mask_t[5]; + + +/**@brief GAP advertising parameters. */ +typedef struct +{ + ble_gap_adv_properties_t properties; /**< The properties of the advertising events. */ + ble_gap_addr_t const *p_peer_addr; /**< Address of a known peer. + @note ble_gap_addr_t::addr_type cannot be + @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. + - When privacy is enabled and the local device uses + @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE addresses, + the device identity list is searched for a matching entry. If + the local IRK for that device identity is set, the local IRK + for that device will be used to generate the advertiser address + field in the advertising packet. + - If @ref ble_gap_adv_properties_t::type is directed, this must be + set to the targeted scanner or initiator. If the peer address is + in the device identity list, the peer IRK for that device will be + used to generate @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE + target addresses used in the advertising event PDUs. */ + uint32_t interval; /**< Advertising interval in 625 us units. @sa BLE_GAP_ADV_INTERVALS. + @note If @ref ble_gap_adv_properties_t::type is set to + @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE + advertising, this parameter is ignored. */ + uint16_t duration; /**< Advertising duration in 10 ms units. When timeout is reached, + an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised. + @sa BLE_GAP_ADV_TIMEOUT_VALUES. + @note The SoftDevice will always complete at least one advertising + event even if the duration is set too low. */ + uint8_t max_adv_evts; /**< Maximum advertising events that shall be sent prior to disabling + advertising. Setting the value to 0 disables the limitation. When + the count of advertising events specified by this parameter + (if not 0) is reached, advertising will be automatically stopped + and an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised + @note If @ref ble_gap_adv_properties_t::type is set to + @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE, + this parameter is ignored. */ + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + At least one of the primary channels, that is channel index 37-39, must be used. + Masking away secondary advertising channels is not supported. */ + uint8_t filter_policy; /**< Filter Policy. @sa BLE_GAP_ADV_FILTER_POLICIES. */ + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising channel packets + are transmitted. If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS + will be used. + The only supported value by this SoftDevice is @ref BLE_GAP_PHY_1MBPS. */ + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising channel packets + are transmitted. + If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS will be used. + Valid values are + @ref BLE_GAP_PHY_1MBPS and @ref BLE_GAP_PHY_2MBPS. @ref BLE_GAP_PHY_CODED + is not supported by this SoftDevice. + If @ref ble_gap_adv_properties_t::type is an extended advertising type + and connectable, this is the PHY that will be used to establish a + connection and send AUX_ADV_IND packets on. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ + uint8_t set_id:4; /**< The advertising set identifier distinguishes this advertising set from other + advertising sets transmitted by this and other devices. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ + uint8_t scan_req_notification:1; /**< Enable scan request notifications for this advertising set. When a + scan request is received and the scanner address is allowed + by the filter policy, @ref BLE_GAP_EVT_SCAN_REQ_REPORT is raised. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is a non-scannable + advertising type. */ +} ble_gap_adv_params_t; + + +/**@brief GAP advertising data buffers. + * + * The application must provide the buffers for advertisement. The memory shall reside in application RAM, and + * shall never be modified while advertising. The data shall be kept alive until either: + * - @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised. + * - @ref BLE_GAP_EVT_CONNECTED is raised with @ref ble_gap_evt_connected_t::adv_handle set to the corresponding + * advertising handle. + * - Advertising is stopped. + * - Advertising data is changed. + * To update advertising data while advertising, provide new buffers to @ref sd_ble_gap_adv_set_configure. */ +typedef struct +{ + ble_data_t adv_data; /**< Advertising data. + @note + Advertising data can only be specified for a @ref ble_gap_adv_properties_t::type + that is allowed to contain advertising data. */ + ble_data_t scan_rsp_data; /**< Scan response data. + @note + Scan response data can only be specified for a @ref ble_gap_adv_properties_t::type + that is scannable. */ +} ble_gap_adv_data_t; + + +/**@brief GAP scanning parameters. */ +typedef struct +{ + uint8_t extended : 1; /**< If 1, the scanner will accept extended advertising packets. + If set to 0, the scanner will not receive advertising packets + on secondary advertising channels, and will not be able + to receive long advertising PDUs. */ + uint8_t report_incomplete_evts : 1; /**< If 1, events of type @ref ble_gap_evt_adv_report_t may have + @ref ble_gap_adv_report_type_t::status set to + @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. + This parameter is ignored when used with @ref sd_ble_gap_connect + @note This may be used to abort receiving more packets from an extended + advertising event, and is only available for extended + scanning, see @ref sd_ble_gap_scan_start. + @note This feature is not supported by this SoftDevice. */ + uint8_t active : 1; /**< If 1, perform active scanning by sending scan requests. + This parameter is ignored when used with @ref sd_ble_gap_connect. */ + uint8_t filter_policy : 2; /**< Scanning filter policy. @sa BLE_GAP_SCAN_FILTER_POLICIES. + @note Only @ref BLE_GAP_SCAN_FP_ACCEPT_ALL and + @ref BLE_GAP_SCAN_FP_WHITELIST are valid when used with + @ref sd_ble_gap_connect */ + uint8_t scan_phys; /**< Bitfield of PHYs to scan on. If set to @ref BLE_GAP_PHY_AUTO, + scan_phys will default to @ref BLE_GAP_PHY_1MBPS. + - If @ref ble_gap_scan_params_t::extended is set to 0, the only + supported PHY is @ref BLE_GAP_PHY_1MBPS. + - When used with @ref sd_ble_gap_scan_start, + the bitfield indicates the PHYs the scanner will use for scanning + on primary advertising channels. The scanner will accept + @ref BLE_GAP_PHYS_SUPPORTED as secondary advertising channel PHYs. + - When used with @ref sd_ble_gap_connect, the bitfield indicates + the PHYs the initiator will use for scanning on primary advertising + channels. The initiator will accept connections initiated on either + of the @ref BLE_GAP_PHYS_SUPPORTED PHYs. + If scan_phys contains @ref BLE_GAP_PHY_1MBPS and/or @ref BLE_GAP_PHY_2MBPS, + the primary scan PHY is @ref BLE_GAP_PHY_1MBPS. */ + uint16_t interval; /**< Scan interval in 625 us units. @sa BLE_GAP_SCAN_INTERVALS. */ + uint16_t window; /**< Scan window in 625 us units. @sa BLE_GAP_SCAN_WINDOW. */ + uint16_t timeout; /**< Scan timeout in 10 ms units. @sa BLE_GAP_SCAN_TIMEOUT. */ + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + At least one of the primary channels, that is channel index 37-39, must be + set to 0. + Masking away secondary channels is not supported. */ +} ble_gap_scan_params_t; + + +/**@brief Privacy. + * + * The privacy feature provides a way for the device to avoid being tracked over a period of time. + * The privacy feature, when enabled, hides the local device identity and replaces it with a private address + * that is automatically refreshed at a specified interval. + * + * If a device still wants to be recognized by other peers, it needs to share it's Identity Resolving Key (IRK). + * With this key, a device can generate a random private address that can only be recognized by peers in possession of that key, + * and devices can establish connections without revealing their real identities. + * + * Both network privacy (@ref BLE_GAP_PRIVACY_MODE_NETWORK_PRIVACY) and device privacy (@ref BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY) + * are supported. + * + * @note If the device IRK is updated, the new IRK becomes the one to be distributed in all + * bonding procedures performed after @ref sd_ble_gap_privacy_set returns. + * The IRK distributed during bonding procedure is the device IRK that is active when @ref sd_ble_gap_sec_params_reply is called. + */ +typedef struct +{ + uint8_t privacy_mode; /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */ + uint8_t private_addr_type; /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */ + uint16_t private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */ + ble_gap_irk_t *p_device_irk; /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used. + When used as output, pointer to IRK structure where the current default IRK will be written to. If NULL, this argument is ignored. + By default, the default IRK is used to generate random private resolvable addresses for the local device unless instructed otherwise. */ +} ble_gap_privacy_params_t; + + +/**@brief PHY preferences for TX and RX + * @note tx_phys and rx_phys are bit fields. Multiple bits can be set in them to indicate multiple preferred PHYs for each direction. + * @code + * p_gap_phys->tx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS; + * p_gap_phys->rx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS; + * @endcode + * + */ +typedef struct +{ + uint8_t tx_phys; /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phys; /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */ +} ble_gap_phys_t; + +/** @brief Keys that can be exchanged during a bonding procedure. */ +typedef struct +{ + uint8_t enc : 1; /**< Long Term Key and Master Identification. */ + uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */ + uint8_t sign : 1; /**< Connection Signature Resolving Key. */ + uint8_t link : 1; /**< Derive the Link Key from the LTK. */ +} ble_gap_sec_kdist_t; + + +/**@brief GAP security parameters. */ +typedef struct +{ + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Enable Man In The Middle protection. */ + uint8_t lesc : 1; /**< Enable LE Secure Connection pairing. */ + uint8_t keypress : 1; /**< Enable generation of keypress notifications. */ + uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ + uint8_t oob : 1; /**< The OOB data flag. + - In LE legacy pairing, this flag is set if a device has out of band authentication data. + The OOB method is used if both of the devices have out of band authentication data. + - In LE Secure Connections pairing, this flag is set if a device has the peer device's out of band authentication data. + The OOB method is used if at least one device has the peer device's OOB data available. */ + uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */ + uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ + ble_gap_sec_kdist_t kdist_own; /**< Key distribution bitmap: keys that the local device will distribute. */ + ble_gap_sec_kdist_t kdist_peer; /**< Key distribution bitmap: keys that the remote device will distribute. */ +} ble_gap_sec_params_t; + + +/**@brief GAP Encryption Information. */ +typedef struct +{ + uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ + uint8_t lesc : 1; /**< Key generated using LE Secure Connections. */ + uint8_t auth : 1; /**< Authenticated Key. */ + uint8_t ltk_len : 6; /**< LTK length in octets. */ +} ble_gap_enc_info_t; + + +/**@brief GAP Master Identification. */ +typedef struct +{ + uint16_t ediv; /**< Encrypted Diversifier. */ + uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */ +} ble_gap_master_id_t; + + +/**@brief GAP Signing Information. */ +typedef struct +{ + uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */ +} ble_gap_sign_info_t; + + +/**@brief GAP LE Secure Connections P-256 Public Key. */ +typedef struct +{ + uint8_t pk[BLE_GAP_LESC_P256_PK_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */ +} ble_gap_lesc_p256_pk_t; + + +/**@brief GAP LE Secure Connections DHKey. */ +typedef struct +{ + uint8_t key[BLE_GAP_LESC_DHKEY_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */ +} ble_gap_lesc_dhkey_t; + + +/**@brief GAP LE Secure Connections OOB data. */ +typedef struct +{ + ble_gap_addr_t addr; /**< Bluetooth address of the device. */ + uint8_t r[BLE_GAP_SEC_KEY_LEN]; /**< Random Number. */ + uint8_t c[BLE_GAP_SEC_KEY_LEN]; /**< Confirm Value. */ +} ble_gap_lesc_oob_data_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */ +typedef struct +{ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + and the address is the device's identity address. */ + uint8_t role; /**< BLE role for this connection, see @ref BLE_GAP_ROLES */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. + This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + advertising set. The advertising buffers provided in + @ref sd_ble_gap_adv_set_configure are now released. + This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ +} ble_gap_evt_connected_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */ +typedef struct +{ + uint8_t reason; /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */ +} ble_gap_evt_disconnected_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */ +typedef struct +{ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ +} ble_gap_evt_conn_param_update_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_PHY_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_phys_t peer_preferred_phys; /**< The PHYs the peer prefers to use. */ +} ble_gap_evt_phy_update_request_t; + +/**@brief Event Structure for @ref BLE_GAP_EVT_PHY_UPDATE. */ +typedef struct +{ + uint8_t status; /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES.*/ + uint8_t tx_phy; /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phy; /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */ +} ble_gap_evt_phy_update_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */ +typedef struct +{ + ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ +} ble_gap_evt_sec_params_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */ +typedef struct +{ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ + ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */ + uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ + uint8_t id_info : 1; /**< If 1, Identity Information required. */ + uint8_t sign_info : 1; /**< If 1, Signing Information required. */ +} ble_gap_evt_sec_info_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */ +typedef struct +{ + uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ + uint8_t match_request : 1; /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply + with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or + @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */ +} ble_gap_evt_passkey_display_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */ +typedef struct +{ + uint8_t kp_not; /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */ +} ble_gap_evt_key_pressed_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */ +typedef struct +{ + uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ +} ble_gap_evt_auth_key_request_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */ +typedef struct +{ + ble_gap_lesc_p256_pk_t *p_pk_peer; /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory + inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */ + uint8_t oobd_req :1; /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */ +} ble_gap_evt_lesc_dhkey_request_t; + + +/**@brief Security levels supported. + * @note See Bluetooth Specification Version 4.2 Volume 3, Part C, Chapter 10, Section 10.2.1. +*/ +typedef struct +{ + uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ + uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ + uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ + uint8_t lv4 : 1; /**< If 1: Level 4 is supported. */ +} ble_gap_sec_levels_t; + + +/**@brief Encryption Key. */ +typedef struct +{ + ble_gap_enc_info_t enc_info; /**< Encryption Information. */ + ble_gap_master_id_t master_id; /**< Master Identification. */ +} ble_gap_enc_key_t; + + +/**@brief Identity Key. */ +typedef struct +{ + ble_gap_irk_t id_info; /**< Identity Resolving Key. */ + ble_gap_addr_t id_addr_info; /**< Identity Address. */ +} ble_gap_id_key_t; + + +/**@brief Security Keys. */ +typedef struct +{ + ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */ + ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */ + ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */ + ble_gap_lesc_p256_pk_t *p_pk; /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined + in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */ +} ble_gap_sec_keys_t; + + +/**@brief Security key set for both local and peer keys. */ +typedef struct +{ + ble_gap_sec_keys_t keys_own; /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */ + ble_gap_sec_keys_t keys_peer; /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */ +} ble_gap_sec_keyset_t; + + +/**@brief Data Length Update Procedure parameters. */ +typedef struct +{ + uint16_t max_tx_octets; /**< Maximum number of payload octets that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_octets; /**< Maximum number of payload octets that a Controller supports for reception of a single Link Layer Data Channel PDU. */ + uint16_t max_tx_time_us; /**< Maximum time, in microseconds, that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_time_us; /**< Maximum time, in microseconds, that a Controller supports for reception of a single Link Layer Data Channel PDU. */ +} ble_gap_data_length_params_t; + + +/**@brief Data Length Update Procedure local limitation. */ +typedef struct +{ + uint16_t tx_payload_limited_octets; /**< If > 0, the requested TX packet length is too long by this many octets. */ + uint16_t rx_payload_limited_octets; /**< If > 0, the requested RX packet length is too long by this many octets. */ + uint16_t tx_rx_time_limited_us; /**< If > 0, the requested combination of TX and RX packet lengths is too long by this many microseconds. */ +} ble_gap_data_length_limitation_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */ +typedef struct +{ + uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ + uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ + uint8_t bonded : 1; /**< Procedure resulted in a bond. */ + uint8_t lesc : 1; /**< Procedure resulted in a LE Secure Connection. */ + ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ + ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ + ble_gap_sec_kdist_t kdist_own; /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */ + ble_gap_sec_kdist_t kdist_peer; /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */ +} ble_gap_evt_auth_status_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */ +typedef struct +{ + ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ +} ble_gap_evt_conn_sec_update_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ + union + { + ble_data_t adv_report_buffer; /**< If source is set to @ref BLE_GAP_TIMEOUT_SRC_SCAN, the released + scan buffer is contained in this field. */ + } params; /**< Event Parameters. */ +} ble_gap_evt_timeout_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */ +typedef struct +{ + int8_t rssi; /**< Received Signal Strength Indication in dBm. */ + uint8_t ch_index; /**< Data Channel Index on which the Signal Strength is measured (0-36). */ +} ble_gap_evt_rssi_changed_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_ADV_SET_TERMINATED */ +typedef struct +{ + uint8_t reason; /**< Reason for why the advertising set terminated. See + @ref BLE_GAP_EVT_ADV_SET_TERMINATED_REASON. */ + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. */ + uint8_t num_completed_adv_events; /**< If @ref ble_gap_adv_params_t::max_adv_evts was not set to 0, + this field indicates the number of completed advertising events. */ + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + advertising set. The advertising buffers provided in + @ref sd_ble_gap_adv_set_configure are now released. */ +} ble_gap_evt_adv_set_terminated_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_ADV_REPORT. + * + * @note If @ref ble_gap_adv_report_type_t::status is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, + * not all fields in the advertising report may be available. + * + * @note When ble_gap_adv_report_type_t::status is not set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, + * scanning will be paused. To continue scanning, call @ref sd_ble_gap_scan_start. + */ +typedef struct +{ + ble_gap_adv_report_type_t type; /**< Advertising report type. See @ref ble_gap_adv_report_type_t. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr is resolved: + @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the + peer's identity address. */ + ble_gap_addr_t direct_addr; /**< Contains the target address of the advertising event if + @ref ble_gap_adv_report_type_t::directed is set to 1. If the + SoftDevice was able to resolve the address, + @ref ble_gap_addr_t::addr_id_peer is set to 1 and the direct_addr + contains the local identity address. If the target address of the + advertising event is @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE, + and the SoftDevice was unable to resolve it, the application may try + to resolve this address to find out if the advertising event was + directed to us. */ + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising packet was received. + See @ref BLE_GAP_PHYS. */ + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising packet was received. + See @ref BLE_GAP_PHYS. This field is set to @ref BLE_GAP_PHY_NOT_SET if no packets + were received on a secondary advertising channel. */ + int8_t tx_power; /**< TX Power reported by the advertiser in the last packet header received. + This field is set to @ref BLE_GAP_POWER_LEVEL_INVALID if the + last received packet did not contain the Tx Power field. + @note TX Power is only included in extended advertising packets. */ + int8_t rssi; /**< Received Signal Strength Indication in dBm of the last packet received. */ + uint8_t ch_index; /**< Channel Index on which the last advertising packet is received (0-39). */ + uint8_t set_id; /**< Set ID of the received advertising data. Set ID is not present + if set to @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ + uint16_t data_id:12; /**< The advertising data ID of the received advertising data. Data ID + is not present if @ref ble_gap_evt_adv_report_t::set_id is set to + @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ + ble_data_t data; /**< Received advertising or scan response data. If + @ref ble_gap_adv_report_type_t::status is not set to + @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the data buffer provided + in @ref sd_ble_gap_scan_start is now released. */ + ble_gap_aux_pointer_t aux_pointer; /**< The offset and PHY of the next advertising packet in this extended advertising + event. @note This field is only set if @ref ble_gap_adv_report_type_t::status + is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. */ +} ble_gap_evt_adv_report_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */ +typedef struct +{ + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Man In The Middle protection requested. */ + uint8_t lesc : 1; /**< LE Secure Connections requested. */ + uint8_t keypress : 1; /**< Generation of keypress notifications requested. */ +} ble_gap_evt_sec_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ +} ble_gap_evt_conn_param_update_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */ +typedef struct +{ + uint8_t adv_handle; /**< Advertising handle for the advertising set which received the Scan Request */ + int8_t rssi; /**< Received Signal Strength Indication in dBm. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + and the address is the device's identity address. */ +} ble_gap_evt_scan_req_report_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_data_length_params_t peer_params; /**< Peer data length parameters. */ +} ble_gap_evt_data_length_update_request_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE. */ +typedef struct +{ + ble_gap_data_length_params_t effective_params; /**< The effective data length parameters. */ +} ble_gap_evt_data_length_update_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT. */ +typedef struct +{ + int8_t channel_energy[BLE_GAP_CHANNEL_COUNT]; /**< The measured energy on the Bluetooth Low Energy + channels, in dBm, indexed by Channel Index. + If no measurement is available for the given channel, channel_energy is set to + @ref BLE_GAP_POWER_LEVEL_INVALID. */ +} ble_gap_evt_qos_channel_survey_report_t; + +/**@brief GAP event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + union /**< union alternative identified by evt_id in enclosing struct. */ + { + ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ + ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ + ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ + ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ + ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ + ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. */ + ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ + ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. */ + ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ + ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ + ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event Parameters. */ + ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */ + ble_gap_evt_adv_set_terminated_t adv_set_terminated; /**< Advertising Set Terminated Event Parameters. */ + ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */ + ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report Parameters. */ + ble_gap_evt_phy_update_request_t phy_update_request; /**< PHY Update Request Event Parameters. */ + ble_gap_evt_phy_update_t phy_update; /**< PHY Update Parameters. */ + ble_gap_evt_data_length_update_request_t data_length_update_request; /**< Data Length Update Request Event Parameters. */ + ble_gap_evt_data_length_update_t data_length_update; /**< Data Length Update Event Parameters. */ + ble_gap_evt_qos_channel_survey_report_t qos_channel_survey_report; /**< Quality of Service (QoS) Channel Survey Report Parameters. */ + } params; /**< Event Parameters. */ +} ble_gap_evt_t; + + +/** + * @brief BLE GAP connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_CONN_COUNT The connection count for the connection configurations is zero. + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - The sum of conn_count for all connection configurations combined exceeds UINT8_MAX. + * - The event length is smaller than @ref BLE_GAP_EVENT_LENGTH_MIN. + */ +typedef struct +{ + uint8_t conn_count; /**< The number of concurrent connections the application can create with this configuration. + The default and minimum value is @ref BLE_GAP_CONN_COUNT_DEFAULT. */ + uint16_t event_length; /**< The time set aside for this connection on every connection interval in 1.25 ms units. + The default value is @ref BLE_GAP_EVENT_LENGTH_DEFAULT, the minimum value is @ref BLE_GAP_EVENT_LENGTH_MIN. + The event length and the connection interval are the primary parameters + for setting the throughput of a connection. + See the SoftDevice Specification for details on throughput. */ +} ble_gap_conn_cfg_t; + + +/** + * @brief Configuration of maximum concurrent connections in the different connected roles, set with + * @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_CONN_COUNT The sum of periph_role_count and central_role_count is too + * large. The maximum supported sum of concurrent connections is + * @ref BLE_GAP_ROLE_COUNT_COMBINED_MAX. + * @retval ::NRF_ERROR_INVALID_PARAM central_sec_count is larger than central_role_count. + * @retval ::NRF_ERROR_RESOURCES The adv_set_count is too large. The maximum + * supported advertising handles is + * @ref BLE_GAP_ADV_SET_COUNT_MAX. + */ +typedef struct +{ + uint8_t adv_set_count; /**< Maximum number of advertising sets. Default value is @ref BLE_GAP_ADV_SET_COUNT_DEFAULT. */ + uint8_t periph_role_count; /**< Maximum number of connections concurrently acting as a peripheral. Default value is @ref BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT. */ + uint8_t central_role_count; /**< Maximum number of connections concurrently acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT. */ + uint8_t central_sec_count; /**< Number of SMP instances shared between all connections acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT. */ + uint8_t qos_channel_survey_role_available:1; /**< If set, the Quality of Service (QoS) channel survey module is available to the + application using @ref sd_ble_gap_qos_channel_survey_start. */ +} ble_gap_cfg_role_count_t; + + +/** + * @brief Device name and its properties, set with @ref sd_ble_cfg_set. + * + * @note If the device name is not configured, the default device name will be + * @ref BLE_GAP_DEVNAME_DEFAULT, the maximum device name length will be + * @ref BLE_GAP_DEVNAME_DEFAULT_LEN, vloc will be set to @ref BLE_GATTS_VLOC_STACK and the device name + * will have no write access. + * + * @note If @ref max_len is more than @ref BLE_GAP_DEVNAME_DEFAULT_LEN and vloc is set to @ref BLE_GATTS_VLOC_STACK, + * the attribute table size must be increased to have room for the longer device name (see + * @ref sd_ble_cfg_set and @ref ble_gatts_cfg_attr_tab_size_t). + * + * @note If vloc is @ref BLE_GATTS_VLOC_STACK : + * - p_value must point to non-volatile memory (flash) or be NULL. + * - If p_value is NULL, the device name will initially be empty. + * + * @note If vloc is @ref BLE_GATTS_VLOC_USER : + * - p_value cannot be NULL. + * - If the device name is writable, p_value must point to volatile memory (RAM). + * + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - Invalid device name location (vloc). + * - Invalid device name security mode. + * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true: + * - The device name length is invalid (must be between 0 and @ref BLE_GAP_DEVNAME_MAX_LEN). + * - The device name length is too long for the given Attribute Table. + * @retval ::NRF_ERROR_NOT_SUPPORTED Device name security mode is not supported. + */ +typedef struct +{ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vloc:2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t *p_value; /**< Pointer to where the value (device name) is stored or will be stored. */ + uint16_t current_len; /**< Current length in bytes of the memory pointed to by p_value.*/ + uint16_t max_len; /**< Maximum length in bytes of the memory pointed to by p_value.*/ +} ble_gap_cfg_device_name_t; + + +/**@brief Configuration structure for GAP configurations. */ +typedef union +{ + ble_gap_cfg_role_count_t role_count_cfg; /**< Role count configuration, cfg_id is @ref BLE_GAP_CFG_ROLE_COUNT. */ + ble_gap_cfg_device_name_t device_name_cfg; /**< Device name configuration, cfg_id is @ref BLE_GAP_CFG_DEVICE_NAME. */ +} ble_gap_cfg_t; + + +/**@brief Channel Map option. + * + * @details Used with @ref sd_ble_opt_get to get the current channel map + * or @ref sd_ble_opt_set to set a new channel map. When setting the + * channel map, it applies to all current and future connections. When getting the + * current channel map, it applies to a single connection and the connection handle + * must be supplied. + * + * @note Setting the channel map may take some time, depending on connection parameters. + * The time taken may be different for each connection and the get operation will + * return the previous channel map until the new one has taken effect. + * + * @note After setting the channel map, by spec it can not be set again until at least 1 s has passed. + * See Bluetooth Specification Version 4.1 Volume 2, Part E, Section 7.3.46. + * + * @retval ::NRF_SUCCESS Get or set successful. + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - Less then two bits in @ref ch_map are set. + * - Bits for primary advertising channels (37-39) are set. + * @retval ::NRF_ERROR_BUSY Channel map was set again before enough time had passed. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied for get. + * + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle (only applicable for get) */ + uint8_t ch_map[5]; /**< Channel Map (37-bit). */ +} ble_gap_opt_ch_map_t; + + +/**@brief Local connection latency option. + * + * @details Local connection latency is a feature which enables the slave to improve + * current consumption by ignoring the slave latency set by the peer. The + * local connection latency can only be set to a multiple of the slave latency, + * and cannot be longer than half of the supervision timeout. + * + * @details Used with @ref sd_ble_opt_set to set the local connection latency. The + * @ref sd_ble_opt_get is not supported for this option, but the actual + * local connection latency (unless set to NULL) is set as a return parameter + * when setting the option. + * + * @note The latency set will be truncated down to the closest slave latency event + * multiple, or the nearest multiple before half of the supervision timeout. + * + * @note The local connection latency is disabled by default, and needs to be enabled for new + * connections and whenever the connection is updated. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t requested_latency; /**< Requested local connection latency. */ + uint16_t * p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ +} ble_gap_opt_local_conn_latency_t; + +/**@brief Disable slave latency + * + * @details Used with @ref sd_ble_opt_set to temporarily disable slave latency of a peripheral connection + * (see @ref ble_gap_conn_params_t::slave_latency). And to re-enable it again. When disabled, the + * peripheral will ignore the slave_latency set by the central. + * + * @note Shall only be called on peripheral links. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint8_t disable : 1; /**< Set to 1 to disable slave latency. Set to 0 enable it again.*/ +} ble_gap_opt_slave_latency_disable_t; + +/**@brief Passkey Option. + * + * @details Structure containing the passkey to be used during pairing. This can be used with @ref + * sd_ble_opt_set to make the SoftDevice use a preprogrammed passkey for authentication + * instead of generating a random one. + * + * @note Repeated pairing attempts using the same preprogrammed passkey makes pairing vulnerable to MITM attacks. + * + * @note @ref sd_ble_opt_get is not supported for this option. + * + */ +typedef struct +{ + uint8_t const * p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ +} ble_gap_opt_passkey_t; + + +/**@brief Compatibility mode 1 option. + * + * @details This can be used with @ref sd_ble_opt_set to enable and disable + * compatibility mode 1. Compatibility mode 1 is disabled by default. + * + * @note Compatibility mode 1 enables interoperability with devices that do not support a value of + * 0 for the WinOffset parameter in the Link Layer CONNECT_IND packet. This applies to a + * limited set of legacy peripheral devices from another vendor. Enabling this compatibility + * mode will only have an effect if the local device will act as a central device and + * initiate a connection to a peripheral device. In that case it may lead to the connection + * creation taking up to one connection interval longer to complete for all connections. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_INVALID_STATE When connection creation is ongoing while mode 1 is set. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable compatibility mode 1.*/ +} ble_gap_opt_compat_mode_1_t; + + +/**@brief Authenticated payload timeout option. + * + * @details This can be used with @ref sd_ble_opt_set to change the Authenticated payload timeout to a value other + * than the default of @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MAX. + * + * @note The authenticated payload timeout event ::BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD will be generated + * if auth_payload_timeout time has elapsed without receiving a packet with a valid MIC on an encrypted + * link. + * + * @note The LE ping procedure will be initiated before the timer expires to give the peer a chance + * to reset the timer. In addition the stack will try to prioritize running of LE ping over other + * activities to increase chances of finishing LE ping before timer expires. To avoid side-effects + * on other activities, it is recommended to use high timeout values. + * Recommended timeout > 2*(connInterval * (6 + connSlaveLatency)). + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. auth_payload_timeout was outside of allowed range. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t auth_payload_timeout; /**< Requested timeout in 10 ms unit, see @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT. */ +} ble_gap_opt_auth_payload_timeout_t; + +/**@brief Option structure for GAP options. */ +typedef union +{ + ble_gap_opt_ch_map_t ch_map; /**< Parameters for the Channel Map option. */ + ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Parameters for the Local connection latency option */ + ble_gap_opt_passkey_t passkey; /**< Parameters for the Passkey option.*/ + ble_gap_opt_compat_mode_1_t compat_mode_1; /**< Parameters for the compatibility mode 1 option.*/ + ble_gap_opt_auth_payload_timeout_t auth_payload_timeout; /**< Parameters for the authenticated payload timeout option.*/ + ble_gap_opt_slave_latency_disable_t slave_latency_disable; /**< Parameters for the Disable slave latency option */ +} ble_gap_opt_t; +/**@} */ + + +/**@addtogroup BLE_GAP_FUNCTIONS Functions + * @{ */ + +/**@brief Set the local Bluetooth identity address. + * + * The local Bluetooth identity address is the address that identifies this device to other peers. + * The address type must be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC. + * + * @note The identity address cannot be changed while advertising, scanning or creating a connection. + * + * @note This address will be distributed to the peer during bonding. + * If the address changes, the address stored in the peer device will not be valid and the ability to + * reconnect using the old address will be lost. + * + * @note By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC upon being + * enabled. The address is a random number populated during the IC manufacturing process and remains unchanged + * for the lifetime of each IC. + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @endmscs + * + * @param[in] p_addr Pointer to address structure. + * + * @retval ::NRF_SUCCESS Address successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_STATE The identity address cannot be changed while advertising, + * scanning or creating a connection. + */ +SVCALL(SD_BLE_GAP_ADDR_SET, uint32_t, sd_ble_gap_addr_set(ble_gap_addr_t const *p_addr)); + + +/**@brief Get local Bluetooth identity address. + * + * @note This will always return the identity address irrespective of the privacy settings, + * i.e. the address type will always be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC. + * + * @param[out] p_addr Pointer to address structure to be filled in. + * + * @retval ::NRF_SUCCESS Address successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + */ +SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr)); + + +/**@brief Get the Bluetooth device address used by the advertiser. + * + * @note This function will return the local Bluetooth address used in advertising PDUs. When + * using privacy, the SoftDevice will generate a new private address every + * @ref ble_gap_privacy_params_t::private_addr_cycle_s configured using + * @ref sd_ble_gap_privacy_set. Hence depending on when the application calls this API, the + * address returned may not be the latest address that is used in the advertising PDUs. + * + * @param[in] adv_handle The advertising handle to get the address from. + * @param[out] p_addr Pointer to address structure to be filled in. + * + * @retval ::NRF_SUCCESS Address successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. + * @retval ::NRF_ERROR_INVALID_STATE The advertising set is currently not advertising. + */ +SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr)); + + +/**@brief Set the active whitelist in the SoftDevice. + * + * @note Only one whitelist can be used at a time and the whitelist is shared between the BLE roles. + * The whitelist cannot be set if a BLE role is using the whitelist. + * + * @note If an address is resolved using the information in the device identity list, then the whitelist + * filter policy applies to the peer identity address and not the resolvable address sent on air. + * + * @mscs + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC} + * @endmscs + * + * @param[in] pp_wl_addrs Pointer to a whitelist of peer addresses, if NULL the whitelist will be cleared. + * @param[in] len Length of the whitelist, maximum @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. + * + * @retval ::NRF_SUCCESS The whitelist is successfully set/cleared. + * @retval ::NRF_ERROR_INVALID_ADDR The whitelist (or one of its entries) provided is invalid. + * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE The whitelist is in use by a BLE role and cannot be set or cleared. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_DATA_SIZE The given whitelist size is invalid (zero or too large); this can only return when + * pp_wl_addrs is not NULL. + */ +SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const * const * pp_wl_addrs, uint8_t len)); + + +/**@brief Set device identity list. + * + * @note Only one device identity list can be used at a time and the list is shared between the BLE roles. + * The device identity list cannot be set if a BLE role is using the list. + * + * @param[in] pp_id_keys Pointer to an array of peer identity addresses and peer IRKs, if NULL the device identity list will be cleared. + * @param[in] pp_local_irks Pointer to an array of local IRKs. Each entry in the array maps to the entry in pp_id_keys at the same index. + * To fill in the list with the currently set device IRK for all peers, set to NULL. + * @param[in] len Length of the device identity list, maximum @ref BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT. + * + * @mscs + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS The device identity list successfully set/cleared. + * @retval ::NRF_ERROR_INVALID_ADDR The device identity list (or one of its entries) provided is invalid. + * This code may be returned if the local IRK list also has an invalid entry. + * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE The device identity list is in use and cannot be set or cleared. + * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE The device identity list contains multiple entries with the same identity address. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_DATA_SIZE The given device identity list size invalid (zero or too large); this can + * only return when pp_id_keys is not NULL. + */ +SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const * const * pp_id_keys, ble_gap_irk_t const * const * pp_local_irks, uint8_t len)); + + +/**@brief Set privacy settings. + * + * @note Privacy settings cannot be changed while advertising, scanning or creating a connection. + * + * @param[in] p_privacy_params Privacy settings. + * + * @mscs + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_INVALID_ADDR The pointer to privacy settings is NULL or invalid. + * Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer. + * @retval ::NRF_ERROR_INVALID_PARAM Out of range parameters are provided. + * @retval ::NRF_ERROR_INVALID_STATE Privacy settings cannot be changed while advertising, scanning + * or creating a connection. + */ +SVCALL(SD_BLE_GAP_PRIVACY_SET, uint32_t, sd_ble_gap_privacy_set(ble_gap_privacy_params_t const *p_privacy_params)); + + +/**@brief Get privacy settings. + * + * @note ::ble_gap_privacy_params_t::p_device_irk must be initialized to NULL or a valid address before this function is called. + * If it is initialized to a valid address, the address pointed to will contain the current device IRK on return. + * + * @param[in,out] p_privacy_params Privacy settings. + * + * @retval ::NRF_SUCCESS Privacy settings read. + * @retval ::NRF_ERROR_INVALID_ADDR The pointer given for returning the privacy settings may be NULL or invalid. + * Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer. + */ +SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t *p_privacy_params)); + + +/**@brief Configure an advertising set. Set, clear or update advertising and scan response data. + * + * @note The format of the advertising data will be checked by this call to ensure interoperability. + * Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and + * duplicating the local name in the advertising data and scan response data. + * + * @note In order to update advertising data while advertising, new advertising buffers must be provided. + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in,out] p_adv_handle Provide a pointer to a handle containing @ref BLE_GAP_ADV_SET_HANDLE_NOT_SET to configure + * a new advertising set. On success, a new handle is then returned through the pointer. + * Provide a pointer to an existing advertising handle to configure an existing advertising set. + * @param[in] p_adv_data Advertising data. If set to NULL, no advertising data will be used. See @ref ble_gap_adv_data_t. + * @param[in] p_adv_params Advertising parameters. When this function is used to update advertising data while advertising, + * this parameter must be NULL. See @ref ble_gap_adv_params_t. + * + * @retval ::NRF_SUCCESS Advertising set successfully configured. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied: + * - Invalid advertising data configuration specified. See @ref ble_gap_adv_data_t. + * - Invalid configuration of p_adv_params. See @ref ble_gap_adv_params_t. + * - Use of whitelist requested but whitelist has not been set, + * see @ref sd_ble_gap_whitelist_set. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR ble_gap_adv_params_t::p_peer_addr is invalid. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - It is invalid to provide non-NULL advertising set parameters while advertising. + * - It is invalid to provide the same data buffers while advertising. To update + * advertising data, provide new advertising buffers. + * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. Use @ref BLE_GAP_ADV_SET_HANDLE_NOT_SET to + * configure a new advertising handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied. + * @retval ::NRF_ERROR_INVALID_DATA Invalid data type(s) supplied. Check the advertising data format specification + * given in Bluetooth Specification Version 5.0, Volume 3, Part C, Chapter 11. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported data length or advertising parameter configuration. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to configure a new advertising handle. Update an + * existing advertising handle instead. + * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied. + */ +SVCALL(SD_BLE_GAP_ADV_SET_CONFIGURE, uint32_t, sd_ble_gap_adv_set_configure(uint8_t *p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params)); + + +/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). + * + * @note Only one advertiser may be active at any time. + * + * @events + * @event{@ref BLE_GAP_EVT_CONNECTED, Generated after connection has been established through connectable advertising.} + * @event{@ref BLE_GAP_EVT_ADV_SET_TERMINATED, Advertising set has terminated.} + * @event{@ref BLE_GAP_EVT_SCAN_REQ_REPORT, A scan request was received.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] adv_handle Advertising handle to advertise on, received from @ref sd_ble_gap_adv_set_configure. + * @param[in] conn_cfg_tag Tag identifying a configuration set by @ref sd_ble_cfg_set or + * @ref BLE_CONN_CFG_TAG_DEFAULT to use the default connection configuration. For non-connectable + * advertising, this is ignored. + * + * @retval ::NRF_SUCCESS The BLE stack has started advertising. + * @retval ::NRF_ERROR_INVALID_STATE adv_handle is not configured or already advertising. + * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached; connectable advertiser cannot be started. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Advertising handle not found. Configure a new adveriting handle with @ref sd_ble_gap_adv_set_configure. + * @retval ::NRF_ERROR_NOT_FOUND conn_cfg_tag not found. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied: + * - Invalid configuration of p_adv_params. See @ref ble_gap_adv_params_t. + * - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set. + * @retval ::NRF_ERROR_RESOURCES Either: + * - adv_handle is configured with connectable advertising, but the event_length parameter + * associated with conn_cfg_tag is too small to be able to establish a connection on + * the selected advertising phys. Use @ref sd_ble_cfg_set to increase the event length. + * - Not enough BLE role slots available. + Stop one or more currently active roles (Central, Peripheral, Broadcaster or Observer) and try again. + * - p_adv_params is configured with connectable advertising, but the event_length parameter + * associated with conn_cfg_tag is too small to be able to establish a connection on + * the selected advertising phys. Use @ref sd_ble_cfg_set to increase the event length. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported PHYs supplied to the call. + */ +SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(uint8_t adv_handle, uint8_t conn_cfg_tag)); + + +/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] adv_handle The advertising handle that should stop advertising. + * + * @retval ::NRF_SUCCESS The BLE stack has stopped advertising. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Invalid advertising handle. + * @retval ::NRF_ERROR_INVALID_STATE The advertising handle is not advertising. + */ +SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(uint8_t adv_handle)); + + + +/**@brief Update connection parameters. + * + * @details In the central role this will initiate a Link Layer connection parameter update procedure, + * otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for + * the central to perform the procedure. In both cases, and regardless of success or failure, the application + * will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event. + * + * @details This function can be used as a central both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested. + * + * @events + * @event{@ref BLE_GAP_EVT_CONN_PARAM_UPDATE, Result of the connection parameter update procedure.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CPU_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CPU_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CPU_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_conn_params Pointer to desired connection parameters. If NULL is provided on a peripheral role, + * the parameters in the PPCP characteristic of the GAP service will be used instead. + * If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected + * + * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress or link has not been established. + * @retval ::NRF_ERROR_BUSY Procedure already in progress, wait for pending procedures to complete and retry. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params)); + + +/**@brief Disconnect (GAP Link Termination). + * + * @details This call initiates the disconnection procedure, and its completion will be communicated to the application + * with a @ref BLE_GAP_EVT_DISCONNECTED event. + * + * @events + * @event{@ref BLE_GAP_EVT_DISCONNECTED, Generated when disconnection procedure is complete.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CONN_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are @ref BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION and @ref BLE_HCI_CONN_INTERVAL_UNACCEPTABLE). + * + * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress or link has not been established. + */ +SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code)); + + +/**@brief Set the radio's transmit power. + * + * @param[in] role The role to set the transmit power for, see @ref BLE_GAP_TX_POWER_ROLES for + * possible roles. + * @param[in] handle The handle parameter is interpreted depending on role: + * - If role is @ref BLE_GAP_TX_POWER_ROLE_CONN, this value is the specific connection handle. + * - If role is @ref BLE_GAP_TX_POWER_ROLE_ADV, the advertising set identified with the advertising handle, + * will use the specified transmit power, and include it in the advertising packet headers if + * @ref ble_gap_adv_properties_t::include_tx_power set. + * - For all other roles handle is ignored. + * @param[in] tx_power Radio transmit power in dBm (see note for accepted values). + * + * @note Supported tx_power values: -40dBm, -20dBm, -16dBm, -12dBm, -8dBm, -4dBm, 0dBm, +3dBm and +4dBm. + * @note The initiator will have the same transmit power as the scanner. + * @note When a connection is created it will inherit the transmit power from the initiator or + * advertiser leading to the connection. + * + * @retval ::NRF_SUCCESS Successfully changed the transmit power. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Advertising handle not found. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(uint8_t role, uint16_t handle, int8_t tx_power)); + + +/**@brief Set GAP Appearance value. + * + * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES. + * + * @retval ::NRF_SUCCESS Appearance value set successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + */ +SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance)); + + +/**@brief Get GAP Appearance value. + * + * @param[out] p_appearance Pointer to appearance (16-bit) to be filled in, see @ref BLE_APPEARANCES. + * + * @retval ::NRF_SUCCESS Appearance value retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance)); + + +/**@brief Set GAP Peripheral Preferred Connection Parameters. + * + * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters. + * + * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + */ +SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params)); + + +/**@brief Get GAP Peripheral Preferred Connection Parameters. + * + * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored. + * + * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params)); + + +/**@brief Set GAP device name. + * + * @note If the device name is located in application flash memory (see @ref ble_gap_cfg_device_name_t), + * it cannot be changed. Then @ref NRF_ERROR_FORBIDDEN will be returned. + * + * @param[in] p_write_perm Write permissions for the Device Name characteristic, see @ref ble_gap_conn_sec_mode_t. + * @param[in] p_dev_name Pointer to a UTF-8 encoded, <b>non NULL-terminated</b> string. + * @param[in] len Length of the UTF-8, <b>non NULL-terminated</b> string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN). + * + * @retval ::NRF_SUCCESS GAP device name and permissions set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_FORBIDDEN Device name is not writable. + */ +SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len)); + + +/**@brief Get GAP device name. + * + * @note If the device name is longer than the size of the supplied buffer, + * p_len will return the complete device name length, + * and not the number of bytes actually returned in p_dev_name. + * The application may use this information to allocate a suitable buffer size. + * + * @param[out] p_dev_name Pointer to an empty buffer where the UTF-8 <b>non NULL-terminated</b> string will be placed. Set to NULL to obtain the complete device name length. + * @param[in,out] p_len Length of the buffer pointed by p_dev_name, complete device name length on output. + * + * @retval ::NRF_SUCCESS GAP device name retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + */ +SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len)); + + +/**@brief Initiate the GAP Authentication procedure. + * + * @details In the central role, this function will send an SMP Pairing Request (or an SMP Pairing Failed if rejected), + * otherwise in the peripheral role, an SMP Security Request will be sent. + * + * @events + * @event{Depending on the security parameters set and the packet exchanges with the peer\, the following events may be generated:} + * @event{@ref BLE_GAP_EVT_SEC_PARAMS_REQUEST} + * @event{@ref BLE_GAP_EVT_SEC_INFO_REQUEST} + * @event{@ref BLE_GAP_EVT_PASSKEY_DISPLAY} + * @event{@ref BLE_GAP_EVT_KEY_PRESSED} + * @event{@ref BLE_GAP_EVT_AUTH_KEY_REQUEST} + * @event{@ref BLE_GAP_EVT_LESC_DHKEY_REQUEST} + * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE} + * @event{@ref BLE_GAP_EVT_AUTH_STATUS} + * @event{@ref BLE_GAP_EVT_TIMEOUT} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_SEC_REQ_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing or bonding procedure. + * In the peripheral role, only the bond, mitm, lesc and keypress fields of this structure are used. + * In the central role, this pointer may be NULL to reject a Security Request. + * + * @retval ::NRF_SUCCESS Successfully initiated authentication procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - No link has been established. + * - An encryption is already executing or queued. + * @retval ::NRF_ERROR_NO_MEM The maximum number of authentication procedures that can run in parallel for the given role is reached. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported. + * @retval ::NRF_ERROR_TIMEOUT A SMP timeout has occurred, and further SMP operations on this link is prohibited. + */ +SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params)); + + +/**@brief Reply with GAP security parameters. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_CONFIRM_FAIL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_KS_TOO_SMALL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_APP_ERROR_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_REMOTE_PAIRING_FAIL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_TIMEOUT_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS. + * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. In the central role this must be set to NULL, as the parameters have + * already been provided during a previous call to @ref sd_ble_gap_authenticate. + * @param[in,out] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys generated and/or distributed as a result of the ongoing security procedure + * will be stored into the memory referenced by the pointers inside this structure. The keys will be stored and available to the application + * upon reception of a @ref BLE_GAP_EVT_AUTH_STATUS event. + * Note that the SoftDevice expects the application to provide memory for storing the + * peer's keys. So it must be ensured that the relevant pointers inside this structure are not NULL. The pointers to the local key + * can, however, be NULL, in which case, the local key data will not be available to the application upon reception of the + * @ref BLE_GAP_EVT_AUTH_STATUS event. + * + * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Security parameters has not been requested. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported. + */ +SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset)); + + +/**@brief Reply with an authentication key. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST or a @ref BLE_GAP_EVT_PASSKEY_DISPLAY, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES. + * @param[in] p_key If key type is @ref BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL. + * If key type is @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination) + * or NULL when confirming LE Secure Connections Numeric Comparison. + * If key type is @ref BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in little-endian format. + * + * @retval ::NRF_SUCCESS Authentication key successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Authentication key has not been requested. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key)); + + +/**@brief Reply with an LE Secure connections DHKey. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_dhkey LE Secure Connections DHKey. + * + * @retval ::NRF_SUCCESS DHKey successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - The peer is not authenticated. + * - The application has not pulled a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_DHKEY_REPLY, uint32_t, sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey)); + + +/**@brief Notify the peer of a local keypress. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] kp_not See @ref BLE_GAP_KP_NOT_TYPES. + * + * @retval ::NRF_SUCCESS Keypress notification successfully queued for transmission. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Authentication key not requested. + * - Passkey has not been entered. + * - Keypresses have not been enabled by both peers. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time. + */ +SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not)); + + +/**@brief Generate a set of OOB data to send to a peer out of band. + * + * @note The @ref ble_gap_addr_t included in the OOB data returned will be the currently active one (or, if a connection has already been established, + * the one used during connection setup). The application may manually overwrite it with an updated value. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. Can be @ref BLE_CONN_HANDLE_INVALID if a BLE connection has not been established yet. + * @param[in] p_pk_own LE Secure Connections local P-256 Public Key. + * @param[out] p_oobd_own The OOB data to be sent out of band to a peer. + * + * @retval ::NRF_SUCCESS OOB data successfully generated. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own)); + +/**@brief Provide the OOB data sent/received out of band. + * + * @note An authentication procedure with OOB selected as an algorithm must be in progress when calling this function. + * @note A @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event with the oobd_req set to 1 must have been received prior to calling this function. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_oobd_own The OOB data sent out of band to a peer or NULL if the peer has not received OOB data. + * Must correspond to @ref ble_gap_sec_params_t::oob flag in @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. + * @param[in] p_oobd_peer The OOB data received out of band from a peer or NULL if none received. + * Must correspond to @ref ble_gap_sec_params_t::oob flag + * in @ref sd_ble_gap_authenticate in the central role or + * in @ref sd_ble_gap_sec_params_reply in the peripheral role. + * + * @retval ::NRF_SUCCESS OOB data accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Authentication key not requested + * - Not expecting LESC OOB data + * - Have not actually exchanged passkeys. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_OOB_DATA_SET, uint32_t, sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer)); + + +/**@brief Initiate GAP Encryption procedure. + * + * @details In the central role, this function will initiate the encryption procedure using the encryption information provided. + * + * @events + * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE, The connection security has been updated.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure. + * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. + * + * @retval ::NRF_SUCCESS Successfully initiated authentication procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in the Peripheral role. + * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, wait for pending procedures to complete and retry. + */ +SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info)); + + +/**@brief Reply with GAP security information. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * @note Data signing is not yet supported, and p_sign_info must therefore be NULL. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_ENC_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available. + * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available. + * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available. + * + * @retval ::NRF_SUCCESS Successfully accepted security information. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - No link has been established. + * - No @ref BLE_GAP_EVT_SEC_REQUEST pending. + * - LE long term key requested command not allowed. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info)); + + +/**@brief Get the current connection security. + * + * @param[in] conn_handle Connection handle. + * @param[out] p_conn_sec Pointer to a @ref ble_gap_conn_sec_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Current connection security successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec)); + + +/**@brief Start reporting the received signal strength to the application. + * + * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called. + * + * @events + * @event{@ref BLE_GAP_EVT_RSSI_CHANGED, New RSSI data available. How often the event is generated is + * dependent on the settings of the <code>threshold_dbm</code> + * and <code>skip_count</code> input parameters.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] threshold_dbm Minimum change in dBm before triggering the @ref BLE_GAP_EVT_RSSI_CHANGED event. Events are disabled if threshold_dbm equals @ref BLE_GAP_RSSI_THRESHOLD_INVALID. + * @param[in] skip_count Number of RSSI samples with a change of threshold_dbm or more before sending a new @ref BLE_GAP_EVT_RSSI_CHANGED event. + * + * @retval ::NRF_SUCCESS Successfully activated RSSI reporting. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is already ongoing. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count)); + + +/**@brief Stop reporting the received signal strength. + * + * @note An RSSI change detected before the call but not yet received by the application + * may be reported after @ref sd_ble_gap_rssi_stop has been called. + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * + * @retval ::NRF_SUCCESS Successfully deactivated RSSI reporting. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle)); + + +/**@brief Get the received signal strength for the last connection event. + * + * @ref sd_ble_gap_rssi_start must be called to start reporting RSSI before using this function. @ref NRF_ERROR_NOT_FOUND + * will be returned until RSSI was sampled for the first time after calling @ref sd_ble_gap_rssi_start. + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[out] p_rssi Pointer to the location where the RSSI measurement shall be stored. + * @param[out] p_ch_index Pointer to the location where Channel Index for the RSSI measurement shall be stored. + * + * @retval ::NRF_SUCCESS Successfully read the RSSI. + * @retval ::NRF_ERROR_NOT_FOUND No sample is available. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing. + */ +SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi, uint8_t *p_ch_index)); + + +/**@brief Start or continue scanning (GAP Discovery procedure, Observer Procedure). + * + * @note A call to this function will require the application to keep the memory pointed by + * p_adv_report_buffer alive until the buffer is released. The buffer is released when the scanner is stopped + * or when this function is called with another buffer. + * + * @note The scanner will automatically stop in the following cases: + * - @ref sd_ble_gap_scan_stop is called. + * - @ref sd_ble_gap_connect is called. + * - A @ref BLE_GAP_EVT_TIMEOUT with source set to @ref BLE_GAP_TIMEOUT_SRC_SCAN is received. + * - When a @ref BLE_GAP_EVT_ADV_REPORT event is received and @ref ble_gap_adv_report_type_t::status is not set to + * @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. In this case scanning is only paused to let the application + * access received data. The application must call this function to continue scanning, or call @ref sd_ble_gap_scan_stop + * to stop scanning. + * + * @note If a @ref BLE_GAP_EVT_ADV_REPORT event is received with @ref ble_gap_adv_report_type_t::status set to + * @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the scanner will continue scanning, and the application will + * receive more reports from this advertising event. The following reports will include the old and new received data. + * + * @events + * @event{@ref BLE_GAP_EVT_ADV_REPORT, An advertising or scan response packet has been received.} + * @event{@ref BLE_GAP_EVT_TIMEOUT, Scanner has timed out.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_SCAN_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] p_scan_params Pointer to scan parameters structure. When this function is used to continue + * scanning, this parameter must be NULL. + * @param[in] p_adv_report_buffer Pointer to buffer used to store incoming advertising data. + * The memory pointed to should be kept alive until the scanning is stopped. + * See @ref BLE_GAP_SCAN_BUFFER_SIZE for minimum and maximum buffer size. + * If the scanner receives advertising data larger than can be stored in the buffer, + * a @ref BLE_GAP_EVT_ADV_REPORT will be raised with @ref ble_gap_adv_report_type_t::status + * set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_TRUNCATED. + * + * @retval ::NRF_SUCCESS Successfully initiated scanning procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Scanning is already ongoing and p_scan_params was not NULL + * - Scanning is not running and p_scan_params was NULL. + * - The scanner has timed out when this function is called to continue scanning. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. See @ref ble_gap_scan_params_t. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported parameters supplied. See @ref ble_gap_scan_params_t. + * @retval ::NRF_ERROR_INVALID_LENGTH The provided buffer length is invalid. See @ref BLE_GAP_SCAN_BUFFER_MIN. + * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available. + * Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported PHYs supplied to the call. + */ +SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const * p_adv_report_buffer)); + + +/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure). + * + * @note The buffer provided in @ref sd_ble_gap_scan_start is released. + * + * @mscs + * @mmsc{@ref BLE_GAP_SCAN_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully stopped scanning procedure. + * @retval ::NRF_ERROR_INVALID_STATE Not in the scanning state. + */ +SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void)); + + +/**@brief Create a connection (GAP Link Establishment). + * + * @note If a scanning procedure is currently in progress it will be automatically stopped when calling this function. + * The scanning procedure will be stopped even if the function returns an error. + * + * @events + * @event{@ref BLE_GAP_EVT_CONNECTED, A connection was established.} + * @event{@ref BLE_GAP_EVT_TIMEOUT, Failed to establish a connection.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC} + * @endmscs + * + * @param[in] p_peer_addr Pointer to peer identity address. If @ref ble_gap_scan_params_t::filter_policy is set to use + * whitelist, then p_peer_addr is ignored. + * @param[in] p_scan_params Pointer to scan parameters structure. + * @param[in] p_conn_params Pointer to desired connection parameters. + * @param[in] conn_cfg_tag Tag identifying a configuration set by @ref sd_ble_cfg_set or + * @ref BLE_CONN_CFG_TAG_DEFAULT to use the default connection configuration. + * + * @retval ::NRF_SUCCESS Successfully initiated connection procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * - Invalid parameter(s) in p_scan_params or p_conn_params. + * - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set. + * - Peer address was not present in the device identity list, see @ref sd_ble_gap_device_identities_set. + * @retval ::NRF_ERROR_NOT_FOUND conn_cfg_tag not found. + * @retval ::NRF_ERROR_INVALID_STATE The SoftDevice is in an invalid state to perform this operation. This may be due to an + * existing locally initiated connect procedure, which must complete before initiating again. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address. + * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached. + * @retval ::NRF_ERROR_RESOURCES Either: + * - Not enough BLE role slots available. + * Stop one or more currently active roles (Central, Peripheral or Observer) and try again. + * - The event_length parameter associated with conn_cfg_tag is too small to be able to + * establish a connection on the selected @ref ble_gap_scan_params_t::scan_phys. + * Use @ref sd_ble_cfg_set to increase the event length. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported PHYs supplied to the call. + */ +SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params, uint8_t conn_cfg_tag)); + + +/**@brief Cancel a connection establishment. + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully canceled an ongoing connection procedure. + * @retval ::NRF_ERROR_INVALID_STATE No locally initiated connect procedure started or connection + * completed occurred. + */ +SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void)); + + +/**@brief Initiate or respond to a PHY Update Procedure + * + * @details This function is used to initiate or respond to a PHY Update Procedure. It will always + * generate a @ref BLE_GAP_EVT_PHY_UPDATE event if successfully executed. + * If this function is used to initiate a PHY Update procedure and the only option + * provided in @ref ble_gap_phys_t::tx_phys and @ref ble_gap_phys_t::rx_phys is the + * currently active PHYs in the respective directions, the SoftDevice will generate a + * @ref BLE_GAP_EVT_PHY_UPDATE with the current PHYs set and will not initiate the + * procedure in the Link Layer. + * + * If @ref ble_gap_phys_t::tx_phys or @ref ble_gap_phys_t::rx_phys is @ref BLE_GAP_PHY_AUTO, + * then the stack will select PHYs based on the peer's PHY preferences and the local link + * configuration. The PHY Update procedure will for this case result in a PHY combination + * that respects the time constraints configured with @ref sd_ble_cfg_set and the current + * link layer data length. + * + * When acting as a central, the SoftDevice will select the fastest common PHY in each direction. + * + * If the peer does not support the PHY Update Procedure, then the resulting + * @ref BLE_GAP_EVT_PHY_UPDATE event will have a status set to + * @ref BLE_HCI_UNSUPPORTED_REMOTE_FEATURE. + * + * If the PHY procedure was rejected by the peer due to a procedure collision, the status + * will be @ref BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION or + * @ref BLE_HCI_DIFFERENT_TRANSACTION_COLLISION. + * If the peer responds to the PHY Update procedure with invalid parameters, the status + * will be @ref BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS. + * If the PHY procedure was rejected by the peer for a different reason, the status will + * contain the reason as specified by the peer. + * + * @events + * @event{@ref BLE_GAP_EVT_PHY_UPDATE, Result of the PHY Update Procedure.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_PHY_UPDATE} + * @mmsc{@ref BLE_GAP_PERIPHERAL_PHY_UPDATE} + * @endmscs + * + * @param[in] conn_handle Connection handle to indicate the connection for which the PHY Update is requested. + * @param[in] p_gap_phys Pointer to PHY structure. + * + * @retval ::NRF_SUCCESS Successfully requested a PHY Update. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported PHYs supplied to the call. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::NRF_ERROR_BUSY Procedure is already in progress or not allowed at this time. Process pending events and wait for the pending procedure to complete and retry. + * + */ +SVCALL(SD_BLE_GAP_PHY_UPDATE, uint32_t, sd_ble_gap_phy_update(uint16_t conn_handle, ble_gap_phys_t const *p_gap_phys)); + + +/**@brief Initiate or respond to a Data Length Update Procedure. + * + * @note If the application uses @ref BLE_GAP_DATA_LENGTH_AUTO for one or more members of + * p_dl_params, the SoftDevice will choose the highest value supported in current + * configuration and connection parameters. + * + * @param[in] conn_handle Connection handle. + * @param[in] p_dl_params Pointer to local parameters to be used in Data Length Update + * Procedure. Set any member to @ref BLE_GAP_DATA_LENGTH_AUTO to let + * the SoftDevice automatically decide the value for that member. + * Set to NULL to use automatic values for all members. + * @param[out] p_dl_limitation Pointer to limitation to be written when local device does not + * have enough resources or does not support the requested Data Length + * Update parameters. Ignored if NULL. + * + * @mscs + * @mmsc{@ref BLE_GAP_DATA_LENGTH_UPDATE_PROCEDURE_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully set Data Length Extension initiation/response parameters. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter supplied. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED The requested parameters are not supported by the SoftDevice. Inspect + * p_dl_limitation to see which parameter is not supported. + * @retval ::NRF_ERROR_RESOURCES The connection event length configured for this link is not sufficient for the requested parameters. + * Use @ref sd_ble_cfg_set with @ref BLE_CONN_CFG_GAP to increase the connection event length. + * Inspect p_dl_limitation to see where the limitation is. + * @retval ::NRF_ERROR_BUSY Peer has already initiated a Data Length Update Procedure. Process the + * pending @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST event to respond. + */ +SVCALL(SD_BLE_GAP_DATA_LENGTH_UPDATE, uint32_t, sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t *p_dl_limitation)); + +/**@brief Start the Quality of Service (QoS) channel survey module. + * + * @details The channel survey module provides measurements of the energy levels on + * the Bluetooth Low Energy channels. When the module is enabled, @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT + * events will periodically report the measured energy levels for each channel. + * + * @note The measurements are scheduled with lower priority than other Bluetooth Low Energy roles, + * Radio Timeslot API events and Flash API events. + * + * @note The channel survey module will attempt to do measurements so that the average interval + * between measurements will be interval_us. However due to the channel survey module + * having the lowest priority of all roles and modules, this may not be possible. In that + * case fewer than expected channel survey reports may be given. + * + * @note In order to use the channel survey module, @ref ble_gap_cfg_role_count_t::qos_channel_survey_role_available + * must be set. This is done using @ref sd_ble_cfg_set. + * + * @param[in] interval_us Requested average interval for the measurements and reports. See + * @ref BLE_GAP_QOS_CHANNEL_SURVEY_INTERVALS for valid ranges. If set + * to @ref BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS, the channel + * survey role will be scheduled at every available opportunity. + * + * @retval ::NRF_SUCCESS The module is successfully started. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter supplied. interval_us is out of the + * allowed range. + * @retval ::NRF_ERROR_INVALID_STATE Trying to start the module when already running. + * @retval ::NRF_ERROR_RESOURCES The channel survey module is not available to the application. + * Set @ref ble_gap_cfg_role_count_t::qos_channel_survey_role_available using + * @ref sd_ble_cfg_set. + */ +SVCALL(SD_BLE_GAP_QOS_CHANNEL_SURVEY_START, uint32_t, sd_ble_gap_qos_channel_survey_start(uint32_t interval_us)); + +/**@brief Stop the Quality of Service (QoS) channel survey module. + * + * @retval ::NRF_SUCCESS The module is successfully stopped. + * @retval ::NRF_ERROR_INVALID_STATE Trying to stop the module when it is not running. + */ +SVCALL(SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP, uint32_t, sd_ble_gap_qos_channel_survey_stop(void)); + + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GAP_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gatt.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gatt.h new file mode 100755 index 0000000..9cb577c --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gatt.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common + @{ + @brief Common definitions and prototypes for the GATT interfaces. + */ + +#ifndef BLE_GATT_H__ +#define BLE_GATT_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATT_DEFINES Defines + * @{ */ + +/** @brief Default ATT MTU, in bytes. */ +#define BLE_GATT_ATT_MTU_DEFAULT 23 + +/**@brief Invalid Attribute Handle. */ +#define BLE_GATT_HANDLE_INVALID 0x0000 + +/**@brief First Attribute Handle. */ +#define BLE_GATT_HANDLE_START 0x0001 + +/**@brief Last Attribute Handle. */ +#define BLE_GATT_HANDLE_END 0xFFFF + +/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources + * @{ */ +#define BLE_GATT_TIMEOUT_SRC_PROTOCOL 0x00 /**< ATT Protocol timeout. */ +/** @} */ + +/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations + * @{ */ +#define BLE_GATT_OP_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATT_OP_WRITE_REQ 0x01 /**< Write Request. */ +#define BLE_GATT_OP_WRITE_CMD 0x02 /**< Write Command. */ +#define BLE_GATT_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ +#define BLE_GATT_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ +#define BLE_GATT_OP_EXEC_WRITE_REQ 0x05 /**< Execute Write Request. */ +/** @} */ + +/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags + * @{ */ +#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00 /**< Cancel prepared write. */ +#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE 0x01 /**< Execute prepared write. */ +/** @} */ + +/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations + * @{ */ +#define BLE_GATT_HVX_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATT_HVX_NOTIFICATION 0x01 /**< Handle Value Notification. */ +#define BLE_GATT_HVX_INDICATION 0x02 /**< Handle Value Indication. */ +/** @} */ + +/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes + * @{ */ +#define BLE_GATT_STATUS_SUCCESS 0x0000 /**< Success. */ +#define BLE_GATT_STATUS_UNKNOWN 0x0001 /**< Unknown or not applicable status. */ +#define BLE_GATT_STATUS_ATTERR_INVALID 0x0100 /**< ATT Error: Invalid Error Code. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE 0x0101 /**< ATT Error: Invalid Attribute Handle. */ +#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED 0x0102 /**< ATT Error: Read not permitted. */ +#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED 0x0103 /**< ATT Error: Write not permitted. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_PDU 0x0104 /**< ATT Error: Used in ATT as Invalid PDU. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION 0x0105 /**< ATT Error: Authenticated link required. */ +#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED 0x0106 /**< ATT Error: Used in ATT as Request Not Supported. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET 0x0107 /**< ATT Error: Offset specified was past the end of the attribute. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION 0x0108 /**< ATT Error: Used in ATT as Insufficient Authorization. */ +#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL 0x0109 /**< ATT Error: Used in ATT as Prepare Queue Full. */ +#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND 0x010A /**< ATT Error: Used in ATT as Attribute not found. */ +#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG 0x010B /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE 0x010C /**< ATT Error: Encryption key size used is insufficient. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH 0x010D /**< ATT Error: Invalid value size. */ +#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR 0x010E /**< ATT Error: Very unlikely error. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION 0x010F /**< ATT Error: Encrypted link required. */ +#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE 0x0110 /**< ATT Error: Attribute type is not a supported grouping attribute. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES 0x0111 /**< ATT Error: Encrypted link required. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN 0x0112 /**< ATT Error: Reserved for Future Use range #1 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END 0x017F /**< ATT Error: Reserved for Future Use range #1 end. */ +#define BLE_GATT_STATUS_ATTERR_APP_BEGIN 0x0180 /**< ATT Error: Application range begin. */ +#define BLE_GATT_STATUS_ATTERR_APP_END 0x019F /**< ATT Error: Application range end. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN 0x01A0 /**< ATT Error: Reserved for Future Use range #2 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END 0x01DF /**< ATT Error: Reserved for Future Use range #2 end. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN 0x01E0 /**< ATT Error: Reserved for Future Use range #3 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END 0x01FC /**< ATT Error: Reserved for Future Use range #3 end. */ +#define BLE_GATT_STATUS_ATTERR_CPS_WRITE_REQ_REJECTED 0x01FC /**< ATT Common Profile and Service Error: Write request rejected. */ +#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR 0x01FD /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */ +#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG 0x01FE /**< ATT Common Profile and Service Error: Procedure Already in Progress. */ +#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE 0x01FF /**< ATT Common Profile and Service Error: Out Of Range. */ +/** @} */ + + +/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats + * @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml + * @{ */ +#define BLE_GATT_CPF_FORMAT_RFU 0x00 /**< Reserved For Future Use. */ +#define BLE_GATT_CPF_FORMAT_BOOLEAN 0x01 /**< Boolean. */ +#define BLE_GATT_CPF_FORMAT_2BIT 0x02 /**< Unsigned 2-bit integer. */ +#define BLE_GATT_CPF_FORMAT_NIBBLE 0x03 /**< Unsigned 4-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT8 0x04 /**< Unsigned 8-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT12 0x05 /**< Unsigned 12-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT16 0x06 /**< Unsigned 16-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT24 0x07 /**< Unsigned 24-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT32 0x08 /**< Unsigned 32-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT48 0x09 /**< Unsigned 48-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT64 0x0A /**< Unsigned 64-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT128 0x0B /**< Unsigned 128-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT8 0x0C /**< Signed 2-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT12 0x0D /**< Signed 12-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT16 0x0E /**< Signed 16-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT24 0x0F /**< Signed 24-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT32 0x10 /**< Signed 32-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT48 0x11 /**< Signed 48-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT64 0x12 /**< Signed 64-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT128 0x13 /**< Signed 128-bit integer. */ +#define BLE_GATT_CPF_FORMAT_FLOAT32 0x14 /**< IEEE-754 32-bit floating point. */ +#define BLE_GATT_CPF_FORMAT_FLOAT64 0x15 /**< IEEE-754 64-bit floating point. */ +#define BLE_GATT_CPF_FORMAT_SFLOAT 0x16 /**< IEEE-11073 16-bit SFLOAT. */ +#define BLE_GATT_CPF_FORMAT_FLOAT 0x17 /**< IEEE-11073 32-bit FLOAT. */ +#define BLE_GATT_CPF_FORMAT_DUINT16 0x18 /**< IEEE-20601 format. */ +#define BLE_GATT_CPF_FORMAT_UTF8S 0x19 /**< UTF-8 string. */ +#define BLE_GATT_CPF_FORMAT_UTF16S 0x1A /**< UTF-16 string. */ +#define BLE_GATT_CPF_FORMAT_STRUCT 0x1B /**< Opaque Structure. */ +/** @} */ + +/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces + * @{ + */ +#define BLE_GATT_CPF_NAMESPACE_BTSIG 0x01 /**< Bluetooth SIG defined Namespace. */ +#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATT_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATT connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_PARAM att_mtu is smaller than @ref BLE_GATT_ATT_MTU_DEFAULT. + */ +typedef struct +{ + uint16_t att_mtu; /**< Maximum size of ATT packet the SoftDevice can send or receive. + The default and minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + @mscs + @mmsc{@ref BLE_GATTC_MTU_EXCHANGE} + @mmsc{@ref BLE_GATTS_MTU_EXCHANGE} + @endmscs + */ +} ble_gatt_conn_cfg_t; + +/**@brief GATT Characteristic Properties. */ +typedef struct +{ + /* Standard properties */ + uint8_t broadcast :1; /**< Broadcasting of the value permitted. */ + uint8_t read :1; /**< Reading the value permitted. */ + uint8_t write_wo_resp :1; /**< Writing the value with Write Command permitted. */ + uint8_t write :1; /**< Writing the value with Write Request permitted. */ + uint8_t notify :1; /**< Notification of the value permitted. */ + uint8_t indicate :1; /**< Indications of the value permitted. */ + uint8_t auth_signed_wr :1; /**< Writing the value with Signed Write Command permitted. */ +} ble_gatt_char_props_t; + +/**@brief GATT Characteristic Extended Properties. */ +typedef struct +{ + /* Extended properties */ + uint8_t reliable_wr :1; /**< Writing the value with Queued Write operations permitted. */ + uint8_t wr_aux :1; /**< Writing the Characteristic User Description descriptor permitted. */ +} ble_gatt_char_ext_props_t; + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GATT_H__ + +/** @} */ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gattc.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gattc.h new file mode 100755 index 0000000..7fb3920 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gattc.h @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2011 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client + @{ + @brief Definitions and prototypes for the GATT Client interface. + */ + +#ifndef BLE_GATTC_H__ +#define BLE_GATTC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" +#include "ble_gatt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations + * @{ */ + +/**@brief GATTC API SVC numbers. */ +enum BLE_GATTC_SVCS +{ + SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ + SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ + SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ + SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ + SD_BLE_GATTC_ATTR_INFO_DISCOVER, /**< Attribute Information Discovery. */ + SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ + SD_BLE_GATTC_READ, /**< Generic read. */ + SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ + SD_BLE_GATTC_WRITE, /**< Generic write. */ + SD_BLE_GATTC_HV_CONFIRM, /**< Handle Value Confirmation. */ + SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. */ +}; + +/** + * @brief GATT Client Event IDs. + */ +enum BLE_GATTC_EVTS +{ + BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t. */ + BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. \n See @ref ble_gattc_evt_rel_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. \n See @ref ble_gattc_evt_char_disc_rsp_t. */ + BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. \n See @ref ble_gattc_evt_desc_disc_rsp_t. */ + BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, /**< Attribute Information Response event. \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t. */ + BLE_GATTC_EVT_READ_RSP, /**< Read Response event. \n See @ref ble_gattc_evt_read_rsp_t. */ + BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. \n See @ref ble_gattc_evt_char_vals_read_rsp_t. */ + BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. \n See @ref ble_gattc_evt_write_rsp_t. */ + BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm. \n See @ref ble_gattc_evt_hvx_t. */ + BLE_GATTC_EVT_EXCHANGE_MTU_RSP, /**< Exchange MTU Response event. \n See @ref ble_gattc_evt_exchange_mtu_rsp_t. */ + BLE_GATTC_EVT_TIMEOUT, /**< Timeout event. \n See @ref ble_gattc_evt_timeout_t. */ + BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE /**< Write without Response transmission complete. \n See @ref ble_gattc_evt_write_cmd_tx_complete_t. */ +}; + +/** @} */ + +/** @addtogroup BLE_GATTC_DEFINES Defines + * @{ */ + +/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC + * @{ */ +#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */ +/** @} */ + +/** @defgroup BLE_GATTC_ATTR_INFO_FORMAT Attribute Information Formats + * @{ */ +#define BLE_GATTC_ATTR_INFO_FORMAT_16BIT 1 /**< 16-bit Attribute Information Format. */ +#define BLE_GATTC_ATTR_INFO_FORMAT_128BIT 2 /**< 128-bit Attribute Information Format. */ +/** @} */ + +/** @defgroup BLE_GATTC_DEFAULTS GATT Client defaults + * @{ */ +#define BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT 1 /**< Default number of Write without Response that can be queued for transmission. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATTC_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATTC connection configuration parameters, set with @ref sd_ble_cfg_set. + */ +typedef struct +{ + uint8_t write_cmd_tx_queue_size; /**< The guaranteed minimum number of Write without Response that can be queued for transmission. + The default value is @ref BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT */ +} ble_gattc_conn_cfg_t; + +/**@brief Operation Handle Range. */ +typedef struct +{ + uint16_t start_handle; /**< Start Handle. */ + uint16_t end_handle; /**< End Handle. */ +} ble_gattc_handle_range_t; + + +/**@brief GATT service. */ +typedef struct +{ + ble_uuid_t uuid; /**< Service UUID. */ + ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ +} ble_gattc_service_t; + + +/**@brief GATT include. */ +typedef struct +{ + uint16_t handle; /**< Include Handle. */ + ble_gattc_service_t included_srvc; /**< Handle of the included service. */ +} ble_gattc_include_t; + + +/**@brief GATT characteristic. */ +typedef struct +{ + ble_uuid_t uuid; /**< Characteristic UUID. */ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + uint8_t char_ext_props : 1; /**< Extended properties present. */ + uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ + uint16_t handle_value; /**< Handle of the Characteristic Value. */ +} ble_gattc_char_t; + + +/**@brief GATT descriptor. */ +typedef struct +{ + uint16_t handle; /**< Descriptor Handle. */ + ble_uuid_t uuid; /**< Descriptor UUID. */ +} ble_gattc_desc_t; + + +/**@brief Write Parameters. */ +typedef struct +{ + uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ + uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ + uint16_t handle; /**< Handle to the attribute to be written. */ + uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ + uint16_t len; /**< Length of data in bytes. */ + uint8_t const *p_value; /**< Pointer to the value data. */ +} ble_gattc_write_params_t; + +/**@brief Attribute Information for 16-bit Attribute UUID. */ +typedef struct +{ + uint16_t handle; /**< Attribute handle. */ + ble_uuid_t uuid; /**< 16-bit Attribute UUID. */ +} ble_gattc_attr_info16_t; + +/**@brief Attribute Information for 128-bit Attribute UUID. */ +typedef struct +{ + uint16_t handle; /**< Attribute handle. */ + ble_uuid128_t uuid; /**< 128-bit Attribute UUID. */ +} ble_gattc_attr_info128_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Service count. */ + ble_gattc_service_t services[1]; /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_prim_srvc_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Include count. */ + ble_gattc_include_t includes[1]; /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_rel_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Characteristic count. */ + ble_gattc_char_t chars[1]; /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Descriptor count. */ + ble_gattc_desc_t descs[1]; /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_desc_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Attribute count. */ + uint8_t format; /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */ + union { + ble_gattc_attr_info16_t attr_info16[1]; /**< Attribute information for 16-bit Attribute UUID. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ + ble_gattc_attr_info128_t attr_info128[1]; /**< Attribute information for 128-bit Attribute UUID. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ + } info; /**< Attribute information union. */ +} ble_gattc_evt_attr_info_disc_rsp_t; + +/**@brief GATT read by UUID handle value pair. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint8_t *p_value; /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */ +} ble_gattc_handle_value_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */ +typedef struct +{ + uint16_t count; /**< Handle-Value Pair Count. */ + uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ + uint8_t handle_value[1]; /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_val_by_uuid_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint16_t offset; /**< Offset of the attribute data. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */ +typedef struct +{ + uint16_t len; /**< Concatenated Attribute values length. */ + uint8_t values[1]; /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_vals_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ + uint16_t offset; /**< Data offset. */ + uint16_t len; /**< Data length. */ + uint8_t data[1]; /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_write_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */ +typedef struct +{ + uint16_t handle; /**< Handle to which the HVx operation applies. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_hvx_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. */ +typedef struct +{ + uint16_t server_rx_mtu; /**< Server RX MTU size. */ +} ble_gattc_evt_exchange_mtu_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ +} ble_gattc_evt_timeout_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE. */ +typedef struct +{ + uint8_t count; /**< Number of write without response transmissions completed. */ +} ble_gattc_evt_write_cmd_tx_complete_t; + +/**@brief GATTC event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ + union + { + ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ + ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ + ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ + ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ + ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ + ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ + ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ + ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ + ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ + ble_gattc_evt_exchange_mtu_rsp_t exchange_mtu_rsp; /**< Exchange MTU Response Event Parameters. */ + ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gattc_evt_attr_info_disc_rsp_t attr_info_disc_rsp; /**< Attribute Information Discovery Event Parameters. */ + ble_gattc_evt_write_cmd_tx_complete_t write_cmd_tx_complete; /**< Write without Response transmission complete Event Parameters. */ + } params; /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */ +} ble_gattc_evt_t; +/** @} */ + +/** @addtogroup BLE_GATTC_FUNCTIONS Functions + * @{ */ + +/**@brief Initiate or continue a GATT Primary Service Discovery procedure. + * + * @details This function initiates or resumes a Primary Service discovery procedure, starting from the supplied handle. + * If the last service has not been reached, this function must be called again with an updated start handle value to continue the search. + * + * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with + * type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. + * + * @events + * @event{@ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_PRIM_SRVC_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] start_handle Handle to start searching from. + * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid)); + + +/**@brief Initiate or continue a GATT Relationship Discovery procedure. + * + * @details This function initiates or resumes the Find Included Services sub-procedure. If the last included service has not been reached, + * this must be called again with an updated handle range to continue the search. + * + * @events + * @event{@ref BLE_GATTC_EVT_REL_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_REL_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Characteristic Discovery procedure. + * + * @details This function initiates or resumes a Characteristic discovery procedure. If the last Characteristic has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with + * type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_CHAR_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure. + * + * @details This function initiates or resumes a Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @events + * @event{@ref BLE_GATTC_EVT_DESC_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_DESC_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure. + * + * @details This function initiates or resumes a Read using Characteristic UUID procedure. If the last Characteristic has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_READ_UUID_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_uuid Pointer to a Characteristic value UUID to read. + * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure. + * + * @details This function initiates or resumes a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor + * to be read is longer than ATT_MTU - 1, this function must be called multiple times with appropriate offset to read the + * complete value. + * + * @events + * @event{@ref BLE_GATTC_EVT_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_VALUE_READ_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] handle The handle of the attribute to be read. + * @param[in] offset Offset into the attribute value to be read. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset)); + + +/**@brief Initiate a GATT Read Multiple Characteristic Values procedure. + * + * @details This function initiates a GATT Read Multiple Characteristic Values procedure. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_READ_MULT_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read. + * @param[in] handle_count The number of handles in p_handles. + * + * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count)); + + +/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure. + * + * @details This function can perform all write procedures described in GATT. + * + * @note Only one write with response procedure can be ongoing per connection at a time. + * If the application tries to write with response while another write with response procedure is ongoing, + * the function call will return @ref NRF_ERROR_BUSY. + * A @ref BLE_GATTC_EVT_WRITE_RSP event will be issued as soon as the write response arrives from the peer. + * + * @note The number of Write without Response that can be queued is configured by @ref ble_gattc_conn_cfg_t::write_cmd_tx_queue_size + * When the queue is full, the function call will return @ref NRF_ERROR_RESOURCES. + * A @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event will be issued as soon as the transmission of the write without response is complete. + * + * @note The application can keep track of the available queue element count for writes without responses by following the procedure below: + * - Store initial queue element count in a variable. + * - Decrement the variable, which stores the currently available queue element count, by one when a call to this function returns @ref NRF_SUCCESS. + * - Increment the variable, which stores the current available queue element count, by the count variable in @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event. + * + * @events + * @event{@ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE, Write without response transmission complete.} + * @event{@ref BLE_GATTC_EVT_WRITE_RSP, Write response received from the peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_VALUE_WRITE_WITHOUT_RESP_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_WRITE_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_LONG_WRITE_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_RELIABLE_WRITE_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_write_params A pointer to a write parameters structure. + * + * @retval ::NRF_SUCCESS Successfully started the Write procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_BUSY For write with response, procedure already in progress. Wait for a @ref BLE_GATTC_EVT_WRITE_RSP event and retry. + * @retval ::NRF_ERROR_RESOURCES Too many writes without responses queued. + * Wait for a @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event and retry. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params)); + + +/**@brief Send a Handle Value Confirmation to the GATT Server. + * + * @mscs + * @mmsc{@ref BLE_GATTC_HVI_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] handle The handle of the attribute in the indication. + * + * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no Indication pending to be confirmed. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle)); + +/**@brief Discovers information about a range of attributes on a GATT server. + * + * @events + * @event{@ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, Generated when information about a range of attributes has been received.} + * @endevents + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range The range of handles to request information about. + * + * @retval ::NRF_SUCCESS Successfully started an attribute information discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range)); + +/**@brief Start an ATT_MTU exchange by sending an Exchange MTU Request to the server. + * + * @details The SoftDevice sets ATT_MTU to the minimum of: + * - The Client RX MTU value, and + * - The Server RX MTU value from @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. + * + * However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_ATT_MTU_DEFAULT. + * + * @events + * @event{@ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_MTU_EXCHANGE} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] client_rx_mtu Client RX MTU size. + * - The minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + * - The maximum value is @ref ble_gatt_conn_cfg_t::att_mtu in the connection configuration + used for this connection. + * - The value must be equal to Server RX MTU size given in @ref sd_ble_gatts_exchange_mtu_reply + * if an ATT_MTU exchange has already been performed in the other direction. + * + * @retval ::NRF_SUCCESS Successfully sent request to the server. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state or an ATT_MTU exchange was already requested once. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid Client RX MTU size supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, uint32_t, sd_ble_gattc_exchange_mtu_request(uint16_t conn_handle, uint16_t client_rx_mtu)); + +/**@brief Iterate through Handle-Value(s) list in @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event. + * + * @param[in] p_gattc_evt Pointer to event buffer containing @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event. + * @note If the buffer contains different event, behavior is undefined. + * @param[in,out] p_iter Iterator, points to @ref ble_gattc_handle_value_t structure that will be filled in with + * the next Handle-Value pair in each iteration. If the function returns other than + * @ref NRF_SUCCESS, it will not be changed. + * - To start iteration, initialize the structure to zero. + * - To continue, pass the value from previous iteration. + * + * \code + * ble_gattc_handle_value_t iter; + * memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); + * while (sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(&ble_evt.evt.gattc_evt, &iter) == NRF_SUCCESS) + * { + * app_handle = iter.handle; + * memcpy(app_value, iter.p_value, ble_evt.evt.gattc_evt.params.char_val_by_uuid_read_rsp.value_len); + * } + * \endcode + * + * @retval ::NRF_SUCCESS Successfully retrieved the next Handle-Value pair. + * @retval ::NRF_ERROR_NOT_FOUND No more Handle-Value pairs available in the list. + */ +__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter); + +/** @} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter) +{ + uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len; + uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value; + uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first; + + if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count) + { + p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0]; + p_iter->p_value = p_next + sizeof(uint16_t); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_NOT_FOUND; + } +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +#ifdef __cplusplus +} +#endif +#endif /* BLE_GATTC_H__ */ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gatts.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gatts.h new file mode 100755 index 0000000..394d8d1 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_gatts.h @@ -0,0 +1,845 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server + @{ + @brief Definitions and prototypes for the GATTS interface. + */ + +#ifndef BLE_GATTS_H__ +#define BLE_GATTS_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" +#include "ble_gatt.h" +#include "ble_gap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations + * @{ */ + +/** + * @brief GATTS API SVC numbers. + */ +enum BLE_GATTS_SVCS +{ + SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ + SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ + SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ + SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ + SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ + SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ + SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ + SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ + SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ + SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ + SD_BLE_GATTS_SYS_ATTR_GET, /**< Retrieve the persistent system attributes. */ + SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, /**< Retrieve the first valid user handle. */ + SD_BLE_GATTS_ATTR_GET, /**< Retrieve the UUID and/or metadata of an attribute. */ + SD_BLE_GATTS_EXCHANGE_MTU_REPLY /**< Reply to Exchange MTU Request. */ +}; + +/** + * @brief GATT Server Event IDs. + */ +enum BLE_GATTS_EVTS +{ + BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. \n See @ref ble_gatts_evt_write_t. */ + BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */ + BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending. \n Respond with @ref sd_ble_gatts_sys_attr_set. \n See @ref ble_gatts_evt_sys_attr_missing_t. */ + BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. \n See @ref ble_gatts_evt_hvc_t. */ + BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. \n No additional event structure applies. */ + BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */ + BLE_GATTS_EVT_TIMEOUT, /**< Peer failed to respond to an ATT request in time. \n See @ref ble_gatts_evt_timeout_t. */ + BLE_GATTS_EVT_HVN_TX_COMPLETE /**< Handle Value Notification transmission complete. \n See @ref ble_gatts_evt_hvn_tx_complete_t. */ +}; + +/**@brief GATTS Configuration IDs. + * + * IDs that uniquely identify a GATTS configuration. + */ +enum BLE_GATTS_CFGS +{ + BLE_GATTS_CFG_SERVICE_CHANGED = BLE_GATTS_CFG_BASE, /**< Service changed configuration. */ + BLE_GATTS_CFG_ATTR_TAB_SIZE, /**< Attribute table size configuration. */ +}; + +/** @} */ + +/** @addtogroup BLE_GATTS_DEFINES Defines + * @{ */ + +/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS + * @{ */ +#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */ +#define BLE_ERROR_GATTS_SYS_ATTR_MISSING (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */ +/** @} */ + +/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths + * @{ */ +#define BLE_GATTS_FIX_ATTR_LEN_MAX (510) /**< Maximum length for fixed length Attribute Values. */ +#define BLE_GATTS_VAR_ATTR_LEN_MAX (512) /**< Maximum length for variable length Attribute Values. */ +/** @} */ + +/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types + * @{ */ +#define BLE_GATTS_SRVC_TYPE_INVALID 0x00 /**< Invalid Service Type. */ +#define BLE_GATTS_SRVC_TYPE_PRIMARY 0x01 /**< Primary Service. */ +#define BLE_GATTS_SRVC_TYPE_SECONDARY 0x02 /**< Secondary Type. */ +/** @} */ + + +/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types + * @{ */ +#define BLE_GATTS_ATTR_TYPE_INVALID 0x00 /**< Invalid Attribute Type. */ +#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL 0x01 /**< Primary Service Declaration. */ +#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL 0x02 /**< Secondary Service Declaration. */ +#define BLE_GATTS_ATTR_TYPE_INC_DECL 0x03 /**< Include Declaration. */ +#define BLE_GATTS_ATTR_TYPE_CHAR_DECL 0x04 /**< Characteristic Declaration. */ +#define BLE_GATTS_ATTR_TYPE_CHAR_VAL 0x05 /**< Characteristic Value. */ +#define BLE_GATTS_ATTR_TYPE_DESC 0x06 /**< Descriptor. */ +#define BLE_GATTS_ATTR_TYPE_OTHER 0x07 /**< Other, non-GATT specific type. */ +/** @} */ + + +/** @defgroup BLE_GATTS_OPS GATT Server Operations + * @{ */ +#define BLE_GATTS_OP_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATTS_OP_WRITE_REQ 0x01 /**< Write Request. */ +#define BLE_GATTS_OP_WRITE_CMD 0x02 /**< Write Command. */ +#define BLE_GATTS_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ +#define BLE_GATTS_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ +#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL 0x05 /**< Execute Write Request: Cancel all prepared writes. */ +#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW 0x06 /**< Execute Write Request: Immediately execute all prepared writes. */ +/** @} */ + +/** @defgroup BLE_GATTS_VLOCS GATT Value Locations + * @{ */ +#define BLE_GATTS_VLOC_INVALID 0x00 /**< Invalid Location. */ +#define BLE_GATTS_VLOC_STACK 0x01 /**< Attribute Value is located in stack memory, no user memory is required. */ +#define BLE_GATTS_VLOC_USER 0x02 /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack + will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */ +/** @} */ + +/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types + * @{ */ +#define BLE_GATTS_AUTHORIZE_TYPE_INVALID 0x00 /**< Invalid Type. */ +#define BLE_GATTS_AUTHORIZE_TYPE_READ 0x01 /**< Authorize a Read Operation. */ +#define BLE_GATTS_AUTHORIZE_TYPE_WRITE 0x02 /**< Authorize a Write Request Operation. */ +/** @} */ + +/** @defgroup BLE_GATTS_SYS_ATTR_FLAGS System Attribute Flags + * @{ */ +#define BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS (1 << 0) /**< Restrict system attributes to system services only. */ +#define BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS (1 << 1) /**< Restrict system attributes to user services only. */ +/** @} */ + +/** @defgroup BLE_GATTS_SERVICE_CHANGED Service Changed Inclusion Values + * @{ + */ +#define BLE_GATTS_SERVICE_CHANGED_DEFAULT (1) /**< Default is to include the Service Changed characteristic in the Attribute Table. */ +/** @} */ + +/** @defgroup BLE_GATTS_ATTR_TAB_SIZE Attribute Table size + * @{ + */ +#define BLE_GATTS_ATTR_TAB_SIZE_MIN (248) /**< Minimum Attribute Table size */ +#define BLE_GATTS_ATTR_TAB_SIZE_DEFAULT (1408) /**< Default Attribute Table size. */ +/** @} */ + +/** @defgroup BLE_GATTS_DEFAULTS GATT Server defaults + * @{ + */ +#define BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT 1 /**< Default number of Handle Value Notifications that can be queued for transmission. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATTS_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATTS connection configuration parameters, set with @ref sd_ble_cfg_set. + */ +typedef struct +{ + uint8_t hvn_tx_queue_size; /**< Minimum guaranteed number of Handle Value Notifications that can be queued for transmission. + The default value is @ref BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT */ +} ble_gatts_conn_cfg_t; + +/**@brief Attribute metadata. */ +typedef struct +{ + ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vlen :1; /**< Variable length attribute. */ + uint8_t vloc :2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t rd_auth :1; /**< Read authorization and value will be requested from the application on every read operation. */ + uint8_t wr_auth :1; /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */ +} ble_gatts_attr_md_t; + + +/**@brief GATT Attribute. */ +typedef struct +{ + ble_uuid_t const *p_uuid; /**< Pointer to the attribute UUID. */ + ble_gatts_attr_md_t const *p_attr_md; /**< Pointer to the attribute metadata structure. */ + uint16_t init_len; /**< Initial attribute value length in bytes. */ + uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ + uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ + uint8_t *p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer + that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location. + The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/ +} ble_gatts_attr_t; + +/**@brief GATT Attribute Value. */ +typedef struct +{ + uint16_t len; /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/ + uint16_t offset; /**< Attribute value offset. */ + uint8_t *p_value; /**< Pointer to where value is stored or will be stored. + If value is stored in user memory, only the attribute length is updated when p_value == NULL. + Set to NULL when reading to obtain the complete length of the attribute value */ +} ble_gatts_value_t; + + +/**@brief GATT Characteristic Presentation Format. */ +typedef struct +{ + uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ + int8_t exponent; /**< Exponent for integer data types. */ + uint16_t unit; /**< Unit from Bluetooth Assigned Numbers. */ + uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ + uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ +} ble_gatts_char_pf_t; + + +/**@brief GATT Characteristic metadata. */ +typedef struct +{ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ + uint8_t const *p_char_user_desc; /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */ + uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ + uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ + ble_gatts_char_pf_t const *p_char_pf; /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */ + ble_gatts_attr_md_t const *p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ +} ble_gatts_char_md_t; + + +/**@brief GATT Characteristic Definition Handles. */ +typedef struct +{ + uint16_t value_handle; /**< Handle to the characteristic value. */ + uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ +} ble_gatts_char_handles_t; + + +/**@brief GATT HVx parameters. */ +typedef struct +{ + uint16_t handle; /**< Characteristic Value Handle. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t offset; /**< Offset within the attribute value. */ + uint16_t *p_len; /**< Length in bytes to be written, length in bytes written after return. */ + uint8_t const *p_data; /**< Actual data content, use NULL to use the current attribute value. */ +} ble_gatts_hvx_params_t; + +/**@brief GATT Authorization parameters. */ +typedef struct +{ + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint8_t update : 1; /**< If set, data supplied in p_data will be used to update the attribute value. + Please note that for @ref BLE_GATTS_AUTHORIZE_TYPE_WRITE operations this bit must always be set, + as the data to be written needs to be stored and later provided by the application. */ + uint16_t offset; /**< Offset of the attribute value being updated. */ + uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ + uint8_t const *p_data; /**< Pointer to new value used to update the attribute value. */ +} ble_gatts_authorize_params_t; + +/**@brief GATT Read or Write Authorize Reply parameters. */ +typedef struct +{ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_authorize_params_t read; /**< Read authorization parameters. */ + ble_gatts_authorize_params_t write; /**< Write authorization parameters. */ + } params; /**< Reply Parameters. */ +} ble_gatts_rw_authorize_reply_params_t; + +/**@brief Service Changed Inclusion configuration parameters, set with @ref sd_ble_cfg_set. */ +typedef struct +{ + uint8_t service_changed : 1; /**< If 1, include the Service Changed characteristic in the Attribute Table. Default is @ref BLE_GATTS_SERVICE_CHANGED_DEFAULT. */ +} ble_gatts_cfg_service_changed_t; + +/**@brief Attribute table size configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true: + * - The specified Attribute Table size is too small. + * The minimum acceptable size is defined by @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. + * - The specified Attribute Table size is not a multiple of 4. + */ +typedef struct +{ + uint32_t attr_tab_size; /**< Attribute table size. Default is @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT, minimum is @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. */ +} ble_gatts_cfg_attr_tab_size_t; + +/**@brief Config structure for GATTS configurations. */ +typedef union +{ + ble_gatts_cfg_service_changed_t service_changed; /**< Include service changed characteristic, cfg_id is @ref BLE_GATTS_CFG_SERVICE_CHANGED. */ + ble_gatts_cfg_attr_tab_size_t attr_tab_size; /**< Attribute table size, cfg_id is @ref BLE_GATTS_CFG_ATTR_TAB_SIZE. */ +} ble_gatts_cfg_t; + + +/**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ + uint8_t auth_required; /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalize the writing operation. */ + uint16_t offset; /**< Offset for the write operation. */ + uint16_t len; /**< Length of the received data. */ + uint8_t data[1]; /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gatts_evt_write_t; + +/**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint16_t offset; /**< Offset for the read operation. */ +} ble_gatts_evt_read_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */ +typedef struct +{ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ + ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ + } request; /**< Request Parameters. */ +} ble_gatts_evt_rw_authorize_request_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */ +typedef struct +{ + uint8_t hint; /**< Hint (currently unused). */ +} ble_gatts_evt_sys_attr_missing_t; + + +/**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ +} ble_gatts_evt_hvc_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST. */ +typedef struct +{ + uint16_t client_rx_mtu; /**< Client RX MTU size. */ +} ble_gatts_evt_exchange_mtu_request_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ +} ble_gatts_evt_timeout_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_HVN_TX_COMPLETE. */ +typedef struct +{ + uint8_t count; /**< Number of notification transmissions completed. */ +} ble_gatts_evt_hvn_tx_complete_t; + +/**@brief GATTS event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which the event occurred. */ + union + { + ble_gatts_evt_write_t write; /**< Write Event Parameters. */ + ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ + ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ + ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ + ble_gatts_evt_exchange_mtu_request_t exchange_mtu_request; /**< Exchange MTU Request Event Parameters. */ + ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ + ble_gatts_evt_hvn_tx_complete_t hvn_tx_complete; /**< Handle Value Notification transmission complete Event Parameters. */ + } params; /**< Event Parameters. */ +} ble_gatts_evt_t; + +/** @} */ + +/** @addtogroup BLE_GATTS_FUNCTIONS Functions + * @{ */ + +/**@brief Add a service declaration to the Attribute Table. + * + * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to + * add a secondary service declaration that is not referenced by another service later in the Attribute Table. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] type Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES. + * @param[in] p_uuid Pointer to service UUID. + * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a service declaration. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle)); + + +/**@brief Add an include declaration to the Attribute Table. + * + * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential population is supported at this time). + * + * @note The included service must already be present in the Attribute Table prior to this call. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] service_handle Handle of the service where the included service is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] inc_srvc_handle Handle of the included service. + * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added an include declaration. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required. + * @retval ::NRF_ERROR_NOT_SUPPORTED Feature is not supported, service_handle must be that of the last added service. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + */ +SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle)); + + +/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table. + * + * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential population is supported at this time). + * + * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writable auxiliaries bits, + * readable (no security) and writable (selectable) CCCDs and SCCDs and valid presentation format values. + * + * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] service_handle Handle of the service where the characteristic is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] p_char_md Characteristic metadata. + * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value. + * @param[out] p_handles Pointer to the structure where the assigned handles will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a characteristic. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + */ +SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles)); + + +/**@brief Add a descriptor to the Attribute Table. + * + * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential population is supported at this time). + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] char_handle Handle of the characteristic where the descriptor is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] p_attr Pointer to the attribute structure. + * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a descriptor. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + */ +SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle)); + +/**@brief Set the value of a given attribute. + * + * @note Values other than system attributes can be set at any time, regardless of whether any active connections exist. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. Ignored if the value does not belong to a system attribute. + * @param[in] handle Attribute handle. + * @param[in,out] p_value Attribute value information. + * + * @retval ::NRF_SUCCESS Successfully set the value of the attribute. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. + */ +SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); + +/**@brief Get the value of a given attribute. + * + * @note If the attribute value is longer than the size of the supplied buffer, + * @ref ble_gatts_value_t::len will return the total attribute value length (excluding offset), + * and not the number of bytes actually returned in @ref ble_gatts_value_t::p_value. + * The application may use this information to allocate a suitable buffer size. + * + * @note When retrieving system attribute values with this function, the connection handle + * may refer to an already disconnected connection. Refer to the documentation of + * @ref sd_ble_gatts_sys_attr_get for further information. + * + * @param[in] conn_handle Connection handle. Ignored if the value does not belong to a system attribute. + * @param[in] handle Attribute handle. + * @param[in,out] p_value Attribute value information. + * + * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid attribute offset supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + */ +SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); + +/**@brief Notify or Indicate an attribute value. + * + * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation + * (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that + * the application can atomically perform a value update and a server initiated transaction with a single API call. + * + * @note The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution. + * The Attribute Table has been updated if one of the following error codes is returned: @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY, + * @ref NRF_ERROR_FORBIDDEN, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and @ref NRF_ERROR_RESOURCES. + * The caller can check whether the value has been updated by looking at the contents of *(@ref ble_gatts_hvx_params_t::p_len). + * + * @note Only one indication procedure can be ongoing per connection at a time. + * If the application tries to indicate an attribute value while another indication procedure is ongoing, + * the function call will return @ref NRF_ERROR_BUSY. + * A @ref BLE_GATTS_EVT_HVC event will be issued as soon as the confirmation arrives from the peer. + * + * @note The number of Handle Value Notifications that can be queued is configured by @ref ble_gatts_conn_cfg_t::hvn_tx_queue_size + * When the queue is full, the function call will return @ref NRF_ERROR_RESOURCES. + * A @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event will be issued as soon as the transmission of the notification is complete. + * + * @note The application can keep track of the available queue element count for notifications by following the procedure below: + * - Store initial queue element count in a variable. + * - Decrement the variable, which stores the currently available queue element count, by one when a call to this function returns @ref NRF_SUCCESS. + * - Increment the variable, which stores the current available queue element count, by the count variable in @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event. + * + * @events + * @event{@ref BLE_GATTS_EVT_HVN_TX_COMPLETE, Notification transmission complete.} + * @event{@ref BLE_GATTS_EVT_HVC, Confirmation received from the peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC} + * @mmsc{@ref BLE_GATTS_HVN_MSC} + * @mmsc{@ref BLE_GATTS_HVI_MSC} + * @mmsc{@ref BLE_GATTS_HVX_DISABLED_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in,out] p_hvx_params Pointer to an HVx parameters structure. If @ref ble_gatts_hvx_params_t::p_data + * contains a non-NULL pointer the attribute value will be updated with the contents + * pointed by it before sending the notification or indication. If the attribute value + * is updated, @ref ble_gatts_hvx_params_t::p_len is updated by the SoftDevice to + * contain the number of actual bytes written, else it will be set to 0. + * + * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true: + * - Invalid Connection State + * - Notifications and/or indications not enabled in the CCCD + * - An ATT_MTU exchange is ongoing + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate. + * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_FORBIDDEN The connection's current security level is lower than the one required by the write permissions of the CCCD associated with this characteristic. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_BUSY For @ref BLE_GATT_HVX_INDICATION Procedure already in progress. Wait for a @ref BLE_GATTS_EVT_HVC event and retry. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + * @retval ::NRF_ERROR_RESOURCES Too many notifications queued. + * Wait for a @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event and retry. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params)); + +/**@brief Indicate the Service Changed attribute value. + * + * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the Attribute + * Table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will + * be issued. + * + * @note Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here. + * + * @events + * @event{@ref BLE_GATTS_EVT_SC_CONFIRM, Confirmation of attribute table change received from peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTS_SC_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] start_handle Start of affected attribute handle range. + * @param[in] end_handle End of affected attribute handle range. + * + * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_NOT_SUPPORTED Service Changed not enabled at initialization. See @ref + * sd_ble_cfg_set and @ref ble_gatts_cfg_service_changed_t. + * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true: + * - Invalid Connection State + * - Notifications and/or indications not enabled in the CCCD + * - An ATT_MTU exchange is ongoing + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application. + * @retval ::NRF_ERROR_BUSY Procedure already in progress. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle)); + +/**@brief Respond to a Read/Write authorization request. + * + * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_READ_REQ_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_WRITE_REQ_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_PEER_CANCEL_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application. + * + * @note @ref ble_gatts_authorize_params_t::p_data is ignored when this function is used to respond + * to a @ref BLE_GATTS_AUTHORIZE_TYPE_READ event if @ref ble_gatts_authorize_params_t::update + * is set to 0. + * + * @retval ::NRF_SUCCESS Successfully queued a response to the peer, and in the case of a write operation, Attribute Table updated. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no authorization request pending. + * @retval ::NRF_ERROR_INVALID_PARAM Authorization op invalid, + * handle supplied does not match requested handle, + * or invalid data to be written provided by the application. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params)); + + +/**@brief Update persistent system attribute information. + * + * @details Supply information about persistent system attributes to the stack, + * previously obtained using @ref sd_ble_gatts_sys_attr_get. + * This call is only allowed for active connections, and is usually + * made immediately after a connection is established with an known bonded device, + * often as a response to a @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. + * + * p_sysattrs may point directly to the application's stored copy of the system attributes + * obtained using @ref sd_ble_gatts_sys_attr_get. + * If the pointer is NULL, the system attribute info is initialized, assuming that + * the application does not have any previously saved system attribute data for this device. + * + * @note The state of persistent system attributes is reset upon connection establishment and then remembered for its duration. + * + * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially. + * This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or + * reset the SoftDevice to return to a known state. + * + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be modified. + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be modified. + * + * @mscs + * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC} + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC} + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_sys_attr_data Pointer to a saved copy of system attributes supplied to the stack, or NULL. + * @param[in] len Size of data pointed by p_sys_attr_data, in octets. + * @param[in] flags Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS + * + * @retval ::NRF_SUCCESS Successfully set the system attribute information. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied. + * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags)); + + +/**@brief Retrieve persistent system attribute information from the stack. + * + * @details This call is used to retrieve information about values to be stored persistently by the application + * during the lifetime of a connection or after it has been terminated. When a new connection is established with the same bonded device, + * the system attribute information retrieved with this function should be restored using using @ref sd_ble_gatts_sys_attr_set. + * If retrieved after disconnection, the data should be read before a new connection established. The connection handle for + * the previous, now disconnected, connection will remain valid until a new one is created to allow this API call to refer to it. + * Connection handles belonging to active connections can be used as well, but care should be taken since the system attributes + * may be written to at any time by the peer during a connection's lifetime. + * + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be returned. + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be returned. + * + * @mscs + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle of the recently terminated connection. + * @param[out] p_sys_attr_data Pointer to a buffer where updated information about system attributes will be filled in. The format of the data is described + * in @ref BLE_GATTS_SYS_ATTRS_FORMAT. NULL can be provided to obtain the length of the data. + * @param[in,out] p_len Size of application buffer if p_sys_attr_data is not NULL. Unconditionally updated to actual length of system attribute data. + * @param[in] flags Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS + * + * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied. + * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer. + * @retval ::NRF_ERROR_NOT_FOUND No system attributes found. + */ +SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags)); + + +/**@brief Retrieve the first valid user attribute handle. + * + * @param[out] p_handle Pointer to an integer where the handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully retrieved the handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle)); + +/**@brief Retrieve the attribute UUID and/or metadata. + * + * @param[in] handle Attribute handle + * @param[out] p_uuid UUID of the attribute. Use NULL to omit this field. + * @param[out] p_md Metadata of the attribute. Use NULL to omit this field. + * + * @retval ::NRF_SUCCESS Successfully retrieved the attribute metadata, + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. Returned when both @c p_uuid and @c p_md are NULL. + * @retval ::NRF_ERROR_NOT_FOUND Attribute was not found. + */ +SVCALL(SD_BLE_GATTS_ATTR_GET, uint32_t, sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md)); + +/**@brief Reply to an ATT_MTU exchange request by sending an Exchange MTU Response to the client. + * + * @details This function is only used to reply to a @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST event. + * + * @details The SoftDevice sets ATT_MTU to the minimum of: + * - The Client RX MTU value from @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, and + * - The Server RX MTU value. + * + * However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_ATT_MTU_DEFAULT. + * + * @mscs + * @mmsc{@ref BLE_GATTS_MTU_EXCHANGE} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] server_rx_mtu Server RX MTU size. + * - The minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + * - The maximum value is @ref ble_gatt_conn_cfg_t::att_mtu in the connection configuration + * used for this connection. + * - The value must be equal to Client RX MTU size given in @ref sd_ble_gattc_exchange_mtu_request + * if an ATT_MTU exchange has already been performed in the other direction. + * + * @retval ::NRF_SUCCESS Successfully sent response to the client. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no ATT_MTU exchange request pending. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid Server RX MTU size supplied. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_EXCHANGE_MTU_REPLY, uint32_t, sd_ble_gatts_exchange_mtu_reply(uint16_t conn_handle, uint16_t server_rx_mtu)); +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GATTS_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_hci.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_hci.h new file mode 100755 index 0000000..f0dde9a --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_hci.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ +*/ + + +#ifndef BLE_HCI_H__ +#define BLE_HCI_H__ +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes + * @{ */ + +#define BLE_HCI_STATUS_CODE_SUCCESS 0x00 /**< Success. */ +#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND 0x01 /**< Unknown BLE Command. */ +#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER 0x02 /**< Unknown Connection Identifier. */ +/*0x03 Hardware Failure +0x04 Page Timeout +*/ +#define BLE_HCI_AUTHENTICATION_FAILURE 0x05 /**< Authentication Failure. */ +#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING 0x06 /**< Pin or Key missing. */ +#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED 0x07 /**< Memory Capacity Exceeded. */ +#define BLE_HCI_CONNECTION_TIMEOUT 0x08 /**< Connection Timeout. */ +/*0x09 Connection Limit Exceeded +0x0A Synchronous Connection Limit To A Device Exceeded +0x0B ACL Connection Already Exists*/ +#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED 0x0C /**< Command Disallowed. */ +/*0x0D Connection Rejected due to Limited Resources +0x0E Connection Rejected Due To Security Reasons +0x0F Connection Rejected due to Unacceptable BD_ADDR +0x10 Connection Accept Timeout Exceeded +0x11 Unsupported Feature or Parameter Value*/ +#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12 /**< Invalid BLE Command Parameters. */ +#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION 0x13 /**< Remote User Terminated Connection. */ +#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14 /**< Remote Device Terminated Connection due to low resources.*/ +#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF 0x15 /**< Remote Device Terminated Connection due to power off. */ +#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION 0x16 /**< Local Host Terminated Connection. */ +/* +0x17 Repeated Attempts +0x18 Pairing Not Allowed +0x19 Unknown LMP PDU +*/ +#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A /**< Unsupported Remote Feature. */ +/* +0x1B SCO Offset Rejected +0x1C SCO Interval Rejected +0x1D SCO Air Mode Rejected*/ +#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS 0x1E /**< Invalid LMP Parameters. */ +#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR 0x1F /**< Unspecified Error. */ +/*0x20 Unsupported LMP Parameter Value +0x21 Role Change Not Allowed +*/ +#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT 0x22 /**< LMP Response Timeout. */ +#define BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION 0x23 /**< LMP Error Transaction Collision/LL Procedure Collision. */ +#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED 0x24 /**< LMP PDU Not Allowed. */ +/*0x25 Encryption Mode Not Acceptable +0x26 Link Key Can Not be Changed +0x27 Requested QoS Not Supported +*/ +#define BLE_HCI_INSTANT_PASSED 0x28 /**< Instant Passed. */ +#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED 0x29 /**< Pairing with Unit Key Unsupported. */ +#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION 0x2A /**< Different Transaction Collision. */ +/* +0x2B Reserved +0x2C QoS Unacceptable Parameter +0x2D QoS Rejected +0x2E Channel Classification Not Supported +0x2F Insufficient Security +*/ +#define BLE_HCI_PARAMETER_OUT_OF_MANDATORY_RANGE 0x30 /**< Parameter Out Of Mandatory Range. */ +/* +0x31 Reserved +0x32 Role Switch Pending +0x33 Reserved +0x34 Reserved Slot Violation +0x35 Role Switch Failed +0x36 Extended Inquiry Response Too Large +0x37 Secure Simple Pairing Not Supported By Host. +0x38 Host Busy - Pairing +0x39 Connection Rejected due to No Suitable Channel Found*/ +#define BLE_HCI_CONTROLLER_BUSY 0x3A /**< Controller Busy. */ +#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE 0x3B /**< Connection Interval Unacceptable. */ +#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT 0x3C /**< Directed Advertisement Timeout. */ +#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE 0x3D /**< Connection Terminated due to MIC Failure. */ +#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED 0x3E /**< Connection Failed to be Established. */ + +/** @} */ + + +#ifdef __cplusplus +} +#endif +#endif // BLE_HCI_H__ + +/** @} */ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_l2cap.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_l2cap.h new file mode 100755 index 0000000..edaf664 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_l2cap.h @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP) + @{ + @brief Definitions and prototypes for the L2CAP interface. + */ + +#ifndef BLE_L2CAP_H__ +#define BLE_L2CAP_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup BLE_L2CAP_TERMINOLOGY Terminology + * @{ + * @details + * + * L2CAP SDU + * - A data unit that the application can send/receive to/from a peer. + * + * L2CAP PDU + * - A data unit that is exchanged between local and remote L2CAP entities. + * It consists of L2CAP protocol control information and payload fields. + * The payload field can contain an L2CAP SDU or a part of an L2CAP SDU. + * + * L2CAP MTU + * - The maximum length of an L2CAP SDU. + * + * L2CAP MPS + * - The maximum length of an L2CAP PDU payload field. + * + * Credits + * - A value indicating the number of L2CAP PDUs that the receiver of the credit can send to the peer. + * @} */ + +/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations + * @{ */ + +/**@brief L2CAP API SVC numbers. */ +enum BLE_L2CAP_SVCS +{ + SD_BLE_L2CAP_CH_SETUP = BLE_L2CAP_SVC_BASE + 0, /**< Set up an L2CAP channel. */ + SD_BLE_L2CAP_CH_RELEASE = BLE_L2CAP_SVC_BASE + 1, /**< Release an L2CAP channel. */ + SD_BLE_L2CAP_CH_RX = BLE_L2CAP_SVC_BASE + 2, /**< Receive an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_TX = BLE_L2CAP_SVC_BASE + 3, /**< Transmit an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_FLOW_CONTROL = BLE_L2CAP_SVC_BASE + 4, /**< Advanced SDU reception flow control. */ +}; + +/**@brief L2CAP Event IDs. */ +enum BLE_L2CAP_EVTS +{ + BLE_L2CAP_EVT_CH_SETUP_REQUEST = BLE_L2CAP_EVT_BASE + 0, /**< L2CAP Channel Setup Request event. + \n See @ref ble_l2cap_evt_ch_setup_request_t. */ + BLE_L2CAP_EVT_CH_SETUP_REFUSED = BLE_L2CAP_EVT_BASE + 1, /**< L2CAP Channel Setup Refused event. + \n See @ref ble_l2cap_evt_ch_setup_refused_t. */ + BLE_L2CAP_EVT_CH_SETUP = BLE_L2CAP_EVT_BASE + 2, /**< L2CAP Channel Setup Completed event. + \n See @ref ble_l2cap_evt_ch_setup_t. */ + BLE_L2CAP_EVT_CH_RELEASED = BLE_L2CAP_EVT_BASE + 3, /**< L2CAP Channel Released event. + \n No additional event structure applies. */ + BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED = BLE_L2CAP_EVT_BASE + 4, /**< L2CAP Channel SDU data buffer released event. + \n See @ref ble_l2cap_evt_ch_sdu_buf_released_t. */ + BLE_L2CAP_EVT_CH_CREDIT = BLE_L2CAP_EVT_BASE + 5, /**< L2CAP Channel Credit received. + \n See @ref ble_l2cap_evt_ch_credit_t. */ + BLE_L2CAP_EVT_CH_RX = BLE_L2CAP_EVT_BASE + 6, /**< L2CAP Channel SDU received. + \n See @ref ble_l2cap_evt_ch_rx_t. */ + BLE_L2CAP_EVT_CH_TX = BLE_L2CAP_EVT_BASE + 7, /**< L2CAP Channel SDU transmitted. + \n See @ref ble_l2cap_evt_ch_tx_t. */ +}; + +/** @} */ + +/**@addtogroup BLE_L2CAP_DEFINES Defines + * @{ */ + +/**@brief Maximum number of L2CAP channels per connection. */ +#define BLE_L2CAP_CH_COUNT_MAX (64) + +/**@brief Minimum L2CAP MTU, in bytes. */ +#define BLE_L2CAP_MTU_MIN (23) + +/**@brief Minimum L2CAP MPS, in bytes. */ +#define BLE_L2CAP_MPS_MIN (23) + +/**@brief Invalid CID. */ +#define BLE_L2CAP_CID_INVALID (0x0000) + +/**@brief Default number of credits for @ref sd_ble_l2cap_ch_flow_control. */ +#define BLE_L2CAP_CREDITS_DEFAULT (1) + +/**@defgroup BLE_L2CAP_CH_SETUP_REFUSED_SRCS L2CAP channel setup refused sources + * @{ */ +#define BLE_L2CAP_CH_SETUP_REFUSED_SRC_LOCAL (0x01) /**< Local. */ +#define BLE_L2CAP_CH_SETUP_REFUSED_SRC_REMOTE (0x02) /**< Remote. */ + /** @} */ + + /** @defgroup BLE_L2CAP_CH_STATUS_CODES L2CAP channel status codes + * @{ */ +#define BLE_L2CAP_CH_STATUS_CODE_SUCCESS (0x0000) /**< Success. */ +#define BLE_L2CAP_CH_STATUS_CODE_LE_PSM_NOT_SUPPORTED (0x0002) /**< LE_PSM not supported. */ +#define BLE_L2CAP_CH_STATUS_CODE_NO_RESOURCES (0x0004) /**< No resources available. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_AUTHENTICATION (0x0005) /**< Insufficient authentication. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_AUTHORIZATION (0x0006) /**< Insufficient authorization. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_ENC_KEY_SIZE (0x0007) /**< Insufficient encryption key size. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_ENC (0x0008) /**< Insufficient encryption. */ +#define BLE_L2CAP_CH_STATUS_CODE_INVALID_SCID (0x0009) /**< Invalid Source CID. */ +#define BLE_L2CAP_CH_STATUS_CODE_SCID_ALLOCATED (0x000A) /**< Source CID already allocated. */ +#define BLE_L2CAP_CH_STATUS_CODE_UNACCEPTABLE_PARAMS (0x000B) /**< Unacceptable parameters. */ +#define BLE_L2CAP_CH_STATUS_CODE_NOT_UNDERSTOOD (0x8000) /**< Command Reject received instead of LE Credit Based Connection Response. */ +#define BLE_L2CAP_CH_STATUS_CODE_TIMEOUT (0xC000) /**< Operation timed out. */ +/** @} */ + +/** @} */ + +/**@addtogroup BLE_L2CAP_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE L2CAP connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @note These parameters are set per connection, so all L2CAP channels created on this connection + * will have the same parameters. + * + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - rx_mps is smaller than @ref BLE_L2CAP_MPS_MIN. + * - tx_mps is smaller than @ref BLE_L2CAP_MPS_MIN. + * - ch_count is greater than @ref BLE_L2CAP_CH_COUNT_MAX. + * @retval ::NRF_ERROR_NO_MEM rx_mps or tx_mps is set too high. + */ +typedef struct +{ + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + be able to receive on L2CAP channels on connections with this + configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + be able to transmit on L2CAP channels on connections with this + configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ + uint8_t rx_queue_size; /**< Number of SDU data buffers that can be queued for reception per + L2CAP channel. The minimum value is one. */ + uint8_t tx_queue_size; /**< Number of SDU data buffers that can be queued for transmission + per L2CAP channel. The minimum value is one. */ + uint8_t ch_count; /**< Number of L2CAP channels the application can create per connection + with this configuration. The default value is zero, the maximum + value is @ref BLE_L2CAP_CH_COUNT_MAX. + @note if this parameter is set to zero, all other parameters in + @ref ble_l2cap_conn_cfg_t are ignored. */ +} ble_l2cap_conn_cfg_t; + +/**@brief L2CAP channel RX parameters. */ +typedef struct +{ + uint16_t rx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP shall be able to + receive on this L2CAP channel. + - Must be equal to or greater than @ref BLE_L2CAP_MTU_MIN. */ + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be + able to receive on this L2CAP channel. + - Must be equal to or greater than @ref BLE_L2CAP_MPS_MIN. + - Must be equal to or less than @ref ble_l2cap_conn_cfg_t::rx_mps. */ + ble_data_t sdu_buf; /**< SDU data buffer for reception. + - If @ref ble_data_t::p_data is non-NULL, initial credits are + issued to the peer. + - If @ref ble_data_t::p_data is NULL, no initial credits are + issued to the peer. */ +} ble_l2cap_ch_rx_params_t; + +/**@brief L2CAP channel setup parameters. */ +typedef struct +{ + ble_l2cap_ch_rx_params_t rx_params; /**< L2CAP channel RX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. Used when requesting + setup of an L2CAP channel, ignored otherwise. */ + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES. + Used when replying to a setup request of an L2CAP + channel, ignored otherwise. */ +} ble_l2cap_ch_setup_params_t; + +/**@brief L2CAP channel TX parameters. */ +typedef struct +{ + uint16_t tx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP is able to + transmit on this L2CAP channel. */ + uint16_t peer_mps; /**< The maximum L2CAP PDU payload size, in bytes, that the peer is + able to receive on this L2CAP channel. */ + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP is able + to transmit on this L2CAP channel. This is effective tx_mps, + selected by the SoftDevice as + MIN( @ref ble_l2cap_ch_tx_params_t::peer_mps, @ref ble_l2cap_conn_cfg_t::tx_mps ) */ + uint16_t credits; /**< Initial credits given by the peer. */ +} ble_l2cap_ch_tx_params_t; + +/**@brief L2CAP Channel Setup Request event. */ +typedef struct +{ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. */ +} ble_l2cap_evt_ch_setup_request_t; + +/**@brief L2CAP Channel Setup Refused event. */ +typedef struct +{ + uint8_t source; /**< Source, see @ref BLE_L2CAP_CH_SETUP_REFUSED_SRCS */ + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES */ +} ble_l2cap_evt_ch_setup_refused_t; + +/**@brief L2CAP Channel Setup Completed event. */ +typedef struct +{ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ +} ble_l2cap_evt_ch_setup_t; + +/**@brief L2CAP Channel SDU Data Buffer Released event. */ +typedef struct +{ + ble_data_t sdu_buf; /**< Returned reception or transmission SDU data buffer. The SoftDevice + returns SDU data buffers supplied by the application, which have + not yet been returned previously via a @ref BLE_L2CAP_EVT_CH_RX or + @ref BLE_L2CAP_EVT_CH_TX event. */ +} ble_l2cap_evt_ch_sdu_buf_released_t; + +/**@brief L2CAP Channel Credit received event. */ +typedef struct +{ + uint16_t credits; /**< Additional credits given by the peer. */ +} ble_l2cap_evt_ch_credit_t; + +/**@brief L2CAP Channel received SDU event. */ +typedef struct +{ + uint16_t sdu_len; /**< Total SDU length, in bytes. */ + ble_data_t sdu_buf; /**< SDU data buffer. + @note If there is not enough space in the buffer + (sdu_buf.len < sdu_len) then the rest of the SDU will be + silently discarded by the SoftDevice. */ +} ble_l2cap_evt_ch_rx_t; + +/**@brief L2CAP Channel transmitted SDU event. */ +typedef struct +{ + ble_data_t sdu_buf; /**< SDU data buffer. */ +} ble_l2cap_evt_ch_tx_t; + +/**@brief L2CAP event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which the event occured. */ + uint16_t local_cid; /**< Local Channel ID of the L2CAP channel, or + @ref BLE_L2CAP_CID_INVALID if not present. */ + union + { + ble_l2cap_evt_ch_setup_request_t ch_setup_request; /**< L2CAP Channel Setup Request Event Parameters. */ + ble_l2cap_evt_ch_setup_refused_t ch_setup_refused; /**< L2CAP Channel Setup Refused Event Parameters. */ + ble_l2cap_evt_ch_setup_t ch_setup; /**< L2CAP Channel Setup Completed Event Parameters. */ + ble_l2cap_evt_ch_sdu_buf_released_t ch_sdu_buf_released;/**< L2CAP Channel SDU Data Buffer Released Event Parameters. */ + ble_l2cap_evt_ch_credit_t credit; /**< L2CAP Channel Credit Received Event Parameters. */ + ble_l2cap_evt_ch_rx_t rx; /**< L2CAP Channel SDU Received Event Parameters. */ + ble_l2cap_evt_ch_tx_t tx; /**< L2CAP Channel SDU Transmitted Event Parameters. */ + } params; /**< Event Parameters. */ +} ble_l2cap_evt_t; + +/** @} */ + +/**@addtogroup BLE_L2CAP_FUNCTIONS Functions + * @{ */ + +/**@brief Set up an L2CAP channel. + * + * @details This function is used to: + * - Request setup of an L2CAP channel: sends an LE Credit Based Connection Request packet to a peer. + * - Reply to a setup request of an L2CAP channel (if called in response to a + * @ref BLE_L2CAP_EVT_CH_SETUP_REQUEST event): sends an LE Credit Based Connection + * Response packet to a peer. + * + * @note A call to this function will require the application to keep the SDU data buffer alive + * until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_RX or + * @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_SETUP, Setup successful.} + * @event{@ref BLE_L2CAP_EVT_CH_SETUP_REFUSED, Setup failed.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_SETUP_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in,out] p_local_cid Pointer to a uint16_t containing Local Channel ID of the L2CAP channel: + * - As input: @ref BLE_L2CAP_CID_INVALID when requesting setup of an L2CAP + * channel or local_cid provided in the @ref BLE_L2CAP_EVT_CH_SETUP_REQUEST + * event when replying to a setup request of an L2CAP channel. + * - As output: local_cid for this channel. + * @param[in] p_params L2CAP channel parameters. + * + * @retval ::NRF_SUCCESS Successfully queued request or response for transmission. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_LENGTH Supplied higher rx_mps than has been configured on this link. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (L2CAP channel already set up). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_RESOURCES The limit has been reached for available L2CAP channels, + * see @ref ble_l2cap_conn_cfg_t::ch_count. + */ +SVCALL(SD_BLE_L2CAP_CH_SETUP, uint32_t, sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t *p_local_cid, ble_l2cap_ch_setup_params_t const *p_params)); + +/**@brief Release an L2CAP channel. + * + * @details This sends a Disconnection Request packet to a peer. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_RELEASED, Release complete.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_RELEASE_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * + * @retval ::NRF_SUCCESS Successfully queued request for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for the L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + */ +SVCALL(SD_BLE_L2CAP_CH_RELEASE, uint32_t, sd_ble_l2cap_ch_release(uint16_t conn_handle, uint16_t local_cid)); + +/**@brief Receive an SDU on an L2CAP channel. + * + * @details This may issue additional credits to the peer using an LE Flow Control Credit packet. + * + * @note A call to this function will require the application to keep the memory pointed by + * @ref ble_data_t::p_data alive until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_RX + * or @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @note The SoftDevice can queue up to @ref ble_l2cap_conn_cfg_t::rx_queue_size SDU data buffers + * for reception per L2CAP channel. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_RX, The SDU is received.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_RX_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * @param[in] p_sdu_buf Pointer to the SDU data buffer. + * + * @retval ::NRF_SUCCESS Buffer accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for an L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_RESOURCES Too many SDU data buffers supplied. Wait for a + * @ref BLE_L2CAP_EVT_CH_RX event and retry. + */ +SVCALL(SD_BLE_L2CAP_CH_RX, uint32_t, sd_ble_l2cap_ch_rx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf)); + +/**@brief Transmit an SDU on an L2CAP channel. + * + * @note A call to this function will require the application to keep the memory pointed by + * @ref ble_data_t::p_data alive until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_TX + * or @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @note The SoftDevice can queue up to @ref ble_l2cap_conn_cfg_t::tx_queue_size SDUs for + * transmission per L2CAP channel. + * + * @note The application can keep track of the available credits for transmission by following + * the procedure below: + * - Store initial credits given by the peer in a variable. + * (Initial credits are provided in a @ref BLE_L2CAP_EVT_CH_SETUP event.) + * - Decrement the variable, which stores the currently available credits, by + * ceiling((@ref ble_data_t::len + 2) / tx_mps) when a call to this function returns + * @ref NRF_SUCCESS. (tx_mps is provided in a @ref BLE_L2CAP_EVT_CH_SETUP event.) + * - Increment the variable, which stores the currently available credits, by additional + * credits given by the peer in a @ref BLE_L2CAP_EVT_CH_CREDIT event. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_TX, The SDU is transmitted.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_TX_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * @param[in] p_sdu_buf Pointer to the SDU data buffer. + * + * @retval ::NRF_SUCCESS Successfully queued L2CAP SDU for transmission. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for the L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_DATA_SIZE Invalid SDU length supplied, must not be more than + * @ref ble_l2cap_ch_tx_params_t::tx_mtu provided in + * @ref BLE_L2CAP_EVT_CH_SETUP event. + * @retval ::NRF_ERROR_RESOURCES Too many SDUs queued for transmission. Wait for a + * @ref BLE_L2CAP_EVT_CH_TX event and retry. + */ +SVCALL(SD_BLE_L2CAP_CH_TX, uint32_t, sd_ble_l2cap_ch_tx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf)); + +/**@brief Advanced SDU reception flow control. + * + * @details Adjust the way the SoftDevice issues credits to the peer. + * This may issue additional credits to the peer using an LE Flow Control Credit packet. + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_FLOW_CONTROL_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel or @ref BLE_L2CAP_CID_INVALID to set + * the value that will be used for newly created channels. + * @param[in] credits Number of credits that the SoftDevice will make sure the peer has every + * time it starts using a new reception buffer. + * - @ref BLE_L2CAP_CREDITS_DEFAULT is the default value the SoftDevice will + * use if this function is not called. + * - If set to zero, the SoftDevice will stop issuing credits for new reception + * buffers the application provides or has provided. SDU reception that is + * currently ongoing will be allowed to complete. + * @param[out] p_credits NULL or pointer to a uint16_t. If a valid pointer is provided, it will be + * written by the SoftDevice with the number of credits that is or will be + * available to the peer. If the value written by the SoftDevice is 0 when + * credits parameter was set to 0, the peer will not be able to send more + * data until more credits are provided by calling this function again with + * credits > 0. This parameter is ignored when local_cid is set to + * @ref BLE_L2CAP_CID_INVALID. + * + * @note Application should take care when setting number of credits higher than default value. In + * this case the application must make sure that the SoftDevice always has reception buffers + * available (see @ref sd_ble_l2cap_ch_rx) for that channel. If the SoftDevice does not have + * such buffers available, packets may be NACKed on the Link Layer and all Bluetooth traffic + * on the connection handle may be stalled until the SoftDevice again has an available + * reception buffer. This applies even if the application has used this call to set the + * credits back to default, or zero. + * + * @retval ::NRF_SUCCESS Flow control parameters accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for an L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + */ +SVCALL(SD_BLE_L2CAP_CH_FLOW_CONTROL, uint32_t, sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t *p_credits)); + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_L2CAP_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_ranges.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_ranges.h new file mode 100755 index 0000000..0935bca --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_ranges.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @defgroup ble_ranges Module specific SVC, event and option number subranges + @{ + + @brief Definition of SVC, event and option number subranges for each API module. + + @note + SVCs, event and option numbers are split into subranges for each API module. + Each module receives its entire allocated range of SVC calls, whether implemented or not, + but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range. + + Note that the symbols BLE_<module>_SVC_LAST is the end of the allocated SVC range, + rather than the last SVC function call actually defined and implemented. + + Specific SVC, event and option values are defined in each module's ble_<module>.h file, + which defines names of each individual SVC code based on the range start value. +*/ + +#ifndef BLE_RANGES_H__ +#define BLE_RANGES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BLE_SVC_BASE 0x60 /**< Common BLE SVC base. */ +#define BLE_SVC_LAST 0x6B /**< Common BLE SVC last. */ + +#define BLE_GAP_SVC_BASE 0x6C /**< GAP BLE SVC base. */ +#define BLE_GAP_SVC_LAST 0x9A /**< GAP BLE SVC last. */ + +#define BLE_GATTC_SVC_BASE 0x9B /**< GATTC BLE SVC base. */ +#define BLE_GATTC_SVC_LAST 0xA7 /**< GATTC BLE SVC last. */ + +#define BLE_GATTS_SVC_BASE 0xA8 /**< GATTS BLE SVC base. */ +#define BLE_GATTS_SVC_LAST 0xB7 /**< GATTS BLE SVC last. */ + +#define BLE_L2CAP_SVC_BASE 0xB8 /**< L2CAP BLE SVC base. */ +#define BLE_L2CAP_SVC_LAST 0xBF /**< L2CAP BLE SVC last. */ + + +#define BLE_EVT_INVALID 0x00 /**< Invalid BLE Event. */ + +#define BLE_EVT_BASE 0x01 /**< Common BLE Event base. */ +#define BLE_EVT_LAST 0x0F /**< Common BLE Event last. */ + +#define BLE_GAP_EVT_BASE 0x10 /**< GAP BLE Event base. */ +#define BLE_GAP_EVT_LAST 0x2F /**< GAP BLE Event last. */ + +#define BLE_GATTC_EVT_BASE 0x30 /**< GATTC BLE Event base. */ +#define BLE_GATTC_EVT_LAST 0x4F /**< GATTC BLE Event last. */ + +#define BLE_GATTS_EVT_BASE 0x50 /**< GATTS BLE Event base. */ +#define BLE_GATTS_EVT_LAST 0x6F /**< GATTS BLE Event last. */ + +#define BLE_L2CAP_EVT_BASE 0x70 /**< L2CAP BLE Event base. */ +#define BLE_L2CAP_EVT_LAST 0x8F /**< L2CAP BLE Event last. */ + + +#define BLE_OPT_INVALID 0x00 /**< Invalid BLE Option. */ + +#define BLE_OPT_BASE 0x01 /**< Common BLE Option base. */ +#define BLE_OPT_LAST 0x1F /**< Common BLE Option last. */ + +#define BLE_GAP_OPT_BASE 0x20 /**< GAP BLE Option base. */ +#define BLE_GAP_OPT_LAST 0x3F /**< GAP BLE Option last. */ + +#define BLE_GATT_OPT_BASE 0x40 /**< GATT BLE Option base. */ +#define BLE_GATT_OPT_LAST 0x5F /**< GATT BLE Option last. */ + +#define BLE_GATTC_OPT_BASE 0x60 /**< GATTC BLE Option base. */ +#define BLE_GATTC_OPT_LAST 0x7F /**< GATTC BLE Option last. */ + +#define BLE_GATTS_OPT_BASE 0x80 /**< GATTS BLE Option base. */ +#define BLE_GATTS_OPT_LAST 0x9F /**< GATTS BLE Option last. */ + +#define BLE_L2CAP_OPT_BASE 0xA0 /**< L2CAP BLE Option base. */ +#define BLE_L2CAP_OPT_LAST 0xBF /**< L2CAP BLE Option last. */ + + +#define BLE_CFG_INVALID 0x00 /**< Invalid BLE configuration. */ + +#define BLE_CFG_BASE 0x01 /**< Common BLE configuration base. */ +#define BLE_CFG_LAST 0x1F /**< Common BLE configuration last. */ + +#define BLE_CONN_CFG_BASE 0x20 /**< BLE connection configuration base. */ +#define BLE_CONN_CFG_LAST 0x3F /**< BLE connection configuration last. */ + +#define BLE_GAP_CFG_BASE 0x40 /**< GAP BLE configuration base. */ +#define BLE_GAP_CFG_LAST 0x5F /**< GAP BLE configuration last. */ + +#define BLE_GATT_CFG_BASE 0x60 /**< GATT BLE configuration base. */ +#define BLE_GATT_CFG_LAST 0x7F /**< GATT BLE configuration last. */ + +#define BLE_GATTC_CFG_BASE 0x80 /**< GATTC BLE configuration base. */ +#define BLE_GATTC_CFG_LAST 0x9F /**< GATTC BLE configuration last. */ + +#define BLE_GATTS_CFG_BASE 0xA0 /**< GATTS BLE configuration base. */ +#define BLE_GATTS_CFG_LAST 0xBF /**< GATTS BLE configuration last. */ + +#define BLE_L2CAP_CFG_BASE 0xC0 /**< L2CAP BLE configuration base. */ +#define BLE_L2CAP_CFG_LAST 0xDF /**< L2CAP BLE configuration last. */ + + + + + +#ifdef __cplusplus +} +#endif +#endif /* BLE_RANGES_H__ */ + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_types.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_types.h new file mode 100755 index 0000000..88c9318 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/ble_types.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @defgroup ble_types Common types and macro definitions + @{ + + @brief Common types and macro definitions for the BLE SoftDevice. + */ + +#ifndef BLE_TYPES_H__ +#define BLE_TYPES_H__ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_TYPES_DEFINES Defines + * @{ */ + +/** @defgroup BLE_CONN_HANDLES BLE Connection Handles + * @{ */ +#define BLE_CONN_HANDLE_INVALID 0xFFFF /**< Invalid Connection Handle. */ +#define BLE_CONN_HANDLE_ALL 0xFFFE /**< Applies to all Connection Handles. */ +/** @} */ + + +/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs + * @{ */ +/* Generic UUIDs, applicable to all services */ +#define BLE_UUID_UNKNOWN 0x0000 /**< Reserved UUID. */ +#define BLE_UUID_SERVICE_PRIMARY 0x2800 /**< Primary Service. */ +#define BLE_UUID_SERVICE_SECONDARY 0x2801 /**< Secondary Service. */ +#define BLE_UUID_SERVICE_INCLUDE 0x2802 /**< Include. */ +#define BLE_UUID_CHARACTERISTIC 0x2803 /**< Characteristic. */ +#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP 0x2900 /**< Characteristic Extended Properties Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC 0x2901 /**< Characteristic User Description Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG 0x2902 /**< Client Characteristic Configuration Descriptor. */ +#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG 0x2903 /**< Server Characteristic Configuration Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT 0x2904 /**< Characteristic Presentation Format Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT 0x2905 /**< Characteristic Aggregate Format Descriptor. */ +/* GATT specific UUIDs */ +#define BLE_UUID_GATT 0x1801 /**< Generic Attribute Profile. */ +#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED 0x2A05 /**< Service Changed Characteristic. */ +/* GAP specific UUIDs */ +#define BLE_UUID_GAP 0x1800 /**< Generic Access Profile. */ +#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME 0x2A00 /**< Device Name Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE 0x2A01 /**< Appearance Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR 0x2A03 /**< Reconnection Address Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_PPCP 0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_CAR 0x2AA6 /**< Central Address Resolution Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_RPA_ONLY 0x2AC9 /**< Resolvable Private Address Only Characteristic. */ +/** @} */ + + +/** @defgroup BLE_UUID_TYPES Types of UUID + * @{ */ +#define BLE_UUID_TYPE_UNKNOWN 0x00 /**< Invalid UUID type. */ +#define BLE_UUID_TYPE_BLE 0x01 /**< Bluetooth SIG UUID (16-bit). */ +#define BLE_UUID_TYPE_VENDOR_BEGIN 0x02 /**< Vendor UUID types start at this index (128-bit). */ +/** @} */ + + +/** @defgroup BLE_APPEARANCES Bluetooth Appearance values + * @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml + * @{ */ +#define BLE_APPEARANCE_UNKNOWN 0 /**< Unknown. */ +#define BLE_APPEARANCE_GENERIC_PHONE 64 /**< Generic Phone. */ +#define BLE_APPEARANCE_GENERIC_COMPUTER 128 /**< Generic Computer. */ +#define BLE_APPEARANCE_GENERIC_WATCH 192 /**< Generic Watch. */ +#define BLE_APPEARANCE_WATCH_SPORTS_WATCH 193 /**< Watch: Sports Watch. */ +#define BLE_APPEARANCE_GENERIC_CLOCK 256 /**< Generic Clock. */ +#define BLE_APPEARANCE_GENERIC_DISPLAY 320 /**< Generic Display. */ +#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL 384 /**< Generic Remote Control. */ +#define BLE_APPEARANCE_GENERIC_EYE_GLASSES 448 /**< Generic Eye-glasses. */ +#define BLE_APPEARANCE_GENERIC_TAG 512 /**< Generic Tag. */ +#define BLE_APPEARANCE_GENERIC_KEYRING 576 /**< Generic Keyring. */ +#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER 640 /**< Generic Media Player. */ +#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER 704 /**< Generic Barcode Scanner. */ +#define BLE_APPEARANCE_GENERIC_THERMOMETER 768 /**< Generic Thermometer. */ +#define BLE_APPEARANCE_THERMOMETER_EAR 769 /**< Thermometer: Ear. */ +#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR 832 /**< Generic Heart rate Sensor. */ +#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT 833 /**< Heart Rate Sensor: Heart Rate Belt. */ +#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE 896 /**< Generic Blood Pressure. */ +#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM 897 /**< Blood Pressure: Arm. */ +#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST 898 /**< Blood Pressure: Wrist. */ +#define BLE_APPEARANCE_GENERIC_HID 960 /**< Human Interface Device (HID). */ +#define BLE_APPEARANCE_HID_KEYBOARD 961 /**< Keyboard (HID Subtype). */ +#define BLE_APPEARANCE_HID_MOUSE 962 /**< Mouse (HID Subtype). */ +#define BLE_APPEARANCE_HID_JOYSTICK 963 /**< Joystick (HID Subtype). */ +#define BLE_APPEARANCE_HID_GAMEPAD 964 /**< Gamepad (HID Subtype). */ +#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE 965 /**< Digitizer Tablet (HID Subtype). */ +#define BLE_APPEARANCE_HID_CARD_READER 966 /**< Card Reader (HID Subtype). */ +#define BLE_APPEARANCE_HID_DIGITAL_PEN 967 /**< Digital Pen (HID Subtype). */ +#define BLE_APPEARANCE_HID_BARCODE 968 /**< Barcode Scanner (HID Subtype). */ +#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER 1024 /**< Generic Glucose Meter. */ +#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR 1088 /**< Generic Running Walking Sensor. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE 1089 /**< Running Walking Sensor: In-Shoe. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE 1090 /**< Running Walking Sensor: On-Shoe. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP 1091 /**< Running Walking Sensor: On-Hip. */ +#define BLE_APPEARANCE_GENERIC_CYCLING 1152 /**< Generic Cycling. */ +#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER 1153 /**< Cycling: Cycling Computer. */ +#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR 1154 /**< Cycling: Speed Sensor. */ +#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR 1155 /**< Cycling: Cadence Sensor. */ +#define BLE_APPEARANCE_CYCLING_POWER_SENSOR 1156 /**< Cycling: Power Sensor. */ +#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR 1157 /**< Cycling: Speed and Cadence Sensor. */ +#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER 3136 /**< Generic Pulse Oximeter. */ +#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP 3137 /**< Fingertip (Pulse Oximeter subtype). */ +#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN 3138 /**< Wrist Worn(Pulse Oximeter subtype). */ +#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE 3200 /**< Generic Weight Scale. */ +#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT 5184 /**< Generic Outdoor Sports Activity. */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP 5185 /**< Location Display Device (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD 5187 /**< Location Pod (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD 5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */ +/** @} */ + +/** @brief Set .type and .uuid fields of ble_uuid_struct to specified UUID value. */ +#define BLE_UUID_BLE_ASSIGN(instance, value) do {\ + instance.type = BLE_UUID_TYPE_BLE; \ + instance.uuid = value;} while(0) + +/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */ +#define BLE_UUID_COPY_PTR(dst, src) do {\ + (dst)->type = (src)->type; \ + (dst)->uuid = (src)->uuid;} while(0) + +/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */ +#define BLE_UUID_COPY_INST(dst, src) do {\ + (dst).type = (src).type; \ + (dst).uuid = (src).uuid;} while(0) + +/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ +#define BLE_UUID_EQ(p_uuid1, p_uuid2) \ + (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) + +/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ +#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \ + (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) + +/** @} */ + +/** @addtogroup BLE_TYPES_STRUCTURES Structures + * @{ */ + +/** @brief 128 bit UUID values. */ +typedef struct +{ + uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */ +} ble_uuid128_t; + +/** @brief Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */ +typedef struct +{ + uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ + uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ +} ble_uuid_t; + +/**@brief Data structure. */ +typedef struct +{ + uint8_t *p_data; /**< Pointer to the data buffer provided to/from the application. */ + uint16_t len; /**< Length of the data buffer, in bytes. */ +} ble_data_t; + +/** @} */ +#ifdef __cplusplus +} +#endif + +#endif /* BLE_TYPES_H__ */ + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h new file mode 100755 index 0000000..389cc37 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h @@ -0,0 +1,268 @@ +/*
+ * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ * Semiconductor ASA integrated circuit in a product or a software update for
+ * such product, must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or other
+ * materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ * Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ * engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ @defgroup nrf_mbr_api Master Boot Record API
+ @{
+
+ @brief APIs for updating SoftDevice and BootLoader
+
+*/
+
+#ifndef NRF_MBR_H__
+#define NRF_MBR_H__
+
+#include "nrf_svc.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NRF_MBR_DEFINES Defines
+ * @{ */
+
+/**@brief MBR SVC Base number. */
+#define MBR_SVC_BASE (0x18)
+
+/**@brief Page size in words. */
+#define MBR_PAGE_SIZE_IN_WORDS (1024)
+
+/** @brief The size that must be reserved for the MBR when a SoftDevice is written to flash.
+This is the offset where the first byte of the SoftDevice hex file is written. */
+#define MBR_SIZE (0x1000)
+
+/** @brief Location (in the flash memory) of the bootloader address. */
+#define MBR_BOOTLOADER_ADDR (0xFF8)
+
+/** @brief Location (in UICR) of the bootloader address. */
+#define MBR_UICR_BOOTLOADER_ADDR (&(NRF_UICR->NRFFW[0]))
+
+/** @brief Location (in the flash memory) of the address of the MBR parameter page. */
+#define MBR_PARAM_PAGE_ADDR (0xFFC)
+
+/** @brief Location (in UICR) of the address of the MBR parameter page. */
+#define MBR_UICR_PARAM_PAGE_ADDR (&(NRF_UICR->NRFFW[1]))
+
+
+/** @} */
+
+/** @addtogroup NRF_MBR_ENUMS Enumerations
+ * @{ */
+
+/**@brief nRF Master Boot Record API SVC numbers. */
+enum NRF_MBR_SVCS
+{
+ SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */
+};
+
+/**@brief Possible values for ::sd_mbr_command_t.command */
+enum NRF_MBR_COMMANDS
+{
+ SD_MBR_COMMAND_COPY_BL, /**< Copy a new BootLoader. @see ::sd_mbr_command_copy_bl_t*/
+ SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/
+ SD_MBR_COMMAND_INIT_SD, /**< Initialize forwarding interrupts to SD, and run reset function in SD. Does not require any parameters in ::sd_mbr_command_t params.*/
+ SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/
+ SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Change the address the MBR starts after a reset. @see ::sd_mbr_command_vector_table_base_set_t*/
+ SD_MBR_COMMAND_RESERVED,
+ SD_MBR_COMMAND_IRQ_FORWARD_ADDRESS_SET, /**< Start forwarding all interrupts to this address. @see ::sd_mbr_command_irq_forward_address_set_t*/
+};
+
+/** @} */
+
+/** @addtogroup NRF_MBR_TYPES Types
+ * @{ */
+
+/**@brief This command copies part of a new SoftDevice
+ *
+ * The destination area is erased before copying.
+ * If dst is in the middle of a flash page, that whole flash page will be erased.
+ * If (dst+len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ * The user of this function is responsible for setting the BPROT registers.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly.
+ * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying.
+ */
+typedef struct
+{
+ uint32_t *src; /**< Pointer to the source of data to be copied.*/
+ uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/
+ uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/
+} sd_mbr_command_copy_sd_t;
+
+
+/**@brief This command works like memcmp, but takes the length in words.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal.
+ * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal.
+ */
+typedef struct
+{
+ uint32_t *ptr1; /**< Pointer to block of memory. */
+ uint32_t *ptr2; /**< Pointer to block of memory. */
+ uint32_t len; /**< Number of 32 bit words to compare.*/
+} sd_mbr_command_compare_t;
+
+
+/**@brief This command copies a new BootLoader.
+ *
+ * The MBR assumes that either @ref MBR_BOOTLOADER_ADDR or @ref MBR_UICR_BOOTLOADER_ADDR is set to
+ * the address where the bootloader will be copied. If both addresses are set, the MBR will prioritize
+ * @ref MBR_BOOTLOADER_ADDR.
+ *
+ * The bootloader destination is erased by this function.
+ * If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ * This command requires that @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR is set,
+ * see @ref sd_mbr_command.
+ *
+ * This command will use the flash protect peripheral (BPROT or ACL) to protect the flash that is
+ * not intended to be written.
+ *
+ * On success, this function will not return. It will start the new bootloader from reset-vector as normal.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_FORBIDDEN if the bootloader address is not set.
+ * @retval ::NRF_ERROR_INVALID_LENGTH if parameters attempts to read or write outside flash area.
+ * @retval ::NRF_ERROR_NO_MEM No MBR parameter page is provided. See @ref sd_mbr_command.
+ */
+typedef struct
+{
+ uint32_t *bl_src; /**< Pointer to the source of the bootloader to be be copied.*/
+ uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader. */
+} sd_mbr_command_copy_bl_t;
+
+/**@brief Change the address the MBR starts after a reset
+ *
+ * Once this function has been called, this address is where the MBR will start to forward
+ * interrupts to after a reset.
+ *
+ * To restore default forwarding, this function should be called with @ref address set to 0. If a
+ * bootloader is present, interrupts will be forwarded to the bootloader. If not, interrupts will
+ * be forwarded to the SoftDevice.
+ *
+ * The location of a bootloader can be specified in @ref MBR_BOOTLOADER_ADDR or
+ * @ref MBR_UICR_BOOTLOADER_ADDR. If both addresses are set, the MBR will prioritize
+ * @ref MBR_BOOTLOADER_ADDR.
+ *
+ * This command requires that @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR is set,
+ * see @ref sd_mbr_command.
+ *
+ * On success, this function will not return. It will reset the device.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_INVALID_ADDR if parameter address is outside of the flash size.
+ * @retval ::NRF_ERROR_NO_MEM No MBR parameter page is provided. See @ref sd_mbr_command.
+ */
+typedef struct
+{
+ uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
+} sd_mbr_command_vector_table_base_set_t;
+
+/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR
+ *
+ * Unlike sd_mbr_command_vector_table_base_set_t, this function does not reset, and it does not
+ * change where the MBR starts after reset.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+typedef struct
+{
+ uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
+} sd_mbr_command_irq_forward_address_set_t;
+
+/**@brief Input structure containing data used when calling ::sd_mbr_command
+ *
+ * Depending on what command value that is set, the corresponding params value type must also be
+ * set. See @ref NRF_MBR_COMMANDS for command types and corresponding params value type. If command
+ * @ref SD_MBR_COMMAND_INIT_SD is set, it is not necessary to set any values under params.
+ */
+typedef struct
+{
+ uint32_t command; /**< Type of command to be issued. See @ref NRF_MBR_COMMANDS. */
+ union
+ {
+ sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy SoftDevice.*/
+ sd_mbr_command_compare_t compare; /**< Parameters for verify.*/
+ sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy BootLoader. Requires parameter page. */
+ sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/
+ sd_mbr_command_irq_forward_address_set_t irq_forward_address_set; /**< Parameters for irq forward address set*/
+ } params; /**< Command parameters. */
+} sd_mbr_command_t;
+
+/** @} */
+
+/** @addtogroup NRF_MBR_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Issue Master Boot Record commands
+ *
+ * Commands used when updating a SoftDevice and bootloader.
+ *
+ * The @ref SD_MBR_COMMAND_COPY_BL and @ref SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET requires
+ * parameters to be retained by the MBR when resetting the IC. This is done in a separate flash
+ * page. The location of the flash page should be provided by the application in either
+ * @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR. If both addresses are set, the MBR
+ * will prioritize @ref MBR_PARAM_PAGE_ADDR. This page will be cleared by the MBR and is used to
+ * store the command before reset. When an address is specified, the page it refers to must not be
+ * used by the application. If no address is provided by the application, i.e. both
+ * @ref MBR_PARAM_PAGE_ADDR and @ref MBR_UICR_PARAM_PAGE_ADDR is 0xFFFFFFFF, MBR commands which use
+ * flash will be unavailable and return @ref NRF_ERROR_NO_MEM.
+ *
+ * @param[in] param Pointer to a struct describing the command.
+ *
+ * @note For a complete set of return values, see ::sd_mbr_command_copy_sd_t,
+ * ::sd_mbr_command_copy_bl_t, ::sd_mbr_command_compare_t,
+ * ::sd_mbr_command_vector_table_base_set_t, ::sd_mbr_command_irq_forward_address_set_t
+ *
+ * @retval ::NRF_ERROR_NO_MEM No MBR parameter page provided
+ * @retval ::NRF_ERROR_INVALID_PARAM if an invalid command is given.
+*/
+SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_MBR_H__
+
+/**
+ @}
+*/
diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error.h new file mode 100755 index 0000000..6badee9 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** + @defgroup nrf_error SoftDevice Global Error Codes + @{ + + @brief Global Error definitions +*/ + +/* Header guard */ +#ifndef NRF_ERROR_H__ +#define NRF_ERROR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions + * @{ */ +#define NRF_ERROR_BASE_NUM (0x0) ///< Global error base +#define NRF_ERROR_SDM_BASE_NUM (0x1000) ///< SDM error base +#define NRF_ERROR_SOC_BASE_NUM (0x2000) ///< SoC error base +#define NRF_ERROR_STK_BASE_NUM (0x3000) ///< STK error base +/** @} */ + +#define NRF_SUCCESS (NRF_ERROR_BASE_NUM + 0) ///< Successful command +#define NRF_ERROR_SVC_HANDLER_MISSING (NRF_ERROR_BASE_NUM + 1) ///< SVC handler is missing +#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED (NRF_ERROR_BASE_NUM + 2) ///< SoftDevice has not been enabled +#define NRF_ERROR_INTERNAL (NRF_ERROR_BASE_NUM + 3) ///< Internal Error +#define NRF_ERROR_NO_MEM (NRF_ERROR_BASE_NUM + 4) ///< No Memory for operation +#define NRF_ERROR_NOT_FOUND (NRF_ERROR_BASE_NUM + 5) ///< Not found +#define NRF_ERROR_NOT_SUPPORTED (NRF_ERROR_BASE_NUM + 6) ///< Not supported +#define NRF_ERROR_INVALID_PARAM (NRF_ERROR_BASE_NUM + 7) ///< Invalid Parameter +#define NRF_ERROR_INVALID_STATE (NRF_ERROR_BASE_NUM + 8) ///< Invalid state, operation disallowed in this state +#define NRF_ERROR_INVALID_LENGTH (NRF_ERROR_BASE_NUM + 9) ///< Invalid Length +#define NRF_ERROR_INVALID_FLAGS (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags +#define NRF_ERROR_INVALID_DATA (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data +#define NRF_ERROR_DATA_SIZE (NRF_ERROR_BASE_NUM + 12) ///< Invalid Data size +#define NRF_ERROR_TIMEOUT (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out +#define NRF_ERROR_NULL (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer +#define NRF_ERROR_FORBIDDEN (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation +#define NRF_ERROR_INVALID_ADDR (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address +#define NRF_ERROR_BUSY (NRF_ERROR_BASE_NUM + 17) ///< Busy +#define NRF_ERROR_CONN_COUNT (NRF_ERROR_BASE_NUM + 18) ///< Maximum connection count exceeded. +#define NRF_ERROR_RESOURCES (NRF_ERROR_BASE_NUM + 19) ///< Not enough resources for operation + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error_sdm.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error_sdm.h new file mode 100755 index 0000000..530959b --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error_sdm.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** + @addtogroup nrf_sdm_api + @{ + @defgroup nrf_sdm_error SoftDevice Manager Error Codes + @{ + + @brief Error definitions for the SDM API +*/ + +/* Header guard */ +#ifndef NRF_ERROR_SDM_H__ +#define NRF_ERROR_SDM_H__ + +#include "nrf_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN (NRF_ERROR_SDM_BASE_NUM + 0) ///< Unknown LFCLK source. +#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1) ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts). +#define NRF_ERROR_SDM_INCORRECT_CLENR0 (NRF_ERROR_SDM_BASE_NUM + 2) ///< Incorrect CLENR0 (can be caused by erroneous SoftDevice flashing). + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_SDM_H__ + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error_soc.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error_soc.h new file mode 100755 index 0000000..1e784b8 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_error_soc.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup nrf_soc_api + @{ + @defgroup nrf_soc_error SoC Library Error Codes + @{ + + @brief Error definitions for the SoC library + +*/ + +/* Header guard */ +#ifndef NRF_ERROR_SOC_H__ +#define NRF_ERROR_SOC_H__ + +#include "nrf_error.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* Mutex Errors */ +#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN (NRF_ERROR_SOC_BASE_NUM + 0) ///< Mutex already taken + +/* NVIC errors */ +#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE (NRF_ERROR_SOC_BASE_NUM + 1) ///< NVIC interrupt not available +#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2) ///< NVIC interrupt priority not allowed +#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 3) ///< NVIC should not return + +/* Power errors */ +#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 4) ///< Power mode unknown +#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 5) ///< Power POF threshold unknown +#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 6) ///< Power off should not return + +/* Rand errors */ +#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES (NRF_ERROR_SOC_BASE_NUM + 7) ///< RAND not enough values + +/* PPI errors */ +#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL (NRF_ERROR_SOC_BASE_NUM + 8) ///< Invalid PPI Channel +#define NRF_ERROR_SOC_PPI_INVALID_GROUP (NRF_ERROR_SOC_BASE_NUM + 9) ///< Invalid PPI Group + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_SOC_H__ +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_nvic.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_nvic.h new file mode 100755 index 0000000..1f79cc3 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_nvic.h @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup nrf_nvic_api SoftDevice NVIC API + * @{ + * + * @note In order to use this module, the following code has to be added to a .c file: + * \code + * nrf_nvic_state_t nrf_nvic_state = {0}; + * \endcode + * + * @note Definitions and declarations starting with __ (double underscore) in this header file are + * not intended for direct use by the application. + * + * @brief APIs for the accessing NVIC when using a SoftDevice. + * + */ + +#ifndef NRF_NVIC_H__ +#define NRF_NVIC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup NRF_NVIC_DEFINES Defines + * @{ */ + +/**@defgroup NRF_NVIC_ISER_DEFINES SoftDevice NVIC internal definitions + * @{ */ + +#define __NRF_NVIC_NVMC_IRQn (30) /**< The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK. */ + +#define __NRF_NVIC_ISER_COUNT (2) /**< The number of ISER/ICER registers in the NVIC that are used. */ + +/**@brief Interrupt priority levels used by the SoftDevice. */ +#define __NRF_NVIC_SD_IRQ_PRIOS ((uint8_t)( \ + (1U << 0) /**< Priority level high .*/ \ + | (1U << 1) /**< Priority level medium. */ \ + | (1U << 4) /**< Priority level low. */ \ + )) + +/**@brief Interrupt priority levels available to the application. */ +#define __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t)~__NRF_NVIC_SD_IRQ_PRIOS) + +/**@brief Interrupts used by the SoftDevice, with IRQn in the range 0-31. */ +#define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \ + (1U << POWER_CLOCK_IRQn) \ + | (1U << RADIO_IRQn) \ + | (1U << RTC0_IRQn) \ + | (1U << TIMER0_IRQn) \ + | (1U << RNG_IRQn) \ + | (1U << ECB_IRQn) \ + | (1U << CCM_AAR_IRQn) \ + | (1U << TEMP_IRQn) \ + | (1U << __NRF_NVIC_NVMC_IRQn) \ + | (1U << (uint32_t)SWI5_IRQn) \ + )) + +/**@brief Interrupts used by the SoftDevice, with IRQn in the range 32-63. */ +#define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0) + +/**@brief Interrupts available for to application, with IRQn in the range 0-31. */ +#define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0) + +/**@brief Interrupts available for to application, with IRQn in the range 32-63. */ +#define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1) + +/**@} */ + +/**@} */ + +/**@addtogroup NRF_NVIC_VARIABLES Variables + * @{ */ + +/**@brief Type representing the state struct for the SoftDevice NVIC module. */ +typedef struct +{ + uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */ + uint32_t volatile __cr_flag; /**< Non-zero if already in a critical region */ +} nrf_nvic_state_t; + +/**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an + * application source file. */ +extern nrf_nvic_state_t nrf_nvic_state; + +/**@} */ + +/**@addtogroup NRF_NVIC_INTERNAL_FUNCTIONS SoftDevice NVIC internal functions + * @{ */ + +/**@brief Disables IRQ interrupts globally, including the SoftDevice's interrupts. + * + * @retval The value of PRIMASK prior to disabling the interrupts. + */ +__STATIC_INLINE int __sd_nvic_irq_disable(void); + +/**@brief Enables IRQ interrupts globally, including the SoftDevice's interrupts. + */ +__STATIC_INLINE void __sd_nvic_irq_enable(void); + +/**@brief Checks if IRQn is available to application + * @param[in] IRQn IRQ to check + * + * @retval 1 (true) if the IRQ to check is available to the application + */ +__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn); + +/**@brief Checks if priority is available to application + * @param[in] priority priority to check + * + * @retval 1 (true) if the priority to check is available to the application + */ +__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority); + +/**@} */ + +/**@addtogroup NRF_NVIC_FUNCTIONS SoftDevice NVIC public functions + * @{ */ + +/**@brief Enable External Interrupt. + * @note Corresponds to NVIC_EnableIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt was enabled. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn); + +/**@brief Disable External Interrupt. + * @note Corresponds to NVIC_DisableIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt was disabled. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn); + +/**@brief Get Pending Interrupt. + * @note Corresponds to NVIC_GetPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS. + * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ. + * + * @retval ::NRF_SUCCESS The interrupt is available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq); + +/**@brief Set Pending Interrupt. + * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt is set pending. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn); + +/**@brief Clear Pending Interrupt. + * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt pending flag is cleared. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn); + +/**@brief Set Interrupt Priority. + * @note Corresponds to NVIC_SetPriority in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * @pre Priority is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS. + * @param[in] priority A valid IRQ priority for use by the application. + * + * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority); + +/**@brief Get Interrupt Priority. + * @note Corresponds to NVIC_GetPriority in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS. + * @param[out] p_priority Return value from NVIC_GetPriority. + * + * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority); + +/**@brief System Reset. + * @note Corresponds to NVIC_SystemReset in CMSIS. + * + * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN + */ +__STATIC_INLINE uint32_t sd_nvic_SystemReset(void); + +/**@brief Enter critical region. + * + * @post Application interrupts will be disabled. + * @note sd_nvic_critical_region_enter() and ::sd_nvic_critical_region_exit() must be called in matching pairs inside each + * execution context + * @sa sd_nvic_critical_region_exit + * + * @param[out] p_is_nested_critical_region If 1, the application is now in a nested critical region. + * + * @retval ::NRF_SUCCESS + */ +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region); + +/**@brief Exit critical region. + * + * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter. + * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called. + * + * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter. + * + * @retval ::NRF_SUCCESS + */ +__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region); + +/**@} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE int __sd_nvic_irq_disable(void) +{ + int pm = __get_PRIMASK(); + __disable_irq(); + return pm; +} + +__STATIC_INLINE void __sd_nvic_irq_enable(void) +{ + __enable_irq(); +} + +__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn) +{ + if (IRQn < 32) + { + return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0; + } + else if (IRQn < 64) + { + return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0; + } + else + { + return 1; + } +} + +__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority) +{ + if( (priority >= (1 << __NVIC_PRIO_BITS)) + || (((1 << priority) & __NRF_NVIC_APP_IRQ_PRIOS) == 0) + ) + { + return 0; + } + return 1; +} + + +__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn))) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } + + if (nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); + } + else + { + NVIC_EnableIRQ(IRQn); + } + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F)); + } + else + { + NVIC_DisableIRQ(IRQn); + } + + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + *p_pending_irq = NVIC_GetPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + NVIC_SetPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + NVIC_ClearPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (!__sd_nvic_is_app_accessible_priority(priority)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } + + NVIC_SetPriority(IRQn, (uint32_t)priority); + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + *p_priority = (NVIC_GetPriority(IRQn) & 0xFF); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SystemReset(void) +{ + NVIC_SystemReset(); + return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN; +} + +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region) +{ + int was_masked = __sd_nvic_irq_disable(); + if (!nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__cr_flag = 1; + nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); + NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; + nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); + NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; + *p_is_nested_critical_region = 0; + } + else + { + *p_is_nested_critical_region = 1; + } + if (!was_masked) + { + __sd_nvic_irq_enable(); + } + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) +{ + if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0)) + { + int was_masked = __sd_nvic_irq_disable(); + NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; + NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; + nrf_nvic_state.__cr_flag = 0; + if (!was_masked) + { + __sd_nvic_irq_enable(); + } + } + + return NRF_SUCCESS; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_NVIC_H__ + +/**@} */ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_sdm.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_sdm.h new file mode 100755 index 0000000..c0e0eec --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_sdm.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @defgroup nrf_sdm_api SoftDevice Manager API + @{ + + @brief APIs for SoftDevice management. + +*/ + +#ifndef NRF_SDM_H__ +#define NRF_SDM_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_sdm.h" +#include "nrf_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup NRF_SDM_DEFINES Defines + * @{ */ +#ifdef NRFSOC_DOXYGEN +/// Declared in nrf_mbr.h +#define MBR_SIZE 0 +#warning test +#endif + +/** @brief The major version for the SoftDevice binary distributed with this header file. */ +#define SD_MAJOR_VERSION (6) + +/** @brief The minor version for the SoftDevice binary distributed with this header file. */ +#define SD_MINOR_VERSION (1) + +/** @brief The bugfix version for the SoftDevice binary distributed with this header file. */ +#define SD_BUGFIX_VERSION (1) + +/** @brief The SoftDevice variant of this firmware. */ +#define SD_VARIANT_ID 132 + +/** @brief The full version number for the SoftDevice binary this header file was distributed + * with, as a decimal number in the form Mmmmbbb, where: + * - M is major version (one or more digits) + * - mmm is minor version (three digits) + * - bbb is bugfix version (three digits). */ +#define SD_VERSION (SD_MAJOR_VERSION * 1000000 + SD_MINOR_VERSION * 1000 + SD_BUGFIX_VERSION) + +/** @brief SoftDevice Manager SVC Base number. */ +#define SDM_SVC_BASE 0x10 + +/** @brief SoftDevice unique string size in bytes. */ +#define SD_UNIQUE_STR_SIZE 20 + +/** @brief Invalid info field. Returned when an info field does not exist. */ +#define SDM_INFO_FIELD_INVALID (0) + +/** @brief Defines the SoftDevice Information Structure location (address) as an offset from +the start of the SoftDevice (without MBR)*/ +#define SOFTDEVICE_INFO_STRUCT_OFFSET (0x2000) + +/** @brief Defines the absolute SoftDevice Information Structure location (address) when the + * SoftDevice is installed just above the MBR (the usual case). */ +#define SOFTDEVICE_INFO_STRUCT_ADDRESS (SOFTDEVICE_INFO_STRUCT_OFFSET + MBR_SIZE) + +/** @brief Defines the offset for the SoftDevice Information Structure size value relative to the + * SoftDevice base address. The size value is of type uint8_t. */ +#define SD_INFO_STRUCT_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET) + +/** @brief Defines the offset for the SoftDevice size value relative to the SoftDevice base address. + * The size value is of type uint32_t. */ +#define SD_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x08) + +/** @brief Defines the offset for FWID value relative to the SoftDevice base address. The FWID value + * is of type uint16_t. */ +#define SD_FWID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x0C) + +/** @brief Defines the offset for the SoftDevice ID relative to the SoftDevice base address. The ID + * is of type uint32_t. */ +#define SD_ID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x10) + +/** @brief Defines the offset for the SoftDevice version relative to the SoftDevice base address in + * the same format as @ref SD_VERSION, stored as an uint32_t. */ +#define SD_VERSION_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x14) + +/** @brief Defines the offset for the SoftDevice unique string relative to the SoftDevice base address. + * The SD_UNIQUE_STR is stored as an array of uint8_t. The size of array is @ref SD_UNIQUE_STR_SIZE. + */ +#define SD_UNIQUE_STR_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x18) + +/** @brief Defines a macro for retrieving the actual SoftDevice Information Structure size value + * from a given base address. Use @ref MBR_SIZE as the argument when the SoftDevice is + * installed just above the MBR (the usual case). */ +#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *) ((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET))) + +/** @brief Defines a macro for retrieving the actual SoftDevice size value from a given base + * address. Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above + * the MBR (the usual case). */ +#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET))) + +/** @brief Defines the amount of flash that is used by the SoftDevice. + * Add @ref MBR_SIZE to find the first available flash address when the SoftDevice is installed + * just above the MBR (the usual case). + */ +#define SD_FLASH_SIZE 0x25000 + +/** @brief Defines a macro for retrieving the actual FWID value from a given base address. Use + * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the usual + * case). */ +#define SD_FWID_GET(baseaddr) (*((uint16_t *) ((baseaddr) + SD_FWID_OFFSET))) + +/** @brief Defines a macro for retrieving the actual SoftDevice ID from a given base address. Use + * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the + * usual case). */ +#define SD_ID_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_ID_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (*((uint32_t *) ((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/** @brief Defines a macro for retrieving the actual SoftDevice version from a given base address. + * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR + * (the usual case). */ +#define SD_VERSION_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_VERSION_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (*((uint32_t *) ((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/** @brief Defines a macro for retrieving the address of SoftDevice unique str based on a given base address. + * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR + * (the usual case). */ +#define SD_UNIQUE_STR_ADDR_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_UNIQUE_STR_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (((uint8_t *) ((baseaddr) + SD_UNIQUE_STR_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges + * @{ */ +#define NRF_FAULT_ID_SD_RANGE_START 0x00000000 /**< SoftDevice ID range start. */ +#define NRF_FAULT_ID_APP_RANGE_START 0x00001000 /**< Application ID range start. */ +/**@} */ + +/**@defgroup NRF_FAULT_IDS Fault ID types + * @{ */ +#define NRF_FAULT_ID_SD_ASSERT (NRF_FAULT_ID_SD_RANGE_START + 1) /**< SoftDevice assertion. The info parameter is reserved for future used. */ +#define NRF_FAULT_ID_APP_MEMACC (NRF_FAULT_ID_APP_RANGE_START + 1) /**< Application invalid memory access. The info parameter will contain 0x00000000, + in case of SoftDevice RAM access violation. In case of SoftDevice peripheral + register violation the info parameter will contain the sub-region number of + PREGION[0], on whose address range the disallowed write access caused the + memory access fault. */ +/**@} */ + +/** @} */ + +/** @addtogroup NRF_SDM_ENUMS Enumerations + * @{ */ + +/**@brief nRF SoftDevice Manager API SVC numbers. */ +enum NRF_SD_SVCS +{ + SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ + SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ + SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ + SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ + SVC_SDM_LAST /**< Placeholder for last SDM SVC */ +}; + +/** @} */ + +/** @addtogroup NRF_SDM_DEFINES Defines + * @{ */ + +/**@defgroup NRF_CLOCK_LF_ACCURACY Clock accuracy + * @{ */ + +#define NRF_CLOCK_LF_ACCURACY_250_PPM (0) /**< Default: 250 ppm */ +#define NRF_CLOCK_LF_ACCURACY_500_PPM (1) /**< 500 ppm */ +#define NRF_CLOCK_LF_ACCURACY_150_PPM (2) /**< 150 ppm */ +#define NRF_CLOCK_LF_ACCURACY_100_PPM (3) /**< 100 ppm */ +#define NRF_CLOCK_LF_ACCURACY_75_PPM (4) /**< 75 ppm */ +#define NRF_CLOCK_LF_ACCURACY_50_PPM (5) /**< 50 ppm */ +#define NRF_CLOCK_LF_ACCURACY_30_PPM (6) /**< 30 ppm */ +#define NRF_CLOCK_LF_ACCURACY_20_PPM (7) /**< 20 ppm */ +#define NRF_CLOCK_LF_ACCURACY_10_PPM (8) /**< 10 ppm */ +#define NRF_CLOCK_LF_ACCURACY_5_PPM (9) /**< 5 ppm */ +#define NRF_CLOCK_LF_ACCURACY_2_PPM (10) /**< 2 ppm */ +#define NRF_CLOCK_LF_ACCURACY_1_PPM (11) /**< 1 ppm */ + +/** @} */ + +/**@defgroup NRF_CLOCK_LF_SRC Possible LFCLK oscillator sources + * @{ */ + +#define NRF_CLOCK_LF_SRC_RC (0) /**< LFCLK RC oscillator. */ +#define NRF_CLOCK_LF_SRC_XTAL (1) /**< LFCLK crystal oscillator. */ +#define NRF_CLOCK_LF_SRC_SYNTH (2) /**< LFCLK Synthesized from HFCLK. */ + +/** @} */ + +/** @} */ + +/** @addtogroup NRF_SDM_TYPES Types + * @{ */ + +/**@brief Type representing LFCLK oscillator source. */ +typedef struct +{ + uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ + uint8_t rc_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second + units (nRF52: 1-32). + @note To avoid excessive clock drift, 0.5 degrees Celsius is the + maximum temperature change allowed in one calibration timer + interval. The interval should be selected to ensure this. + + @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC. */ + uint8_t rc_temp_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: How often (in number of calibration + intervals) the RC oscillator shall be calibrated if the temperature + hasn't changed. + 0: Always calibrate even if the temperature hasn't changed. + 1: Only calibrate if the temperature has changed (legacy - nRF51 only). + 2-33: Check the temperature and only calibrate if it has changed, + however calibration will take place every rc_temp_ctiv + intervals in any case. + + @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC. + + @note For nRF52, the application must ensure calibration at least once + every 8 seconds to ensure +/-500 ppm clock stability. The + recommended configuration for ::NRF_CLOCK_LF_SRC_RC on nRF52 is + rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at + least once every 8 seconds and for temperature changes of 0.5 + degrees Celsius every 4 seconds. See the Product Specification + for the nRF52 device being used for more information.*/ + uint8_t accuracy; /**< External clock accuracy used in the LL to compute timing + windows, see @ref NRF_CLOCK_LF_ACCURACY.*/ +} nrf_clock_lf_cfg_t; + +/**@brief Fault Handler type. + * + * When certain unrecoverable errors occur within the application or SoftDevice the fault handler will be called back. + * The protocol stack will be in an undefined state when this happens and the only way to recover will be to + * perform a reset, using e.g. CMSIS NVIC_SystemReset(). + * If the application returns from the fault handler the SoftDevice will call NVIC_SystemReset(). + * + * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the fault callback. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault. + * @param[in] info Optional additional information regarding the fault. Refer to each Fault identifier for details. + * + * @note When id is set to @ref NRF_FAULT_ID_APP_MEMACC, pc will contain the address of the instruction being executed at the time when + * the fault is detected by the CPU. The CPU program counter may have advanced up to 2 instructions (no branching) after the one that triggered the fault. + */ +typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info); + +/** @} */ + +/** @addtogroup NRF_SDM_FUNCTIONS Functions + * @{ */ + +/**@brief Enables the SoftDevice and by extension the protocol stack. + * + * @note Some care must be taken if a low frequency clock source is already running when calling this function: + * If the LF clock has a different source then the one currently running, it will be stopped. Then, the new + * clock source will be started. + * + * @note This function has no effect when returning with an error. + * + * @post If return code is ::NRF_SUCCESS + * - SoC library and protocol stack APIs are made available. + * - A portion of RAM will be unavailable (see relevant SDS documentation). + * - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation). + * - Interrupts will not arrive from protected peripherals or interrupts. + * - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the SoftDevice. + * - Interrupt latency may be affected by the SoftDevice (see relevant SDS documentation). + * - Chosen low frequency clock source will be running. + * + * @param p_clock_lf_cfg Low frequency clock source and accuracy. + If NULL the clock will be configured as an RC source with rc_ctiv = 16 and .rc_temp_ctiv = 2 + In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock. + * @param fault_handler Callback to be invoked in case of fault, cannot be NULL. + * + * @retval ::NRF_SUCCESS + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE SoftDevice is already enabled, and the clock source and fault handler cannot be updated. + * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDevice interrupt is already enabled, or an enabled interrupt has an illegal priority level. + * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid clock source configuration supplied in p_clock_lf_cfg. + */ +SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler)); + + +/**@brief Disables the SoftDevice and by extension the protocol stack. + * + * Idempotent function to disable the SoftDevice. + * + * @post SoC library and protocol stack APIs are made unavailable. + * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest). + * @post All peripherals used by the SoftDevice will be reset to default values. + * @post All of RAM become available. + * @post All interrupts are forwarded to the application. + * @post LFCLK source chosen in ::sd_softdevice_enable will be left running. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void)); + +/**@brief Check if the SoftDevice is enabled. + * + * @param[out] p_softdevice_enabled If the SoftDevice is enabled: 1 else 0. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled)); + +/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice + * + * This function is only intended to be called when a bootloader is enabled. + * + * @param[in] address The base address of the interrupt vector table for forwarded interrupts. + + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address)); + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // NRF_SDM_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_soc.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_soc.h new file mode 100755 index 0000000..d599576 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_soc.h @@ -0,0 +1,1007 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup nrf_soc_api SoC Library API + * @{ + * + * @brief APIs for the SoC library. + * + */ + +#ifndef NRF_SOC_H__ +#define NRF_SOC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup NRF_SOC_DEFINES Defines + * @{ */ + +/**@brief The number of the lowest SVC number reserved for the SoC library. */ +#define SOC_SVC_BASE (0x20) /**< Base value for SVCs that are available when the SoftDevice is disabled. */ +#define SOC_SVC_BASE_NOT_AVAILABLE (0x2C) /**< Base value for SVCs that are not available when the SoftDevice is disabled. */ + +/**@brief Guaranteed time for application to process radio inactive notification. */ +#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US (62) + +/**@brief The minimum allowed timeslot extension time. */ +#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200) + +/**@brief The maximum processing time to handle a timeslot extension. */ +#define NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US (17) + +/**@brief The latest time before the end of a timeslot the timeslot can be extended. */ +#define NRF_RADIO_MIN_EXTENSION_MARGIN_US (79) + +#define SOC_ECB_KEY_LENGTH (16) /**< ECB key length. */ +#define SOC_ECB_CLEARTEXT_LENGTH (16) /**< ECB cleartext length. */ +#define SOC_ECB_CIPHERTEXT_LENGTH (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */ + +#define SD_EVT_IRQn (SWI2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */ +#define SD_EVT_IRQHandler (SWI2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. + The default interrupt priority for this handler is set to 6 */ +#define RADIO_NOTIFICATION_IRQn (SWI1_IRQn) /**< The radio notification IRQ number. */ +#define RADIO_NOTIFICATION_IRQHandler (SWI1_IRQHandler) /**< The radio notification IRQ handler. + The default interrupt priority for this handler is set to 6 */ +#define NRF_RADIO_LENGTH_MIN_US (100) /**< The shortest allowed radio timeslot, in microseconds. */ +#define NRF_RADIO_LENGTH_MAX_US (100000) /**< The longest allowed radio timeslot, in microseconds. */ + +#define NRF_RADIO_DISTANCE_MAX_US (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */ + +#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */ + +#define NRF_RADIO_START_JITTER_US (2) /**< The maximum jitter in @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */ + +/**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is disabled. */ +#define NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK ((uint32_t)(0)) + +/**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is enabled. */ +#define NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK ((uint32_t)( \ + (1U << 17) \ + | (1U << 18) \ + | (1U << 19) \ + | (1U << 20) \ + | (1U << 21) \ + | (1U << 22) \ + | (1U << 23) \ + | (1U << 24) \ + | (1U << 25) \ + | (1U << 26) \ + | (1U << 27) \ + | (1U << 28) \ + | (1U << 29) \ + | (1U << 30) \ + | (1U << 31) \ + )) + +/**@brief Mask of PPI channels available to the application when the SoftDevice is disabled. */ +#define NRF_SOC_APP_PPI_CHANNELS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK) + +/**@brief Mask of PPI channels available to the application when the SoftDevice is enabled. */ +#define NRF_SOC_APP_PPI_CHANNELS_SD_ENABLED_MSK (~NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK) + +/**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is disabled. */ +#define NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK ((uint32_t)(0)) + +/**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is enabled. */ +#define NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK ((uint32_t)( \ + (1U << 4) \ + | (1U << 5) \ + )) + +/**@brief Mask of PPI groups available to the application when the SoftDevice is disabled. */ +#define NRF_SOC_APP_PPI_GROUPS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK) + +/**@brief Mask of PPI groups available to the application when the SoftDevice is enabled. */ +#define NRF_SOC_APP_PPI_GROUPS_SD_ENABLED_MSK (~NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK) + +/**@} */ + +/**@addtogroup NRF_SOC_ENUMS Enumerations + * @{ */ + +/**@brief The SVC numbers used by the SVC functions in the SoC library. */ +enum NRF_SOC_SVCS +{ + SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE, + SD_PPI_CHANNEL_ENABLE_SET = SOC_SVC_BASE + 1, + SD_PPI_CHANNEL_ENABLE_CLR = SOC_SVC_BASE + 2, + SD_PPI_CHANNEL_ASSIGN = SOC_SVC_BASE + 3, + SD_PPI_GROUP_TASK_ENABLE = SOC_SVC_BASE + 4, + SD_PPI_GROUP_TASK_DISABLE = SOC_SVC_BASE + 5, + SD_PPI_GROUP_ASSIGN = SOC_SVC_BASE + 6, + SD_PPI_GROUP_GET = SOC_SVC_BASE + 7, + SD_FLASH_PAGE_ERASE = SOC_SVC_BASE + 8, + SD_FLASH_WRITE = SOC_SVC_BASE + 9, + SD_FLASH_PROTECT = SOC_SVC_BASE + 10, + SD_PROTECTED_REGISTER_WRITE = SOC_SVC_BASE + 11, + SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, + SD_MUTEX_ACQUIRE = SOC_SVC_BASE_NOT_AVAILABLE + 1, + SD_MUTEX_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 2, + SD_RAND_APPLICATION_POOL_CAPACITY_GET = SOC_SVC_BASE_NOT_AVAILABLE + 3, + SD_RAND_APPLICATION_BYTES_AVAILABLE_GET = SOC_SVC_BASE_NOT_AVAILABLE + 4, + SD_RAND_APPLICATION_VECTOR_GET = SOC_SVC_BASE_NOT_AVAILABLE + 5, + SD_POWER_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 6, + SD_POWER_SYSTEM_OFF = SOC_SVC_BASE_NOT_AVAILABLE + 7, + SD_POWER_RESET_REASON_GET = SOC_SVC_BASE_NOT_AVAILABLE + 8, + SD_POWER_RESET_REASON_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 9, + SD_POWER_POF_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 10, + SD_POWER_POF_THRESHOLD_SET = SOC_SVC_BASE_NOT_AVAILABLE + 11, + SD_POWER_RAM_POWER_SET = SOC_SVC_BASE_NOT_AVAILABLE + 13, + SD_POWER_RAM_POWER_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 14, + SD_POWER_RAM_POWER_GET = SOC_SVC_BASE_NOT_AVAILABLE + 15, + SD_POWER_GPREGRET_SET = SOC_SVC_BASE_NOT_AVAILABLE + 16, + SD_POWER_GPREGRET_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 17, + SD_POWER_GPREGRET_GET = SOC_SVC_BASE_NOT_AVAILABLE + 18, + SD_POWER_DCDC_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 19, + SD_APP_EVT_WAIT = SOC_SVC_BASE_NOT_AVAILABLE + 21, + SD_CLOCK_HFCLK_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 22, + SD_CLOCK_HFCLK_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 23, + SD_CLOCK_HFCLK_IS_RUNNING = SOC_SVC_BASE_NOT_AVAILABLE + 24, + SD_RADIO_NOTIFICATION_CFG_SET = SOC_SVC_BASE_NOT_AVAILABLE + 25, + SD_ECB_BLOCK_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 26, + SD_ECB_BLOCKS_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 27, + SD_RADIO_SESSION_OPEN = SOC_SVC_BASE_NOT_AVAILABLE + 28, + SD_RADIO_SESSION_CLOSE = SOC_SVC_BASE_NOT_AVAILABLE + 29, + SD_RADIO_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 30, + SD_EVT_GET = SOC_SVC_BASE_NOT_AVAILABLE + 31, + SD_TEMP_GET = SOC_SVC_BASE_NOT_AVAILABLE + 32, + SVC_SOC_LAST = SOC_SVC_BASE_NOT_AVAILABLE + 37 +}; + +/**@brief Possible values of a ::nrf_mutex_t. */ +enum NRF_MUTEX_VALUES +{ + NRF_MUTEX_FREE, + NRF_MUTEX_TAKEN +}; + +/**@brief Power modes. */ +enum NRF_POWER_MODES +{ + NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ + NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ +}; + + +/**@brief Power failure thresholds */ +enum NRF_POWER_THRESHOLDS +{ + NRF_POWER_THRESHOLD_V17 = 4UL, /**< 1.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V18, /**< 1.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V19, /**< 1.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V20, /**< 2.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V22, /**< 2.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V24, /**< 2.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V26, /**< 2.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V28 /**< 2.8 Volts power failure threshold. */ +}; + + + +/**@brief DC/DC converter modes. */ +enum NRF_POWER_DCDC_MODES +{ + NRF_POWER_DCDC_DISABLE, /**< The DCDC is disabled. */ + NRF_POWER_DCDC_ENABLE /**< The DCDC is enabled. */ +}; + +/**@brief Radio notification distances. */ +enum NRF_RADIO_NOTIFICATION_DISTANCES +{ + NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ + NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ +}; + + +/**@brief Radio notification types. */ +enum NRF_RADIO_NOTIFICATION_TYPES +{ + NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ +}; + +/**@brief The Radio signal callback types. */ +enum NRF_RADIO_CALLBACK_SIGNAL_TYPE +{ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ +}; + +/**@brief The actions requested by the signal callback. + * + * This code gives the SOC instructions about what action to take when the signal callback has + * returned. + */ +enum NRF_RADIO_SIGNAL_CALLBACK_ACTION +{ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current + timeslot. Maximum execution time for this action: + @ref NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US. + This action must be started at least + @ref NRF_RADIO_MIN_EXTENSION_MARGIN_US before + the end of the timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ +}; + +/**@brief Radio timeslot high frequency clock source configuration. */ +enum NRF_RADIO_HFCLK_CFG +{ + NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the + external crystal for the whole duration of the timeslot. This should be the + preferred option for events that use the radio or require high timing accuracy. + @note The SoftDevice will automatically turn on and off the external crystal, + at the beginning and end of the timeslot, respectively. The crystal may also + intentionally be left running after the timeslot, in cases where it is needed + by the SoftDevice shortly after the end of the timeslot. */ + NRF_RADIO_HFCLK_CFG_NO_GUARANTEE /**< This configuration allows for earlier and tighter scheduling of timeslots. + The RC oscillator may be the clock source in part or for the whole duration of the timeslot. + The RC oscillator's accuracy must therefore be taken into consideration. + @note If the application will use the radio peripheral in timeslots with this configuration, + it must make sure that the crystal is running and stable before starting the radio. */ +}; + +/**@brief Radio timeslot priorities. */ +enum NRF_RADIO_PRIORITY +{ + NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ + NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activities of the SoftDevice stack(s)). */ +}; + +/**@brief Radio timeslot request type. */ +enum NRF_RADIO_REQUEST_TYPE +{ + NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */ + NRF_RADIO_REQ_TYPE_NORMAL /**< Normal radio timeslot request. */ +}; + +/**@brief SoC Events. */ +enum NRF_SOC_EVTS +{ + NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ + NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ + NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ + NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ + NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ + NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ + NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */ + NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio timeslot session is idle. */ + NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio timeslot session is closed. */ + NRF_EVT_NUMBER_OF_EVTS +}; + +/**@} */ + + +/**@addtogroup NRF_SOC_STRUCTURES Structures + * @{ */ + +/**@brief Represents a mutex for use with the nrf_mutex functions. + * @note Accessing the value directly is not safe, use the mutex functions! + */ +typedef volatile uint8_t nrf_mutex_t; + +/**@brief Parameters for a request for a timeslot as early as possible. */ +typedef struct +{ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ + uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ +} nrf_radio_request_earliest_t; + +/**@brief Parameters for a normal radio timeslot request. */ +typedef struct +{ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ + uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ +} nrf_radio_request_normal_t; + +/**@brief Radio timeslot request parameters. */ +typedef struct +{ + uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ + union + { + nrf_radio_request_earliest_t earliest; /**< Parameters for requesting a radio timeslot as early as possible. */ + nrf_radio_request_normal_t normal; /**< Parameters for requesting a normal radio timeslot. */ + } params; /**< Parameter union. */ +} nrf_radio_request_t; + +/**@brief Return parameters of the radio timeslot signal callback. */ +typedef struct +{ + uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ + union + { + struct + { + nrf_radio_request_t * p_next; /**< The request parameters for the next radio timeslot. */ + } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ + struct + { + uint32_t length_us; /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ + } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ + } params; /**< Parameter union. */ +} nrf_radio_signal_callback_return_param_t; + +/**@brief The radio timeslot signal callback type. + * + * @note In case of invalid return parameters, the radio timeslot will automatically end + * immediately after returning from the signal callback and the + * @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent. + * @note The returned struct pointer must remain valid after the signal callback + * function returns. For instance, this means that it must not point to a stack variable. + * + * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE. + * + * @return Pointer to structure containing action requested by the application. + */ +typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type); + +/**@brief AES ECB parameter typedefs */ +typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH]; /**< Encryption key type. */ +typedef uint8_t soc_ecb_cleartext_t[SOC_ECB_CLEARTEXT_LENGTH]; /**< Cleartext data type. */ +typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Ciphertext data type. */ + +/**@brief AES ECB data structure */ +typedef struct +{ + soc_ecb_key_t key; /**< Encryption key. */ + soc_ecb_cleartext_t cleartext; /**< Cleartext data. */ + soc_ecb_ciphertext_t ciphertext; /**< Ciphertext data. */ +} nrf_ecb_hal_data_t; + +/**@brief AES ECB block. Used to provide multiple blocks in a single call + to @ref sd_ecb_blocks_encrypt.*/ +typedef struct +{ + soc_ecb_key_t const * p_key; /**< Pointer to the Encryption key. */ + soc_ecb_cleartext_t const * p_cleartext; /**< Pointer to the Cleartext data. */ + soc_ecb_ciphertext_t * p_ciphertext; /**< Pointer to the Ciphertext data. */ +} nrf_ecb_hal_data_block_t; + +/**@} */ + +/**@addtogroup NRF_SOC_FUNCTIONS Functions + * @{ */ + +/**@brief Initialize a mutex. + * + * @param[in] p_mutex Pointer to the mutex to initialize. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex)); + +/**@brief Attempt to acquire a mutex. + * + * @param[in] p_mutex Pointer to the mutex to acquire. + * + * @retval ::NRF_SUCCESS The mutex was successfully acquired. + * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired. + */ +SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex)); + +/**@brief Release a mutex. + * + * @param[in] p_mutex Pointer to the mutex to release. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex)); + +/**@brief Query the capacity of the application random pool. + * + * @param[out] p_pool_capacity The capacity of the pool. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY_GET, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity)); + +/**@brief Get number of random bytes available to the application. + * + * @param[out] p_bytes_available The number of bytes currently available in the pool. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available)); + +/**@brief Get random bytes from the application pool. + * + * @param[out] p_buff Pointer to unit8_t buffer for storing the bytes. + * @param[in] length Number of bytes to take from pool and place in p_buff. + * + * @retval ::NRF_SUCCESS The requested bytes were written to p_buff. + * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available. +*/ +SVCALL(SD_RAND_APPLICATION_VECTOR_GET, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length)); + +/**@brief Gets the reset reason register. + * + * @param[out] p_reset_reason Contents of the NRF_POWER->RESETREAS register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason)); + +/**@brief Clears the bits of the reset reason register. + * + * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk)); + +/**@brief Sets the power mode when in CPU sleep. + * + * @param[in] power_mode The power mode to use when in CPU sleep, see @ref NRF_POWER_MODES. @sa sd_app_evt_wait + * + * @retval ::NRF_SUCCESS The power mode was set. + * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown. + */ +SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(uint8_t power_mode)); + +/**@brief Puts the chip in System OFF mode. + * + * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN + */ +SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void)); + +/**@brief Enables or disables the power-fail comparator. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] pof_enable True if the power-fail comparator should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable)); + + +/**@brief Sets the power failure comparator threshold value. + * + * + * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDS. + * + * @retval ::NRF_SUCCESS The power failure threshold was set. + * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown. + */ +SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(uint8_t threshold)); + + +/**@brief Writes the NRF_POWER->RAM[index].POWERSET register. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWERSET register to write to. + * @param[in] ram_powerset Contains the word to write to the NRF_POWER->RAM[index].POWERSET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_SET, uint32_t, sd_power_ram_power_set(uint8_t index, uint32_t ram_powerset)); + +/**@brief Writes the NRF_POWER->RAM[index].POWERCLR register. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWERCLR register to write to. + * @param[in] ram_powerclr Contains the word to write to the NRF_POWER->RAM[index].POWERCLR register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_CLR, uint32_t, sd_power_ram_power_clr(uint8_t index, uint32_t ram_powerclr)); + +/**@brief Get contents of NRF_POWER->RAM[index].POWER register, indicates power status of RAM[index] blocks. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWER register to read from. + * @param[out] p_ram_power Content of NRF_POWER->RAM[index].POWER register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_GET, uint32_t, sd_power_ram_power_get(uint8_t index, uint32_t * p_ram_power)); + +/**@brief Set bits in the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[in] gpregret_msk Bits to be set in the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_id, uint32_t gpregret_msk)); + +/**@brief Clear bits in the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[in] gpregret_msk Bits to be clear in the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_id, uint32_t gpregret_msk)); + +/**@brief Get contents of the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[out] p_gpregret Contents of the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t *p_gpregret)); + +/**@brief Enable or disable the DC/DC regulator. + * + * @param[in] dcdc_mode The mode of the DCDC, see @ref NRF_POWER_DCDC_MODES. + * + * @retval ::NRF_SUCCESS + * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid. + */ +SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(uint8_t dcdc_mode)); + + +/**@brief Request the high frequency crystal oscillator. + * + * Will start the high frequency crystal oscillator, the startup time of the crystal varies + * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started. + * + * @see sd_clock_hfclk_is_running + * @see sd_clock_hfclk_release + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void)); + +/**@brief Releases the high frequency crystal oscillator. + * + * Will stop the high frequency crystal oscillator, this happens immediately. + * + * @see sd_clock_hfclk_is_running + * @see sd_clock_hfclk_request + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void)); + +/**@brief Checks if the high frequency crystal oscillator is running. + * + * @see sd_clock_hfclk_request + * @see sd_clock_hfclk_release + * + * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running)); + +/**@brief Waits for an application event. + * + * An application event is either an application interrupt or a pended interrupt when the interrupt + * is disabled. + * + * When the application waits for an application event by calling this function, an interrupt that + * is enabled will be taken immediately on pending since this function will wait in thread mode, + * then the execution will return in the application's main thread. + * + * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M + * MCU's System Control Register (SCR), CMSIS_SCB. In that case, when a disabled interrupt gets + * pended, this function will return to the application's main thread. + * + * @note The application must ensure that the pended flag is cleared using ::sd_nvic_ClearPendingIRQ + * in order to sleep using this function. This is only necessary for disabled interrupts, as + * the interrupt handler will clear the pending flag automatically for enabled interrupts. + * + * @note If an application interrupt has happened since the last time sd_app_evt_wait was + * called this function will return immediately and not go to sleep. This is to avoid race + * conditions that can occur when a flag is updated in the interrupt handler and processed + * in the main loop. + * + * @post An application interrupt has happened or a interrupt pending flag is set. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void)); + +/**@brief Get PPI channel enable register contents. + * + * @param[out] p_channel_enable The contents of the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable)); + +/**@brief Set PPI channel enable register. + * + * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk)); + +/**@brief Clear PPI channel enable register. + * + * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk)); + +/**@brief Assign endpoints to a PPI channel. + * + * @param[in] channel_num Number of the PPI channel to assign. + * @param[in] evt_endpoint Event endpoint of the PPI channel. + * @param[in] task_endpoint Task endpoint of the PPI channel. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)); + +/**@brief Task to enable a channel group. + * + * @param[in] group_num Number of the channel group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num)); + +/**@brief Task to disable a channel group. + * + * @param[in] group_num Number of the PPI group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num)); + +/**@brief Assign PPI channels to a channel group. + * + * @param[in] group_num Number of the channel group. + * @param[in] channel_msk Mask of the channels to assign to the group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk)); + +/**@brief Gets the PPI channels of a channel group. + * + * @param[in] group_num Number of the channel group. + * @param[out] p_channel_msk Mask of the channels assigned to the group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk)); + +/**@brief Configures the Radio Notification signal. + * + * @note + * - The notification signal latency depends on the interrupt priority settings of SWI used + * for notification signal. + * - To ensure that the radio notification signal behaves in a consistent way, the radio + * notifications must be configured when there is no protocol stack or other SoftDevice + * activity in progress. It is recommended that the radio notification signal is + * configured directly after the SoftDevice has been enabled. + * - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice + * will interrupt the application to do Radio Event preparation. + * - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have + * to shorten the connection events to have time for the Radio Notification signals. + * + * @param[in] type Type of notification signal, see @ref NRF_RADIO_NOTIFICATION_TYPES. + * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio + * notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is + * recommended (but not required) to be used with + * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE. + * + * @param[in] distance Distance between the notification signal and start of radio activity, see @ref NRF_RADIO_NOTIFICATION_DISTANCES. + * This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or + * @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. + * + * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid. + * @retval ::NRF_ERROR_INVALID_STATE A protocol stack or other SoftDevice is running. Stop all + * running activities and retry. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(uint8_t type, uint8_t distance)); + +/**@brief Encrypts a block according to the specified parameters. + * + * 128-bit AES encryption. + * + * @note: + * - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while + * the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application + * main or low interrupt level. + * + * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input + * parameters and one output parameter). + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data)); + +/**@brief Encrypts multiple data blocks provided as an array of data block structures. + * + * @details: Performs 128-bit AES encryption on multiple data blocks + * + * @note: + * - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while + * the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application + * main or low interrupt level. + * + * @param[in] block_count Count of blocks in the p_data_blocks array. + * @param[in,out] p_data_blocks Pointer to the first entry in a contiguous array of + * @ref nrf_ecb_hal_data_block_t structures. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_ECB_BLOCKS_ENCRYPT, uint32_t, sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks)); + +/**@brief Gets any pending events generated by the SoC API. + * + * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned. + * + * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending. + * + * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter. + * @retval ::NRF_ERROR_NOT_FOUND No pending events. + */ +SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id)); + +/**@brief Get the temperature measured on the chip + * + * This function will block until the temperature measurement is done. + * It takes around 50 us from call to return. + * + * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees Celsius. + * + * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp + */ +SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp)); + +/**@brief Flash Write +* +* Commands to write a buffer to flash +* +* If the SoftDevice is enabled: +* This call initiates the flash access command, and its completion will be communicated to the +* application with exactly one of the following events: +* - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. +* - @ref NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. +* +* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the + * write has been completed +* +* @note +* - This call takes control over the radio and the CPU during flash erase and write to make sure that +* they will not interfere with the flash access. This means that all interrupts will be blocked +* for a predictable time (depending on the NVMC specification in the device's Product Specification +* and the command parameters). +* - The data in the p_src buffer should not be modified before the @ref NRF_EVT_FLASH_OPERATION_SUCCESS +* or the @ref NRF_EVT_FLASH_OPERATION_ERROR have been received if the SoftDevice is enabled. +* - This call will make the SoftDevice trigger a hardfault when the page is written, if it is +* protected. +* +* +* @param[in] p_dst Pointer to start of flash location to be written. +* @param[in] p_src Pointer to buffer with data to be written. +* @param[in] size Number of 32-bit words to write. Maximum size is the number of words in one +* flash page. See the device's Product Specification for details. +* +* @retval ::NRF_ERROR_INVALID_ADDR Tried to write to a non existing flash address, or p_dst or p_src was unaligned. +* @retval ::NRF_ERROR_BUSY The previous command has not yet completed. +* @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or higher than the maximum allowed size. +* @retval ::NRF_ERROR_FORBIDDEN Tried to write to an address outside the application flash area. +* @retval ::NRF_SUCCESS The command was accepted. +*/ +SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * p_dst, uint32_t const * p_src, uint32_t size)); + + +/**@brief Flash Erase page +* +* Commands to erase a flash page +* If the SoftDevice is enabled: +* This call initiates the flash access command, and its completion will be communicated to the +* application with exactly one of the following events: +* - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. +* - @ref NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. +* +* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the +* erase has been completed +* +* @note +* - This call takes control over the radio and the CPU during flash erase and write to make sure that +* they will not interfere with the flash access. This means that all interrupts will be blocked +* for a predictable time (depending on the NVMC specification in the device's Product Specification +* and the command parameters). +* - This call will make the SoftDevice trigger a hardfault when the page is erased, if it is +* protected. +* +* +* @param[in] page_number Page number of the page to erase +* +* @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. +* @retval ::NRF_ERROR_INVALID_ADDR Tried to erase to a non existing flash page. +* @retval ::NRF_ERROR_BUSY The previous command has not yet completed. +* @retval ::NRF_ERROR_FORBIDDEN Tried to erase a page outside the application flash area. +* @retval ::NRF_SUCCESS The command was accepted. +*/ +SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)); + + +/**@brief Flash Protection set + * + * Commands to set the flash protection configuration registers. + This sets the CONFIGx registers of the BPROT peripheral. + * + * @note Not all parameters are valid for all products. Some bits in each parameter may not be + * valid for your product. Please refer your Product Specification for more details. + * + * @note To read the values read them directly. They are only write-protected. + * + * @note It is possible to use @ref sd_protected_register_write instead of this function. + * + * @param[in] block_cfg0 Value to be written to the configuration register. + * @param[in] block_cfg1 Value to be written to the configuration register. + * @param[in] block_cfg2 Value to be written to the configuration register. + * @param[in] block_cfg3 Value to be written to the configuration register. + * + * @retval ::NRF_ERROR_NOT_SUPPORTED Non-zero value supplied to one or more of the unsupported parameters. + * @retval ::NRF_SUCCESS Values successfully written to configuration registers. + */ +SVCALL(SD_FLASH_PROTECT, uint32_t, sd_flash_protect(uint32_t block_cfg0, uint32_t block_cfg1, uint32_t block_cfg2, uint32_t block_cfg3)); + +/**@brief Opens a session for radio timeslot requests. + * + * @note Only one session can be open at a time. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot + * starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed + * by the application. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0 + * interrupt occurs. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO + * interrupt occurs. + * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This + * implies that none of the sd_* API calls can be used from p_radio_signal_callback(). + * + * @param[in] p_radio_signal_callback The signal callback. + * + * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer. + * @retval ::NRF_ERROR_BUSY If session cannot be opened. + * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); + +/**@brief Closes a session for radio timeslot requests. + * + * @note Any current radio timeslot will be finished before the session is closed. + * @note If a radio timeslot is scheduled when the session is closed, it will be canceled. + * @note The application cannot consider the session closed until the @ref NRF_EVT_RADIO_SESSION_CLOSED + * event is received. + * + * @retval ::NRF_ERROR_FORBIDDEN If session not opened. + * @retval ::NRF_ERROR_BUSY If session is currently being closed. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); + +/**@brief Requests a radio timeslot. + * + * @note The request type is determined by p_request->request_type, and can be one of @ref NRF_RADIO_REQ_TYPE_EARLIEST + * and @ref NRF_RADIO_REQ_TYPE_NORMAL. The first request in a session must always be of type @ref NRF_RADIO_REQ_TYPE_EARLIEST. + * @note For a normal request (@ref NRF_RADIO_REQ_TYPE_NORMAL), the start time of a radio timeslot is specified by + * p_request->distance_us and is given relative to the start of the previous timeslot. + * @note A too small p_request->distance_us will lead to a @ref NRF_EVT_RADIO_BLOCKED event. + * @note Timeslots scheduled too close will lead to a @ref NRF_EVT_RADIO_BLOCKED event. + * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths. + * @note If an opportunity for the first radio timeslot is not found before 100 ms after the call to this + * function, it is not scheduled, and instead a @ref NRF_EVT_RADIO_BLOCKED event is sent. + * The application may then try to schedule the first radio timeslot again. + * @note Successful requests will result in nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START). + * Unsuccessful requests will result in a @ref NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS. + * @note The jitter in the start time of the radio timeslots is +/- @ref NRF_RADIO_START_JITTER_US us. + * @note The nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the + * specified radio timeslot start, but this does not affect the actual start time of the timeslot. + * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency + * (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is + * guaranteed to be clocked from the external crystal. + * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral + * during the radio timeslot. + * + * @param[in] p_request Pointer to the request parameters. + * + * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE. + * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid. + * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t const * p_request)); + +/**@brief Write register protected by the SoftDevice + * + * This function writes to a register that is write-protected by the SoftDevice. Please refer to your + * SoftDevice Specification for more details about which registers that are protected by SoftDevice. + * This function can write to the following protected peripheral: + * - BPROT + * + * @note Protected registers may be read directly. + * @note Register that are write-once will return @ref NRF_SUCCESS on second set, even the value in + * the register has not changed. See the Product Specification for more details about register + * properties. + * + * @param[in] p_register Pointer to register to be written. + * @param[in] value Value to be written to the register. + * + * @retval ::NRF_ERROR_INVALID_ADDR This function can not write to the reguested register. + * @retval ::NRF_SUCCESS Value successfully written to register. + * + */ +SVCALL(SD_PROTECTED_REGISTER_WRITE, uint32_t, sd_protected_register_write(volatile uint32_t * p_register, uint32_t value)); + +/**@} */ + +#ifdef __cplusplus +} +#endif +#endif // NRF_SOC_H__ + +/**@} */ diff --git a/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_svc.h b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_svc.h new file mode 100755 index 0000000..292c692 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s132_nrf52_6.1.1_API/include/nrf_svc.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_SVC__ +#define NRF_SVC__ + +#include "stdint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SVCALL_AS_NORMAL_FUNCTION +#define SVCALL(number, return_type, signature) return_type signature +#else + +#ifndef SVCALL +#if defined (__CC_ARM) +#define SVCALL(number, return_type, signature) return_type __svc(number) signature +#elif defined (__GNUC__) +#ifdef __cplusplus +#define GCC_CAST_CPP (uint16_t) +#else +#define GCC_CAST_CPP +#endif +#define SVCALL(number, return_type, signature) \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ + __attribute__((naked)) \ + __attribute__((unused)) \ + static return_type signature \ + { \ + __asm( \ + "svc %0\n" \ + "bx r14" : : "I" (GCC_CAST_CPP number) : "r0" \ + ); \ + } \ + _Pragma("GCC diagnostic pop") + +#elif defined (__ICCARM__) +#define PRAGMA(x) _Pragma(#x) +#define SVCALL(number, return_type, signature) \ +PRAGMA(swi_number = (number)) \ + __swi return_type signature; +#else +#define SVCALL(number, return_type, signature) return_type signature +#endif +#endif // SVCALL + +#endif // SVCALL_AS_NORMAL_FUNCTION + +#ifdef __cplusplus +} +#endif +#endif // NRF_SVC__ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble.h new file mode 100755 index 0000000..76a432b --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble.h @@ -0,0 +1,685 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON BLE SoftDevice Common + @{ + @defgroup ble_api Events, type definitions and API calls + @{ + + @brief Module independent events, type definitions and API calls for the BLE SoftDevice. + + */ + +#ifndef BLE_H__ +#define BLE_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_err.h" +#include "ble_gap.h" +#include "ble_l2cap.h" +#include "ble_gatt.h" +#include "ble_gattc.h" +#include "ble_gatts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations + * @{ */ + +/** + * @brief Common API SVC numbers. + */ +enum BLE_COMMON_SVCS +{ + SD_BLE_ENABLE = BLE_SVC_BASE, /**< Enable and initialize the BLE stack */ + SD_BLE_EVT_GET, /**< Get an event from the pending events queue. */ + SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific base UUID. */ + SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */ + SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */ + SD_BLE_VERSION_GET, /**< Get the local version information (company ID, Link Layer Version, Link Layer Subversion). */ + SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */ + SD_BLE_OPT_SET, /**< Set a BLE option. */ + SD_BLE_OPT_GET, /**< Get a BLE option. */ + SD_BLE_CFG_SET, /**< Add a configuration to the BLE stack. */ + SD_BLE_UUID_VS_REMOVE, /**< Remove a Vendor Specific base UUID. */ +}; + +/** + * @brief BLE Module Independent Event IDs. + */ +enum BLE_COMMON_EVTS +{ + BLE_EVT_USER_MEM_REQUEST = BLE_EVT_BASE + 0, /**< User Memory request. @ref ble_evt_user_mem_request_t */ + BLE_EVT_USER_MEM_RELEASE = BLE_EVT_BASE + 1, /**< User Memory release. @ref ble_evt_user_mem_release_t */ +}; + +/**@brief BLE Connection Configuration IDs. + * + * IDs that uniquely identify a connection configuration. + */ +enum BLE_CONN_CFGS +{ + BLE_CONN_CFG_GAP = BLE_CONN_CFG_BASE + 0, /**< BLE GAP specific connection configuration. */ + BLE_CONN_CFG_GATTC = BLE_CONN_CFG_BASE + 1, /**< BLE GATTC specific connection configuration. */ + BLE_CONN_CFG_GATTS = BLE_CONN_CFG_BASE + 2, /**< BLE GATTS specific connection configuration. */ + BLE_CONN_CFG_GATT = BLE_CONN_CFG_BASE + 3, /**< BLE GATT specific connection configuration. */ + BLE_CONN_CFG_L2CAP = BLE_CONN_CFG_BASE + 4, /**< BLE L2CAP specific connection configuration. */ +}; + +/**@brief BLE Common Configuration IDs. + * + * IDs that uniquely identify a common configuration. + */ +enum BLE_COMMON_CFGS +{ + BLE_COMMON_CFG_VS_UUID = BLE_CFG_BASE, /**< Vendor specific base UUID configuration */ +}; + +/**@brief Common Option IDs. + * IDs that uniquely identify a common option. + */ +enum BLE_COMMON_OPTS +{ + BLE_COMMON_OPT_PA_LNA = BLE_OPT_BASE + 0, /**< PA and LNA options */ + BLE_COMMON_OPT_CONN_EVT_EXT = BLE_OPT_BASE + 1, /**< Extended connection events option */ + BLE_COMMON_OPT_EXTENDED_RC_CAL = BLE_OPT_BASE + 2, /**< Extended RC calibration option */ + BLE_COMMON_OPT_ADV_SCHED_CFG = BLE_OPT_BASE + 3, /**< Advertiser role scheduling configuration option */ +}; + +/** @} */ + +/** @addtogroup BLE_COMMON_DEFINES Defines + * @{ */ + +/** @brief Required pointer alignment for BLE Events. +*/ +#define BLE_EVT_PTR_ALIGNMENT 4 + +/** @brief Leaves the maximum of the two arguments. +*/ +#define BLE_MAX(a, b) ((a) < (b) ? (b) : (a)) + +/** @brief Maximum possible length for BLE Events. + * @note The highest value used for @ref ble_gatt_conn_cfg_t::att_mtu in any connection configuration shall be used as a parameter. + * If that value has not been configured for any connections then @ref BLE_GATT_ATT_MTU_DEFAULT must be used instead. +*/ +#define BLE_EVT_LEN_MAX(ATT_MTU) ( \ + offsetof(ble_evt_t, evt.gattc_evt.params.prim_srvc_disc_rsp.services) + ((ATT_MTU) - 1) / 4 * sizeof(ble_gattc_service_t) \ +) + +/** @defgroup ADV_SCHED_CFG Advertiser Role Scheduling Configuration + * @{ */ +#define ADV_SCHED_CFG_DEFAULT 0 /**< Default advertiser role scheduling configuration. */ +#define ADV_SCHED_CFG_IMPROVED 1 /**< Improved advertiser role scheduling configuration in which the housekeeping time is reduced. */ +/** @} */ + +/** @defgroup BLE_USER_MEM_TYPES User Memory Types + * @{ */ +#define BLE_USER_MEM_TYPE_INVALID 0x00 /**< Invalid User Memory Types. */ +#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES 0x01 /**< User Memory for GATTS queued writes. */ +/** @} */ + +/** @defgroup BLE_UUID_VS_COUNTS Vendor Specific base UUID counts + * @{ + */ +#define BLE_UUID_VS_COUNT_DEFAULT 10 /**< Default VS UUID count. */ +#define BLE_UUID_VS_COUNT_MAX 254 /**< Maximum VS UUID count. */ +/** @} */ + +/** @defgroup BLE_COMMON_CFG_DEFAULTS Configuration defaults. + * @{ + */ +#define BLE_CONN_CFG_TAG_DEFAULT 0 /**< Default configuration tag, SoftDevice default connection configuration. */ + +/** @} */ + +/** @} */ + +/** @addtogroup BLE_COMMON_STRUCTURES Structures + * @{ */ + +/**@brief User Memory Block. */ +typedef struct +{ + uint8_t *p_mem; /**< Pointer to the start of the user memory block. */ + uint16_t len; /**< Length in bytes of the user memory block. */ +} ble_user_mem_block_t; + +/**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */ +typedef struct +{ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ +} ble_evt_user_mem_request_t; + +/**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */ +typedef struct +{ + uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ + ble_user_mem_block_t mem_block; /**< User memory block */ +} ble_evt_user_mem_release_t; + +/**@brief Event structure for events not associated with a specific function module. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which this event occurred. */ + union + { + ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */ + ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */ + } params; /**< Event parameter union. */ +} ble_common_evt_t; + +/**@brief BLE Event header. */ +typedef struct +{ + uint16_t evt_id; /**< Value from a BLE_<module>_EVT series. */ + uint16_t evt_len; /**< Length in octets including this header. */ +} ble_evt_hdr_t; + +/**@brief Common BLE Event type, wrapping the module specific event reports. */ +typedef struct +{ + ble_evt_hdr_t header; /**< Event header. */ + union + { + ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ + ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ + ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ + ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ + ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ + } evt; /**< Event union. */ +} ble_evt_t; + + +/** + * @brief Version Information. + */ +typedef struct +{ + uint8_t version_number; /**< Link Layer Version number. See https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer for assigned values. */ + uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ + uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ +} ble_version_t; + +/** + * @brief Configuration parameters for the PA and LNA. + */ +typedef struct +{ + uint8_t enable :1; /**< Enable toggling for this amplifier */ + uint8_t active_high :1; /**< Set the pin to be active high */ + uint8_t gpio_pin :6; /**< The GPIO pin to toggle for this amplifier */ +} ble_pa_lna_cfg_t; + +/** + * @brief PA & LNA GPIO toggle configuration + * + * This option configures the SoftDevice to toggle pins when the radio is active for use with a power amplifier and/or + * a low noise amplifier. + * + * Toggling the pins is achieved by using two PPI channels and a GPIOTE channel. The hardware channel IDs are provided + * by the application and should be regarded as reserved as long as any PA/LNA toggling is enabled. + * + * @note @ref sd_ble_opt_get is not supported for this option. + * @note Setting this option while the radio is in use (i.e. any of the roles are active) may have undefined consequences + * and must be avoided by the application. + */ +typedef struct +{ + ble_pa_lna_cfg_t pa_cfg; /**< Power Amplifier configuration */ + ble_pa_lna_cfg_t lna_cfg; /**< Low Noise Amplifier configuration */ + + uint8_t ppi_ch_id_set; /**< PPI channel used for radio pin setting */ + uint8_t ppi_ch_id_clr; /**< PPI channel used for radio pin clearing */ + uint8_t gpiote_ch_id; /**< GPIOTE channel used for radio pin toggling */ +} ble_common_opt_pa_lna_t; + +/** + * @brief Configuration of extended BLE connection events. + * + * When enabled the SoftDevice will dynamically extend the connection event when possible. + * + * The connection event length is controlled by the connection configuration as set by @ref ble_gap_conn_cfg_t::event_length. + * The connection event can be extended if there is time to send another packet pair before the start of the next connection interval, + * and if there are no conflicts with other BLE roles requesting radio time. + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */ +} ble_common_opt_conn_evt_ext_t; + +/** + * @brief Enable/disable extended RC calibration. + * + * If extended RC calibration is enabled and the internal RC oscillator (@ref NRF_CLOCK_LF_SRC_RC) is used as the SoftDevice + * LFCLK source, the SoftDevice as a peripheral will by default try to increase the receive window if two consecutive packets + * are not received. If it turns out that the packets were not received due to clock drift, the RC calibration is started. + * This calibration comes in addition to the periodic calibration that is configured by @ref sd_softdevice_enable(). When + * using only peripheral connections, the periodic calibration can therefore be configured with a much longer interval as the + * peripheral will be able to detect and adjust automatically to clock drift, and calibrate on demand. + * + * If extended RC calibration is disabled and the internal RC oscillator is used as the SoftDevice LFCLK source, the + * RC oscillator is calibrated periodically as configured by @ref sd_softdevice_enable(). + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable extended RC calibration, enabled by default. */ +} ble_common_opt_extended_rc_cal_t; + +/** + * @brief Configuration of BLE advertiser role scheduling. + * + * @note @ref sd_ble_opt_get is not supported for this option. + */ +typedef struct +{ + uint8_t sched_cfg; /**< See @ref ADV_SCHED_CFG. */ +} ble_common_opt_adv_sched_cfg_t; + +/**@brief Option structure for common options. */ +typedef union +{ + ble_common_opt_pa_lna_t pa_lna; /**< Parameters for controlling PA and LNA pin toggling. */ + ble_common_opt_conn_evt_ext_t conn_evt_ext; /**< Parameters for enabling extended connection events. */ + ble_common_opt_extended_rc_cal_t extended_rc_cal; /**< Parameters for enabling extended RC calibration. */ + ble_common_opt_adv_sched_cfg_t adv_sched_cfg; /**< Parameters for configuring advertiser role scheduling. */ +} ble_common_opt_t; + +/**@brief Common BLE Option type, wrapping the module specific options. */ +typedef union +{ + ble_common_opt_t common_opt; /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */ + ble_gap_opt_t gap_opt; /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */ +} ble_opt_t; + +/**@brief BLE connection configuration type, wrapping the module specific configurations, set with + * @ref sd_ble_cfg_set. + * + * @note Connection configurations don't have to be set. + * In the case that no configurations has been set, or fewer connection configurations has been set than enabled connections, + * the default connection configuration will be automatically added for the remaining connections. + * When creating connections with the default configuration, @ref BLE_CONN_CFG_TAG_DEFAULT should be used in + * place of @ref ble_conn_cfg_t::conn_cfg_tag. + * + * @sa sd_ble_gap_adv_start() + * @sa sd_ble_gap_connect() + * + * @mscs + * @mmsc{@ref BLE_CONN_CFG} + * @endmscs + + */ +typedef struct +{ + uint8_t conn_cfg_tag; /**< The application chosen tag it can use with the + @ref sd_ble_gap_adv_start() and @ref sd_ble_gap_connect() calls + to select this configuration when creating a connection. + Must be different for all connection configurations added and not @ref BLE_CONN_CFG_TAG_DEFAULT. */ + union { + ble_gap_conn_cfg_t gap_conn_cfg; /**< GAP connection configuration, cfg_id is @ref BLE_CONN_CFG_GAP. */ + ble_gattc_conn_cfg_t gattc_conn_cfg; /**< GATTC connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTC. */ + ble_gatts_conn_cfg_t gatts_conn_cfg; /**< GATTS connection configuration, cfg_id is @ref BLE_CONN_CFG_GATTS. */ + ble_gatt_conn_cfg_t gatt_conn_cfg; /**< GATT connection configuration, cfg_id is @ref BLE_CONN_CFG_GATT. */ + ble_l2cap_conn_cfg_t l2cap_conn_cfg; /**< L2CAP connection configuration, cfg_id is @ref BLE_CONN_CFG_L2CAP. */ + } params; /**< Connection configuration union. */ +} ble_conn_cfg_t; + +/** + * @brief Configuration of Vendor Specific base UUIDs, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_PARAM Too many UUIDs configured. + */ +typedef struct +{ + uint8_t vs_uuid_count; /**< Number of 128-bit Vendor Specific base UUID bases to allocate memory for. + Default value is @ref BLE_UUID_VS_COUNT_DEFAULT. Maximum value is + @ref BLE_UUID_VS_COUNT_MAX. */ +} ble_common_cfg_vs_uuid_t; + +/**@brief Common BLE Configuration type, wrapping the common configurations. */ +typedef union +{ + ble_common_cfg_vs_uuid_t vs_uuid_cfg; /**< Vendor Specific base UUID configuration, cfg_id is @ref BLE_COMMON_CFG_VS_UUID. */ +} ble_common_cfg_t; + +/**@brief BLE Configuration type, wrapping the module specific configurations. */ +typedef union +{ + ble_conn_cfg_t conn_cfg; /**< Connection specific configurations, cfg_id in @ref BLE_CONN_CFGS series. */ + ble_common_cfg_t common_cfg; /**< Global common configurations, cfg_id in @ref BLE_COMMON_CFGS series. */ + ble_gap_cfg_t gap_cfg; /**< Global GAP configurations, cfg_id in @ref BLE_GAP_CFGS series. */ + ble_gatts_cfg_t gatts_cfg; /**< Global GATTS configuration, cfg_id in @ref BLE_GATTS_CFGS series. */ +} ble_cfg_t; + +/** @} */ + +/** @addtogroup BLE_COMMON_FUNCTIONS Functions + * @{ */ + +/**@brief Enable the BLE stack + * + * @param[in, out] p_app_ram_base Pointer to a variable containing the start address of the + * application RAM region (APP_RAM_BASE). On return, this will + * contain the minimum start address of the application RAM region + * required by the SoftDevice for this configuration. + * + * @note The memory requirement for a specific configuration will not increase between SoftDevices + * with the same major version number. + * + * @note At runtime the IC's RAM is split into 2 regions: The SoftDevice RAM region is located + * between 0x20000000 and APP_RAM_BASE-1 and the application's RAM region is located between + * APP_RAM_BASE and the start of the call stack. + * + * @details This call initializes the BLE stack, no BLE related function other than @ref + * sd_ble_cfg_set can be called before this one. + * + * @mscs + * @mmsc{@ref BLE_COMMON_ENABLE} + * @endmscs + * + * @retval ::NRF_SUCCESS The BLE stack has been initialized successfully. + * @retval ::NRF_ERROR_INVALID_STATE The BLE stack had already been initialized and cannot be reinitialized. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_NO_MEM One or more of the following is true: + * - The amount of memory assigned to the SoftDevice by *p_app_ram_base is not + * large enough to fit this configuration's memory requirement. Check *p_app_ram_base + * and set the start address of the application RAM region accordingly. + * - Dynamic part of the SoftDevice RAM region is larger then 64 kB which + * is currently not supported. + * @retval ::NRF_ERROR_RESOURCES The total number of L2CAP Channels configured using @ref sd_ble_cfg_set is too large. + */ +SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(uint32_t * p_app_ram_base)); + +/**@brief Add configurations for the BLE stack + * + * @param[in] cfg_id Config ID, see @ref BLE_CONN_CFGS, @ref BLE_COMMON_CFGS, @ref + * BLE_GAP_CFGS or @ref BLE_GATTS_CFGS. + * @param[in] p_cfg Pointer to a ble_cfg_t structure containing the configuration value. + * @param[in] app_ram_base The start address of the application RAM region (APP_RAM_BASE). + * See @ref sd_ble_enable for details about APP_RAM_BASE. + * + * @note The memory requirement for a specific configuration will not increase between SoftDevices + * with the same major version number. + * + * @note If a configuration is set more than once, the last one set is the one that takes effect on + * @ref sd_ble_enable. + * + * @note Any part of the BLE stack that is NOT configured with @ref sd_ble_cfg_set will have default + * configuration. + * + * @note @ref sd_ble_cfg_set may be called at any time when the SoftDevice is enabled (see @ref + * sd_softdevice_enable) while the BLE part of the SoftDevice is not enabled (see @ref + * sd_ble_enable). + * + * @note Error codes for the configurations are described in the configuration structs. + * + * @mscs + * @mmsc{@ref BLE_COMMON_ENABLE} + * @endmscs + * + * @retval ::NRF_SUCCESS The configuration has been added successfully. + * @retval ::NRF_ERROR_INVALID_STATE The BLE stack had already been initialized. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid cfg_id supplied. + * @retval ::NRF_ERROR_NO_MEM The amount of memory assigned to the SoftDevice by app_ram_base is not + * large enough to fit this configuration's memory requirement. + */ +SVCALL(SD_BLE_CFG_SET, uint32_t, sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * p_cfg, uint32_t app_ram_base)); + +/**@brief Get an event from the pending events queue. + * + * @param[out] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length. + * This buffer <b>must be aligned to the extend defined by @ref BLE_EVT_PTR_ALIGNMENT</b>. + * The buffer should be interpreted as a @ref ble_evt_t struct. + * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length. + * + * @details This call allows the application to pull a BLE event from the BLE stack. The application is signaled that + * an event is available from the BLE stack by the triggering of the SD_EVT_IRQn interrupt. + * The application is free to choose whether to call this function from thread mode (main context) or directly from the + * Interrupt Service Routine that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher + * priority than the application, this function should be called in a loop (until @ref NRF_ERROR_NOT_FOUND is returned) + * every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the BLE stack. Failure to do so + * could potentially leave events in the internal queue without the application being aware of this fact. + * + * Sizing the p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to + * be copied into application memory. If the buffer provided is not large enough to fit the entire contents of the event, + * @ref NRF_ERROR_DATA_SIZE will be returned and the application can then call again with a larger buffer size. + * The maximum possible event length is defined by @ref BLE_EVT_LEN_MAX. The application may also "peek" the event length + * by providing p_dest as a NULL pointer and inspecting the value of *p_len upon return: + * + * \code + * uint16_t len; + * errcode = sd_ble_evt_get(NULL, &len); + * \endcode + * + * @mscs + * @mmsc{@ref BLE_COMMON_IRQ_EVT_MSC} + * @mmsc{@ref BLE_COMMON_THREAD_EVT_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. + * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled. + * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer. + */ +SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len)); + + +/**@brief Add a Vendor Specific base UUID. + * + * @details This call enables the application to add a Vendor Specific base UUID to the BLE stack's table, for later + * use with all other modules and APIs. This then allows the application to use the shorter, 24-bit @ref ble_uuid_t + * format when dealing with both 16-bit and 128-bit UUIDs without having to check for lengths and having split code + * paths. This is accomplished by extending the grouping mechanism that the Bluetooth SIG standard base UUID uses + * for all other 128-bit UUIDs. The type field in the @ref ble_uuid_t structure is an index (relative to + * @ref BLE_UUID_TYPE_VENDOR_BEGIN) to the table populated by multiple calls to this function, and the UUID field + * in the same structure contains the 2 bytes at indexes 12 and 13. The number of possible 128-bit UUIDs available to + * the application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536, + * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array. + * + * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by + * the 16-bit uuid field in @ref ble_uuid_t. + * + * @note If a UUID is already present in the BLE stack's internal table, the corresponding index will be returned in + * p_uuid_type along with an @ref NRF_SUCCESS error code. + * + * @param[in] p_vs_uuid Pointer to a 16-octet (128-bit) little endian Vendor Specific base UUID disregarding + * bytes 12 and 13. + * @param[out] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponding to this UUID will be stored. + * + * @retval ::NRF_SUCCESS Successfully added the Vendor Specific base UUID. + * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid. + * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs. + */ +SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type)); + + +/**@brief Remove a Vendor Specific base UUID. + * + * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows + * the application to reuse memory allocated for Vendor Specific base UUIDs. + * + * @note Currently this function can only be called with a p_uuid_type set to @ref BLE_UUID_TYPE_UNKNOWN or the last added UUID type. + * + * @param[in] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t::type corresponds to the UUID type that + * shall be removed. If the type is set to @ref BLE_UUID_TYPE_UNKNOWN, or the pointer is NULL, the last + * Vendor Specific base UUID will be removed. + * @param[out] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponds to the UUID type that was + * removed. If function returns with a failure, it contains the last type that is in use by the ATT Server. + * + * @retval ::NRF_SUCCESS Successfully removed the Vendor Specific base UUID. + * @retval ::NRF_ERROR_INVALID_ADDR If p_uuid_type is invalid. + * @retval ::NRF_ERROR_INVALID_PARAM If p_uuid_type points to a non-valid UUID type. + * @retval ::NRF_ERROR_FORBIDDEN If the Vendor Specific base UUID is in use by the ATT Server. + */ + +SVCALL(SD_BLE_UUID_VS_REMOVE, uint32_t, sd_ble_uuid_vs_remove(uint8_t *p_uuid_type)); + + +/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure. + * + * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared + * to the corresponding ones in each entry of the table of Vendor Specific base UUIDs populated with @ref sd_ble_uuid_vs_add + * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index + * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type. + * + * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE. + * + * @param[in] uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes). + * @param[in] p_uuid_le Pointer pointing to little endian raw UUID bytes. + * @param[out] p_uuid Pointer to a @ref ble_uuid_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length. + * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs. + */ +SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid)); + + +/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit). + * + * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed. + * + * @param[in] p_uuid Pointer to a @ref ble_uuid_t structure that will be encoded into bytes. + * @param[out] p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes). + * @param[out] p_uuid_le Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored. + * + * @retval ::NRF_SUCCESS Successfully encoded into the buffer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type. + */ +SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le)); + + +/**@brief Get Version Information. + * + * @details This call allows the application to get the BLE stack version information. + * + * @param[out] p_version Pointer to a ble_version_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Version information stored successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure). + */ +SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version)); + + +/**@brief Provide a user memory block. + * + * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application. + * + * @param[in] conn_handle Connection handle. + * @param[in] p_block Pointer to a user memory block structure or NULL if memory is managed by the application. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_PEER_CANCEL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully queued a response to the peer. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid user memory block length supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection state or no user memory request pending. + */ +SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block)); + +/**@brief Set a BLE option. + * + * @details This call allows the application to set the value of an option. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC} + * @endmscs + * + * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS. + * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value. + * + * @retval ::NRF_SUCCESS Option set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed. + */ +SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt)); + + +/**@brief Get a BLE option. + * + * @details This call allows the application to retrieve the value of an option. + * + * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS. + * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Option retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed. + * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported. + * + */ +SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt)); + +/** @} */ +#ifdef __cplusplus +} +#endif +#endif /* BLE_H__ */ + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_err.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_err.h new file mode 100755 index 0000000..1b4820d --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_err.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @addtogroup nrf_error + @{ + @ingroup BLE_COMMON + @} + + @defgroup ble_err General error codes + @{ + + @brief General error code definitions for the BLE API. + + @ingroup BLE_COMMON +*/ +#ifndef NRF_BLE_ERR_H__ +#define NRF_BLE_ERR_H__ + +#include "nrf_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* @defgroup BLE_ERRORS Error Codes + * @{ */ +#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */ +#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */ +#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */ +#define BLE_ERROR_INVALID_ADV_HANDLE (NRF_ERROR_STK_BASE_NUM+0x004) /**< Invalid advertising handle. */ +#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */ +#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM+0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */ +/** @} */ + + +/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges + * @brief Assignment of subranges for module specific error codes. + * @note For specific error codes, see ble_<module>.h or ble_error_<module>.h. + * @{ */ +#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */ +#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */ +#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */ +#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */ +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif + + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gap.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gap.h new file mode 100755 index 0000000..c434fef --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gap.h @@ -0,0 +1,2696 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GAP Generic Access Profile (GAP) + @{ + @brief Definitions and prototypes for the GAP interface. + */ + +#ifndef BLE_GAP_H__ +#define BLE_GAP_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations + * @{ */ + +/**@brief GAP API SVC numbers. + */ +enum BLE_GAP_SVCS +{ + SD_BLE_GAP_ADDR_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ + SD_BLE_GAP_ADDR_GET = BLE_GAP_SVC_BASE + 1, /**< Get own Bluetooth Address. */ + SD_BLE_GAP_WHITELIST_SET = BLE_GAP_SVC_BASE + 2, /**< Set active whitelist. */ + SD_BLE_GAP_DEVICE_IDENTITIES_SET = BLE_GAP_SVC_BASE + 3, /**< Set device identity list. */ + SD_BLE_GAP_PRIVACY_SET = BLE_GAP_SVC_BASE + 4, /**< Set Privacy settings*/ + SD_BLE_GAP_PRIVACY_GET = BLE_GAP_SVC_BASE + 5, /**< Get Privacy settings*/ + SD_BLE_GAP_ADV_SET_CONFIGURE = BLE_GAP_SVC_BASE + 6, /**< Configure an advertising set. */ + SD_BLE_GAP_ADV_START = BLE_GAP_SVC_BASE + 7, /**< Start Advertising. */ + SD_BLE_GAP_ADV_STOP = BLE_GAP_SVC_BASE + 8, /**< Stop Advertising. */ + SD_BLE_GAP_CONN_PARAM_UPDATE = BLE_GAP_SVC_BASE + 9, /**< Connection Parameter Update. */ + SD_BLE_GAP_DISCONNECT = BLE_GAP_SVC_BASE + 10, /**< Disconnect. */ + SD_BLE_GAP_TX_POWER_SET = BLE_GAP_SVC_BASE + 11, /**< Set TX Power. */ + SD_BLE_GAP_APPEARANCE_SET = BLE_GAP_SVC_BASE + 12, /**< Set Appearance. */ + SD_BLE_GAP_APPEARANCE_GET = BLE_GAP_SVC_BASE + 13, /**< Get Appearance. */ + SD_BLE_GAP_PPCP_SET = BLE_GAP_SVC_BASE + 14, /**< Set PPCP. */ + SD_BLE_GAP_PPCP_GET = BLE_GAP_SVC_BASE + 15, /**< Get PPCP. */ + SD_BLE_GAP_DEVICE_NAME_SET = BLE_GAP_SVC_BASE + 16, /**< Set Device Name. */ + SD_BLE_GAP_DEVICE_NAME_GET = BLE_GAP_SVC_BASE + 17, /**< Get Device Name. */ + SD_BLE_GAP_AUTHENTICATE = BLE_GAP_SVC_BASE + 18, /**< Initiate Pairing/Bonding. */ + SD_BLE_GAP_SEC_PARAMS_REPLY = BLE_GAP_SVC_BASE + 19, /**< Reply with Security Parameters. */ + SD_BLE_GAP_AUTH_KEY_REPLY = BLE_GAP_SVC_BASE + 20, /**< Reply with an authentication key. */ + SD_BLE_GAP_LESC_DHKEY_REPLY = BLE_GAP_SVC_BASE + 21, /**< Reply with an LE Secure Connections DHKey. */ + SD_BLE_GAP_KEYPRESS_NOTIFY = BLE_GAP_SVC_BASE + 22, /**< Notify of a keypress during an authentication procedure. */ + SD_BLE_GAP_LESC_OOB_DATA_GET = BLE_GAP_SVC_BASE + 23, /**< Get the local LE Secure Connections OOB data. */ + SD_BLE_GAP_LESC_OOB_DATA_SET = BLE_GAP_SVC_BASE + 24, /**< Set the remote LE Secure Connections OOB data. */ + SD_BLE_GAP_ENCRYPT = BLE_GAP_SVC_BASE + 25, /**< Initiate encryption procedure. */ + SD_BLE_GAP_SEC_INFO_REPLY = BLE_GAP_SVC_BASE + 26, /**< Reply with Security Information. */ + SD_BLE_GAP_CONN_SEC_GET = BLE_GAP_SVC_BASE + 27, /**< Obtain connection security level. */ + SD_BLE_GAP_RSSI_START = BLE_GAP_SVC_BASE + 28, /**< Start reporting of changes in RSSI. */ + SD_BLE_GAP_RSSI_STOP = BLE_GAP_SVC_BASE + 29, /**< Stop reporting of changes in RSSI. */ + SD_BLE_GAP_SCAN_START = BLE_GAP_SVC_BASE + 30, /**< Start Scanning. */ + SD_BLE_GAP_SCAN_STOP = BLE_GAP_SVC_BASE + 31, /**< Stop Scanning. */ + SD_BLE_GAP_CONNECT = BLE_GAP_SVC_BASE + 32, /**< Connect. */ + SD_BLE_GAP_CONNECT_CANCEL = BLE_GAP_SVC_BASE + 33, /**< Cancel ongoing connection procedure. */ + SD_BLE_GAP_RSSI_GET = BLE_GAP_SVC_BASE + 34, /**< Get the last RSSI sample. */ + SD_BLE_GAP_PHY_UPDATE = BLE_GAP_SVC_BASE + 35, /**< Initiate or respond to a PHY Update Procedure. */ + SD_BLE_GAP_DATA_LENGTH_UPDATE = BLE_GAP_SVC_BASE + 36, /**< Initiate or respond to a Data Length Update Procedure. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_START = BLE_GAP_SVC_BASE + 37, /**< Start Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP = BLE_GAP_SVC_BASE + 38, /**< Stop Quality of Service (QoS) channel survey module. */ + SD_BLE_GAP_ADV_ADDR_GET = BLE_GAP_SVC_BASE + 39, /**< Get the Address used on air while Advertising. */ +}; + +/**@brief GAP Event IDs. + * IDs that uniquely identify an event coming from the stack to the application. + */ +enum BLE_GAP_EVTS +{ + BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connected to peer. \n See @ref ble_gap_evt_connected_t */ + BLE_GAP_EVT_DISCONNECTED = BLE_GAP_EVT_BASE + 1, /**< Disconnected from peer. \n See @ref ble_gap_evt_disconnected_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE = BLE_GAP_EVT_BASE + 2, /**< Connection Parameters updated. \n See @ref ble_gap_evt_conn_param_update_t. */ + BLE_GAP_EVT_SEC_PARAMS_REQUEST = BLE_GAP_EVT_BASE + 3, /**< Request to provide security parameters. \n Reply with @ref sd_ble_gap_sec_params_reply. \n See @ref ble_gap_evt_sec_params_request_t. */ + BLE_GAP_EVT_SEC_INFO_REQUEST = BLE_GAP_EVT_BASE + 4, /**< Request to provide security information. \n Reply with @ref sd_ble_gap_sec_info_reply. \n See @ref ble_gap_evt_sec_info_request_t. */ + BLE_GAP_EVT_PASSKEY_DISPLAY = BLE_GAP_EVT_BASE + 5, /**< Request to display a passkey to the user. \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */ + BLE_GAP_EVT_KEY_PRESSED = BLE_GAP_EVT_BASE + 6, /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t */ + BLE_GAP_EVT_AUTH_KEY_REQUEST = BLE_GAP_EVT_BASE + 7, /**< Request to provide an authentication key. \n Reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_auth_key_request_t. */ + BLE_GAP_EVT_LESC_DHKEY_REQUEST = BLE_GAP_EVT_BASE + 8, /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply. \n See @ref ble_gap_evt_lesc_dhkey_request_t */ + BLE_GAP_EVT_AUTH_STATUS = BLE_GAP_EVT_BASE + 9, /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t. */ + BLE_GAP_EVT_CONN_SEC_UPDATE = BLE_GAP_EVT_BASE + 10, /**< Connection security updated. \n See @ref ble_gap_evt_conn_sec_update_t. */ + BLE_GAP_EVT_TIMEOUT = BLE_GAP_EVT_BASE + 11, /**< Timeout expired. \n See @ref ble_gap_evt_timeout_t. */ + BLE_GAP_EVT_RSSI_CHANGED = BLE_GAP_EVT_BASE + 12, /**< RSSI report. \n See @ref ble_gap_evt_rssi_changed_t. */ + BLE_GAP_EVT_ADV_REPORT = BLE_GAP_EVT_BASE + 13, /**< Advertising report. \n See @ref ble_gap_evt_adv_report_t. */ + BLE_GAP_EVT_SEC_REQUEST = BLE_GAP_EVT_BASE + 14, /**< Security Request. \n See @ref ble_gap_evt_sec_request_t. */ + BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 15, /**< Connection Parameter Update Request. \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */ + BLE_GAP_EVT_SCAN_REQ_REPORT = BLE_GAP_EVT_BASE + 16, /**< Scan request report. \n See @ref ble_gap_evt_scan_req_report_t. */ + BLE_GAP_EVT_PHY_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 17, /**< PHY Update Request. \n Reply with @ref sd_ble_gap_phy_update. \n See @ref ble_gap_evt_phy_update_request_t. */ + BLE_GAP_EVT_PHY_UPDATE = BLE_GAP_EVT_BASE + 18, /**< PHY Update Procedure is complete. \n See @ref ble_gap_evt_phy_update_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST = BLE_GAP_EVT_BASE + 19, /**< Data Length Update Request. \n Reply with @ref sd_ble_gap_data_length_update.\n See @ref ble_gap_evt_data_length_update_request_t. */ + BLE_GAP_EVT_DATA_LENGTH_UPDATE = BLE_GAP_EVT_BASE + 20, /**< LL Data Channel PDU payload length updated. \n See @ref ble_gap_evt_data_length_update_t. */ + BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT = BLE_GAP_EVT_BASE + 21, /**< Channel survey report. \n See @ref ble_gap_evt_qos_channel_survey_report_t. */ + BLE_GAP_EVT_ADV_SET_TERMINATED = BLE_GAP_EVT_BASE + 22, /**< Advertising set terminated. \n See @ref ble_gap_evt_adv_set_terminated_t. */ +}; + +/**@brief GAP Option IDs. + * IDs that uniquely identify a GAP option. + */ +enum BLE_GAP_OPTS +{ + BLE_GAP_OPT_CH_MAP = BLE_GAP_OPT_BASE, /**< Channel Map. @ref ble_gap_opt_ch_map_t */ + BLE_GAP_OPT_LOCAL_CONN_LATENCY = BLE_GAP_OPT_BASE + 1, /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */ + BLE_GAP_OPT_PASSKEY = BLE_GAP_OPT_BASE + 2, /**< Set passkey. @ref ble_gap_opt_passkey_t */ + BLE_GAP_OPT_COMPAT_MODE_1 = BLE_GAP_OPT_BASE + 3, /**< Compatibility mode. @ref ble_gap_opt_compat_mode_1_t */ + BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT = BLE_GAP_OPT_BASE + 4, /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */ + BLE_GAP_OPT_SLAVE_LATENCY_DISABLE = BLE_GAP_OPT_BASE + 5, /**< Disable slave latency. @ref ble_gap_opt_slave_latency_disable_t */ +}; + +/**@brief GAP Configuration IDs. + * + * IDs that uniquely identify a GAP configuration. + */ +enum BLE_GAP_CFGS +{ + BLE_GAP_CFG_ROLE_COUNT = BLE_GAP_CFG_BASE, /**< Role count configuration. */ + BLE_GAP_CFG_DEVICE_NAME = BLE_GAP_CFG_BASE + 1, /**< Device name configuration. */ +}; + +/**@brief GAP TX Power roles. + */ +enum BLE_GAP_TX_POWER_ROLES +{ + BLE_GAP_TX_POWER_ROLE_ADV = 1, /**< Advertiser role. */ + BLE_GAP_TX_POWER_ROLE_SCAN_INIT = 2, /**< Scanner and initiator role. */ + BLE_GAP_TX_POWER_ROLE_CONN = 3, /**< Connection role. */ +}; + +/** @} */ + +/**@addtogroup BLE_GAP_DEFINES Defines + * @{ */ + +/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP + * @{ */ +#define BLE_ERROR_GAP_UUID_LIST_MISMATCH (NRF_GAP_ERR_BASE + 0x000) /**< UUID list does not contain an integral number of UUIDs. */ +#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST (NRF_GAP_ERR_BASE + 0x001) /**< Use of Whitelist not permitted with discoverable advertising. */ +#define BLE_ERROR_GAP_INVALID_BLE_ADDR (NRF_GAP_ERR_BASE + 0x002) /**< The upper two bits of the address do not correspond to the specified address type. */ +#define BLE_ERROR_GAP_WHITELIST_IN_USE (NRF_GAP_ERR_BASE + 0x003) /**< Attempt to modify the whitelist while already in use by another operation. */ +#define BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE (NRF_GAP_ERR_BASE + 0x004) /**< Attempt to modify the device identity list while already in use by another operation. */ +#define BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE (NRF_GAP_ERR_BASE + 0x005) /**< The device identity list contains entries with duplicate identity addresses. */ +/**@} */ + + +/**@defgroup BLE_GAP_ROLES GAP Roles + * @{ */ +#define BLE_GAP_ROLE_INVALID 0x0 /**< Invalid Role. */ +#define BLE_GAP_ROLE_PERIPH 0x1 /**< Peripheral Role. */ +#define BLE_GAP_ROLE_CENTRAL 0x2 /**< Central Role. */ +/**@} */ + + +/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources + * @{ */ +#define BLE_GAP_TIMEOUT_SRC_SCAN 0x01 /**< Scanning timeout. */ +#define BLE_GAP_TIMEOUT_SRC_CONN 0x02 /**< Connection timeout. */ +#define BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD 0x03 /**< Authenticated payload timeout. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types + * @{ */ +#define BLE_GAP_ADDR_TYPE_PUBLIC 0x00 /**< Public (identity) address.*/ +#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC 0x01 /**< Random static (identity) address. */ +#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE 0x02 /**< Random private resolvable address. */ +#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Random private non-resolvable address. */ +#define BLE_GAP_ADDR_TYPE_ANONYMOUS 0x7F /**< An advertiser may advertise without its address. + This type of advertising is called anonymous. */ +/**@} */ + + +/**@brief The default interval in seconds at which a private address is refreshed. */ +#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (900) /* 15 minutes. */ +/**@brief The maximum interval in seconds at which a private address can be refreshed. */ +#define BLE_GAP_MAX_PRIVATE_ADDR_CYCLE_INTERVAL_S (41400) /* 11 hours 30 minutes. */ + + +/** @brief BLE address length. */ +#define BLE_GAP_ADDR_LEN (6) + +/**@defgroup BLE_GAP_PRIVACY_MODES Privacy modes + * @{ */ +#define BLE_GAP_PRIVACY_MODE_OFF 0x00 /**< Device will send and accept its identity address for its own address. */ +#define BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY 0x01 /**< Device will send and accept only private addresses for its own address. */ +#define BLE_GAP_PRIVACY_MODE_NETWORK_PRIVACY 0x02 /**< Device will send and accept only private addresses for its own address, + and will not accept a peer using identity address as sender address when + the peer IRK is exchanged, non-zero and added to the identity list. */ +/**@} */ + +/** @brief Invalid power level. */ +#define BLE_GAP_POWER_LEVEL_INVALID 127 + +/** @brief Advertising set handle not set. */ +#define BLE_GAP_ADV_SET_HANDLE_NOT_SET (0xFF) + +/** @brief The default number of advertising sets. */ +#define BLE_GAP_ADV_SET_COUNT_DEFAULT (1) + +/** @brief The maximum number of advertising sets supported by this SoftDevice. */ +#define BLE_GAP_ADV_SET_COUNT_MAX (1) + +/**@defgroup BLE_GAP_ADV_SET_DATA_SIZES Advertising data sizes. + * @{ */ +#define BLE_GAP_ADV_SET_DATA_SIZE_MAX (31) /**< Maximum data length for an advertising set. + If more advertising data is required, use extended advertising instead. */ +#define BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED (255) /**< Maximum supported data length for an extended advertising set. */ + +#define BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_CONNECTABLE_MAX_SUPPORTED (238) /**< Maximum supported data length for an extended connectable advertising set. */ +/**@}. */ + +/** @brief Set ID not available in advertising report. */ +#define BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE 0xFF + +/**@defgroup BLE_GAP_EVT_ADV_SET_TERMINATED_REASON GAP Advertising Set Terminated reasons + * @{ */ +#define BLE_GAP_EVT_ADV_SET_TERMINATED_REASON_TIMEOUT 0x01 /**< Timeout value reached. */ +#define BLE_GAP_EVT_ADV_SET_TERMINATED_REASON_LIMIT_REACHED 0x02 /**< @ref ble_gap_adv_params_t::max_adv_evts was reached. */ +/**@} */ + +/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format + * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm + * @{ */ +#define BLE_GAP_AD_TYPE_FLAGS 0x01 /**< Flags for discoverability. */ +#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE 0x02 /**< Partial list of 16 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE 0x03 /**< Complete list of 16 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE 0x04 /**< Partial list of 32 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE 0x05 /**< Complete list of 32 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE 0x06 /**< Partial list of 128 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE 0x07 /**< Complete list of 128 bit service UUIDs. */ +#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME 0x08 /**< Short local device name. */ +#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME 0x09 /**< Complete local device name. */ +#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL 0x0A /**< Transmit power level. */ +#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE 0x0D /**< Class of device. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C 0x0E /**< Simple Pairing Hash C. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R 0x0F /**< Simple Pairing Randomizer R. */ +#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE 0x10 /**< Security Manager TK Value. */ +#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS 0x11 /**< Security Manager Out Of Band Flags. */ +#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 /**< Slave Connection Interval Range. */ +#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT 0x14 /**< List of 16-bit Service Solicitation UUIDs. */ +#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT 0x15 /**< List of 128-bit Service Solicitation UUIDs. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA 0x16 /**< Service Data - 16-bit UUID. */ +#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS 0x17 /**< Public Target Address. */ +#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS 0x18 /**< Random Target Address. */ +#define BLE_GAP_AD_TYPE_APPEARANCE 0x19 /**< Appearance. */ +#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL 0x1A /**< Advertising Interval. */ +#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B /**< LE Bluetooth Device Address. */ +#define BLE_GAP_AD_TYPE_LE_ROLE 0x1C /**< LE Role. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256 0x1D /**< Simple Pairing Hash C-256. */ +#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256 0x1E /**< Simple Pairing Randomizer R-256. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID 0x20 /**< Service Data - 32-bit UUID. */ +#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID 0x21 /**< Service Data - 128-bit UUID. */ +#define BLE_GAP_AD_TYPE_LESC_CONFIRMATION_VALUE 0x22 /**< LE Secure Connections Confirmation Value */ +#define BLE_GAP_AD_TYPE_LESC_RANDOM_VALUE 0x23 /**< LE Secure Connections Random Value */ +#define BLE_GAP_AD_TYPE_URI 0x24 /**< URI */ +#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA 0x3D /**< 3D Information Data. */ +#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA 0xFF /**< Manufacturer Specific Data. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags + * @{ */ +#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE (0x01) /**< LE Limited Discoverable Mode. */ +#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE (0x02) /**< LE General Discoverable Mode. */ +#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED (0x04) /**< BR/EDR not supported. */ +#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER (0x08) /**< Simultaneous LE and BR/EDR, Controller. */ +#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST (0x10) /**< Simultaneous LE and BR/EDR, Host. */ +#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE Limited Discoverable Mode, BR/EDR not supported. */ +#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE General Discoverable Mode, BR/EDR not supported. */ +/**@} */ + + +/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min + * @{ */ +#define BLE_GAP_ADV_INTERVAL_MIN 0x000020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */ +#define BLE_GAP_ADV_INTERVAL_MAX 0x004000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */ + /**@} */ + + +/**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min + * @{ */ +#define BLE_GAP_SCAN_INTERVAL_MIN 0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */ +#define BLE_GAP_SCAN_INTERVAL_MAX 0xFFFF /**< Maximum Scan interval in 625 us units, i.e. 40,959.375 s. */ + /** @} */ + + +/**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min + * @{ */ +#define BLE_GAP_SCAN_WINDOW_MIN 0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */ +#define BLE_GAP_SCAN_WINDOW_MAX 0xFFFF /**< Maximum Scan window in 625 us units, i.e. 40,959.375 s. */ + /** @} */ + + +/**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min + * @{ */ +#define BLE_GAP_SCAN_TIMEOUT_MIN 0x0001 /**< Minimum Scan timeout in 10 ms units, i.e 10 ms. */ +#define BLE_GAP_SCAN_TIMEOUT_UNLIMITED 0x0000 /**< Continue to scan forever. */ + /** @} */ + +/**@defgroup BLE_GAP_SCAN_BUFFER_SIZE GAP Minimum scanner buffer size + * + * Scan buffers are used for storing advertising data received from an advertiser. + * If ble_gap_scan_params_t::extended is set to 0, @ref BLE_GAP_SCAN_BUFFER_MIN is the minimum scan buffer length. + * else the minimum scan buffer size is @ref BLE_GAP_SCAN_BUFFER_EXTENDED_MIN. + * @{ */ +#define BLE_GAP_SCAN_BUFFER_MIN (31) /**< Minimum data length for an + advertising set. */ +#define BLE_GAP_SCAN_BUFFER_MAX (31) /**< Maximum data length for an + advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MIN (255) /**< Minimum data length for an + extended advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MAX (1650) /**< Maximum data length for an + extended advertising set. */ +#define BLE_GAP_SCAN_BUFFER_EXTENDED_MAX_SUPPORTED (255) /**< Maximum supported data length for + an extended advertising set. */ +/** @} */ + +/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types + * + * Advertising types defined in Bluetooth Core Specification v5.0, Vol 6, Part B, Section 4.4.2. + * + * The maximum advertising data length is defined by @ref BLE_GAP_ADV_SET_DATA_SIZE_MAX. + * The maximum supported data length for an extended advertiser is defined by + * @ref BLE_GAP_ADV_SET_DATA_SIZE_EXTENDED_MAX_SUPPORTED + * Note that some of the advertising types do not support advertising data. Non-scannable types do not support + * scan response data. + * + * @{ */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_SCANNABLE_UNDIRECTED 0x01 /**< Connectable and scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE 0x02 /**< Connectable non-scannable directed advertising + events. Advertising interval is less that 3.75 ms. + Use this type for fast reconnections. + @note Advertising data is not supported. */ +#define BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED 0x03 /**< Connectable non-scannable directed advertising + events. + @note Advertising data is not supported. */ +#define BLE_GAP_ADV_TYPE_NONCONNECTABLE_SCANNABLE_UNDIRECTED 0x04 /**< Non-connectable scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED 0x05 /**< Non-connectable non-scannable undirected + advertising events. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_CONNECTABLE_NONSCANNABLE_UNDIRECTED 0x06 /**< Connectable non-scannable undirected advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_CONNECTABLE_NONSCANNABLE_DIRECTED 0x07 /**< Connectable non-scannable directed advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_SCANNABLE_UNDIRECTED 0x08 /**< Non-connectable scannable undirected advertising + events using extended advertising PDUs. + @note Only scan response data is supported. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_SCANNABLE_DIRECTED 0x09 /**< Non-connectable scannable directed advertising + events using extended advertising PDUs. + @note Only scan response data is supported. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED 0x0A /**< Non-connectable non-scannable undirected advertising + events using extended advertising PDUs. */ +#define BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED 0x0B /**< Non-connectable non-scannable directed advertising + events using extended advertising PDUs. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies + * @{ */ +#define BLE_GAP_ADV_FP_ANY 0x00 /**< Allow scan requests and connect requests from any device. */ +#define BLE_GAP_ADV_FP_FILTER_SCANREQ 0x01 /**< Filter scan requests with whitelist. */ +#define BLE_GAP_ADV_FP_FILTER_CONNREQ 0x02 /**< Filter connect requests with whitelist. */ +#define BLE_GAP_ADV_FP_FILTER_BOTH 0x03 /**< Filter both scan and connect requests with whitelist. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_DATA_STATUS GAP Advertising data status + * @{ */ +#define BLE_GAP_ADV_DATA_STATUS_COMPLETE 0x00 /**< All data in the advertising event have been received. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA 0x01 /**< More data to be received. + @note This value will only be used if + @ref ble_gap_scan_params_t::report_incomplete_evts and + @ref ble_gap_adv_report_type_t::extended_pdu are set to true. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_TRUNCATED 0x02 /**< Incomplete data. Buffer size insufficient to receive more. + @note This value will only be used if + @ref ble_gap_adv_report_type_t::extended_pdu is set to true. */ +#define BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MISSED 0x03 /**< Failed to receive the remaining data. + @note This value will only be used if + @ref ble_gap_adv_report_type_t::extended_pdu is set to true. */ +/**@} */ + +/**@defgroup BLE_GAP_SCAN_FILTER_POLICIES GAP Scanner filter policies + * @{ */ +#define BLE_GAP_SCAN_FP_ACCEPT_ALL 0x00 /**< Accept all advertising packets except directed advertising packets + not addressed to this device. */ +#define BLE_GAP_SCAN_FP_WHITELIST 0x01 /**< Accept advertising packets from devices in the whitelist except directed + packets not addressed to this device. */ +#define BLE_GAP_SCAN_FP_ALL_NOT_RESOLVED_DIRECTED 0x02 /**< Accept all advertising packets specified in @ref BLE_GAP_SCAN_FP_ACCEPT_ALL. + In addition, accept directed advertising packets, where the advertiser's + address is a resolvable private address that cannot be resolved. */ +#define BLE_GAP_SCAN_FP_WHITELIST_NOT_RESOLVED_DIRECTED 0x03 /**< Accept all advertising packets specified in @ref BLE_GAP_SCAN_FP_WHITELIST. + In addition, accept directed advertising packets, where the advertiser's + address is a resolvable private address that cannot be resolved. */ +/**@} */ + +/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values in 10 ms units + * @{ */ +#define BLE_GAP_ADV_TIMEOUT_HIGH_DUTY_MAX (128) /**< Maximum high duty advertising time in 10 ms units. Corresponds to 1.28 s. */ +#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX (18000) /**< Maximum advertising time in 10 ms units corresponding to TGAP(lim_adv_timeout) = 180 s in limited discoverable mode. */ +#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED (0) /**< Unlimited advertising in general discoverable mode. + For high duty cycle advertising, this corresponds to @ref BLE_GAP_ADV_TIMEOUT_HIGH_DUTY_MAX. */ +/**@} */ + + +/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes + * @{ */ +#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE 0x00 /**< Not discoverable discovery Mode. */ +#define BLE_GAP_DISC_MODE_LIMITED 0x01 /**< Limited Discovery Mode. */ +#define BLE_GAP_DISC_MODE_GENERAL 0x02 /**< General Discovery Mode. */ +/**@} */ + + +/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities + * @{ */ +#define BLE_GAP_IO_CAPS_DISPLAY_ONLY 0x00 /**< Display Only. */ +#define BLE_GAP_IO_CAPS_DISPLAY_YESNO 0x01 /**< Display and Yes/No entry. */ +#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY 0x02 /**< Keyboard Only. */ +#define BLE_GAP_IO_CAPS_NONE 0x03 /**< No I/O capabilities. */ +#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY 0x04 /**< Keyboard and Display. */ +/**@} */ + + +/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types + * @{ */ +#define BLE_GAP_AUTH_KEY_TYPE_NONE 0x00 /**< No key (may be used to reject). */ +#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY 0x01 /**< 6-digit Passkey. */ +#define BLE_GAP_AUTH_KEY_TYPE_OOB 0x02 /**< Out Of Band data. */ +/**@} */ + + +/**@defgroup BLE_GAP_KP_NOT_TYPES GAP Keypress Notification Types + * @{ */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_START 0x00 /**< Passkey entry started. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_IN 0x01 /**< Passkey digit entered. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_OUT 0x02 /**< Passkey digit erased. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_CLEAR 0x03 /**< Passkey cleared. */ +#define BLE_GAP_KP_NOT_TYPE_PASSKEY_END 0x04 /**< Passkey entry completed. */ +/**@} */ + + +/**@defgroup BLE_GAP_SEC_STATUS GAP Security status + * @{ */ +#define BLE_GAP_SEC_STATUS_SUCCESS 0x00 /**< Procedure completed with success. */ +#define BLE_GAP_SEC_STATUS_TIMEOUT 0x01 /**< Procedure timed out. */ +#define BLE_GAP_SEC_STATUS_PDU_INVALID 0x02 /**< Invalid PDU received. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE1_BEGIN 0x03 /**< Reserved for Future Use range #1 begin. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE1_END 0x80 /**< Reserved for Future Use range #1 end. */ +#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED 0x81 /**< Passkey entry failed (user canceled or other). */ +#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE 0x82 /**< Out of Band Key not available. */ +#define BLE_GAP_SEC_STATUS_AUTH_REQ 0x83 /**< Authentication requirements not met. */ +#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE 0x84 /**< Confirm value failed. */ +#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP 0x85 /**< Pairing not supported. */ +#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE 0x86 /**< Encryption key size. */ +#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED 0x87 /**< Unsupported SMP command. */ +#define BLE_GAP_SEC_STATUS_UNSPECIFIED 0x88 /**< Unspecified reason. */ +#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS 0x89 /**< Too little time elapsed since last attempt. */ +#define BLE_GAP_SEC_STATUS_INVALID_PARAMS 0x8A /**< Invalid parameters. */ +#define BLE_GAP_SEC_STATUS_DHKEY_FAILURE 0x8B /**< DHKey check failure. */ +#define BLE_GAP_SEC_STATUS_NUM_COMP_FAILURE 0x8C /**< Numeric Comparison failure. */ +#define BLE_GAP_SEC_STATUS_BR_EDR_IN_PROG 0x8D /**< BR/EDR pairing in progress. */ +#define BLE_GAP_SEC_STATUS_X_TRANS_KEY_DISALLOWED 0x8E /**< BR/EDR Link Key cannot be used for LE keys. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE2_BEGIN 0x8F /**< Reserved for Future Use range #2 begin. */ +#define BLE_GAP_SEC_STATUS_RFU_RANGE2_END 0xFF /**< Reserved for Future Use range #2 end. */ +/**@} */ + + +/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources + * @{ */ +#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL 0x00 /**< Local failure. */ +#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE 0x01 /**< Remote failure. */ +/**@} */ + + +/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits + * @{ */ +#define BLE_GAP_CP_MIN_CONN_INTVL_NONE 0xFFFF /**< No new minimum connection interval specified in connect parameters. */ +#define BLE_GAP_CP_MIN_CONN_INTVL_MIN 0x0006 /**< Lowest minimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ +#define BLE_GAP_CP_MIN_CONN_INTVL_MAX 0x0C80 /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_NONE 0xFFFF /**< No new maximum connection interval specified in connect parameters. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_MIN 0x0006 /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ +#define BLE_GAP_CP_MAX_CONN_INTVL_MAX 0x0C80 /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ +#define BLE_GAP_CP_SLAVE_LATENCY_MAX 0x01F3 /**< Highest slave latency permitted, in connection events. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE 0xFFFF /**< No new supervision timeout specified in connect parameters. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN 0x000A /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */ +#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX 0x0C80 /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */ +/**@} */ + + +/**@defgroup BLE_GAP_DEVNAME GAP device name defines. + * @{ */ +#define BLE_GAP_DEVNAME_DEFAULT "nRF5x" /**< Default device name value. */ +#define BLE_GAP_DEVNAME_DEFAULT_LEN 31 /**< Default number of octets in device name. */ +#define BLE_GAP_DEVNAME_MAX_LEN 248 /**< Maximum number of octets in device name. */ +/**@} */ + + +/**@brief Disable RSSI events for connections */ +#define BLE_GAP_RSSI_THRESHOLD_INVALID 0xFF + +/**@defgroup BLE_GAP_PHYS GAP PHYs + * @{ */ +#define BLE_GAP_PHY_AUTO 0x00 /**< Automatic PHY selection. Refer @ref sd_ble_gap_phy_update for more information.*/ +#define BLE_GAP_PHY_1MBPS 0x01 /**< 1 Mbps PHY. */ +#define BLE_GAP_PHY_2MBPS 0x02 /**< 2 Mbps PHY. */ +#define BLE_GAP_PHY_CODED 0x04 /**< Coded PHY. */ +#define BLE_GAP_PHY_NOT_SET 0xFF /**< PHY is not configured. */ + +/**@brief Supported PHYs in connections, for scanning, and for advertising. */ +#define BLE_GAP_PHYS_SUPPORTED (BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS | BLE_GAP_PHY_CODED) /**< All PHYs are supported. */ + +/**@} */ + +/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters + * + * See @ref ble_gap_conn_sec_mode_t. + * @{ */ +/**@brief Set sec_mode pointed to by ptr to have no access rights.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0) +/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0) +/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0) +/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0) +/**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0) +/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0) +/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/ +#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0) +/**@} */ + + +/**@brief GAP Security Random Number Length. */ +#define BLE_GAP_SEC_RAND_LEN 8 + + +/**@brief GAP Security Key Length. */ +#define BLE_GAP_SEC_KEY_LEN 16 + + +/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key Length. */ +#define BLE_GAP_LESC_P256_PK_LEN 64 + + +/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman DHKey Length. */ +#define BLE_GAP_LESC_DHKEY_LEN 32 + + +/**@brief GAP Passkey Length. */ +#define BLE_GAP_PASSKEY_LEN 6 + + +/**@brief Maximum amount of addresses in the whitelist. */ +#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8) + + +/**@brief Maximum amount of identities in the device identities list. */ +#define BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT (8) + + +/**@brief Default connection count for a configuration. */ +#define BLE_GAP_CONN_COUNT_DEFAULT (1) + + +/**@defgroup BLE_GAP_EVENT_LENGTH GAP event length defines. + * @{ */ +#define BLE_GAP_EVENT_LENGTH_MIN (2) /**< Minimum event length, in 1.25 ms units. */ +#define BLE_GAP_EVENT_LENGTH_CODED_PHY_MIN (6) /**< The shortest event length in 1.25 ms units supporting LE Coded PHY. */ +#define BLE_GAP_EVENT_LENGTH_DEFAULT (3) /**< Default event length, in 1.25 ms units. */ +/**@} */ + + +/**@defgroup BLE_GAP_ROLE_COUNT GAP concurrent connection count defines. + * @{ */ +#define BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT (1) /**< Default maximum number of connections concurrently acting as peripherals. */ +#define BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT (3) /**< Default maximum number of connections concurrently acting as centrals. */ +#define BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT (1) /**< Default number of SMP instances shared between all connections acting as centrals. */ +#define BLE_GAP_ROLE_COUNT_COMBINED_MAX (20) /**< Maximum supported number of concurrent connections in the peripheral and central roles combined. */ + +/**@} */ + +/**@brief Automatic data length parameter. */ +#define BLE_GAP_DATA_LENGTH_AUTO 0 + +/**@defgroup BLE_GAP_AUTH_PAYLOAD_TIMEOUT Authenticated payload timeout defines. + * @{ */ +#define BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MAX (48000) /**< Maximum authenticated payload timeout in 10 ms units, i.e. 8 minutes. */ +#define BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MIN (1) /**< Minimum authenticated payload timeout in 10 ms units, i.e. 10 ms. */ +/**@} */ + +/**@defgroup GAP_SEC_MODES GAP Security Modes + * @{ */ +#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */ +/**@} */ + +/**@brief The total number of channels in Bluetooth Low Energy. */ +#define BLE_GAP_CHANNEL_COUNT (40) + +/**@defgroup BLE_GAP_QOS_CHANNEL_SURVEY_INTERVALS Quality of Service (QoS) Channel survey interval defines + * @{ */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS (0) /**< Continuous channel survey. */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MIN_US (7500) /**< Minimum channel survey interval in microseconds (7.5 ms). */ +#define BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_MAX_US (4000000) /**< Maximum channel survey interval in microseconds (4 s). */ + /**@} */ + +/** @} */ + + +/**@addtogroup BLE_GAP_STRUCTURES Structures + * @{ */ + +/**@brief Advertising event properties. */ +typedef struct +{ + uint8_t type; /**< Advertising type. See @ref BLE_GAP_ADV_TYPES. */ + uint8_t anonymous : 1; /**< Omit advertiser's address from all PDUs. + @note Anonymous advertising is only available for + @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_UNDIRECTED and + @ref BLE_GAP_ADV_TYPE_EXTENDED_NONCONNECTABLE_NONSCANNABLE_DIRECTED. */ + uint8_t include_tx_power : 1; /**< This feature is not supported on this SoftDevice. */ +} ble_gap_adv_properties_t; + + +/**@brief Advertising report type. */ +typedef struct +{ + uint16_t connectable : 1; /**< Connectable advertising event type. */ + uint16_t scannable : 1; /**< Scannable advertising event type. */ + uint16_t directed : 1; /**< Directed advertising event type. */ + uint16_t scan_response : 1; /**< Received a scan response. */ + uint16_t extended_pdu : 1; /**< Received an extended advertising set. */ + uint16_t status : 2; /**< Data status. See @ref BLE_GAP_ADV_DATA_STATUS. */ + uint16_t reserved : 9; /**< Reserved for future use. */ +} ble_gap_adv_report_type_t; + +/**@brief Advertising Auxiliary Pointer. */ +typedef struct +{ + uint16_t aux_offset; /**< Time offset from the beginning of advertising packet to the auxiliary packet in 100 us units. */ + uint8_t aux_phy; /**< Indicates the PHY on which the auxiliary advertising packet is sent. See @ref BLE_GAP_PHYS. */ +} ble_gap_aux_pointer_t; + +/**@brief Bluetooth Low Energy address. */ +typedef struct +{ + uint8_t addr_id_peer : 1; /**< Only valid for peer addresses. + This bit is set by the SoftDevice to indicate whether the address has been resolved from + a Resolvable Private Address (when the peer is using privacy). + If set to 1, @ref addr and @ref addr_type refer to the identity address of the resolved address. + + This bit is ignored when a variable of type @ref ble_gap_addr_t is used as input to API functions. */ + uint8_t addr_type : 7; /**< See @ref BLE_GAP_ADDR_TYPES. */ + uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. + @ref addr is not used if @ref addr_type is @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. */ +} ble_gap_addr_t; + + +/**@brief GAP connection parameters. + * + * @note When ble_conn_params_t is received in an event, both min_conn_interval and + * max_conn_interval will be equal to the connection interval set by the central. + * + * @note If both conn_sup_timeout and max_conn_interval are specified, then the following constraint applies: + * conn_sup_timeout * 4 > (1 + slave_latency) * max_conn_interval + * that corresponds to the following Bluetooth Spec requirement: + * The Supervision_Timeout in milliseconds shall be larger than + * (1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given in milliseconds. + */ +typedef struct +{ + uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ + uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ +} ble_gap_conn_params_t; + + +/**@brief GAP connection security modes. + * + * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n + * Security Mode 1 Level 1: No security is needed (aka open link).\n + * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n + * Security Mode 1 Level 3: MITM protected encrypted link required.\n + * Security Mode 1 Level 4: LESC MITM protected encrypted link using a 128-bit strength encryption key required.\n + * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n + * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n + */ +typedef struct +{ + uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ + uint8_t lv : 4; /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */ + +} ble_gap_conn_sec_mode_t; + + +/**@brief GAP connection security status.*/ +typedef struct +{ + ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ + uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ +} ble_gap_conn_sec_t; + +/**@brief Identity Resolving Key. */ +typedef struct +{ + uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ +} ble_gap_irk_t; + + +/**@brief Channel mask (40 bits). + * Every channel is represented with a bit positioned as per channel index defined in Bluetooth Core Specification v5.0, + * Vol 6, Part B, Section 1.4.1. The LSB contained in array element 0 represents channel index 0, and bit 39 represents + * channel index 39. If a bit is set to 1, the channel is not used. + */ +typedef uint8_t ble_gap_ch_mask_t[5]; + + +/**@brief GAP advertising parameters. */ +typedef struct +{ + ble_gap_adv_properties_t properties; /**< The properties of the advertising events. */ + ble_gap_addr_t const *p_peer_addr; /**< Address of a known peer. + @note ble_gap_addr_t::addr_type cannot be + @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. + - When privacy is enabled and the local device uses + @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE addresses, + the device identity list is searched for a matching entry. If + the local IRK for that device identity is set, the local IRK + for that device will be used to generate the advertiser address + field in the advertising packet. + - If @ref ble_gap_adv_properties_t::type is directed, this must be + set to the targeted scanner or initiator. If the peer address is + in the device identity list, the peer IRK for that device will be + used to generate @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE + target addresses used in the advertising event PDUs. */ + uint32_t interval; /**< Advertising interval in 625 us units. @sa BLE_GAP_ADV_INTERVALS. + @note If @ref ble_gap_adv_properties_t::type is set to + @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE + advertising, this parameter is ignored. */ + uint16_t duration; /**< Advertising duration in 10 ms units. When timeout is reached, + an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised. + @sa BLE_GAP_ADV_TIMEOUT_VALUES. + @note The SoftDevice will always complete at least one advertising + event even if the duration is set too low. */ + uint8_t max_adv_evts; /**< Maximum advertising events that shall be sent prior to disabling + advertising. Setting the value to 0 disables the limitation. When + the count of advertising events specified by this parameter + (if not 0) is reached, advertising will be automatically stopped + and an event of type @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised + @note If @ref ble_gap_adv_properties_t::type is set to + @ref BLE_GAP_ADV_TYPE_CONNECTABLE_NONSCANNABLE_DIRECTED_HIGH_DUTY_CYCLE, + this parameter is ignored. */ + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + At least one of the primary channels, that is channel index 37-39, must be used. + Masking away secondary advertising channels is not supported. */ + uint8_t filter_policy; /**< Filter Policy. @sa BLE_GAP_ADV_FILTER_POLICIES. */ + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising channel packets + are transmitted. If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS + will be used. + Valid values are @ref BLE_GAP_PHY_1MBPS and @ref BLE_GAP_PHY_CODED. + @note The primary_phy shall indicate @ref BLE_GAP_PHY_1MBPS if + @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising channel packets + are transmitted. + If set to @ref BLE_GAP_PHY_AUTO, @ref BLE_GAP_PHY_1MBPS will be used. + Valid values are + @ref BLE_GAP_PHY_1MBPS, @ref BLE_GAP_PHY_2MBPS, and @ref BLE_GAP_PHY_CODED. + If @ref ble_gap_adv_properties_t::type is an extended advertising type + and connectable, this is the PHY that will be used to establish a + connection and send AUX_ADV_IND packets on. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ + uint8_t set_id:4; /**< The advertising set identifier distinguishes this advertising set from other + advertising sets transmitted by this and other devices. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is not an extended advertising type. */ + uint8_t scan_req_notification:1; /**< Enable scan request notifications for this advertising set. When a + scan request is received and the scanner address is allowed + by the filter policy, @ref BLE_GAP_EVT_SCAN_REQ_REPORT is raised. + @note This parameter will be ignored when + @ref ble_gap_adv_properties_t::type is a non-scannable + advertising type. */ +} ble_gap_adv_params_t; + + +/**@brief GAP advertising data buffers. + * + * The application must provide the buffers for advertisement. The memory shall reside in application RAM, and + * shall never be modified while advertising. The data shall be kept alive until either: + * - @ref BLE_GAP_EVT_ADV_SET_TERMINATED is raised. + * - @ref BLE_GAP_EVT_CONNECTED is raised with @ref ble_gap_evt_connected_t::adv_handle set to the corresponding + * advertising handle. + * - Advertising is stopped. + * - Advertising data is changed. + * To update advertising data while advertising, provide new buffers to @ref sd_ble_gap_adv_set_configure. */ +typedef struct +{ + ble_data_t adv_data; /**< Advertising data. + @note + Advertising data can only be specified for a @ref ble_gap_adv_properties_t::type + that is allowed to contain advertising data. */ + ble_data_t scan_rsp_data; /**< Scan response data. + @note + Scan response data can only be specified for a @ref ble_gap_adv_properties_t::type + that is scannable. */ +} ble_gap_adv_data_t; + + +/**@brief GAP scanning parameters. */ +typedef struct +{ + uint8_t extended : 1; /**< If 1, the scanner will accept extended advertising packets. + If set to 0, the scanner will not receive advertising packets + on secondary advertising channels, and will not be able + to receive long advertising PDUs. */ + uint8_t report_incomplete_evts : 1; /**< If 1, events of type @ref ble_gap_evt_adv_report_t may have + @ref ble_gap_adv_report_type_t::status set to + @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. + This parameter is ignored when used with @ref sd_ble_gap_connect + @note This may be used to abort receiving more packets from an extended + advertising event, and is only available for extended + scanning, see @ref sd_ble_gap_scan_start. + @note This feature is not supported by this SoftDevice. */ + uint8_t active : 1; /**< If 1, perform active scanning by sending scan requests. + This parameter is ignored when used with @ref sd_ble_gap_connect. */ + uint8_t filter_policy : 2; /**< Scanning filter policy. @sa BLE_GAP_SCAN_FILTER_POLICIES. + @note Only @ref BLE_GAP_SCAN_FP_ACCEPT_ALL and + @ref BLE_GAP_SCAN_FP_WHITELIST are valid when used with + @ref sd_ble_gap_connect */ + uint8_t scan_phys; /**< Bitfield of PHYs to scan on. If set to @ref BLE_GAP_PHY_AUTO, + scan_phys will default to @ref BLE_GAP_PHY_1MBPS. + - If @ref ble_gap_scan_params_t::extended is set to 0, the only + supported PHY is @ref BLE_GAP_PHY_1MBPS. + - When used with @ref sd_ble_gap_scan_start, + the bitfield indicates the PHYs the scanner will use for scanning + on primary advertising channels. The scanner will accept + @ref BLE_GAP_PHYS_SUPPORTED as secondary advertising channel PHYs. + - When used with @ref sd_ble_gap_connect, the bitfield indicates + the PHYs the initiator will use for scanning on primary advertising + channels. The initiator will accept connections initiated on either + of the @ref BLE_GAP_PHYS_SUPPORTED PHYs. + If scan_phys contains @ref BLE_GAP_PHY_1MBPS and/or @ref BLE_GAP_PHY_2MBPS, + the primary scan PHY is @ref BLE_GAP_PHY_1MBPS. + If scan_phys also contains @ref BLE_GAP_PHY_CODED, the primary scan + PHY will also contain @ref BLE_GAP_PHY_CODED. If the only scan PHY is + @ref BLE_GAP_PHY_CODED, the primary scan PHY is + @ref BLE_GAP_PHY_CODED only. */ + uint16_t interval; /**< Scan interval in 625 us units. @sa BLE_GAP_SCAN_INTERVALS. */ + uint16_t window; /**< Scan window in 625 us units. @sa BLE_GAP_SCAN_WINDOW. + If scan_phys contains both @ref BLE_GAP_PHY_1MBPS and + @ref BLE_GAP_PHY_CODED interval shall be larger than or + equal to twice the scan window. */ + uint16_t timeout; /**< Scan timeout in 10 ms units. @sa BLE_GAP_SCAN_TIMEOUT. */ + ble_gap_ch_mask_t channel_mask; /**< Channel mask for primary and secondary advertising channels. + At least one of the primary channels, that is channel index 37-39, must be + set to 0. + Masking away secondary channels is not supported. */ +} ble_gap_scan_params_t; + + +/**@brief Privacy. + * + * The privacy feature provides a way for the device to avoid being tracked over a period of time. + * The privacy feature, when enabled, hides the local device identity and replaces it with a private address + * that is automatically refreshed at a specified interval. + * + * If a device still wants to be recognized by other peers, it needs to share it's Identity Resolving Key (IRK). + * With this key, a device can generate a random private address that can only be recognized by peers in possession of that key, + * and devices can establish connections without revealing their real identities. + * + * Both network privacy (@ref BLE_GAP_PRIVACY_MODE_NETWORK_PRIVACY) and device privacy (@ref BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY) + * are supported. + * + * @note If the device IRK is updated, the new IRK becomes the one to be distributed in all + * bonding procedures performed after @ref sd_ble_gap_privacy_set returns. + * The IRK distributed during bonding procedure is the device IRK that is active when @ref sd_ble_gap_sec_params_reply is called. + */ +typedef struct +{ + uint8_t privacy_mode; /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */ + uint8_t private_addr_type; /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */ + uint16_t private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */ + ble_gap_irk_t *p_device_irk; /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used. + When used as output, pointer to IRK structure where the current default IRK will be written to. If NULL, this argument is ignored. + By default, the default IRK is used to generate random private resolvable addresses for the local device unless instructed otherwise. */ +} ble_gap_privacy_params_t; + + +/**@brief PHY preferences for TX and RX + * @note tx_phys and rx_phys are bit fields. Multiple bits can be set in them to indicate multiple preferred PHYs for each direction. + * @code + * p_gap_phys->tx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS; + * p_gap_phys->rx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS; + * @endcode + * + */ +typedef struct +{ + uint8_t tx_phys; /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phys; /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */ +} ble_gap_phys_t; + +/** @brief Keys that can be exchanged during a bonding procedure. */ +typedef struct +{ + uint8_t enc : 1; /**< Long Term Key and Master Identification. */ + uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */ + uint8_t sign : 1; /**< Connection Signature Resolving Key. */ + uint8_t link : 1; /**< Derive the Link Key from the LTK. */ +} ble_gap_sec_kdist_t; + + +/**@brief GAP security parameters. */ +typedef struct +{ + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Enable Man In The Middle protection. */ + uint8_t lesc : 1; /**< Enable LE Secure Connection pairing. */ + uint8_t keypress : 1; /**< Enable generation of keypress notifications. */ + uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ + uint8_t oob : 1; /**< The OOB data flag. + - In LE legacy pairing, this flag is set if a device has out of band authentication data. + The OOB method is used if both of the devices have out of band authentication data. + - In LE Secure Connections pairing, this flag is set if a device has the peer device's out of band authentication data. + The OOB method is used if at least one device has the peer device's OOB data available. */ + uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */ + uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ + ble_gap_sec_kdist_t kdist_own; /**< Key distribution bitmap: keys that the local device will distribute. */ + ble_gap_sec_kdist_t kdist_peer; /**< Key distribution bitmap: keys that the remote device will distribute. */ +} ble_gap_sec_params_t; + + +/**@brief GAP Encryption Information. */ +typedef struct +{ + uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ + uint8_t lesc : 1; /**< Key generated using LE Secure Connections. */ + uint8_t auth : 1; /**< Authenticated Key. */ + uint8_t ltk_len : 6; /**< LTK length in octets. */ +} ble_gap_enc_info_t; + + +/**@brief GAP Master Identification. */ +typedef struct +{ + uint16_t ediv; /**< Encrypted Diversifier. */ + uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */ +} ble_gap_master_id_t; + + +/**@brief GAP Signing Information. */ +typedef struct +{ + uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */ +} ble_gap_sign_info_t; + + +/**@brief GAP LE Secure Connections P-256 Public Key. */ +typedef struct +{ + uint8_t pk[BLE_GAP_LESC_P256_PK_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */ +} ble_gap_lesc_p256_pk_t; + + +/**@brief GAP LE Secure Connections DHKey. */ +typedef struct +{ + uint8_t key[BLE_GAP_LESC_DHKEY_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */ +} ble_gap_lesc_dhkey_t; + + +/**@brief GAP LE Secure Connections OOB data. */ +typedef struct +{ + ble_gap_addr_t addr; /**< Bluetooth address of the device. */ + uint8_t r[BLE_GAP_SEC_KEY_LEN]; /**< Random Number. */ + uint8_t c[BLE_GAP_SEC_KEY_LEN]; /**< Confirm Value. */ +} ble_gap_lesc_oob_data_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */ +typedef struct +{ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + and the address is the device's identity address. */ + uint8_t role; /**< BLE role for this connection, see @ref BLE_GAP_ROLES */ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. + This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + advertising set. The advertising buffers provided in + @ref sd_ble_gap_adv_set_configure are now released. + This variable is only set if role is set to @ref BLE_GAP_ROLE_PERIPH. */ +} ble_gap_evt_connected_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */ +typedef struct +{ + uint8_t reason; /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */ +} ble_gap_evt_disconnected_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */ +typedef struct +{ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ +} ble_gap_evt_conn_param_update_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_PHY_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_phys_t peer_preferred_phys; /**< The PHYs the peer prefers to use. */ +} ble_gap_evt_phy_update_request_t; + +/**@brief Event Structure for @ref BLE_GAP_EVT_PHY_UPDATE. */ +typedef struct +{ + uint8_t status; /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES.*/ + uint8_t tx_phy; /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */ + uint8_t rx_phy; /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */ +} ble_gap_evt_phy_update_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */ +typedef struct +{ + ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ +} ble_gap_evt_sec_params_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */ +typedef struct +{ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ + ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */ + uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ + uint8_t id_info : 1; /**< If 1, Identity Information required. */ + uint8_t sign_info : 1; /**< If 1, Signing Information required. */ +} ble_gap_evt_sec_info_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */ +typedef struct +{ + uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ + uint8_t match_request : 1; /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply + with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or + @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */ +} ble_gap_evt_passkey_display_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */ +typedef struct +{ + uint8_t kp_not; /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */ +} ble_gap_evt_key_pressed_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */ +typedef struct +{ + uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ +} ble_gap_evt_auth_key_request_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */ +typedef struct +{ + ble_gap_lesc_p256_pk_t *p_pk_peer; /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory + inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */ + uint8_t oobd_req :1; /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */ +} ble_gap_evt_lesc_dhkey_request_t; + + +/**@brief Security levels supported. + * @note See Bluetooth Specification Version 4.2 Volume 3, Part C, Chapter 10, Section 10.2.1. +*/ +typedef struct +{ + uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ + uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ + uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ + uint8_t lv4 : 1; /**< If 1: Level 4 is supported. */ +} ble_gap_sec_levels_t; + + +/**@brief Encryption Key. */ +typedef struct +{ + ble_gap_enc_info_t enc_info; /**< Encryption Information. */ + ble_gap_master_id_t master_id; /**< Master Identification. */ +} ble_gap_enc_key_t; + + +/**@brief Identity Key. */ +typedef struct +{ + ble_gap_irk_t id_info; /**< Identity Resolving Key. */ + ble_gap_addr_t id_addr_info; /**< Identity Address. */ +} ble_gap_id_key_t; + + +/**@brief Security Keys. */ +typedef struct +{ + ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */ + ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */ + ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */ + ble_gap_lesc_p256_pk_t *p_pk; /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined + in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */ +} ble_gap_sec_keys_t; + + +/**@brief Security key set for both local and peer keys. */ +typedef struct +{ + ble_gap_sec_keys_t keys_own; /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */ + ble_gap_sec_keys_t keys_peer; /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */ +} ble_gap_sec_keyset_t; + + +/**@brief Data Length Update Procedure parameters. */ +typedef struct +{ + uint16_t max_tx_octets; /**< Maximum number of payload octets that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_octets; /**< Maximum number of payload octets that a Controller supports for reception of a single Link Layer Data Channel PDU. */ + uint16_t max_tx_time_us; /**< Maximum time, in microseconds, that a Controller supports for transmission of a single Link Layer Data Channel PDU. */ + uint16_t max_rx_time_us; /**< Maximum time, in microseconds, that a Controller supports for reception of a single Link Layer Data Channel PDU. */ +} ble_gap_data_length_params_t; + + +/**@brief Data Length Update Procedure local limitation. */ +typedef struct +{ + uint16_t tx_payload_limited_octets; /**< If > 0, the requested TX packet length is too long by this many octets. */ + uint16_t rx_payload_limited_octets; /**< If > 0, the requested RX packet length is too long by this many octets. */ + uint16_t tx_rx_time_limited_us; /**< If > 0, the requested combination of TX and RX packet lengths is too long by this many microseconds. */ +} ble_gap_data_length_limitation_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */ +typedef struct +{ + uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ + uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ + uint8_t bonded : 1; /**< Procedure resulted in a bond. */ + uint8_t lesc : 1; /**< Procedure resulted in a LE Secure Connection. */ + ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ + ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ + ble_gap_sec_kdist_t kdist_own; /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */ + ble_gap_sec_kdist_t kdist_peer; /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */ +} ble_gap_evt_auth_status_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */ +typedef struct +{ + ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ +} ble_gap_evt_conn_sec_update_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ + union + { + ble_data_t adv_report_buffer; /**< If source is set to @ref BLE_GAP_TIMEOUT_SRC_SCAN, the released + scan buffer is contained in this field. */ + } params; /**< Event Parameters. */ +} ble_gap_evt_timeout_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */ +typedef struct +{ + int8_t rssi; /**< Received Signal Strength Indication in dBm. + @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ + uint8_t ch_index; /**< Data Channel Index on which the Signal Strength is measured (0-36). */ +} ble_gap_evt_rssi_changed_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_ADV_SET_TERMINATED */ +typedef struct +{ + uint8_t reason; /**< Reason for why the advertising set terminated. See + @ref BLE_GAP_EVT_ADV_SET_TERMINATED_REASON. */ + uint8_t adv_handle; /**< Advertising handle in which advertising has ended. */ + uint8_t num_completed_adv_events; /**< If @ref ble_gap_adv_params_t::max_adv_evts was not set to 0, + this field indicates the number of completed advertising events. */ + ble_gap_adv_data_t adv_data; /**< Advertising buffers corresponding to the terminated + advertising set. The advertising buffers provided in + @ref sd_ble_gap_adv_set_configure are now released. */ +} ble_gap_evt_adv_set_terminated_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_ADV_REPORT. + * + * @note If @ref ble_gap_adv_report_type_t::status is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, + * not all fields in the advertising report may be available. + * + * @note When ble_gap_adv_report_type_t::status is not set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, + * scanning will be paused. To continue scanning, call @ref sd_ble_gap_scan_start. + */ +typedef struct +{ + ble_gap_adv_report_type_t type; /**< Advertising report type. See @ref ble_gap_adv_report_type_t. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr is resolved: + @ref ble_gap_addr_t::addr_id_peer is set to 1 and the address is the + peer's identity address. */ + ble_gap_addr_t direct_addr; /**< Contains the target address of the advertising event if + @ref ble_gap_adv_report_type_t::directed is set to 1. If the + SoftDevice was able to resolve the address, + @ref ble_gap_addr_t::addr_id_peer is set to 1 and the direct_addr + contains the local identity address. If the target address of the + advertising event is @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE, + and the SoftDevice was unable to resolve it, the application may try + to resolve this address to find out if the advertising event was + directed to us. */ + uint8_t primary_phy; /**< Indicates the PHY on which the primary advertising packet was received. + See @ref BLE_GAP_PHYS. */ + uint8_t secondary_phy; /**< Indicates the PHY on which the secondary advertising packet was received. + See @ref BLE_GAP_PHYS. This field is set to @ref BLE_GAP_PHY_NOT_SET if no packets + were received on a secondary advertising channel. */ + int8_t tx_power; /**< TX Power reported by the advertiser in the last packet header received. + This field is set to @ref BLE_GAP_POWER_LEVEL_INVALID if the + last received packet did not contain the Tx Power field. + @note TX Power is only included in extended advertising packets. */ + int8_t rssi; /**< Received Signal Strength Indication in dBm of the last packet received. + @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ + uint8_t ch_index; /**< Channel Index on which the last advertising packet is received (0-39). */ + uint8_t set_id; /**< Set ID of the received advertising data. Set ID is not present + if set to @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ + uint16_t data_id:12; /**< The advertising data ID of the received advertising data. Data ID + is not present if @ref ble_gap_evt_adv_report_t::set_id is set to + @ref BLE_GAP_ADV_REPORT_SET_ID_NOT_AVAILABLE. */ + ble_data_t data; /**< Received advertising or scan response data. If + @ref ble_gap_adv_report_type_t::status is not set to + @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the data buffer provided + in @ref sd_ble_gap_scan_start is now released. */ + ble_gap_aux_pointer_t aux_pointer; /**< The offset and PHY of the next advertising packet in this extended advertising + event. @note This field is only set if @ref ble_gap_adv_report_type_t::status + is set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. */ +} ble_gap_evt_adv_report_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */ +typedef struct +{ + uint8_t bond : 1; /**< Perform bonding. */ + uint8_t mitm : 1; /**< Man In The Middle protection requested. */ + uint8_t lesc : 1; /**< LE Secure Connections requested. */ + uint8_t keypress : 1; /**< Generation of keypress notifications requested. */ +} ble_gap_evt_sec_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ +} ble_gap_evt_conn_param_update_request_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */ +typedef struct +{ + uint8_t adv_handle; /**< Advertising handle for the advertising set which received the Scan Request */ + int8_t rssi; /**< Received Signal Strength Indication in dBm. + @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. */ + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1 + and the address is the device's identity address. */ +} ble_gap_evt_scan_req_report_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST. */ +typedef struct +{ + ble_gap_data_length_params_t peer_params; /**< Peer data length parameters. */ +} ble_gap_evt_data_length_update_request_t; + +/**@brief Event structure for @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE. */ +typedef struct +{ + ble_gap_data_length_params_t effective_params; /**< The effective data length parameters. */ +} ble_gap_evt_data_length_update_t; + + +/**@brief Event structure for @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT. */ +typedef struct +{ + int8_t channel_energy[BLE_GAP_CHANNEL_COUNT]; /**< The measured energy on the Bluetooth Low Energy + channels, in dBm, indexed by Channel Index. + If no measurement is available for the given channel, channel_energy is set to + @ref BLE_GAP_POWER_LEVEL_INVALID. */ +} ble_gap_evt_qos_channel_survey_report_t; + +/**@brief GAP event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + union /**< union alternative identified by evt_id in enclosing struct. */ + { + ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ + ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ + ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ + ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ + ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ + ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. */ + ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ + ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. */ + ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ + ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ + ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event Parameters. */ + ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */ + ble_gap_evt_adv_set_terminated_t adv_set_terminated; /**< Advertising Set Terminated Event Parameters. */ + ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */ + ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */ + ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report Parameters. */ + ble_gap_evt_phy_update_request_t phy_update_request; /**< PHY Update Request Event Parameters. */ + ble_gap_evt_phy_update_t phy_update; /**< PHY Update Parameters. */ + ble_gap_evt_data_length_update_request_t data_length_update_request; /**< Data Length Update Request Event Parameters. */ + ble_gap_evt_data_length_update_t data_length_update; /**< Data Length Update Event Parameters. */ + ble_gap_evt_qos_channel_survey_report_t qos_channel_survey_report; /**< Quality of Service (QoS) Channel Survey Report Parameters. */ + } params; /**< Event Parameters. */ +} ble_gap_evt_t; + + +/** + * @brief BLE GAP connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_CONN_COUNT The connection count for the connection configurations is zero. + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - The sum of conn_count for all connection configurations combined exceeds UINT8_MAX. + * - The event length is smaller than @ref BLE_GAP_EVENT_LENGTH_MIN. + */ +typedef struct +{ + uint8_t conn_count; /**< The number of concurrent connections the application can create with this configuration. + The default and minimum value is @ref BLE_GAP_CONN_COUNT_DEFAULT. */ + uint16_t event_length; /**< The time set aside for this connection on every connection interval in 1.25 ms units. + The default value is @ref BLE_GAP_EVENT_LENGTH_DEFAULT, the minimum value is @ref BLE_GAP_EVENT_LENGTH_MIN. + The event length and the connection interval are the primary parameters + for setting the throughput of a connection. + See the SoftDevice Specification for details on throughput. */ +} ble_gap_conn_cfg_t; + + +/** + * @brief Configuration of maximum concurrent connections in the different connected roles, set with + * @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_CONN_COUNT The sum of periph_role_count and central_role_count is too + * large. The maximum supported sum of concurrent connections is + * @ref BLE_GAP_ROLE_COUNT_COMBINED_MAX. + * @retval ::NRF_ERROR_INVALID_PARAM central_sec_count is larger than central_role_count. + * @retval ::NRF_ERROR_RESOURCES The adv_set_count is too large. The maximum + * supported advertising handles is + * @ref BLE_GAP_ADV_SET_COUNT_MAX. + */ +typedef struct +{ + uint8_t adv_set_count; /**< Maximum number of advertising sets. Default value is @ref BLE_GAP_ADV_SET_COUNT_DEFAULT. */ + uint8_t periph_role_count; /**< Maximum number of connections concurrently acting as a peripheral. Default value is @ref BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT. */ + uint8_t central_role_count; /**< Maximum number of connections concurrently acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_DEFAULT. */ + uint8_t central_sec_count; /**< Number of SMP instances shared between all connections acting as a central. Default value is @ref BLE_GAP_ROLE_COUNT_CENTRAL_SEC_DEFAULT. */ + uint8_t qos_channel_survey_role_available:1; /**< If set, the Quality of Service (QoS) channel survey module is available to the + application using @ref sd_ble_gap_qos_channel_survey_start. */ +} ble_gap_cfg_role_count_t; + + +/** + * @brief Device name and its properties, set with @ref sd_ble_cfg_set. + * + * @note If the device name is not configured, the default device name will be + * @ref BLE_GAP_DEVNAME_DEFAULT, the maximum device name length will be + * @ref BLE_GAP_DEVNAME_DEFAULT_LEN, vloc will be set to @ref BLE_GATTS_VLOC_STACK and the device name + * will have no write access. + * + * @note If @ref max_len is more than @ref BLE_GAP_DEVNAME_DEFAULT_LEN and vloc is set to @ref BLE_GATTS_VLOC_STACK, + * the attribute table size must be increased to have room for the longer device name (see + * @ref sd_ble_cfg_set and @ref ble_gatts_cfg_attr_tab_size_t). + * + * @note If vloc is @ref BLE_GATTS_VLOC_STACK : + * - p_value must point to non-volatile memory (flash) or be NULL. + * - If p_value is NULL, the device name will initially be empty. + * + * @note If vloc is @ref BLE_GATTS_VLOC_USER : + * - p_value cannot be NULL. + * - If the device name is writable, p_value must point to volatile memory (RAM). + * + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - Invalid device name location (vloc). + * - Invalid device name security mode. + * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true: + * - The device name length is invalid (must be between 0 and @ref BLE_GAP_DEVNAME_MAX_LEN). + * - The device name length is too long for the given Attribute Table. + * @retval ::NRF_ERROR_NOT_SUPPORTED Device name security mode is not supported. + */ +typedef struct +{ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vloc:2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t *p_value; /**< Pointer to where the value (device name) is stored or will be stored. */ + uint16_t current_len; /**< Current length in bytes of the memory pointed to by p_value.*/ + uint16_t max_len; /**< Maximum length in bytes of the memory pointed to by p_value.*/ +} ble_gap_cfg_device_name_t; + + +/**@brief Configuration structure for GAP configurations. */ +typedef union +{ + ble_gap_cfg_role_count_t role_count_cfg; /**< Role count configuration, cfg_id is @ref BLE_GAP_CFG_ROLE_COUNT. */ + ble_gap_cfg_device_name_t device_name_cfg; /**< Device name configuration, cfg_id is @ref BLE_GAP_CFG_DEVICE_NAME. */ +} ble_gap_cfg_t; + + +/**@brief Channel Map option. + * + * @details Used with @ref sd_ble_opt_get to get the current channel map + * or @ref sd_ble_opt_set to set a new channel map. When setting the + * channel map, it applies to all current and future connections. When getting the + * current channel map, it applies to a single connection and the connection handle + * must be supplied. + * + * @note Setting the channel map may take some time, depending on connection parameters. + * The time taken may be different for each connection and the get operation will + * return the previous channel map until the new one has taken effect. + * + * @note After setting the channel map, by spec it can not be set again until at least 1 s has passed. + * See Bluetooth Specification Version 4.1 Volume 2, Part E, Section 7.3.46. + * + * @retval ::NRF_SUCCESS Get or set successful. + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - Less then two bits in @ref ch_map are set. + * - Bits for primary advertising channels (37-39) are set. + * @retval ::NRF_ERROR_BUSY Channel map was set again before enough time had passed. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied for get. + * + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle (only applicable for get) */ + uint8_t ch_map[5]; /**< Channel Map (37-bit). */ +} ble_gap_opt_ch_map_t; + + +/**@brief Local connection latency option. + * + * @details Local connection latency is a feature which enables the slave to improve + * current consumption by ignoring the slave latency set by the peer. The + * local connection latency can only be set to a multiple of the slave latency, + * and cannot be longer than half of the supervision timeout. + * + * @details Used with @ref sd_ble_opt_set to set the local connection latency. The + * @ref sd_ble_opt_get is not supported for this option, but the actual + * local connection latency (unless set to NULL) is set as a return parameter + * when setting the option. + * + * @note The latency set will be truncated down to the closest slave latency event + * multiple, or the nearest multiple before half of the supervision timeout. + * + * @note The local connection latency is disabled by default, and needs to be enabled for new + * connections and whenever the connection is updated. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t requested_latency; /**< Requested local connection latency. */ + uint16_t * p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ +} ble_gap_opt_local_conn_latency_t; + +/**@brief Disable slave latency + * + * @details Used with @ref sd_ble_opt_set to temporarily disable slave latency of a peripheral connection + * (see @ref ble_gap_conn_params_t::slave_latency). And to re-enable it again. When disabled, the + * peripheral will ignore the slave_latency set by the central. + * + * @note Shall only be called on peripheral links. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint8_t disable : 1; /**< Set to 1 to disable slave latency. Set to 0 enable it again.*/ +} ble_gap_opt_slave_latency_disable_t; + +/**@brief Passkey Option. + * + * @details Structure containing the passkey to be used during pairing. This can be used with @ref + * sd_ble_opt_set to make the SoftDevice use a preprogrammed passkey for authentication + * instead of generating a random one. + * + * @note Repeated pairing attempts using the same preprogrammed passkey makes pairing vulnerable to MITM attacks. + * + * @note @ref sd_ble_opt_get is not supported for this option. + * + */ +typedef struct +{ + uint8_t const * p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ +} ble_gap_opt_passkey_t; + + +/**@brief Compatibility mode 1 option. + * + * @details This can be used with @ref sd_ble_opt_set to enable and disable + * compatibility mode 1. Compatibility mode 1 is disabled by default. + * + * @note Compatibility mode 1 enables interoperability with devices that do not support a value of + * 0 for the WinOffset parameter in the Link Layer CONNECT_IND packet. This applies to a + * limited set of legacy peripheral devices from another vendor. Enabling this compatibility + * mode will only have an effect if the local device will act as a central device and + * initiate a connection to a peripheral device. In that case it may lead to the connection + * creation taking up to one connection interval longer to complete for all connections. + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_INVALID_STATE When connection creation is ongoing while mode 1 is set. + */ +typedef struct +{ + uint8_t enable : 1; /**< Enable compatibility mode 1.*/ +} ble_gap_opt_compat_mode_1_t; + + +/**@brief Authenticated payload timeout option. + * + * @details This can be used with @ref sd_ble_opt_set to change the Authenticated payload timeout to a value other + * than the default of @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT_MAX. + * + * @note The authenticated payload timeout event ::BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD will be generated + * if auth_payload_timeout time has elapsed without receiving a packet with a valid MIC on an encrypted + * link. + * + * @note The LE ping procedure will be initiated before the timer expires to give the peer a chance + * to reset the timer. In addition the stack will try to prioritize running of LE ping over other + * activities to increase chances of finishing LE ping before timer expires. To avoid side-effects + * on other activities, it is recommended to use high timeout values. + * Recommended timeout > 2*(connInterval * (6 + connSlaveLatency)). + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. auth_payload_timeout was outside of allowed range. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. + */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle */ + uint16_t auth_payload_timeout; /**< Requested timeout in 10 ms unit, see @ref BLE_GAP_AUTH_PAYLOAD_TIMEOUT. */ +} ble_gap_opt_auth_payload_timeout_t; + +/**@brief Option structure for GAP options. */ +typedef union +{ + ble_gap_opt_ch_map_t ch_map; /**< Parameters for the Channel Map option. */ + ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Parameters for the Local connection latency option */ + ble_gap_opt_passkey_t passkey; /**< Parameters for the Passkey option.*/ + ble_gap_opt_compat_mode_1_t compat_mode_1; /**< Parameters for the compatibility mode 1 option.*/ + ble_gap_opt_auth_payload_timeout_t auth_payload_timeout; /**< Parameters for the authenticated payload timeout option.*/ + ble_gap_opt_slave_latency_disable_t slave_latency_disable; /**< Parameters for the Disable slave latency option */ +} ble_gap_opt_t; +/**@} */ + + +/**@addtogroup BLE_GAP_FUNCTIONS Functions + * @{ */ + +/**@brief Set the local Bluetooth identity address. + * + * The local Bluetooth identity address is the address that identifies this device to other peers. + * The address type must be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC. + * + * @note The identity address cannot be changed while advertising, scanning or creating a connection. + * + * @note This address will be distributed to the peer during bonding. + * If the address changes, the address stored in the peer device will not be valid and the ability to + * reconnect using the old address will be lost. + * + * @note By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC upon being + * enabled. The address is a random number populated during the IC manufacturing process and remains unchanged + * for the lifetime of each IC. + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @endmscs + * + * @param[in] p_addr Pointer to address structure. + * + * @retval ::NRF_SUCCESS Address successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_STATE The identity address cannot be changed while advertising, + * scanning or creating a connection. + */ +SVCALL(SD_BLE_GAP_ADDR_SET, uint32_t, sd_ble_gap_addr_set(ble_gap_addr_t const *p_addr)); + + +/**@brief Get local Bluetooth identity address. + * + * @note This will always return the identity address irrespective of the privacy settings, + * i.e. the address type will always be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC. + * + * @param[out] p_addr Pointer to address structure to be filled in. + * + * @retval ::NRF_SUCCESS Address successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + */ +SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr)); + + +/**@brief Get the Bluetooth device address used by the advertiser. + * + * @note This function will return the local Bluetooth address used in advertising PDUs. When + * using privacy, the SoftDevice will generate a new private address every + * @ref ble_gap_privacy_params_t::private_addr_cycle_s configured using + * @ref sd_ble_gap_privacy_set. Hence depending on when the application calls this API, the + * address returned may not be the latest address that is used in the advertising PDUs. + * + * @param[in] adv_handle The advertising handle to get the address from. + * @param[out] p_addr Pointer to address structure to be filled in. + * + * @retval ::NRF_SUCCESS Address successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. + * @retval ::NRF_ERROR_INVALID_STATE The advertising set is currently not advertising. + */ +SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr)); + + +/**@brief Set the active whitelist in the SoftDevice. + * + * @note Only one whitelist can be used at a time and the whitelist is shared between the BLE roles. + * The whitelist cannot be set if a BLE role is using the whitelist. + * + * @note If an address is resolved using the information in the device identity list, then the whitelist + * filter policy applies to the peer identity address and not the resolvable address sent on air. + * + * @mscs + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC} + * @endmscs + * + * @param[in] pp_wl_addrs Pointer to a whitelist of peer addresses, if NULL the whitelist will be cleared. + * @param[in] len Length of the whitelist, maximum @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. + * + * @retval ::NRF_SUCCESS The whitelist is successfully set/cleared. + * @retval ::NRF_ERROR_INVALID_ADDR The whitelist (or one of its entries) provided is invalid. + * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE The whitelist is in use by a BLE role and cannot be set or cleared. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_DATA_SIZE The given whitelist size is invalid (zero or too large); this can only return when + * pp_wl_addrs is not NULL. + */ +SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const * const * pp_wl_addrs, uint8_t len)); + + +/**@brief Set device identity list. + * + * @note Only one device identity list can be used at a time and the list is shared between the BLE roles. + * The device identity list cannot be set if a BLE role is using the list. + * + * @param[in] pp_id_keys Pointer to an array of peer identity addresses and peer IRKs, if NULL the device identity list will be cleared. + * @param[in] pp_local_irks Pointer to an array of local IRKs. Each entry in the array maps to the entry in pp_id_keys at the same index. + * To fill in the list with the currently set device IRK for all peers, set to NULL. + * @param[in] len Length of the device identity list, maximum @ref BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT. + * + * @mscs + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS The device identity list successfully set/cleared. + * @retval ::NRF_ERROR_INVALID_ADDR The device identity list (or one of its entries) provided is invalid. + * This code may be returned if the local IRK list also has an invalid entry. + * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE The device identity list is in use and cannot be set or cleared. + * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE The device identity list contains multiple entries with the same identity address. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_DATA_SIZE The given device identity list size invalid (zero or too large); this can + * only return when pp_id_keys is not NULL. + */ +SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const * const * pp_id_keys, ble_gap_irk_t const * const * pp_local_irks, uint8_t len)); + + +/**@brief Set privacy settings. + * + * @note Privacy settings cannot be changed while advertising, scanning or creating a connection. + * + * @param[in] p_privacy_params Privacy settings. + * + * @mscs + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Set successfully. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied. + * @retval ::NRF_ERROR_INVALID_ADDR The pointer to privacy settings is NULL or invalid. + * Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer. + * @retval ::NRF_ERROR_INVALID_PARAM Out of range parameters are provided. + * @retval ::NRF_ERROR_INVALID_STATE Privacy settings cannot be changed while advertising, scanning + * or creating a connection. + */ +SVCALL(SD_BLE_GAP_PRIVACY_SET, uint32_t, sd_ble_gap_privacy_set(ble_gap_privacy_params_t const *p_privacy_params)); + + +/**@brief Get privacy settings. + * + * @note ::ble_gap_privacy_params_t::p_device_irk must be initialized to NULL or a valid address before this function is called. + * If it is initialized to a valid address, the address pointed to will contain the current device IRK on return. + * + * @param[in,out] p_privacy_params Privacy settings. + * + * @retval ::NRF_SUCCESS Privacy settings read. + * @retval ::NRF_ERROR_INVALID_ADDR The pointer given for returning the privacy settings may be NULL or invalid. + * Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer. + */ +SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t *p_privacy_params)); + + +/**@brief Configure an advertising set. Set, clear or update advertising and scan response data. + * + * @note The format of the advertising data will be checked by this call to ensure interoperability. + * Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and + * duplicating the local name in the advertising data and scan response data. + * + * @note In order to update advertising data while advertising, new advertising buffers must be provided. + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in,out] p_adv_handle Provide a pointer to a handle containing @ref BLE_GAP_ADV_SET_HANDLE_NOT_SET to configure + * a new advertising set. On success, a new handle is then returned through the pointer. + * Provide a pointer to an existing advertising handle to configure an existing advertising set. + * @param[in] p_adv_data Advertising data. If set to NULL, no advertising data will be used. See @ref ble_gap_adv_data_t. + * @param[in] p_adv_params Advertising parameters. When this function is used to update advertising data while advertising, + * this parameter must be NULL. See @ref ble_gap_adv_params_t. + * + * @retval ::NRF_SUCCESS Advertising set successfully configured. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied: + * - Invalid advertising data configuration specified. See @ref ble_gap_adv_data_t. + * - Invalid configuration of p_adv_params. See @ref ble_gap_adv_params_t. + * - Use of whitelist requested but whitelist has not been set, + * see @ref sd_ble_gap_whitelist_set. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR ble_gap_adv_params_t::p_peer_addr is invalid. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - It is invalid to provide non-NULL advertising set parameters while advertising. + * - It is invalid to provide the same data buffers while advertising. To update + * advertising data, provide new advertising buffers. + * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. Use @ref BLE_GAP_ADV_SET_HANDLE_NOT_SET to + * configure a new advertising handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied. + * @retval ::NRF_ERROR_INVALID_DATA Invalid data type(s) supplied. Check the advertising data format specification + * given in Bluetooth Specification Version 5.0, Volume 3, Part C, Chapter 11. + * @retval ::NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported data length or advertising parameter configuration. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to configure a new advertising handle. Update an + * existing advertising handle instead. + * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied. + */ +SVCALL(SD_BLE_GAP_ADV_SET_CONFIGURE, uint32_t, sd_ble_gap_adv_set_configure(uint8_t *p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params)); + + +/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). + * + * @note Only one advertiser may be active at any time. + * + * @events + * @event{@ref BLE_GAP_EVT_CONNECTED, Generated after connection has been established through connectable advertising.} + * @event{@ref BLE_GAP_EVT_ADV_SET_TERMINATED, Advertising set has terminated.} + * @event{@ref BLE_GAP_EVT_SCAN_REQ_REPORT, A scan request was received.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] adv_handle Advertising handle to advertise on, received from @ref sd_ble_gap_adv_set_configure. + * @param[in] conn_cfg_tag Tag identifying a configuration set by @ref sd_ble_cfg_set or + * @ref BLE_CONN_CFG_TAG_DEFAULT to use the default connection configuration. For non-connectable + * advertising, this is ignored. + * + * @retval ::NRF_SUCCESS The BLE stack has started advertising. + * @retval ::NRF_ERROR_INVALID_STATE adv_handle is not configured or already advertising. + * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached; connectable advertiser cannot be started. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Advertising handle not found. Configure a new adveriting handle with @ref sd_ble_gap_adv_set_configure. + * @retval ::NRF_ERROR_NOT_FOUND conn_cfg_tag not found. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied: + * - Invalid configuration of p_adv_params. See @ref ble_gap_adv_params_t. + * - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set. + * @retval ::NRF_ERROR_RESOURCES Either: + * - adv_handle is configured with connectable advertising, but the event_length parameter + * associated with conn_cfg_tag is too small to be able to establish a connection on + * the selected advertising phys. Use @ref sd_ble_cfg_set to increase the event length. + * - Not enough BLE role slots available. + Stop one or more currently active roles (Central, Peripheral, Broadcaster or Observer) and try again. + * - p_adv_params is configured with connectable advertising, but the event_length parameter + * associated with conn_cfg_tag is too small to be able to establish a connection on + * the selected advertising phys. Use @ref sd_ble_cfg_set to increase the event length. + */ +SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(uint8_t adv_handle, uint8_t conn_cfg_tag)); + + +/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). + * + * @mscs + * @mmsc{@ref BLE_GAP_ADV_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] adv_handle The advertising handle that should stop advertising. + * + * @retval ::NRF_SUCCESS The BLE stack has stopped advertising. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Invalid advertising handle. + * @retval ::NRF_ERROR_INVALID_STATE The advertising handle is not advertising. + */ +SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(uint8_t adv_handle)); + + + +/**@brief Update connection parameters. + * + * @details In the central role this will initiate a Link Layer connection parameter update procedure, + * otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for + * the central to perform the procedure. In both cases, and regardless of success or failure, the application + * will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event. + * + * @details This function can be used as a central both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested. + * + * @events + * @event{@ref BLE_GAP_EVT_CONN_PARAM_UPDATE, Result of the connection parameter update procedure.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CPU_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CPU_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CPU_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_conn_params Pointer to desired connection parameters. If NULL is provided on a peripheral role, + * the parameters in the PPCP characteristic of the GAP service will be used instead. + * If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected + * + * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. + * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress or link has not been established. + * @retval ::NRF_ERROR_BUSY Procedure already in progress, wait for pending procedures to complete and retry. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params)); + + +/**@brief Disconnect (GAP Link Termination). + * + * @details This call initiates the disconnection procedure, and its completion will be communicated to the application + * with a @ref BLE_GAP_EVT_DISCONNECTED event. + * + * @events + * @event{@ref BLE_GAP_EVT_DISCONNECTED, Generated when disconnection procedure is complete.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CONN_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are @ref BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION and @ref BLE_HCI_CONN_INTERVAL_UNACCEPTABLE). + * + * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress or link has not been established. + */ +SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code)); + + +/**@brief Set the radio's transmit power. + * + * @param[in] role The role to set the transmit power for, see @ref BLE_GAP_TX_POWER_ROLES for + * possible roles. + * @param[in] handle The handle parameter is interpreted depending on role: + * - If role is @ref BLE_GAP_TX_POWER_ROLE_CONN, this value is the specific connection handle. + * - If role is @ref BLE_GAP_TX_POWER_ROLE_ADV, the advertising set identified with the advertising handle, + * will use the specified transmit power, and include it in the advertising packet headers if + * @ref ble_gap_adv_properties_t::include_tx_power set. + * - For all other roles handle is ignored. + * @param[in] tx_power Radio transmit power in dBm (see note for accepted values). + * + * @note Supported tx_power values: -40dBm, -20dBm, -16dBm, -12dBm, -8dBm, -4dBm, 0dBm, +2dBm, +3dBm, +4dBm, +5dBm, +6dBm, +7dBm and +8dBm. + * @note The initiator will have the same transmit power as the scanner. + * @note When a connection is created it will inherit the transmit power from the initiator or + * advertiser leading to the connection. + * + * @retval ::NRF_SUCCESS Successfully changed the transmit power. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ADV_HANDLE Advertising handle not found. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(uint8_t role, uint16_t handle, int8_t tx_power)); + + +/**@brief Set GAP Appearance value. + * + * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES. + * + * @retval ::NRF_SUCCESS Appearance value set successfully. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + */ +SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance)); + + +/**@brief Get GAP Appearance value. + * + * @param[out] p_appearance Pointer to appearance (16-bit) to be filled in, see @ref BLE_APPEARANCES. + * + * @retval ::NRF_SUCCESS Appearance value retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance)); + + +/**@brief Set GAP Peripheral Preferred Connection Parameters. + * + * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters. + * + * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + */ +SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params)); + + +/**@brief Get GAP Peripheral Preferred Connection Parameters. + * + * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored. + * + * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params)); + + +/**@brief Set GAP device name. + * + * @note If the device name is located in application flash memory (see @ref ble_gap_cfg_device_name_t), + * it cannot be changed. Then @ref NRF_ERROR_FORBIDDEN will be returned. + * + * @param[in] p_write_perm Write permissions for the Device Name characteristic, see @ref ble_gap_conn_sec_mode_t. + * @param[in] p_dev_name Pointer to a UTF-8 encoded, <b>non NULL-terminated</b> string. + * @param[in] len Length of the UTF-8, <b>non NULL-terminated</b> string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN). + * + * @retval ::NRF_SUCCESS GAP device name and permissions set successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_FORBIDDEN Device name is not writable. + */ +SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len)); + + +/**@brief Get GAP device name. + * + * @note If the device name is longer than the size of the supplied buffer, + * p_len will return the complete device name length, + * and not the number of bytes actually returned in p_dev_name. + * The application may use this information to allocate a suitable buffer size. + * + * @param[out] p_dev_name Pointer to an empty buffer where the UTF-8 <b>non NULL-terminated</b> string will be placed. Set to NULL to obtain the complete device name length. + * @param[in,out] p_len Length of the buffer pointed by p_dev_name, complete device name length on output. + * + * @retval ::NRF_SUCCESS GAP device name retrieved successfully. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + */ +SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len)); + + +/**@brief Initiate the GAP Authentication procedure. + * + * @details In the central role, this function will send an SMP Pairing Request (or an SMP Pairing Failed if rejected), + * otherwise in the peripheral role, an SMP Security Request will be sent. + * + * @events + * @event{Depending on the security parameters set and the packet exchanges with the peer\, the following events may be generated:} + * @event{@ref BLE_GAP_EVT_SEC_PARAMS_REQUEST} + * @event{@ref BLE_GAP_EVT_SEC_INFO_REQUEST} + * @event{@ref BLE_GAP_EVT_PASSKEY_DISPLAY} + * @event{@ref BLE_GAP_EVT_KEY_PRESSED} + * @event{@ref BLE_GAP_EVT_AUTH_KEY_REQUEST} + * @event{@ref BLE_GAP_EVT_LESC_DHKEY_REQUEST} + * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE} + * @event{@ref BLE_GAP_EVT_AUTH_STATUS} + * @event{@ref BLE_GAP_EVT_TIMEOUT} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_SEC_REQ_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing or bonding procedure. + * In the peripheral role, only the bond, mitm, lesc and keypress fields of this structure are used. + * In the central role, this pointer may be NULL to reject a Security Request. + * + * @retval ::NRF_SUCCESS Successfully initiated authentication procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - No link has been established. + * - An encryption is already executing or queued. + * @retval ::NRF_ERROR_NO_MEM The maximum number of authentication procedures that can run in parallel for the given role is reached. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported. + * @retval ::NRF_ERROR_TIMEOUT A SMP timeout has occurred, and further SMP operations on this link is prohibited. + */ +SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params)); + + +/**@brief Reply with GAP security parameters. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_CONFIRM_FAIL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_KS_TOO_SMALL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_APP_ERROR_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_REMOTE_PAIRING_FAIL_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_TIMEOUT_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS. + * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. In the central role this must be set to NULL, as the parameters have + * already been provided during a previous call to @ref sd_ble_gap_authenticate. + * @param[in,out] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys generated and/or distributed as a result of the ongoing security procedure + * will be stored into the memory referenced by the pointers inside this structure. The keys will be stored and available to the application + * upon reception of a @ref BLE_GAP_EVT_AUTH_STATUS event. + * Note that the SoftDevice expects the application to provide memory for storing the + * peer's keys. So it must be ensured that the relevant pointers inside this structure are not NULL. The pointers to the local key + * can, however, be NULL, in which case, the local key data will not be available to the application upon reception of the + * @ref BLE_GAP_EVT_AUTH_STATUS event. + * + * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Security parameters has not been requested. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported. + */ +SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset)); + + +/**@brief Reply with an authentication key. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST or a @ref BLE_GAP_EVT_PASSKEY_DISPLAY, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES. + * @param[in] p_key If key type is @ref BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL. + * If key type is @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination) + * or NULL when confirming LE Secure Connections Numeric Comparison. + * If key type is @ref BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in little-endian format. + * + * @retval ::NRF_SUCCESS Authentication key successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Authentication key has not been requested. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key)); + + +/**@brief Reply with an LE Secure connections DHKey. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_dhkey LE Secure Connections DHKey. + * + * @retval ::NRF_SUCCESS DHKey successfully set. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - The peer is not authenticated. + * - The application has not pulled a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_DHKEY_REPLY, uint32_t, sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey)); + + +/**@brief Notify the peer of a local keypress. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] kp_not See @ref BLE_GAP_KP_NOT_TYPES. + * + * @retval ::NRF_SUCCESS Keypress notification successfully queued for transmission. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Authentication key not requested. + * - Passkey has not been entered. + * - Keypresses have not been enabled by both peers. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time. + */ +SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not)); + + +/**@brief Generate a set of OOB data to send to a peer out of band. + * + * @note The @ref ble_gap_addr_t included in the OOB data returned will be the currently active one (or, if a connection has already been established, + * the one used during connection setup). The application may manually overwrite it with an updated value. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. Can be @ref BLE_CONN_HANDLE_INVALID if a BLE connection has not been established yet. + * @param[in] p_pk_own LE Secure Connections local P-256 Public Key. + * @param[out] p_oobd_own The OOB data to be sent out of band to a peer. + * + * @retval ::NRF_SUCCESS OOB data successfully generated. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own)); + +/**@brief Provide the OOB data sent/received out of band. + * + * @note An authentication procedure with OOB selected as an algorithm must be in progress when calling this function. + * @note A @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event with the oobd_req set to 1 must have been received prior to calling this function. + * + * @events + * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_oobd_own The OOB data sent out of band to a peer or NULL if the peer has not received OOB data. + * Must correspond to @ref ble_gap_sec_params_t::oob flag in @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. + * @param[in] p_oobd_peer The OOB data received out of band from a peer or NULL if none received. + * Must correspond to @ref ble_gap_sec_params_t::oob flag + * in @ref sd_ble_gap_authenticate in the central role or + * in @ref sd_ble_gap_sec_params_reply in the peripheral role. + * + * @retval ::NRF_SUCCESS OOB data accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Authentication key not requested + * - Not expecting LESC OOB data + * - Have not actually exchanged passkeys. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_LESC_OOB_DATA_SET, uint32_t, sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer)); + + +/**@brief Initiate GAP Encryption procedure. + * + * @details In the central role, this function will initiate the encryption procedure using the encryption information provided. + * + * @events + * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE, The connection security has been updated.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_ENC_MSC} + * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure. + * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. + * + * @retval ::NRF_SUCCESS Successfully initiated authentication procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in the Peripheral role. + * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, wait for pending procedures to complete and retry. + */ +SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info)); + + +/**@brief Reply with GAP security information. + * + * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in @ref NRF_ERROR_INVALID_STATE. + * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. + * @note Data signing is not yet supported, and p_sign_info must therefore be NULL. + * + * @mscs + * @mmsc{@ref BLE_GAP_PERIPH_ENC_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available. + * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available. + * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available. + * + * @retval ::NRF_SUCCESS Successfully accepted security information. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - No link has been established. + * - No @ref BLE_GAP_EVT_SEC_REQUEST pending. + * - LE long term key requested command not allowed. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info)); + + +/**@brief Get the current connection security. + * + * @param[in] conn_handle Connection handle. + * @param[out] p_conn_sec Pointer to a @ref ble_gap_conn_sec_t structure to be filled in. + * + * @retval ::NRF_SUCCESS Current connection security successfully retrieved. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec)); + + +/**@brief Start reporting the received signal strength to the application. + * + * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called. + * + * @events + * @event{@ref BLE_GAP_EVT_RSSI_CHANGED, New RSSI data available. How often the event is generated is + * dependent on the settings of the <code>threshold_dbm</code> + * and <code>skip_count</code> input parameters.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] threshold_dbm Minimum change in dBm before triggering the @ref BLE_GAP_EVT_RSSI_CHANGED event. Events are disabled if threshold_dbm equals @ref BLE_GAP_RSSI_THRESHOLD_INVALID. + * @param[in] skip_count Number of RSSI samples with a change of threshold_dbm or more before sending a new @ref BLE_GAP_EVT_RSSI_CHANGED event. + * + * @retval ::NRF_SUCCESS Successfully activated RSSI reporting. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is already ongoing. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count)); + + +/**@brief Stop reporting the received signal strength. + * + * @note An RSSI change detected before the call but not yet received by the application + * may be reported after @ref sd_ble_gap_rssi_stop has been called. + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * + * @retval ::NRF_SUCCESS Successfully deactivated RSSI reporting. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + */ +SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle)); + + +/**@brief Get the received signal strength for the last connection event. + * + * @ref sd_ble_gap_rssi_start must be called to start reporting RSSI before using this function. @ref NRF_ERROR_NOT_FOUND + * will be returned until RSSI was sampled for the first time after calling @ref sd_ble_gap_rssi_start. + * @note ERRATA-153 requires the rssi sample to be compensated based on a temperature measurement. + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[out] p_rssi Pointer to the location where the RSSI measurement shall be stored. + * @param[out] p_ch_index Pointer to the location where Channel Index for the RSSI measurement shall be stored. + * + * @retval ::NRF_SUCCESS Successfully read the RSSI. + * @retval ::NRF_ERROR_NOT_FOUND No sample is available. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing. + */ +SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi, uint8_t *p_ch_index)); + + +/**@brief Start or continue scanning (GAP Discovery procedure, Observer Procedure). + * + * @note A call to this function will require the application to keep the memory pointed by + * p_adv_report_buffer alive until the buffer is released. The buffer is released when the scanner is stopped + * or when this function is called with another buffer. + * + * @note The scanner will automatically stop in the following cases: + * - @ref sd_ble_gap_scan_stop is called. + * - @ref sd_ble_gap_connect is called. + * - A @ref BLE_GAP_EVT_TIMEOUT with source set to @ref BLE_GAP_TIMEOUT_SRC_SCAN is received. + * - When a @ref BLE_GAP_EVT_ADV_REPORT event is received and @ref ble_gap_adv_report_type_t::status is not set to + * @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA. In this case scanning is only paused to let the application + * access received data. The application must call this function to continue scanning, or call @ref sd_ble_gap_scan_stop + * to stop scanning. + * + * @note If a @ref BLE_GAP_EVT_ADV_REPORT event is received with @ref ble_gap_adv_report_type_t::status set to + * @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_MORE_DATA, the scanner will continue scanning, and the application will + * receive more reports from this advertising event. The following reports will include the old and new received data. + * + * @events + * @event{@ref BLE_GAP_EVT_ADV_REPORT, An advertising or scan response packet has been received.} + * @event{@ref BLE_GAP_EVT_TIMEOUT, Scanner has timed out.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_SCAN_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @param[in] p_scan_params Pointer to scan parameters structure. When this function is used to continue + * scanning, this parameter must be NULL. + * @param[in] p_adv_report_buffer Pointer to buffer used to store incoming advertising data. + * The memory pointed to should be kept alive until the scanning is stopped. + * See @ref BLE_GAP_SCAN_BUFFER_SIZE for minimum and maximum buffer size. + * If the scanner receives advertising data larger than can be stored in the buffer, + * a @ref BLE_GAP_EVT_ADV_REPORT will be raised with @ref ble_gap_adv_report_type_t::status + * set to @ref BLE_GAP_ADV_DATA_STATUS_INCOMPLETE_TRUNCATED. + * + * @retval ::NRF_SUCCESS Successfully initiated scanning procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either: + * - Scanning is already ongoing and p_scan_params was not NULL + * - Scanning is not running and p_scan_params was NULL. + * - The scanner has timed out when this function is called to continue scanning. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. See @ref ble_gap_scan_params_t. + * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported parameters supplied. See @ref ble_gap_scan_params_t. + * @retval ::NRF_ERROR_INVALID_LENGTH The provided buffer length is invalid. See @ref BLE_GAP_SCAN_BUFFER_MIN. + * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available. + * Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again + */ +SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const * p_adv_report_buffer)); + + +/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure). + * + * @note The buffer provided in @ref sd_ble_gap_scan_start is released. + * + * @mscs + * @mmsc{@ref BLE_GAP_SCAN_MSC} + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully stopped scanning procedure. + * @retval ::NRF_ERROR_INVALID_STATE Not in the scanning state. + */ +SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void)); + + +/**@brief Create a connection (GAP Link Establishment). + * + * @note If a scanning procedure is currently in progress it will be automatically stopped when calling this function. + * The scanning procedure will be stopped even if the function returns an error. + * + * @events + * @event{@ref BLE_GAP_EVT_CONNECTED, A connection was established.} + * @event{@ref BLE_GAP_EVT_TIMEOUT, Failed to establish a connection.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC} + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC} + * @endmscs + * + * @param[in] p_peer_addr Pointer to peer identity address. If @ref ble_gap_scan_params_t::filter_policy is set to use + * whitelist, then p_peer_addr is ignored. + * @param[in] p_scan_params Pointer to scan parameters structure. + * @param[in] p_conn_params Pointer to desired connection parameters. + * @param[in] conn_cfg_tag Tag identifying a configuration set by @ref sd_ble_cfg_set or + * @ref BLE_CONN_CFG_TAG_DEFAULT to use the default connection configuration. + * + * @retval ::NRF_SUCCESS Successfully initiated connection procedure. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * - Invalid parameter(s) in p_scan_params or p_conn_params. + * - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set. + * - Peer address was not present in the device identity list, see @ref sd_ble_gap_device_identities_set. + * @retval ::NRF_ERROR_NOT_FOUND conn_cfg_tag not found. + * @retval ::NRF_ERROR_INVALID_STATE The SoftDevice is in an invalid state to perform this operation. This may be due to an + * existing locally initiated connect procedure, which must complete before initiating again. + * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address. + * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached. + * @retval ::NRF_ERROR_RESOURCES Either: + * - Not enough BLE role slots available. + * Stop one or more currently active roles (Central, Peripheral or Observer) and try again. + * - The event_length parameter associated with conn_cfg_tag is too small to be able to + * establish a connection on the selected @ref ble_gap_scan_params_t::scan_phys. + * Use @ref sd_ble_cfg_set to increase the event length. + */ +SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params, uint8_t conn_cfg_tag)); + + +/**@brief Cancel a connection establishment. + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully canceled an ongoing connection procedure. + * @retval ::NRF_ERROR_INVALID_STATE No locally initiated connect procedure started or connection + * completed occurred. + */ +SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void)); + + +/**@brief Initiate or respond to a PHY Update Procedure + * + * @details This function is used to initiate or respond to a PHY Update Procedure. It will always + * generate a @ref BLE_GAP_EVT_PHY_UPDATE event if successfully executed. + * If this function is used to initiate a PHY Update procedure and the only option + * provided in @ref ble_gap_phys_t::tx_phys and @ref ble_gap_phys_t::rx_phys is the + * currently active PHYs in the respective directions, the SoftDevice will generate a + * @ref BLE_GAP_EVT_PHY_UPDATE with the current PHYs set and will not initiate the + * procedure in the Link Layer. + * + * If @ref ble_gap_phys_t::tx_phys or @ref ble_gap_phys_t::rx_phys is @ref BLE_GAP_PHY_AUTO, + * then the stack will select PHYs based on the peer's PHY preferences and the local link + * configuration. The PHY Update procedure will for this case result in a PHY combination + * that respects the time constraints configured with @ref sd_ble_cfg_set and the current + * link layer data length. + * + * When acting as a central, the SoftDevice will select the fastest common PHY in each direction. + * + * If the peer does not support the PHY Update Procedure, then the resulting + * @ref BLE_GAP_EVT_PHY_UPDATE event will have a status set to + * @ref BLE_HCI_UNSUPPORTED_REMOTE_FEATURE. + * + * If the PHY procedure was rejected by the peer due to a procedure collision, the status + * will be @ref BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION or + * @ref BLE_HCI_DIFFERENT_TRANSACTION_COLLISION. + * If the peer responds to the PHY Update procedure with invalid parameters, the status + * will be @ref BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS. + * If the PHY procedure was rejected by the peer for a different reason, the status will + * contain the reason as specified by the peer. + * + * @events + * @event{@ref BLE_GAP_EVT_PHY_UPDATE, Result of the PHY Update Procedure.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GAP_CENTRAL_PHY_UPDATE} + * @mmsc{@ref BLE_GAP_PERIPHERAL_PHY_UPDATE} + * @endmscs + * + * @param[in] conn_handle Connection handle to indicate the connection for which the PHY Update is requested. + * @param[in] p_gap_phys Pointer to PHY structure. + * + * @retval ::NRF_SUCCESS Successfully requested a PHY Update. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::NRF_ERROR_RESOURCES The connection event length configured for this link is not sufficient for the combination of + * @ref ble_gap_phys_t::tx_phys, @ref ble_gap_phys_t::rx_phys, and @ref ble_gap_data_length_params_t. + * The connection event length is configured with @ref BLE_CONN_CFG_GAP using @ref sd_ble_cfg_set. + * @retval ::NRF_ERROR_BUSY Procedure is already in progress or not allowed at this time. Process pending events and wait for the pending procedure to complete and retry. + * + */ +SVCALL(SD_BLE_GAP_PHY_UPDATE, uint32_t, sd_ble_gap_phy_update(uint16_t conn_handle, ble_gap_phys_t const *p_gap_phys)); + + +/**@brief Initiate or respond to a Data Length Update Procedure. + * + * @note If the application uses @ref BLE_GAP_DATA_LENGTH_AUTO for one or more members of + * p_dl_params, the SoftDevice will choose the highest value supported in current + * configuration and connection parameters. + * @note If the link PHY is Coded, the SoftDevice will ensure that the MaxTxTime and/or MaxRxTime + * used in the Data Length Update procedure is at least 2704 us. Otherwise, MaxTxTime and + * MaxRxTime will be limited to maximum 2120 us. + * + * @param[in] conn_handle Connection handle. + * @param[in] p_dl_params Pointer to local parameters to be used in Data Length Update + * Procedure. Set any member to @ref BLE_GAP_DATA_LENGTH_AUTO to let + * the SoftDevice automatically decide the value for that member. + * Set to NULL to use automatic values for all members. + * @param[out] p_dl_limitation Pointer to limitation to be written when local device does not + * have enough resources or does not support the requested Data Length + * Update parameters. Ignored if NULL. + * + * @mscs + * @mmsc{@ref BLE_GAP_DATA_LENGTH_UPDATE_PROCEDURE_MSC} + * @endmscs + * + * @retval ::NRF_SUCCESS Successfully set Data Length Extension initiation/response parameters. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter supplied. + * @retval ::NRF_ERROR_INVALID_STATE No link has been established. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. + * @retval ::NRF_ERROR_NOT_SUPPORTED The requested parameters are not supported by the SoftDevice. Inspect + * p_dl_limitation to see which parameter is not supported. + * @retval ::NRF_ERROR_RESOURCES The connection event length configured for this link is not sufficient for the requested parameters. + * Use @ref sd_ble_cfg_set with @ref BLE_CONN_CFG_GAP to increase the connection event length. + * Inspect p_dl_limitation to see where the limitation is. + * @retval ::NRF_ERROR_BUSY Peer has already initiated a Data Length Update Procedure. Process the + * pending @ref BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST event to respond. + */ +SVCALL(SD_BLE_GAP_DATA_LENGTH_UPDATE, uint32_t, sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t *p_dl_limitation)); + +/**@brief Start the Quality of Service (QoS) channel survey module. + * + * @details The channel survey module provides measurements of the energy levels on + * the Bluetooth Low Energy channels. When the module is enabled, @ref BLE_GAP_EVT_QOS_CHANNEL_SURVEY_REPORT + * events will periodically report the measured energy levels for each channel. + * + * @note The measurements are scheduled with lower priority than other Bluetooth Low Energy roles, + * Radio Timeslot API events and Flash API events. + * + * @note The channel survey module will attempt to do measurements so that the average interval + * between measurements will be interval_us. However due to the channel survey module + * having the lowest priority of all roles and modules, this may not be possible. In that + * case fewer than expected channel survey reports may be given. + * + * @note In order to use the channel survey module, @ref ble_gap_cfg_role_count_t::qos_channel_survey_role_available + * must be set. This is done using @ref sd_ble_cfg_set. + * + * @param[in] interval_us Requested average interval for the measurements and reports. See + * @ref BLE_GAP_QOS_CHANNEL_SURVEY_INTERVALS for valid ranges. If set + * to @ref BLE_GAP_QOS_CHANNEL_SURVEY_INTERVAL_CONTINUOUS, the channel + * survey role will be scheduled at every available opportunity. + * + * @retval ::NRF_SUCCESS The module is successfully started. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter supplied. interval_us is out of the + * allowed range. + * @retval ::NRF_ERROR_INVALID_STATE Trying to start the module when already running. + * @retval ::NRF_ERROR_RESOURCES The channel survey module is not available to the application. + * Set @ref ble_gap_cfg_role_count_t::qos_channel_survey_role_available using + * @ref sd_ble_cfg_set. + */ +SVCALL(SD_BLE_GAP_QOS_CHANNEL_SURVEY_START, uint32_t, sd_ble_gap_qos_channel_survey_start(uint32_t interval_us)); + +/**@brief Stop the Quality of Service (QoS) channel survey module. + * + * @retval ::NRF_SUCCESS The module is successfully stopped. + * @retval ::NRF_ERROR_INVALID_STATE Trying to stop the module when it is not running. + */ +SVCALL(SD_BLE_GAP_QOS_CHANNEL_SURVEY_STOP, uint32_t, sd_ble_gap_qos_channel_survey_stop(void)); + + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GAP_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gatt.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gatt.h new file mode 100755 index 0000000..9cb577c --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gatt.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common + @{ + @brief Common definitions and prototypes for the GATT interfaces. + */ + +#ifndef BLE_GATT_H__ +#define BLE_GATT_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATT_DEFINES Defines + * @{ */ + +/** @brief Default ATT MTU, in bytes. */ +#define BLE_GATT_ATT_MTU_DEFAULT 23 + +/**@brief Invalid Attribute Handle. */ +#define BLE_GATT_HANDLE_INVALID 0x0000 + +/**@brief First Attribute Handle. */ +#define BLE_GATT_HANDLE_START 0x0001 + +/**@brief Last Attribute Handle. */ +#define BLE_GATT_HANDLE_END 0xFFFF + +/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources + * @{ */ +#define BLE_GATT_TIMEOUT_SRC_PROTOCOL 0x00 /**< ATT Protocol timeout. */ +/** @} */ + +/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations + * @{ */ +#define BLE_GATT_OP_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATT_OP_WRITE_REQ 0x01 /**< Write Request. */ +#define BLE_GATT_OP_WRITE_CMD 0x02 /**< Write Command. */ +#define BLE_GATT_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ +#define BLE_GATT_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ +#define BLE_GATT_OP_EXEC_WRITE_REQ 0x05 /**< Execute Write Request. */ +/** @} */ + +/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags + * @{ */ +#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00 /**< Cancel prepared write. */ +#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE 0x01 /**< Execute prepared write. */ +/** @} */ + +/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations + * @{ */ +#define BLE_GATT_HVX_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATT_HVX_NOTIFICATION 0x01 /**< Handle Value Notification. */ +#define BLE_GATT_HVX_INDICATION 0x02 /**< Handle Value Indication. */ +/** @} */ + +/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes + * @{ */ +#define BLE_GATT_STATUS_SUCCESS 0x0000 /**< Success. */ +#define BLE_GATT_STATUS_UNKNOWN 0x0001 /**< Unknown or not applicable status. */ +#define BLE_GATT_STATUS_ATTERR_INVALID 0x0100 /**< ATT Error: Invalid Error Code. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE 0x0101 /**< ATT Error: Invalid Attribute Handle. */ +#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED 0x0102 /**< ATT Error: Read not permitted. */ +#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED 0x0103 /**< ATT Error: Write not permitted. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_PDU 0x0104 /**< ATT Error: Used in ATT as Invalid PDU. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION 0x0105 /**< ATT Error: Authenticated link required. */ +#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED 0x0106 /**< ATT Error: Used in ATT as Request Not Supported. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET 0x0107 /**< ATT Error: Offset specified was past the end of the attribute. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION 0x0108 /**< ATT Error: Used in ATT as Insufficient Authorization. */ +#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL 0x0109 /**< ATT Error: Used in ATT as Prepare Queue Full. */ +#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND 0x010A /**< ATT Error: Used in ATT as Attribute not found. */ +#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG 0x010B /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE 0x010C /**< ATT Error: Encryption key size used is insufficient. */ +#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH 0x010D /**< ATT Error: Invalid value size. */ +#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR 0x010E /**< ATT Error: Very unlikely error. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION 0x010F /**< ATT Error: Encrypted link required. */ +#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE 0x0110 /**< ATT Error: Attribute type is not a supported grouping attribute. */ +#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES 0x0111 /**< ATT Error: Encrypted link required. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN 0x0112 /**< ATT Error: Reserved for Future Use range #1 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END 0x017F /**< ATT Error: Reserved for Future Use range #1 end. */ +#define BLE_GATT_STATUS_ATTERR_APP_BEGIN 0x0180 /**< ATT Error: Application range begin. */ +#define BLE_GATT_STATUS_ATTERR_APP_END 0x019F /**< ATT Error: Application range end. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN 0x01A0 /**< ATT Error: Reserved for Future Use range #2 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END 0x01DF /**< ATT Error: Reserved for Future Use range #2 end. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN 0x01E0 /**< ATT Error: Reserved for Future Use range #3 begin. */ +#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END 0x01FC /**< ATT Error: Reserved for Future Use range #3 end. */ +#define BLE_GATT_STATUS_ATTERR_CPS_WRITE_REQ_REJECTED 0x01FC /**< ATT Common Profile and Service Error: Write request rejected. */ +#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR 0x01FD /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */ +#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG 0x01FE /**< ATT Common Profile and Service Error: Procedure Already in Progress. */ +#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE 0x01FF /**< ATT Common Profile and Service Error: Out Of Range. */ +/** @} */ + + +/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats + * @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml + * @{ */ +#define BLE_GATT_CPF_FORMAT_RFU 0x00 /**< Reserved For Future Use. */ +#define BLE_GATT_CPF_FORMAT_BOOLEAN 0x01 /**< Boolean. */ +#define BLE_GATT_CPF_FORMAT_2BIT 0x02 /**< Unsigned 2-bit integer. */ +#define BLE_GATT_CPF_FORMAT_NIBBLE 0x03 /**< Unsigned 4-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT8 0x04 /**< Unsigned 8-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT12 0x05 /**< Unsigned 12-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT16 0x06 /**< Unsigned 16-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT24 0x07 /**< Unsigned 24-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT32 0x08 /**< Unsigned 32-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT48 0x09 /**< Unsigned 48-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT64 0x0A /**< Unsigned 64-bit integer. */ +#define BLE_GATT_CPF_FORMAT_UINT128 0x0B /**< Unsigned 128-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT8 0x0C /**< Signed 2-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT12 0x0D /**< Signed 12-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT16 0x0E /**< Signed 16-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT24 0x0F /**< Signed 24-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT32 0x10 /**< Signed 32-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT48 0x11 /**< Signed 48-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT64 0x12 /**< Signed 64-bit integer. */ +#define BLE_GATT_CPF_FORMAT_SINT128 0x13 /**< Signed 128-bit integer. */ +#define BLE_GATT_CPF_FORMAT_FLOAT32 0x14 /**< IEEE-754 32-bit floating point. */ +#define BLE_GATT_CPF_FORMAT_FLOAT64 0x15 /**< IEEE-754 64-bit floating point. */ +#define BLE_GATT_CPF_FORMAT_SFLOAT 0x16 /**< IEEE-11073 16-bit SFLOAT. */ +#define BLE_GATT_CPF_FORMAT_FLOAT 0x17 /**< IEEE-11073 32-bit FLOAT. */ +#define BLE_GATT_CPF_FORMAT_DUINT16 0x18 /**< IEEE-20601 format. */ +#define BLE_GATT_CPF_FORMAT_UTF8S 0x19 /**< UTF-8 string. */ +#define BLE_GATT_CPF_FORMAT_UTF16S 0x1A /**< UTF-16 string. */ +#define BLE_GATT_CPF_FORMAT_STRUCT 0x1B /**< Opaque Structure. */ +/** @} */ + +/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces + * @{ + */ +#define BLE_GATT_CPF_NAMESPACE_BTSIG 0x01 /**< Bluetooth SIG defined Namespace. */ +#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATT_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATT connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_PARAM att_mtu is smaller than @ref BLE_GATT_ATT_MTU_DEFAULT. + */ +typedef struct +{ + uint16_t att_mtu; /**< Maximum size of ATT packet the SoftDevice can send or receive. + The default and minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + @mscs + @mmsc{@ref BLE_GATTC_MTU_EXCHANGE} + @mmsc{@ref BLE_GATTS_MTU_EXCHANGE} + @endmscs + */ +} ble_gatt_conn_cfg_t; + +/**@brief GATT Characteristic Properties. */ +typedef struct +{ + /* Standard properties */ + uint8_t broadcast :1; /**< Broadcasting of the value permitted. */ + uint8_t read :1; /**< Reading the value permitted. */ + uint8_t write_wo_resp :1; /**< Writing the value with Write Command permitted. */ + uint8_t write :1; /**< Writing the value with Write Request permitted. */ + uint8_t notify :1; /**< Notification of the value permitted. */ + uint8_t indicate :1; /**< Indications of the value permitted. */ + uint8_t auth_signed_wr :1; /**< Writing the value with Signed Write Command permitted. */ +} ble_gatt_char_props_t; + +/**@brief GATT Characteristic Extended Properties. */ +typedef struct +{ + /* Extended properties */ + uint8_t reliable_wr :1; /**< Writing the value with Queued Write operations permitted. */ + uint8_t wr_aux :1; /**< Writing the Characteristic User Description descriptor permitted. */ +} ble_gatt_char_ext_props_t; + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GATT_H__ + +/** @} */ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gattc.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gattc.h new file mode 100755 index 0000000..7fb3920 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gattc.h @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2011 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client + @{ + @brief Definitions and prototypes for the GATT Client interface. + */ + +#ifndef BLE_GATTC_H__ +#define BLE_GATTC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" +#include "ble_gatt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations + * @{ */ + +/**@brief GATTC API SVC numbers. */ +enum BLE_GATTC_SVCS +{ + SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ + SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ + SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ + SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ + SD_BLE_GATTC_ATTR_INFO_DISCOVER, /**< Attribute Information Discovery. */ + SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ + SD_BLE_GATTC_READ, /**< Generic read. */ + SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ + SD_BLE_GATTC_WRITE, /**< Generic write. */ + SD_BLE_GATTC_HV_CONFIRM, /**< Handle Value Confirmation. */ + SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. */ +}; + +/** + * @brief GATT Client Event IDs. + */ +enum BLE_GATTC_EVTS +{ + BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t. */ + BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. \n See @ref ble_gattc_evt_rel_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. \n See @ref ble_gattc_evt_char_disc_rsp_t. */ + BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. \n See @ref ble_gattc_evt_desc_disc_rsp_t. */ + BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, /**< Attribute Information Response event. \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */ + BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t. */ + BLE_GATTC_EVT_READ_RSP, /**< Read Response event. \n See @ref ble_gattc_evt_read_rsp_t. */ + BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. \n See @ref ble_gattc_evt_char_vals_read_rsp_t. */ + BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. \n See @ref ble_gattc_evt_write_rsp_t. */ + BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm. \n See @ref ble_gattc_evt_hvx_t. */ + BLE_GATTC_EVT_EXCHANGE_MTU_RSP, /**< Exchange MTU Response event. \n See @ref ble_gattc_evt_exchange_mtu_rsp_t. */ + BLE_GATTC_EVT_TIMEOUT, /**< Timeout event. \n See @ref ble_gattc_evt_timeout_t. */ + BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE /**< Write without Response transmission complete. \n See @ref ble_gattc_evt_write_cmd_tx_complete_t. */ +}; + +/** @} */ + +/** @addtogroup BLE_GATTC_DEFINES Defines + * @{ */ + +/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC + * @{ */ +#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */ +/** @} */ + +/** @defgroup BLE_GATTC_ATTR_INFO_FORMAT Attribute Information Formats + * @{ */ +#define BLE_GATTC_ATTR_INFO_FORMAT_16BIT 1 /**< 16-bit Attribute Information Format. */ +#define BLE_GATTC_ATTR_INFO_FORMAT_128BIT 2 /**< 128-bit Attribute Information Format. */ +/** @} */ + +/** @defgroup BLE_GATTC_DEFAULTS GATT Client defaults + * @{ */ +#define BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT 1 /**< Default number of Write without Response that can be queued for transmission. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATTC_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATTC connection configuration parameters, set with @ref sd_ble_cfg_set. + */ +typedef struct +{ + uint8_t write_cmd_tx_queue_size; /**< The guaranteed minimum number of Write without Response that can be queued for transmission. + The default value is @ref BLE_GATTC_WRITE_CMD_TX_QUEUE_SIZE_DEFAULT */ +} ble_gattc_conn_cfg_t; + +/**@brief Operation Handle Range. */ +typedef struct +{ + uint16_t start_handle; /**< Start Handle. */ + uint16_t end_handle; /**< End Handle. */ +} ble_gattc_handle_range_t; + + +/**@brief GATT service. */ +typedef struct +{ + ble_uuid_t uuid; /**< Service UUID. */ + ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ +} ble_gattc_service_t; + + +/**@brief GATT include. */ +typedef struct +{ + uint16_t handle; /**< Include Handle. */ + ble_gattc_service_t included_srvc; /**< Handle of the included service. */ +} ble_gattc_include_t; + + +/**@brief GATT characteristic. */ +typedef struct +{ + ble_uuid_t uuid; /**< Characteristic UUID. */ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + uint8_t char_ext_props : 1; /**< Extended properties present. */ + uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ + uint16_t handle_value; /**< Handle of the Characteristic Value. */ +} ble_gattc_char_t; + + +/**@brief GATT descriptor. */ +typedef struct +{ + uint16_t handle; /**< Descriptor Handle. */ + ble_uuid_t uuid; /**< Descriptor UUID. */ +} ble_gattc_desc_t; + + +/**@brief Write Parameters. */ +typedef struct +{ + uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ + uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ + uint16_t handle; /**< Handle to the attribute to be written. */ + uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ + uint16_t len; /**< Length of data in bytes. */ + uint8_t const *p_value; /**< Pointer to the value data. */ +} ble_gattc_write_params_t; + +/**@brief Attribute Information for 16-bit Attribute UUID. */ +typedef struct +{ + uint16_t handle; /**< Attribute handle. */ + ble_uuid_t uuid; /**< 16-bit Attribute UUID. */ +} ble_gattc_attr_info16_t; + +/**@brief Attribute Information for 128-bit Attribute UUID. */ +typedef struct +{ + uint16_t handle; /**< Attribute handle. */ + ble_uuid128_t uuid; /**< 128-bit Attribute UUID. */ +} ble_gattc_attr_info128_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Service count. */ + ble_gattc_service_t services[1]; /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_prim_srvc_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Include count. */ + ble_gattc_include_t includes[1]; /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_rel_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Characteristic count. */ + ble_gattc_char_t chars[1]; /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Descriptor count. */ + ble_gattc_desc_t descs[1]; /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_desc_disc_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */ +typedef struct +{ + uint16_t count; /**< Attribute count. */ + uint8_t format; /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */ + union { + ble_gattc_attr_info16_t attr_info16[1]; /**< Attribute information for 16-bit Attribute UUID. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ + ble_gattc_attr_info128_t attr_info128[1]; /**< Attribute information for 128-bit Attribute UUID. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ + } info; /**< Attribute information union. */ +} ble_gattc_evt_attr_info_disc_rsp_t; + +/**@brief GATT read by UUID handle value pair. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint8_t *p_value; /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */ +} ble_gattc_handle_value_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */ +typedef struct +{ + uint16_t count; /**< Handle-Value Pair Count. */ + uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ + uint8_t handle_value[1]; /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter. + @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_val_by_uuid_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint16_t offset; /**< Offset of the attribute data. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */ +typedef struct +{ + uint16_t len; /**< Concatenated Attribute values length. */ + uint8_t values[1]; /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_char_vals_read_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ + uint16_t offset; /**< Data offset. */ + uint16_t len; /**< Data length. */ + uint8_t data[1]; /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_write_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */ +typedef struct +{ + uint16_t handle; /**< Handle to which the HVx operation applies. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t len; /**< Attribute data length. */ + uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gattc_evt_hvx_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. */ +typedef struct +{ + uint16_t server_rx_mtu; /**< Server RX MTU size. */ +} ble_gattc_evt_exchange_mtu_rsp_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ +} ble_gattc_evt_timeout_t; + +/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE. */ +typedef struct +{ + uint8_t count; /**< Number of write without response transmissions completed. */ +} ble_gattc_evt_write_cmd_tx_complete_t; + +/**@brief GATTC event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ + union + { + ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ + ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ + ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ + ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ + ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ + ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ + ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ + ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ + ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ + ble_gattc_evt_exchange_mtu_rsp_t exchange_mtu_rsp; /**< Exchange MTU Response Event Parameters. */ + ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ + ble_gattc_evt_attr_info_disc_rsp_t attr_info_disc_rsp; /**< Attribute Information Discovery Event Parameters. */ + ble_gattc_evt_write_cmd_tx_complete_t write_cmd_tx_complete; /**< Write without Response transmission complete Event Parameters. */ + } params; /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */ +} ble_gattc_evt_t; +/** @} */ + +/** @addtogroup BLE_GATTC_FUNCTIONS Functions + * @{ */ + +/**@brief Initiate or continue a GATT Primary Service Discovery procedure. + * + * @details This function initiates or resumes a Primary Service discovery procedure, starting from the supplied handle. + * If the last service has not been reached, this function must be called again with an updated start handle value to continue the search. + * + * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with + * type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. + * + * @events + * @event{@ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_PRIM_SRVC_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] start_handle Handle to start searching from. + * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid)); + + +/**@brief Initiate or continue a GATT Relationship Discovery procedure. + * + * @details This function initiates or resumes the Find Included Services sub-procedure. If the last included service has not been reached, + * this must be called again with an updated handle range to continue the search. + * + * @events + * @event{@ref BLE_GATTC_EVT_REL_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_REL_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Characteristic Discovery procedure. + * + * @details This function initiates or resumes a Characteristic discovery procedure. If the last Characteristic has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with + * type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_CHAR_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure. + * + * @details This function initiates or resumes a Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @events + * @event{@ref BLE_GATTC_EVT_DESC_DISC_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_DESC_DISC_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure. + * + * @details This function initiates or resumes a Read using Characteristic UUID procedure. If the last Characteristic has not been reached, + * this must be called again with an updated handle range to continue the discovery. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_READ_UUID_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_uuid Pointer to a Characteristic value UUID to read. + * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range)); + + +/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure. + * + * @details This function initiates or resumes a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor + * to be read is longer than ATT_MTU - 1, this function must be called multiple times with appropriate offset to read the + * complete value. + * + * @events + * @event{@ref BLE_GATTC_EVT_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_VALUE_READ_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] handle The handle of the attribute to be read. + * @param[in] offset Offset into the attribute value to be read. + * + * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset)); + + +/**@brief Initiate a GATT Read Multiple Characteristic Values procedure. + * + * @details This function initiates a GATT Read Multiple Characteristic Values procedure. + * + * @events + * @event{@ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_READ_MULT_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read. + * @param[in] handle_count The number of handles in p_handles. + * + * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count)); + + +/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure. + * + * @details This function can perform all write procedures described in GATT. + * + * @note Only one write with response procedure can be ongoing per connection at a time. + * If the application tries to write with response while another write with response procedure is ongoing, + * the function call will return @ref NRF_ERROR_BUSY. + * A @ref BLE_GATTC_EVT_WRITE_RSP event will be issued as soon as the write response arrives from the peer. + * + * @note The number of Write without Response that can be queued is configured by @ref ble_gattc_conn_cfg_t::write_cmd_tx_queue_size + * When the queue is full, the function call will return @ref NRF_ERROR_RESOURCES. + * A @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event will be issued as soon as the transmission of the write without response is complete. + * + * @note The application can keep track of the available queue element count for writes without responses by following the procedure below: + * - Store initial queue element count in a variable. + * - Decrement the variable, which stores the currently available queue element count, by one when a call to this function returns @ref NRF_SUCCESS. + * - Increment the variable, which stores the current available queue element count, by the count variable in @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event. + * + * @events + * @event{@ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE, Write without response transmission complete.} + * @event{@ref BLE_GATTC_EVT_WRITE_RSP, Write response received from the peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_VALUE_WRITE_WITHOUT_RESP_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_WRITE_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_LONG_WRITE_MSC} + * @mmsc{@ref BLE_GATTC_VALUE_RELIABLE_WRITE_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_write_params A pointer to a write parameters structure. + * + * @retval ::NRF_SUCCESS Successfully started the Write procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_BUSY For write with response, procedure already in progress. Wait for a @ref BLE_GATTC_EVT_WRITE_RSP event and retry. + * @retval ::NRF_ERROR_RESOURCES Too many writes without responses queued. + * Wait for a @ref BLE_GATTC_EVT_WRITE_CMD_TX_COMPLETE event and retry. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params)); + + +/**@brief Send a Handle Value Confirmation to the GATT Server. + * + * @mscs + * @mmsc{@ref BLE_GATTC_HVI_MSC} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] handle The handle of the attribute in the indication. + * + * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no Indication pending to be confirmed. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle)); + +/**@brief Discovers information about a range of attributes on a GATT server. + * + * @events + * @event{@ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, Generated when information about a range of attributes has been received.} + * @endevents + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] p_handle_range The range of handles to request information about. + * + * @retval ::NRF_SUCCESS Successfully started an attribute information discovery procedure. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range)); + +/**@brief Start an ATT_MTU exchange by sending an Exchange MTU Request to the server. + * + * @details The SoftDevice sets ATT_MTU to the minimum of: + * - The Client RX MTU value, and + * - The Server RX MTU value from @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. + * + * However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_ATT_MTU_DEFAULT. + * + * @events + * @event{@ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTC_MTU_EXCHANGE} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] client_rx_mtu Client RX MTU size. + * - The minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + * - The maximum value is @ref ble_gatt_conn_cfg_t::att_mtu in the connection configuration + used for this connection. + * - The value must be equal to Server RX MTU size given in @ref sd_ble_gatts_exchange_mtu_reply + * if an ATT_MTU exchange has already been performed in the other direction. + * + * @retval ::NRF_SUCCESS Successfully sent request to the server. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state or an ATT_MTU exchange was already requested once. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid Client RX MTU size supplied. + * @retval ::NRF_ERROR_BUSY Client procedure already in progress. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, uint32_t, sd_ble_gattc_exchange_mtu_request(uint16_t conn_handle, uint16_t client_rx_mtu)); + +/**@brief Iterate through Handle-Value(s) list in @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event. + * + * @param[in] p_gattc_evt Pointer to event buffer containing @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event. + * @note If the buffer contains different event, behavior is undefined. + * @param[in,out] p_iter Iterator, points to @ref ble_gattc_handle_value_t structure that will be filled in with + * the next Handle-Value pair in each iteration. If the function returns other than + * @ref NRF_SUCCESS, it will not be changed. + * - To start iteration, initialize the structure to zero. + * - To continue, pass the value from previous iteration. + * + * \code + * ble_gattc_handle_value_t iter; + * memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); + * while (sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(&ble_evt.evt.gattc_evt, &iter) == NRF_SUCCESS) + * { + * app_handle = iter.handle; + * memcpy(app_value, iter.p_value, ble_evt.evt.gattc_evt.params.char_val_by_uuid_read_rsp.value_len); + * } + * \endcode + * + * @retval ::NRF_SUCCESS Successfully retrieved the next Handle-Value pair. + * @retval ::NRF_ERROR_NOT_FOUND No more Handle-Value pairs available in the list. + */ +__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter); + +/** @} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter) +{ + uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len; + uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value; + uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first; + + if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count) + { + p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0]; + p_iter->p_value = p_next + sizeof(uint16_t); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_NOT_FOUND; + } +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +#ifdef __cplusplus +} +#endif +#endif /* BLE_GATTC_H__ */ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gatts.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gatts.h new file mode 100755 index 0000000..394d8d1 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_gatts.h @@ -0,0 +1,845 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server + @{ + @brief Definitions and prototypes for the GATTS interface. + */ + +#ifndef BLE_GATTS_H__ +#define BLE_GATTS_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_hci.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" +#include "ble_gatt.h" +#include "ble_gap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations + * @{ */ + +/** + * @brief GATTS API SVC numbers. + */ +enum BLE_GATTS_SVCS +{ + SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ + SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ + SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ + SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ + SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ + SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ + SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ + SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ + SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ + SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ + SD_BLE_GATTS_SYS_ATTR_GET, /**< Retrieve the persistent system attributes. */ + SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, /**< Retrieve the first valid user handle. */ + SD_BLE_GATTS_ATTR_GET, /**< Retrieve the UUID and/or metadata of an attribute. */ + SD_BLE_GATTS_EXCHANGE_MTU_REPLY /**< Reply to Exchange MTU Request. */ +}; + +/** + * @brief GATT Server Event IDs. + */ +enum BLE_GATTS_EVTS +{ + BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. \n See @ref ble_gatts_evt_write_t. */ + BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */ + BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending. \n Respond with @ref sd_ble_gatts_sys_attr_set. \n See @ref ble_gatts_evt_sys_attr_missing_t. */ + BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. \n See @ref ble_gatts_evt_hvc_t. */ + BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. \n No additional event structure applies. */ + BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, /**< Exchange MTU Request. \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */ + BLE_GATTS_EVT_TIMEOUT, /**< Peer failed to respond to an ATT request in time. \n See @ref ble_gatts_evt_timeout_t. */ + BLE_GATTS_EVT_HVN_TX_COMPLETE /**< Handle Value Notification transmission complete. \n See @ref ble_gatts_evt_hvn_tx_complete_t. */ +}; + +/**@brief GATTS Configuration IDs. + * + * IDs that uniquely identify a GATTS configuration. + */ +enum BLE_GATTS_CFGS +{ + BLE_GATTS_CFG_SERVICE_CHANGED = BLE_GATTS_CFG_BASE, /**< Service changed configuration. */ + BLE_GATTS_CFG_ATTR_TAB_SIZE, /**< Attribute table size configuration. */ +}; + +/** @} */ + +/** @addtogroup BLE_GATTS_DEFINES Defines + * @{ */ + +/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS + * @{ */ +#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */ +#define BLE_ERROR_GATTS_SYS_ATTR_MISSING (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */ +/** @} */ + +/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths + * @{ */ +#define BLE_GATTS_FIX_ATTR_LEN_MAX (510) /**< Maximum length for fixed length Attribute Values. */ +#define BLE_GATTS_VAR_ATTR_LEN_MAX (512) /**< Maximum length for variable length Attribute Values. */ +/** @} */ + +/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types + * @{ */ +#define BLE_GATTS_SRVC_TYPE_INVALID 0x00 /**< Invalid Service Type. */ +#define BLE_GATTS_SRVC_TYPE_PRIMARY 0x01 /**< Primary Service. */ +#define BLE_GATTS_SRVC_TYPE_SECONDARY 0x02 /**< Secondary Type. */ +/** @} */ + + +/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types + * @{ */ +#define BLE_GATTS_ATTR_TYPE_INVALID 0x00 /**< Invalid Attribute Type. */ +#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL 0x01 /**< Primary Service Declaration. */ +#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL 0x02 /**< Secondary Service Declaration. */ +#define BLE_GATTS_ATTR_TYPE_INC_DECL 0x03 /**< Include Declaration. */ +#define BLE_GATTS_ATTR_TYPE_CHAR_DECL 0x04 /**< Characteristic Declaration. */ +#define BLE_GATTS_ATTR_TYPE_CHAR_VAL 0x05 /**< Characteristic Value. */ +#define BLE_GATTS_ATTR_TYPE_DESC 0x06 /**< Descriptor. */ +#define BLE_GATTS_ATTR_TYPE_OTHER 0x07 /**< Other, non-GATT specific type. */ +/** @} */ + + +/** @defgroup BLE_GATTS_OPS GATT Server Operations + * @{ */ +#define BLE_GATTS_OP_INVALID 0x00 /**< Invalid Operation. */ +#define BLE_GATTS_OP_WRITE_REQ 0x01 /**< Write Request. */ +#define BLE_GATTS_OP_WRITE_CMD 0x02 /**< Write Command. */ +#define BLE_GATTS_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ +#define BLE_GATTS_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ +#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL 0x05 /**< Execute Write Request: Cancel all prepared writes. */ +#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW 0x06 /**< Execute Write Request: Immediately execute all prepared writes. */ +/** @} */ + +/** @defgroup BLE_GATTS_VLOCS GATT Value Locations + * @{ */ +#define BLE_GATTS_VLOC_INVALID 0x00 /**< Invalid Location. */ +#define BLE_GATTS_VLOC_STACK 0x01 /**< Attribute Value is located in stack memory, no user memory is required. */ +#define BLE_GATTS_VLOC_USER 0x02 /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack + will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */ +/** @} */ + +/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types + * @{ */ +#define BLE_GATTS_AUTHORIZE_TYPE_INVALID 0x00 /**< Invalid Type. */ +#define BLE_GATTS_AUTHORIZE_TYPE_READ 0x01 /**< Authorize a Read Operation. */ +#define BLE_GATTS_AUTHORIZE_TYPE_WRITE 0x02 /**< Authorize a Write Request Operation. */ +/** @} */ + +/** @defgroup BLE_GATTS_SYS_ATTR_FLAGS System Attribute Flags + * @{ */ +#define BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS (1 << 0) /**< Restrict system attributes to system services only. */ +#define BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS (1 << 1) /**< Restrict system attributes to user services only. */ +/** @} */ + +/** @defgroup BLE_GATTS_SERVICE_CHANGED Service Changed Inclusion Values + * @{ + */ +#define BLE_GATTS_SERVICE_CHANGED_DEFAULT (1) /**< Default is to include the Service Changed characteristic in the Attribute Table. */ +/** @} */ + +/** @defgroup BLE_GATTS_ATTR_TAB_SIZE Attribute Table size + * @{ + */ +#define BLE_GATTS_ATTR_TAB_SIZE_MIN (248) /**< Minimum Attribute Table size */ +#define BLE_GATTS_ATTR_TAB_SIZE_DEFAULT (1408) /**< Default Attribute Table size. */ +/** @} */ + +/** @defgroup BLE_GATTS_DEFAULTS GATT Server defaults + * @{ + */ +#define BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT 1 /**< Default number of Handle Value Notifications that can be queued for transmission. */ +/** @} */ + +/** @} */ + +/** @addtogroup BLE_GATTS_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE GATTS connection configuration parameters, set with @ref sd_ble_cfg_set. + */ +typedef struct +{ + uint8_t hvn_tx_queue_size; /**< Minimum guaranteed number of Handle Value Notifications that can be queued for transmission. + The default value is @ref BLE_GATTS_HVN_TX_QUEUE_SIZE_DEFAULT */ +} ble_gatts_conn_cfg_t; + +/**@brief Attribute metadata. */ +typedef struct +{ + ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ + ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ + uint8_t vlen :1; /**< Variable length attribute. */ + uint8_t vloc :2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ + uint8_t rd_auth :1; /**< Read authorization and value will be requested from the application on every read operation. */ + uint8_t wr_auth :1; /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */ +} ble_gatts_attr_md_t; + + +/**@brief GATT Attribute. */ +typedef struct +{ + ble_uuid_t const *p_uuid; /**< Pointer to the attribute UUID. */ + ble_gatts_attr_md_t const *p_attr_md; /**< Pointer to the attribute metadata structure. */ + uint16_t init_len; /**< Initial attribute value length in bytes. */ + uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ + uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ + uint8_t *p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer + that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location. + The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/ +} ble_gatts_attr_t; + +/**@brief GATT Attribute Value. */ +typedef struct +{ + uint16_t len; /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/ + uint16_t offset; /**< Attribute value offset. */ + uint8_t *p_value; /**< Pointer to where value is stored or will be stored. + If value is stored in user memory, only the attribute length is updated when p_value == NULL. + Set to NULL when reading to obtain the complete length of the attribute value */ +} ble_gatts_value_t; + + +/**@brief GATT Characteristic Presentation Format. */ +typedef struct +{ + uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ + int8_t exponent; /**< Exponent for integer data types. */ + uint16_t unit; /**< Unit from Bluetooth Assigned Numbers. */ + uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ + uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ +} ble_gatts_char_pf_t; + + +/**@brief GATT Characteristic metadata. */ +typedef struct +{ + ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ + ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ + uint8_t const *p_char_user_desc; /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */ + uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ + uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ + ble_gatts_char_pf_t const *p_char_pf; /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */ + ble_gatts_attr_md_t const *p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ + ble_gatts_attr_md_t const *p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ +} ble_gatts_char_md_t; + + +/**@brief GATT Characteristic Definition Handles. */ +typedef struct +{ + uint16_t value_handle; /**< Handle to the characteristic value. */ + uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ + uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ +} ble_gatts_char_handles_t; + + +/**@brief GATT HVx parameters. */ +typedef struct +{ + uint16_t handle; /**< Characteristic Value Handle. */ + uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ + uint16_t offset; /**< Offset within the attribute value. */ + uint16_t *p_len; /**< Length in bytes to be written, length in bytes written after return. */ + uint8_t const *p_data; /**< Actual data content, use NULL to use the current attribute value. */ +} ble_gatts_hvx_params_t; + +/**@brief GATT Authorization parameters. */ +typedef struct +{ + uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ + uint8_t update : 1; /**< If set, data supplied in p_data will be used to update the attribute value. + Please note that for @ref BLE_GATTS_AUTHORIZE_TYPE_WRITE operations this bit must always be set, + as the data to be written needs to be stored and later provided by the application. */ + uint16_t offset; /**< Offset of the attribute value being updated. */ + uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ + uint8_t const *p_data; /**< Pointer to new value used to update the attribute value. */ +} ble_gatts_authorize_params_t; + +/**@brief GATT Read or Write Authorize Reply parameters. */ +typedef struct +{ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_authorize_params_t read; /**< Read authorization parameters. */ + ble_gatts_authorize_params_t write; /**< Write authorization parameters. */ + } params; /**< Reply Parameters. */ +} ble_gatts_rw_authorize_reply_params_t; + +/**@brief Service Changed Inclusion configuration parameters, set with @ref sd_ble_cfg_set. */ +typedef struct +{ + uint8_t service_changed : 1; /**< If 1, include the Service Changed characteristic in the Attribute Table. Default is @ref BLE_GATTS_SERVICE_CHANGED_DEFAULT. */ +} ble_gatts_cfg_service_changed_t; + +/**@brief Attribute table size configuration parameters, set with @ref sd_ble_cfg_set. + * + * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true: + * - The specified Attribute Table size is too small. + * The minimum acceptable size is defined by @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. + * - The specified Attribute Table size is not a multiple of 4. + */ +typedef struct +{ + uint32_t attr_tab_size; /**< Attribute table size. Default is @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT, minimum is @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. */ +} ble_gatts_cfg_attr_tab_size_t; + +/**@brief Config structure for GATTS configurations. */ +typedef union +{ + ble_gatts_cfg_service_changed_t service_changed; /**< Include service changed characteristic, cfg_id is @ref BLE_GATTS_CFG_SERVICE_CHANGED. */ + ble_gatts_cfg_attr_tab_size_t attr_tab_size; /**< Attribute table size, cfg_id is @ref BLE_GATTS_CFG_ATTR_TAB_SIZE. */ +} ble_gatts_cfg_t; + + +/**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ + uint8_t auth_required; /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalize the writing operation. */ + uint16_t offset; /**< Offset for the write operation. */ + uint16_t len; /**< Length of the received data. */ + uint8_t data[1]; /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. + See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ +} ble_gatts_evt_write_t; + +/**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ + ble_uuid_t uuid; /**< Attribute UUID. */ + uint16_t offset; /**< Offset for the read operation. */ +} ble_gatts_evt_read_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */ +typedef struct +{ + uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ + union { + ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ + ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ + } request; /**< Request Parameters. */ +} ble_gatts_evt_rw_authorize_request_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */ +typedef struct +{ + uint8_t hint; /**< Hint (currently unused). */ +} ble_gatts_evt_sys_attr_missing_t; + + +/**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */ +typedef struct +{ + uint16_t handle; /**< Attribute Handle. */ +} ble_gatts_evt_hvc_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST. */ +typedef struct +{ + uint16_t client_rx_mtu; /**< Client RX MTU size. */ +} ble_gatts_evt_exchange_mtu_request_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */ +typedef struct +{ + uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ +} ble_gatts_evt_timeout_t; + +/**@brief Event structure for @ref BLE_GATTS_EVT_HVN_TX_COMPLETE. */ +typedef struct +{ + uint8_t count; /**< Number of notification transmissions completed. */ +} ble_gatts_evt_hvn_tx_complete_t; + +/**@brief GATTS event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which the event occurred. */ + union + { + ble_gatts_evt_write_t write; /**< Write Event Parameters. */ + ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ + ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ + ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ + ble_gatts_evt_exchange_mtu_request_t exchange_mtu_request; /**< Exchange MTU Request Event Parameters. */ + ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ + ble_gatts_evt_hvn_tx_complete_t hvn_tx_complete; /**< Handle Value Notification transmission complete Event Parameters. */ + } params; /**< Event Parameters. */ +} ble_gatts_evt_t; + +/** @} */ + +/** @addtogroup BLE_GATTS_FUNCTIONS Functions + * @{ */ + +/**@brief Add a service declaration to the Attribute Table. + * + * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to + * add a secondary service declaration that is not referenced by another service later in the Attribute Table. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] type Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES. + * @param[in] p_uuid Pointer to service UUID. + * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a service declaration. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle)); + + +/**@brief Add an include declaration to the Attribute Table. + * + * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential population is supported at this time). + * + * @note The included service must already be present in the Attribute Table prior to this call. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] service_handle Handle of the service where the included service is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] inc_srvc_handle Handle of the included service. + * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added an include declaration. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required. + * @retval ::NRF_ERROR_NOT_SUPPORTED Feature is not supported, service_handle must be that of the last added service. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + */ +SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle)); + + +/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table. + * + * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential population is supported at this time). + * + * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writable auxiliaries bits, + * readable (no security) and writable (selectable) CCCDs and SCCDs and valid presentation format values. + * + * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions. + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] service_handle Handle of the service where the characteristic is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] p_char_md Characteristic metadata. + * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value. + * @param[out] p_handles Pointer to the structure where the assigned handles will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a characteristic. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + */ +SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles)); + + +/**@brief Add a descriptor to the Attribute Table. + * + * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential population is supported at this time). + * + * @mscs + * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} + * @endmscs + * + * @param[in] char_handle Handle of the characteristic where the descriptor is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. + * @param[in] p_attr Pointer to the attribute structure. + * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully added a descriptor. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. + * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + */ +SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle)); + +/**@brief Set the value of a given attribute. + * + * @note Values other than system attributes can be set at any time, regardless of whether any active connections exist. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. Ignored if the value does not belong to a system attribute. + * @param[in] handle Attribute handle. + * @param[in,out] p_value Attribute value information. + * + * @retval ::NRF_SUCCESS Successfully set the value of the attribute. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. + */ +SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); + +/**@brief Get the value of a given attribute. + * + * @note If the attribute value is longer than the size of the supplied buffer, + * @ref ble_gatts_value_t::len will return the total attribute value length (excluding offset), + * and not the number of bytes actually returned in @ref ble_gatts_value_t::p_value. + * The application may use this information to allocate a suitable buffer size. + * + * @note When retrieving system attribute values with this function, the connection handle + * may refer to an already disconnected connection. Refer to the documentation of + * @ref sd_ble_gatts_sys_attr_get for further information. + * + * @param[in] conn_handle Connection handle. Ignored if the value does not belong to a system attribute. + * @param[in] handle Attribute handle. + * @param[in,out] p_value Attribute value information. + * + * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid attribute offset supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + */ +SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); + +/**@brief Notify or Indicate an attribute value. + * + * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation + * (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that + * the application can atomically perform a value update and a server initiated transaction with a single API call. + * + * @note The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution. + * The Attribute Table has been updated if one of the following error codes is returned: @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY, + * @ref NRF_ERROR_FORBIDDEN, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and @ref NRF_ERROR_RESOURCES. + * The caller can check whether the value has been updated by looking at the contents of *(@ref ble_gatts_hvx_params_t::p_len). + * + * @note Only one indication procedure can be ongoing per connection at a time. + * If the application tries to indicate an attribute value while another indication procedure is ongoing, + * the function call will return @ref NRF_ERROR_BUSY. + * A @ref BLE_GATTS_EVT_HVC event will be issued as soon as the confirmation arrives from the peer. + * + * @note The number of Handle Value Notifications that can be queued is configured by @ref ble_gatts_conn_cfg_t::hvn_tx_queue_size + * When the queue is full, the function call will return @ref NRF_ERROR_RESOURCES. + * A @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event will be issued as soon as the transmission of the notification is complete. + * + * @note The application can keep track of the available queue element count for notifications by following the procedure below: + * - Store initial queue element count in a variable. + * - Decrement the variable, which stores the currently available queue element count, by one when a call to this function returns @ref NRF_SUCCESS. + * - Increment the variable, which stores the current available queue element count, by the count variable in @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event. + * + * @events + * @event{@ref BLE_GATTS_EVT_HVN_TX_COMPLETE, Notification transmission complete.} + * @event{@ref BLE_GATTS_EVT_HVC, Confirmation received from the peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC} + * @mmsc{@ref BLE_GATTS_HVN_MSC} + * @mmsc{@ref BLE_GATTS_HVI_MSC} + * @mmsc{@ref BLE_GATTS_HVX_DISABLED_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in,out] p_hvx_params Pointer to an HVx parameters structure. If @ref ble_gatts_hvx_params_t::p_data + * contains a non-NULL pointer the attribute value will be updated with the contents + * pointed by it before sending the notification or indication. If the attribute value + * is updated, @ref ble_gatts_hvx_params_t::p_len is updated by the SoftDevice to + * contain the number of actual bytes written, else it will be set to 0. + * + * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true: + * - Invalid Connection State + * - Notifications and/or indications not enabled in the CCCD + * - An ATT_MTU exchange is ongoing + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate. + * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated. + * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. + * @retval ::NRF_ERROR_FORBIDDEN The connection's current security level is lower than the one required by the write permissions of the CCCD associated with this characteristic. + * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. + * @retval ::NRF_ERROR_BUSY For @ref BLE_GATT_HVX_INDICATION Procedure already in progress. Wait for a @ref BLE_GATTS_EVT_HVC event and retry. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + * @retval ::NRF_ERROR_RESOURCES Too many notifications queued. + * Wait for a @ref BLE_GATTS_EVT_HVN_TX_COMPLETE event and retry. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params)); + +/**@brief Indicate the Service Changed attribute value. + * + * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the Attribute + * Table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will + * be issued. + * + * @note Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here. + * + * @events + * @event{@ref BLE_GATTS_EVT_SC_CONFIRM, Confirmation of attribute table change received from peer.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_GATTS_SC_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] start_handle Start of affected attribute handle range. + * @param[in] end_handle End of affected attribute handle range. + * + * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_NOT_SUPPORTED Service Changed not enabled at initialization. See @ref + * sd_ble_cfg_set and @ref ble_gatts_cfg_service_changed_t. + * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true: + * - Invalid Connection State + * - Notifications and/or indications not enabled in the CCCD + * - An ATT_MTU exchange is ongoing + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application. + * @retval ::NRF_ERROR_BUSY Procedure already in progress. + * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle)); + +/**@brief Respond to a Read/Write authorization request. + * + * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application. + * + * @mscs + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} + * @mmsc{@ref BLE_GATTS_READ_REQ_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_WRITE_REQ_AUTH_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} + * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_PEER_CANCEL_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application. + * + * @note @ref ble_gatts_authorize_params_t::p_data is ignored when this function is used to respond + * to a @ref BLE_GATTS_AUTHORIZE_TYPE_READ event if @ref ble_gatts_authorize_params_t::update + * is set to 0. + * + * @retval ::NRF_SUCCESS Successfully queued a response to the peer, and in the case of a write operation, Attribute Table updated. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no authorization request pending. + * @retval ::NRF_ERROR_INVALID_PARAM Authorization op invalid, + * handle supplied does not match requested handle, + * or invalid data to be written provided by the application. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params)); + + +/**@brief Update persistent system attribute information. + * + * @details Supply information about persistent system attributes to the stack, + * previously obtained using @ref sd_ble_gatts_sys_attr_get. + * This call is only allowed for active connections, and is usually + * made immediately after a connection is established with an known bonded device, + * often as a response to a @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. + * + * p_sysattrs may point directly to the application's stored copy of the system attributes + * obtained using @ref sd_ble_gatts_sys_attr_get. + * If the pointer is NULL, the system attribute info is initialized, assuming that + * the application does not have any previously saved system attribute data for this device. + * + * @note The state of persistent system attributes is reset upon connection establishment and then remembered for its duration. + * + * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially. + * This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or + * reset the SoftDevice to return to a known state. + * + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be modified. + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be modified. + * + * @mscs + * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC} + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC} + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle. + * @param[in] p_sys_attr_data Pointer to a saved copy of system attributes supplied to the stack, or NULL. + * @param[in] len Size of data pointed by p_sys_attr_data, in octets. + * @param[in] flags Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS + * + * @retval ::NRF_SUCCESS Successfully set the system attribute information. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied. + * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get. + * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. + */ +SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags)); + + +/**@brief Retrieve persistent system attribute information from the stack. + * + * @details This call is used to retrieve information about values to be stored persistently by the application + * during the lifetime of a connection or after it has been terminated. When a new connection is established with the same bonded device, + * the system attribute information retrieved with this function should be restored using using @ref sd_ble_gatts_sys_attr_set. + * If retrieved after disconnection, the data should be read before a new connection established. The connection handle for + * the previous, now disconnected, connection will remain valid until a new one is created to allow this API call to refer to it. + * Connection handles belonging to active connections can be used as well, but care should be taken since the system attributes + * may be written to at any time by the peer during a connection's lifetime. + * + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be returned. + * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be returned. + * + * @mscs + * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC} + * @endmscs + * + * @param[in] conn_handle Connection handle of the recently terminated connection. + * @param[out] p_sys_attr_data Pointer to a buffer where updated information about system attributes will be filled in. The format of the data is described + * in @ref BLE_GATTS_SYS_ATTRS_FORMAT. NULL can be provided to obtain the length of the data. + * @param[in,out] p_len Size of application buffer if p_sys_attr_data is not NULL. Unconditionally updated to actual length of system attribute data. + * @param[in] flags Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS + * + * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied. + * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer. + * @retval ::NRF_ERROR_NOT_FOUND No system attributes found. + */ +SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags)); + + +/**@brief Retrieve the first valid user attribute handle. + * + * @param[out] p_handle Pointer to an integer where the handle will be stored. + * + * @retval ::NRF_SUCCESS Successfully retrieved the handle. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + */ +SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle)); + +/**@brief Retrieve the attribute UUID and/or metadata. + * + * @param[in] handle Attribute handle + * @param[out] p_uuid UUID of the attribute. Use NULL to omit this field. + * @param[out] p_md Metadata of the attribute. Use NULL to omit this field. + * + * @retval ::NRF_SUCCESS Successfully retrieved the attribute metadata, + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. Returned when both @c p_uuid and @c p_md are NULL. + * @retval ::NRF_ERROR_NOT_FOUND Attribute was not found. + */ +SVCALL(SD_BLE_GATTS_ATTR_GET, uint32_t, sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md)); + +/**@brief Reply to an ATT_MTU exchange request by sending an Exchange MTU Response to the client. + * + * @details This function is only used to reply to a @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST event. + * + * @details The SoftDevice sets ATT_MTU to the minimum of: + * - The Client RX MTU value from @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, and + * - The Server RX MTU value. + * + * However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_ATT_MTU_DEFAULT. + * + * @mscs + * @mmsc{@ref BLE_GATTS_MTU_EXCHANGE} + * @endmscs + * + * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. + * @param[in] server_rx_mtu Server RX MTU size. + * - The minimum value is @ref BLE_GATT_ATT_MTU_DEFAULT. + * - The maximum value is @ref ble_gatt_conn_cfg_t::att_mtu in the connection configuration + * used for this connection. + * - The value must be equal to Client RX MTU size given in @ref sd_ble_gattc_exchange_mtu_request + * if an ATT_MTU exchange has already been performed in the other direction. + * + * @retval ::NRF_SUCCESS Successfully sent response to the client. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no ATT_MTU exchange request pending. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid Server RX MTU size supplied. + * @retval ::NRF_ERROR_TIMEOUT There has been a GATT procedure timeout. No new GATT procedure can be performed without reestablishing the connection. + */ +SVCALL(SD_BLE_GATTS_EXCHANGE_MTU_REPLY, uint32_t, sd_ble_gatts_exchange_mtu_reply(uint16_t conn_handle, uint16_t server_rx_mtu)); +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_GATTS_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_hci.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_hci.h new file mode 100755 index 0000000..f0dde9a --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_hci.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ +*/ + + +#ifndef BLE_HCI_H__ +#define BLE_HCI_H__ +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes + * @{ */ + +#define BLE_HCI_STATUS_CODE_SUCCESS 0x00 /**< Success. */ +#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND 0x01 /**< Unknown BLE Command. */ +#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER 0x02 /**< Unknown Connection Identifier. */ +/*0x03 Hardware Failure +0x04 Page Timeout +*/ +#define BLE_HCI_AUTHENTICATION_FAILURE 0x05 /**< Authentication Failure. */ +#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING 0x06 /**< Pin or Key missing. */ +#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED 0x07 /**< Memory Capacity Exceeded. */ +#define BLE_HCI_CONNECTION_TIMEOUT 0x08 /**< Connection Timeout. */ +/*0x09 Connection Limit Exceeded +0x0A Synchronous Connection Limit To A Device Exceeded +0x0B ACL Connection Already Exists*/ +#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED 0x0C /**< Command Disallowed. */ +/*0x0D Connection Rejected due to Limited Resources +0x0E Connection Rejected Due To Security Reasons +0x0F Connection Rejected due to Unacceptable BD_ADDR +0x10 Connection Accept Timeout Exceeded +0x11 Unsupported Feature or Parameter Value*/ +#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12 /**< Invalid BLE Command Parameters. */ +#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION 0x13 /**< Remote User Terminated Connection. */ +#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14 /**< Remote Device Terminated Connection due to low resources.*/ +#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF 0x15 /**< Remote Device Terminated Connection due to power off. */ +#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION 0x16 /**< Local Host Terminated Connection. */ +/* +0x17 Repeated Attempts +0x18 Pairing Not Allowed +0x19 Unknown LMP PDU +*/ +#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A /**< Unsupported Remote Feature. */ +/* +0x1B SCO Offset Rejected +0x1C SCO Interval Rejected +0x1D SCO Air Mode Rejected*/ +#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS 0x1E /**< Invalid LMP Parameters. */ +#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR 0x1F /**< Unspecified Error. */ +/*0x20 Unsupported LMP Parameter Value +0x21 Role Change Not Allowed +*/ +#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT 0x22 /**< LMP Response Timeout. */ +#define BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION 0x23 /**< LMP Error Transaction Collision/LL Procedure Collision. */ +#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED 0x24 /**< LMP PDU Not Allowed. */ +/*0x25 Encryption Mode Not Acceptable +0x26 Link Key Can Not be Changed +0x27 Requested QoS Not Supported +*/ +#define BLE_HCI_INSTANT_PASSED 0x28 /**< Instant Passed. */ +#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED 0x29 /**< Pairing with Unit Key Unsupported. */ +#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION 0x2A /**< Different Transaction Collision. */ +/* +0x2B Reserved +0x2C QoS Unacceptable Parameter +0x2D QoS Rejected +0x2E Channel Classification Not Supported +0x2F Insufficient Security +*/ +#define BLE_HCI_PARAMETER_OUT_OF_MANDATORY_RANGE 0x30 /**< Parameter Out Of Mandatory Range. */ +/* +0x31 Reserved +0x32 Role Switch Pending +0x33 Reserved +0x34 Reserved Slot Violation +0x35 Role Switch Failed +0x36 Extended Inquiry Response Too Large +0x37 Secure Simple Pairing Not Supported By Host. +0x38 Host Busy - Pairing +0x39 Connection Rejected due to No Suitable Channel Found*/ +#define BLE_HCI_CONTROLLER_BUSY 0x3A /**< Controller Busy. */ +#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE 0x3B /**< Connection Interval Unacceptable. */ +#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT 0x3C /**< Directed Advertisement Timeout. */ +#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE 0x3D /**< Connection Terminated due to MIC Failure. */ +#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED 0x3E /**< Connection Failed to be Established. */ + +/** @} */ + + +#ifdef __cplusplus +} +#endif +#endif // BLE_HCI_H__ + +/** @} */ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_l2cap.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_l2cap.h new file mode 100755 index 0000000..edaf664 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_l2cap.h @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2011 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP) + @{ + @brief Definitions and prototypes for the L2CAP interface. + */ + +#ifndef BLE_L2CAP_H__ +#define BLE_L2CAP_H__ + +#include <stdint.h> +#include "nrf_svc.h" +#include "nrf_error.h" +#include "ble_ranges.h" +#include "ble_types.h" +#include "ble_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup BLE_L2CAP_TERMINOLOGY Terminology + * @{ + * @details + * + * L2CAP SDU + * - A data unit that the application can send/receive to/from a peer. + * + * L2CAP PDU + * - A data unit that is exchanged between local and remote L2CAP entities. + * It consists of L2CAP protocol control information and payload fields. + * The payload field can contain an L2CAP SDU or a part of an L2CAP SDU. + * + * L2CAP MTU + * - The maximum length of an L2CAP SDU. + * + * L2CAP MPS + * - The maximum length of an L2CAP PDU payload field. + * + * Credits + * - A value indicating the number of L2CAP PDUs that the receiver of the credit can send to the peer. + * @} */ + +/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations + * @{ */ + +/**@brief L2CAP API SVC numbers. */ +enum BLE_L2CAP_SVCS +{ + SD_BLE_L2CAP_CH_SETUP = BLE_L2CAP_SVC_BASE + 0, /**< Set up an L2CAP channel. */ + SD_BLE_L2CAP_CH_RELEASE = BLE_L2CAP_SVC_BASE + 1, /**< Release an L2CAP channel. */ + SD_BLE_L2CAP_CH_RX = BLE_L2CAP_SVC_BASE + 2, /**< Receive an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_TX = BLE_L2CAP_SVC_BASE + 3, /**< Transmit an SDU on an L2CAP channel. */ + SD_BLE_L2CAP_CH_FLOW_CONTROL = BLE_L2CAP_SVC_BASE + 4, /**< Advanced SDU reception flow control. */ +}; + +/**@brief L2CAP Event IDs. */ +enum BLE_L2CAP_EVTS +{ + BLE_L2CAP_EVT_CH_SETUP_REQUEST = BLE_L2CAP_EVT_BASE + 0, /**< L2CAP Channel Setup Request event. + \n See @ref ble_l2cap_evt_ch_setup_request_t. */ + BLE_L2CAP_EVT_CH_SETUP_REFUSED = BLE_L2CAP_EVT_BASE + 1, /**< L2CAP Channel Setup Refused event. + \n See @ref ble_l2cap_evt_ch_setup_refused_t. */ + BLE_L2CAP_EVT_CH_SETUP = BLE_L2CAP_EVT_BASE + 2, /**< L2CAP Channel Setup Completed event. + \n See @ref ble_l2cap_evt_ch_setup_t. */ + BLE_L2CAP_EVT_CH_RELEASED = BLE_L2CAP_EVT_BASE + 3, /**< L2CAP Channel Released event. + \n No additional event structure applies. */ + BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED = BLE_L2CAP_EVT_BASE + 4, /**< L2CAP Channel SDU data buffer released event. + \n See @ref ble_l2cap_evt_ch_sdu_buf_released_t. */ + BLE_L2CAP_EVT_CH_CREDIT = BLE_L2CAP_EVT_BASE + 5, /**< L2CAP Channel Credit received. + \n See @ref ble_l2cap_evt_ch_credit_t. */ + BLE_L2CAP_EVT_CH_RX = BLE_L2CAP_EVT_BASE + 6, /**< L2CAP Channel SDU received. + \n See @ref ble_l2cap_evt_ch_rx_t. */ + BLE_L2CAP_EVT_CH_TX = BLE_L2CAP_EVT_BASE + 7, /**< L2CAP Channel SDU transmitted. + \n See @ref ble_l2cap_evt_ch_tx_t. */ +}; + +/** @} */ + +/**@addtogroup BLE_L2CAP_DEFINES Defines + * @{ */ + +/**@brief Maximum number of L2CAP channels per connection. */ +#define BLE_L2CAP_CH_COUNT_MAX (64) + +/**@brief Minimum L2CAP MTU, in bytes. */ +#define BLE_L2CAP_MTU_MIN (23) + +/**@brief Minimum L2CAP MPS, in bytes. */ +#define BLE_L2CAP_MPS_MIN (23) + +/**@brief Invalid CID. */ +#define BLE_L2CAP_CID_INVALID (0x0000) + +/**@brief Default number of credits for @ref sd_ble_l2cap_ch_flow_control. */ +#define BLE_L2CAP_CREDITS_DEFAULT (1) + +/**@defgroup BLE_L2CAP_CH_SETUP_REFUSED_SRCS L2CAP channel setup refused sources + * @{ */ +#define BLE_L2CAP_CH_SETUP_REFUSED_SRC_LOCAL (0x01) /**< Local. */ +#define BLE_L2CAP_CH_SETUP_REFUSED_SRC_REMOTE (0x02) /**< Remote. */ + /** @} */ + + /** @defgroup BLE_L2CAP_CH_STATUS_CODES L2CAP channel status codes + * @{ */ +#define BLE_L2CAP_CH_STATUS_CODE_SUCCESS (0x0000) /**< Success. */ +#define BLE_L2CAP_CH_STATUS_CODE_LE_PSM_NOT_SUPPORTED (0x0002) /**< LE_PSM not supported. */ +#define BLE_L2CAP_CH_STATUS_CODE_NO_RESOURCES (0x0004) /**< No resources available. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_AUTHENTICATION (0x0005) /**< Insufficient authentication. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_AUTHORIZATION (0x0006) /**< Insufficient authorization. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_ENC_KEY_SIZE (0x0007) /**< Insufficient encryption key size. */ +#define BLE_L2CAP_CH_STATUS_CODE_INSUFF_ENC (0x0008) /**< Insufficient encryption. */ +#define BLE_L2CAP_CH_STATUS_CODE_INVALID_SCID (0x0009) /**< Invalid Source CID. */ +#define BLE_L2CAP_CH_STATUS_CODE_SCID_ALLOCATED (0x000A) /**< Source CID already allocated. */ +#define BLE_L2CAP_CH_STATUS_CODE_UNACCEPTABLE_PARAMS (0x000B) /**< Unacceptable parameters. */ +#define BLE_L2CAP_CH_STATUS_CODE_NOT_UNDERSTOOD (0x8000) /**< Command Reject received instead of LE Credit Based Connection Response. */ +#define BLE_L2CAP_CH_STATUS_CODE_TIMEOUT (0xC000) /**< Operation timed out. */ +/** @} */ + +/** @} */ + +/**@addtogroup BLE_L2CAP_STRUCTURES Structures + * @{ */ + +/** + * @brief BLE L2CAP connection configuration parameters, set with @ref sd_ble_cfg_set. + * + * @note These parameters are set per connection, so all L2CAP channels created on this connection + * will have the same parameters. + * + * @retval ::NRF_ERROR_INVALID_PARAM One or more of the following is true: + * - rx_mps is smaller than @ref BLE_L2CAP_MPS_MIN. + * - tx_mps is smaller than @ref BLE_L2CAP_MPS_MIN. + * - ch_count is greater than @ref BLE_L2CAP_CH_COUNT_MAX. + * @retval ::NRF_ERROR_NO_MEM rx_mps or tx_mps is set too high. + */ +typedef struct +{ + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + be able to receive on L2CAP channels on connections with this + configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall + be able to transmit on L2CAP channels on connections with this + configuration. The minimum value is @ref BLE_L2CAP_MPS_MIN. */ + uint8_t rx_queue_size; /**< Number of SDU data buffers that can be queued for reception per + L2CAP channel. The minimum value is one. */ + uint8_t tx_queue_size; /**< Number of SDU data buffers that can be queued for transmission + per L2CAP channel. The minimum value is one. */ + uint8_t ch_count; /**< Number of L2CAP channels the application can create per connection + with this configuration. The default value is zero, the maximum + value is @ref BLE_L2CAP_CH_COUNT_MAX. + @note if this parameter is set to zero, all other parameters in + @ref ble_l2cap_conn_cfg_t are ignored. */ +} ble_l2cap_conn_cfg_t; + +/**@brief L2CAP channel RX parameters. */ +typedef struct +{ + uint16_t rx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP shall be able to + receive on this L2CAP channel. + - Must be equal to or greater than @ref BLE_L2CAP_MTU_MIN. */ + uint16_t rx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP shall be + able to receive on this L2CAP channel. + - Must be equal to or greater than @ref BLE_L2CAP_MPS_MIN. + - Must be equal to or less than @ref ble_l2cap_conn_cfg_t::rx_mps. */ + ble_data_t sdu_buf; /**< SDU data buffer for reception. + - If @ref ble_data_t::p_data is non-NULL, initial credits are + issued to the peer. + - If @ref ble_data_t::p_data is NULL, no initial credits are + issued to the peer. */ +} ble_l2cap_ch_rx_params_t; + +/**@brief L2CAP channel setup parameters. */ +typedef struct +{ + ble_l2cap_ch_rx_params_t rx_params; /**< L2CAP channel RX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. Used when requesting + setup of an L2CAP channel, ignored otherwise. */ + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES. + Used when replying to a setup request of an L2CAP + channel, ignored otherwise. */ +} ble_l2cap_ch_setup_params_t; + +/**@brief L2CAP channel TX parameters. */ +typedef struct +{ + uint16_t tx_mtu; /**< The maximum L2CAP SDU size, in bytes, that L2CAP is able to + transmit on this L2CAP channel. */ + uint16_t peer_mps; /**< The maximum L2CAP PDU payload size, in bytes, that the peer is + able to receive on this L2CAP channel. */ + uint16_t tx_mps; /**< The maximum L2CAP PDU payload size, in bytes, that L2CAP is able + to transmit on this L2CAP channel. This is effective tx_mps, + selected by the SoftDevice as + MIN( @ref ble_l2cap_ch_tx_params_t::peer_mps, @ref ble_l2cap_conn_cfg_t::tx_mps ) */ + uint16_t credits; /**< Initial credits given by the peer. */ +} ble_l2cap_ch_tx_params_t; + +/**@brief L2CAP Channel Setup Request event. */ +typedef struct +{ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ + uint16_t le_psm; /**< LE Protocol/Service Multiplexer. */ +} ble_l2cap_evt_ch_setup_request_t; + +/**@brief L2CAP Channel Setup Refused event. */ +typedef struct +{ + uint8_t source; /**< Source, see @ref BLE_L2CAP_CH_SETUP_REFUSED_SRCS */ + uint16_t status; /**< Status code, see @ref BLE_L2CAP_CH_STATUS_CODES */ +} ble_l2cap_evt_ch_setup_refused_t; + +/**@brief L2CAP Channel Setup Completed event. */ +typedef struct +{ + ble_l2cap_ch_tx_params_t tx_params; /**< L2CAP channel TX parameters. */ +} ble_l2cap_evt_ch_setup_t; + +/**@brief L2CAP Channel SDU Data Buffer Released event. */ +typedef struct +{ + ble_data_t sdu_buf; /**< Returned reception or transmission SDU data buffer. The SoftDevice + returns SDU data buffers supplied by the application, which have + not yet been returned previously via a @ref BLE_L2CAP_EVT_CH_RX or + @ref BLE_L2CAP_EVT_CH_TX event. */ +} ble_l2cap_evt_ch_sdu_buf_released_t; + +/**@brief L2CAP Channel Credit received event. */ +typedef struct +{ + uint16_t credits; /**< Additional credits given by the peer. */ +} ble_l2cap_evt_ch_credit_t; + +/**@brief L2CAP Channel received SDU event. */ +typedef struct +{ + uint16_t sdu_len; /**< Total SDU length, in bytes. */ + ble_data_t sdu_buf; /**< SDU data buffer. + @note If there is not enough space in the buffer + (sdu_buf.len < sdu_len) then the rest of the SDU will be + silently discarded by the SoftDevice. */ +} ble_l2cap_evt_ch_rx_t; + +/**@brief L2CAP Channel transmitted SDU event. */ +typedef struct +{ + ble_data_t sdu_buf; /**< SDU data buffer. */ +} ble_l2cap_evt_ch_tx_t; + +/**@brief L2CAP event structure. */ +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which the event occured. */ + uint16_t local_cid; /**< Local Channel ID of the L2CAP channel, or + @ref BLE_L2CAP_CID_INVALID if not present. */ + union + { + ble_l2cap_evt_ch_setup_request_t ch_setup_request; /**< L2CAP Channel Setup Request Event Parameters. */ + ble_l2cap_evt_ch_setup_refused_t ch_setup_refused; /**< L2CAP Channel Setup Refused Event Parameters. */ + ble_l2cap_evt_ch_setup_t ch_setup; /**< L2CAP Channel Setup Completed Event Parameters. */ + ble_l2cap_evt_ch_sdu_buf_released_t ch_sdu_buf_released;/**< L2CAP Channel SDU Data Buffer Released Event Parameters. */ + ble_l2cap_evt_ch_credit_t credit; /**< L2CAP Channel Credit Received Event Parameters. */ + ble_l2cap_evt_ch_rx_t rx; /**< L2CAP Channel SDU Received Event Parameters. */ + ble_l2cap_evt_ch_tx_t tx; /**< L2CAP Channel SDU Transmitted Event Parameters. */ + } params; /**< Event Parameters. */ +} ble_l2cap_evt_t; + +/** @} */ + +/**@addtogroup BLE_L2CAP_FUNCTIONS Functions + * @{ */ + +/**@brief Set up an L2CAP channel. + * + * @details This function is used to: + * - Request setup of an L2CAP channel: sends an LE Credit Based Connection Request packet to a peer. + * - Reply to a setup request of an L2CAP channel (if called in response to a + * @ref BLE_L2CAP_EVT_CH_SETUP_REQUEST event): sends an LE Credit Based Connection + * Response packet to a peer. + * + * @note A call to this function will require the application to keep the SDU data buffer alive + * until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_RX or + * @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_SETUP, Setup successful.} + * @event{@ref BLE_L2CAP_EVT_CH_SETUP_REFUSED, Setup failed.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_SETUP_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in,out] p_local_cid Pointer to a uint16_t containing Local Channel ID of the L2CAP channel: + * - As input: @ref BLE_L2CAP_CID_INVALID when requesting setup of an L2CAP + * channel or local_cid provided in the @ref BLE_L2CAP_EVT_CH_SETUP_REQUEST + * event when replying to a setup request of an L2CAP channel. + * - As output: local_cid for this channel. + * @param[in] p_params L2CAP channel parameters. + * + * @retval ::NRF_SUCCESS Successfully queued request or response for transmission. + * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. + * @retval ::NRF_ERROR_INVALID_LENGTH Supplied higher rx_mps than has been configured on this link. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (L2CAP channel already set up). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_RESOURCES The limit has been reached for available L2CAP channels, + * see @ref ble_l2cap_conn_cfg_t::ch_count. + */ +SVCALL(SD_BLE_L2CAP_CH_SETUP, uint32_t, sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t *p_local_cid, ble_l2cap_ch_setup_params_t const *p_params)); + +/**@brief Release an L2CAP channel. + * + * @details This sends a Disconnection Request packet to a peer. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_RELEASED, Release complete.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_RELEASE_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * + * @retval ::NRF_SUCCESS Successfully queued request for transmission. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for the L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + */ +SVCALL(SD_BLE_L2CAP_CH_RELEASE, uint32_t, sd_ble_l2cap_ch_release(uint16_t conn_handle, uint16_t local_cid)); + +/**@brief Receive an SDU on an L2CAP channel. + * + * @details This may issue additional credits to the peer using an LE Flow Control Credit packet. + * + * @note A call to this function will require the application to keep the memory pointed by + * @ref ble_data_t::p_data alive until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_RX + * or @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @note The SoftDevice can queue up to @ref ble_l2cap_conn_cfg_t::rx_queue_size SDU data buffers + * for reception per L2CAP channel. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_RX, The SDU is received.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_RX_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * @param[in] p_sdu_buf Pointer to the SDU data buffer. + * + * @retval ::NRF_SUCCESS Buffer accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for an L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_RESOURCES Too many SDU data buffers supplied. Wait for a + * @ref BLE_L2CAP_EVT_CH_RX event and retry. + */ +SVCALL(SD_BLE_L2CAP_CH_RX, uint32_t, sd_ble_l2cap_ch_rx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf)); + +/**@brief Transmit an SDU on an L2CAP channel. + * + * @note A call to this function will require the application to keep the memory pointed by + * @ref ble_data_t::p_data alive until the SDU data buffer is returned in @ref BLE_L2CAP_EVT_CH_TX + * or @ref BLE_L2CAP_EVT_CH_SDU_BUF_RELEASED event. + * + * @note The SoftDevice can queue up to @ref ble_l2cap_conn_cfg_t::tx_queue_size SDUs for + * transmission per L2CAP channel. + * + * @note The application can keep track of the available credits for transmission by following + * the procedure below: + * - Store initial credits given by the peer in a variable. + * (Initial credits are provided in a @ref BLE_L2CAP_EVT_CH_SETUP event.) + * - Decrement the variable, which stores the currently available credits, by + * ceiling((@ref ble_data_t::len + 2) / tx_mps) when a call to this function returns + * @ref NRF_SUCCESS. (tx_mps is provided in a @ref BLE_L2CAP_EVT_CH_SETUP event.) + * - Increment the variable, which stores the currently available credits, by additional + * credits given by the peer in a @ref BLE_L2CAP_EVT_CH_CREDIT event. + * + * @events + * @event{@ref BLE_L2CAP_EVT_CH_TX, The SDU is transmitted.} + * @endevents + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_TX_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel. + * @param[in] p_sdu_buf Pointer to the SDU data buffer. + * + * @retval ::NRF_SUCCESS Successfully queued L2CAP SDU for transmission. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for the L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + * @retval ::NRF_ERROR_DATA_SIZE Invalid SDU length supplied, must not be more than + * @ref ble_l2cap_ch_tx_params_t::tx_mtu provided in + * @ref BLE_L2CAP_EVT_CH_SETUP event. + * @retval ::NRF_ERROR_RESOURCES Too many SDUs queued for transmission. Wait for a + * @ref BLE_L2CAP_EVT_CH_TX event and retry. + */ +SVCALL(SD_BLE_L2CAP_CH_TX, uint32_t, sd_ble_l2cap_ch_tx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf)); + +/**@brief Advanced SDU reception flow control. + * + * @details Adjust the way the SoftDevice issues credits to the peer. + * This may issue additional credits to the peer using an LE Flow Control Credit packet. + * + * @mscs + * @mmsc{@ref BLE_L2CAP_CH_FLOW_CONTROL_MSC} + * @endmscs + * + * @param[in] conn_handle Connection Handle. + * @param[in] local_cid Local Channel ID of the L2CAP channel or @ref BLE_L2CAP_CID_INVALID to set + * the value that will be used for newly created channels. + * @param[in] credits Number of credits that the SoftDevice will make sure the peer has every + * time it starts using a new reception buffer. + * - @ref BLE_L2CAP_CREDITS_DEFAULT is the default value the SoftDevice will + * use if this function is not called. + * - If set to zero, the SoftDevice will stop issuing credits for new reception + * buffers the application provides or has provided. SDU reception that is + * currently ongoing will be allowed to complete. + * @param[out] p_credits NULL or pointer to a uint16_t. If a valid pointer is provided, it will be + * written by the SoftDevice with the number of credits that is or will be + * available to the peer. If the value written by the SoftDevice is 0 when + * credits parameter was set to 0, the peer will not be able to send more + * data until more credits are provided by calling this function again with + * credits > 0. This parameter is ignored when local_cid is set to + * @ref BLE_L2CAP_CID_INVALID. + * + * @note Application should take care when setting number of credits higher than default value. In + * this case the application must make sure that the SoftDevice always has reception buffers + * available (see @ref sd_ble_l2cap_ch_rx) for that channel. If the SoftDevice does not have + * such buffers available, packets may be NACKed on the Link Layer and all Bluetooth traffic + * on the connection handle may be stalled until the SoftDevice again has an available + * reception buffer. This applies even if the application has used this call to set the + * credits back to default, or zero. + * + * @retval ::NRF_SUCCESS Flow control parameters accepted. + * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. + * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. + * @retval ::NRF_ERROR_INVALID_STATE Invalid State to perform operation (Setup or release is + * in progress for an L2CAP channel). + * @retval ::NRF_ERROR_NOT_FOUND CID not found. + */ +SVCALL(SD_BLE_L2CAP_CH_FLOW_CONTROL, uint32_t, sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t *p_credits)); + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // BLE_L2CAP_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_ranges.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_ranges.h new file mode 100755 index 0000000..0935bca --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_ranges.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @defgroup ble_ranges Module specific SVC, event and option number subranges + @{ + + @brief Definition of SVC, event and option number subranges for each API module. + + @note + SVCs, event and option numbers are split into subranges for each API module. + Each module receives its entire allocated range of SVC calls, whether implemented or not, + but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range. + + Note that the symbols BLE_<module>_SVC_LAST is the end of the allocated SVC range, + rather than the last SVC function call actually defined and implemented. + + Specific SVC, event and option values are defined in each module's ble_<module>.h file, + which defines names of each individual SVC code based on the range start value. +*/ + +#ifndef BLE_RANGES_H__ +#define BLE_RANGES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define BLE_SVC_BASE 0x60 /**< Common BLE SVC base. */ +#define BLE_SVC_LAST 0x6B /**< Common BLE SVC last. */ + +#define BLE_GAP_SVC_BASE 0x6C /**< GAP BLE SVC base. */ +#define BLE_GAP_SVC_LAST 0x9A /**< GAP BLE SVC last. */ + +#define BLE_GATTC_SVC_BASE 0x9B /**< GATTC BLE SVC base. */ +#define BLE_GATTC_SVC_LAST 0xA7 /**< GATTC BLE SVC last. */ + +#define BLE_GATTS_SVC_BASE 0xA8 /**< GATTS BLE SVC base. */ +#define BLE_GATTS_SVC_LAST 0xB7 /**< GATTS BLE SVC last. */ + +#define BLE_L2CAP_SVC_BASE 0xB8 /**< L2CAP BLE SVC base. */ +#define BLE_L2CAP_SVC_LAST 0xBF /**< L2CAP BLE SVC last. */ + + +#define BLE_EVT_INVALID 0x00 /**< Invalid BLE Event. */ + +#define BLE_EVT_BASE 0x01 /**< Common BLE Event base. */ +#define BLE_EVT_LAST 0x0F /**< Common BLE Event last. */ + +#define BLE_GAP_EVT_BASE 0x10 /**< GAP BLE Event base. */ +#define BLE_GAP_EVT_LAST 0x2F /**< GAP BLE Event last. */ + +#define BLE_GATTC_EVT_BASE 0x30 /**< GATTC BLE Event base. */ +#define BLE_GATTC_EVT_LAST 0x4F /**< GATTC BLE Event last. */ + +#define BLE_GATTS_EVT_BASE 0x50 /**< GATTS BLE Event base. */ +#define BLE_GATTS_EVT_LAST 0x6F /**< GATTS BLE Event last. */ + +#define BLE_L2CAP_EVT_BASE 0x70 /**< L2CAP BLE Event base. */ +#define BLE_L2CAP_EVT_LAST 0x8F /**< L2CAP BLE Event last. */ + + +#define BLE_OPT_INVALID 0x00 /**< Invalid BLE Option. */ + +#define BLE_OPT_BASE 0x01 /**< Common BLE Option base. */ +#define BLE_OPT_LAST 0x1F /**< Common BLE Option last. */ + +#define BLE_GAP_OPT_BASE 0x20 /**< GAP BLE Option base. */ +#define BLE_GAP_OPT_LAST 0x3F /**< GAP BLE Option last. */ + +#define BLE_GATT_OPT_BASE 0x40 /**< GATT BLE Option base. */ +#define BLE_GATT_OPT_LAST 0x5F /**< GATT BLE Option last. */ + +#define BLE_GATTC_OPT_BASE 0x60 /**< GATTC BLE Option base. */ +#define BLE_GATTC_OPT_LAST 0x7F /**< GATTC BLE Option last. */ + +#define BLE_GATTS_OPT_BASE 0x80 /**< GATTS BLE Option base. */ +#define BLE_GATTS_OPT_LAST 0x9F /**< GATTS BLE Option last. */ + +#define BLE_L2CAP_OPT_BASE 0xA0 /**< L2CAP BLE Option base. */ +#define BLE_L2CAP_OPT_LAST 0xBF /**< L2CAP BLE Option last. */ + + +#define BLE_CFG_INVALID 0x00 /**< Invalid BLE configuration. */ + +#define BLE_CFG_BASE 0x01 /**< Common BLE configuration base. */ +#define BLE_CFG_LAST 0x1F /**< Common BLE configuration last. */ + +#define BLE_CONN_CFG_BASE 0x20 /**< BLE connection configuration base. */ +#define BLE_CONN_CFG_LAST 0x3F /**< BLE connection configuration last. */ + +#define BLE_GAP_CFG_BASE 0x40 /**< GAP BLE configuration base. */ +#define BLE_GAP_CFG_LAST 0x5F /**< GAP BLE configuration last. */ + +#define BLE_GATT_CFG_BASE 0x60 /**< GATT BLE configuration base. */ +#define BLE_GATT_CFG_LAST 0x7F /**< GATT BLE configuration last. */ + +#define BLE_GATTC_CFG_BASE 0x80 /**< GATTC BLE configuration base. */ +#define BLE_GATTC_CFG_LAST 0x9F /**< GATTC BLE configuration last. */ + +#define BLE_GATTS_CFG_BASE 0xA0 /**< GATTS BLE configuration base. */ +#define BLE_GATTS_CFG_LAST 0xBF /**< GATTS BLE configuration last. */ + +#define BLE_L2CAP_CFG_BASE 0xC0 /**< L2CAP BLE configuration base. */ +#define BLE_L2CAP_CFG_LAST 0xDF /**< L2CAP BLE configuration last. */ + + + + + +#ifdef __cplusplus +} +#endif +#endif /* BLE_RANGES_H__ */ + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_types.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_types.h new file mode 100755 index 0000000..88c9318 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/ble_types.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup BLE_COMMON + @{ + @defgroup ble_types Common types and macro definitions + @{ + + @brief Common types and macro definitions for the BLE SoftDevice. + */ + +#ifndef BLE_TYPES_H__ +#define BLE_TYPES_H__ + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup BLE_TYPES_DEFINES Defines + * @{ */ + +/** @defgroup BLE_CONN_HANDLES BLE Connection Handles + * @{ */ +#define BLE_CONN_HANDLE_INVALID 0xFFFF /**< Invalid Connection Handle. */ +#define BLE_CONN_HANDLE_ALL 0xFFFE /**< Applies to all Connection Handles. */ +/** @} */ + + +/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs + * @{ */ +/* Generic UUIDs, applicable to all services */ +#define BLE_UUID_UNKNOWN 0x0000 /**< Reserved UUID. */ +#define BLE_UUID_SERVICE_PRIMARY 0x2800 /**< Primary Service. */ +#define BLE_UUID_SERVICE_SECONDARY 0x2801 /**< Secondary Service. */ +#define BLE_UUID_SERVICE_INCLUDE 0x2802 /**< Include. */ +#define BLE_UUID_CHARACTERISTIC 0x2803 /**< Characteristic. */ +#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP 0x2900 /**< Characteristic Extended Properties Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC 0x2901 /**< Characteristic User Description Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG 0x2902 /**< Client Characteristic Configuration Descriptor. */ +#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG 0x2903 /**< Server Characteristic Configuration Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT 0x2904 /**< Characteristic Presentation Format Descriptor. */ +#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT 0x2905 /**< Characteristic Aggregate Format Descriptor. */ +/* GATT specific UUIDs */ +#define BLE_UUID_GATT 0x1801 /**< Generic Attribute Profile. */ +#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED 0x2A05 /**< Service Changed Characteristic. */ +/* GAP specific UUIDs */ +#define BLE_UUID_GAP 0x1800 /**< Generic Access Profile. */ +#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME 0x2A00 /**< Device Name Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE 0x2A01 /**< Appearance Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR 0x2A03 /**< Reconnection Address Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_PPCP 0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_CAR 0x2AA6 /**< Central Address Resolution Characteristic. */ +#define BLE_UUID_GAP_CHARACTERISTIC_RPA_ONLY 0x2AC9 /**< Resolvable Private Address Only Characteristic. */ +/** @} */ + + +/** @defgroup BLE_UUID_TYPES Types of UUID + * @{ */ +#define BLE_UUID_TYPE_UNKNOWN 0x00 /**< Invalid UUID type. */ +#define BLE_UUID_TYPE_BLE 0x01 /**< Bluetooth SIG UUID (16-bit). */ +#define BLE_UUID_TYPE_VENDOR_BEGIN 0x02 /**< Vendor UUID types start at this index (128-bit). */ +/** @} */ + + +/** @defgroup BLE_APPEARANCES Bluetooth Appearance values + * @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml + * @{ */ +#define BLE_APPEARANCE_UNKNOWN 0 /**< Unknown. */ +#define BLE_APPEARANCE_GENERIC_PHONE 64 /**< Generic Phone. */ +#define BLE_APPEARANCE_GENERIC_COMPUTER 128 /**< Generic Computer. */ +#define BLE_APPEARANCE_GENERIC_WATCH 192 /**< Generic Watch. */ +#define BLE_APPEARANCE_WATCH_SPORTS_WATCH 193 /**< Watch: Sports Watch. */ +#define BLE_APPEARANCE_GENERIC_CLOCK 256 /**< Generic Clock. */ +#define BLE_APPEARANCE_GENERIC_DISPLAY 320 /**< Generic Display. */ +#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL 384 /**< Generic Remote Control. */ +#define BLE_APPEARANCE_GENERIC_EYE_GLASSES 448 /**< Generic Eye-glasses. */ +#define BLE_APPEARANCE_GENERIC_TAG 512 /**< Generic Tag. */ +#define BLE_APPEARANCE_GENERIC_KEYRING 576 /**< Generic Keyring. */ +#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER 640 /**< Generic Media Player. */ +#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER 704 /**< Generic Barcode Scanner. */ +#define BLE_APPEARANCE_GENERIC_THERMOMETER 768 /**< Generic Thermometer. */ +#define BLE_APPEARANCE_THERMOMETER_EAR 769 /**< Thermometer: Ear. */ +#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR 832 /**< Generic Heart rate Sensor. */ +#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT 833 /**< Heart Rate Sensor: Heart Rate Belt. */ +#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE 896 /**< Generic Blood Pressure. */ +#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM 897 /**< Blood Pressure: Arm. */ +#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST 898 /**< Blood Pressure: Wrist. */ +#define BLE_APPEARANCE_GENERIC_HID 960 /**< Human Interface Device (HID). */ +#define BLE_APPEARANCE_HID_KEYBOARD 961 /**< Keyboard (HID Subtype). */ +#define BLE_APPEARANCE_HID_MOUSE 962 /**< Mouse (HID Subtype). */ +#define BLE_APPEARANCE_HID_JOYSTICK 963 /**< Joystick (HID Subtype). */ +#define BLE_APPEARANCE_HID_GAMEPAD 964 /**< Gamepad (HID Subtype). */ +#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE 965 /**< Digitizer Tablet (HID Subtype). */ +#define BLE_APPEARANCE_HID_CARD_READER 966 /**< Card Reader (HID Subtype). */ +#define BLE_APPEARANCE_HID_DIGITAL_PEN 967 /**< Digital Pen (HID Subtype). */ +#define BLE_APPEARANCE_HID_BARCODE 968 /**< Barcode Scanner (HID Subtype). */ +#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER 1024 /**< Generic Glucose Meter. */ +#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR 1088 /**< Generic Running Walking Sensor. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE 1089 /**< Running Walking Sensor: In-Shoe. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE 1090 /**< Running Walking Sensor: On-Shoe. */ +#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP 1091 /**< Running Walking Sensor: On-Hip. */ +#define BLE_APPEARANCE_GENERIC_CYCLING 1152 /**< Generic Cycling. */ +#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER 1153 /**< Cycling: Cycling Computer. */ +#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR 1154 /**< Cycling: Speed Sensor. */ +#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR 1155 /**< Cycling: Cadence Sensor. */ +#define BLE_APPEARANCE_CYCLING_POWER_SENSOR 1156 /**< Cycling: Power Sensor. */ +#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR 1157 /**< Cycling: Speed and Cadence Sensor. */ +#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER 3136 /**< Generic Pulse Oximeter. */ +#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP 3137 /**< Fingertip (Pulse Oximeter subtype). */ +#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN 3138 /**< Wrist Worn(Pulse Oximeter subtype). */ +#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE 3200 /**< Generic Weight Scale. */ +#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT 5184 /**< Generic Outdoor Sports Activity. */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP 5185 /**< Location Display Device (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD 5187 /**< Location Pod (Outdoor Sports Activity subtype). */ +#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD 5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */ +/** @} */ + +/** @brief Set .type and .uuid fields of ble_uuid_struct to specified UUID value. */ +#define BLE_UUID_BLE_ASSIGN(instance, value) do {\ + instance.type = BLE_UUID_TYPE_BLE; \ + instance.uuid = value;} while(0) + +/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */ +#define BLE_UUID_COPY_PTR(dst, src) do {\ + (dst)->type = (src)->type; \ + (dst)->uuid = (src)->uuid;} while(0) + +/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */ +#define BLE_UUID_COPY_INST(dst, src) do {\ + (dst).type = (src).type; \ + (dst).uuid = (src).uuid;} while(0) + +/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ +#define BLE_UUID_EQ(p_uuid1, p_uuid2) \ + (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) + +/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ +#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \ + (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) + +/** @} */ + +/** @addtogroup BLE_TYPES_STRUCTURES Structures + * @{ */ + +/** @brief 128 bit UUID values. */ +typedef struct +{ + uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */ +} ble_uuid128_t; + +/** @brief Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */ +typedef struct +{ + uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ + uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ +} ble_uuid_t; + +/**@brief Data structure. */ +typedef struct +{ + uint8_t *p_data; /**< Pointer to the data buffer provided to/from the application. */ + uint16_t len; /**< Length of the data buffer, in bytes. */ +} ble_data_t; + +/** @} */ +#ifdef __cplusplus +} +#endif + +#endif /* BLE_TYPES_H__ */ + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h new file mode 100755 index 0000000..389cc37 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf52/nrf_mbr.h @@ -0,0 +1,268 @@ +/*
+ * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ * Semiconductor ASA integrated circuit in a product or a software update for
+ * such product, must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or other
+ * materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ * Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ * engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ @defgroup nrf_mbr_api Master Boot Record API
+ @{
+
+ @brief APIs for updating SoftDevice and BootLoader
+
+*/
+
+#ifndef NRF_MBR_H__
+#define NRF_MBR_H__
+
+#include "nrf_svc.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NRF_MBR_DEFINES Defines
+ * @{ */
+
+/**@brief MBR SVC Base number. */
+#define MBR_SVC_BASE (0x18)
+
+/**@brief Page size in words. */
+#define MBR_PAGE_SIZE_IN_WORDS (1024)
+
+/** @brief The size that must be reserved for the MBR when a SoftDevice is written to flash.
+This is the offset where the first byte of the SoftDevice hex file is written. */
+#define MBR_SIZE (0x1000)
+
+/** @brief Location (in the flash memory) of the bootloader address. */
+#define MBR_BOOTLOADER_ADDR (0xFF8)
+
+/** @brief Location (in UICR) of the bootloader address. */
+#define MBR_UICR_BOOTLOADER_ADDR (&(NRF_UICR->NRFFW[0]))
+
+/** @brief Location (in the flash memory) of the address of the MBR parameter page. */
+#define MBR_PARAM_PAGE_ADDR (0xFFC)
+
+/** @brief Location (in UICR) of the address of the MBR parameter page. */
+#define MBR_UICR_PARAM_PAGE_ADDR (&(NRF_UICR->NRFFW[1]))
+
+
+/** @} */
+
+/** @addtogroup NRF_MBR_ENUMS Enumerations
+ * @{ */
+
+/**@brief nRF Master Boot Record API SVC numbers. */
+enum NRF_MBR_SVCS
+{
+ SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */
+};
+
+/**@brief Possible values for ::sd_mbr_command_t.command */
+enum NRF_MBR_COMMANDS
+{
+ SD_MBR_COMMAND_COPY_BL, /**< Copy a new BootLoader. @see ::sd_mbr_command_copy_bl_t*/
+ SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/
+ SD_MBR_COMMAND_INIT_SD, /**< Initialize forwarding interrupts to SD, and run reset function in SD. Does not require any parameters in ::sd_mbr_command_t params.*/
+ SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/
+ SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Change the address the MBR starts after a reset. @see ::sd_mbr_command_vector_table_base_set_t*/
+ SD_MBR_COMMAND_RESERVED,
+ SD_MBR_COMMAND_IRQ_FORWARD_ADDRESS_SET, /**< Start forwarding all interrupts to this address. @see ::sd_mbr_command_irq_forward_address_set_t*/
+};
+
+/** @} */
+
+/** @addtogroup NRF_MBR_TYPES Types
+ * @{ */
+
+/**@brief This command copies part of a new SoftDevice
+ *
+ * The destination area is erased before copying.
+ * If dst is in the middle of a flash page, that whole flash page will be erased.
+ * If (dst+len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ * The user of this function is responsible for setting the BPROT registers.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly.
+ * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying.
+ */
+typedef struct
+{
+ uint32_t *src; /**< Pointer to the source of data to be copied.*/
+ uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/
+ uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/
+} sd_mbr_command_copy_sd_t;
+
+
+/**@brief This command works like memcmp, but takes the length in words.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal.
+ * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal.
+ */
+typedef struct
+{
+ uint32_t *ptr1; /**< Pointer to block of memory. */
+ uint32_t *ptr2; /**< Pointer to block of memory. */
+ uint32_t len; /**< Number of 32 bit words to compare.*/
+} sd_mbr_command_compare_t;
+
+
+/**@brief This command copies a new BootLoader.
+ *
+ * The MBR assumes that either @ref MBR_BOOTLOADER_ADDR or @ref MBR_UICR_BOOTLOADER_ADDR is set to
+ * the address where the bootloader will be copied. If both addresses are set, the MBR will prioritize
+ * @ref MBR_BOOTLOADER_ADDR.
+ *
+ * The bootloader destination is erased by this function.
+ * If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ * This command requires that @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR is set,
+ * see @ref sd_mbr_command.
+ *
+ * This command will use the flash protect peripheral (BPROT or ACL) to protect the flash that is
+ * not intended to be written.
+ *
+ * On success, this function will not return. It will start the new bootloader from reset-vector as normal.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_FORBIDDEN if the bootloader address is not set.
+ * @retval ::NRF_ERROR_INVALID_LENGTH if parameters attempts to read or write outside flash area.
+ * @retval ::NRF_ERROR_NO_MEM No MBR parameter page is provided. See @ref sd_mbr_command.
+ */
+typedef struct
+{
+ uint32_t *bl_src; /**< Pointer to the source of the bootloader to be be copied.*/
+ uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader. */
+} sd_mbr_command_copy_bl_t;
+
+/**@brief Change the address the MBR starts after a reset
+ *
+ * Once this function has been called, this address is where the MBR will start to forward
+ * interrupts to after a reset.
+ *
+ * To restore default forwarding, this function should be called with @ref address set to 0. If a
+ * bootloader is present, interrupts will be forwarded to the bootloader. If not, interrupts will
+ * be forwarded to the SoftDevice.
+ *
+ * The location of a bootloader can be specified in @ref MBR_BOOTLOADER_ADDR or
+ * @ref MBR_UICR_BOOTLOADER_ADDR. If both addresses are set, the MBR will prioritize
+ * @ref MBR_BOOTLOADER_ADDR.
+ *
+ * This command requires that @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR is set,
+ * see @ref sd_mbr_command.
+ *
+ * On success, this function will not return. It will reset the device.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_INVALID_ADDR if parameter address is outside of the flash size.
+ * @retval ::NRF_ERROR_NO_MEM No MBR parameter page is provided. See @ref sd_mbr_command.
+ */
+typedef struct
+{
+ uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
+} sd_mbr_command_vector_table_base_set_t;
+
+/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR
+ *
+ * Unlike sd_mbr_command_vector_table_base_set_t, this function does not reset, and it does not
+ * change where the MBR starts after reset.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+typedef struct
+{
+ uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
+} sd_mbr_command_irq_forward_address_set_t;
+
+/**@brief Input structure containing data used when calling ::sd_mbr_command
+ *
+ * Depending on what command value that is set, the corresponding params value type must also be
+ * set. See @ref NRF_MBR_COMMANDS for command types and corresponding params value type. If command
+ * @ref SD_MBR_COMMAND_INIT_SD is set, it is not necessary to set any values under params.
+ */
+typedef struct
+{
+ uint32_t command; /**< Type of command to be issued. See @ref NRF_MBR_COMMANDS. */
+ union
+ {
+ sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy SoftDevice.*/
+ sd_mbr_command_compare_t compare; /**< Parameters for verify.*/
+ sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy BootLoader. Requires parameter page. */
+ sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/
+ sd_mbr_command_irq_forward_address_set_t irq_forward_address_set; /**< Parameters for irq forward address set*/
+ } params; /**< Command parameters. */
+} sd_mbr_command_t;
+
+/** @} */
+
+/** @addtogroup NRF_MBR_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Issue Master Boot Record commands
+ *
+ * Commands used when updating a SoftDevice and bootloader.
+ *
+ * The @ref SD_MBR_COMMAND_COPY_BL and @ref SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET requires
+ * parameters to be retained by the MBR when resetting the IC. This is done in a separate flash
+ * page. The location of the flash page should be provided by the application in either
+ * @ref MBR_PARAM_PAGE_ADDR or @ref MBR_UICR_PARAM_PAGE_ADDR. If both addresses are set, the MBR
+ * will prioritize @ref MBR_PARAM_PAGE_ADDR. This page will be cleared by the MBR and is used to
+ * store the command before reset. When an address is specified, the page it refers to must not be
+ * used by the application. If no address is provided by the application, i.e. both
+ * @ref MBR_PARAM_PAGE_ADDR and @ref MBR_UICR_PARAM_PAGE_ADDR is 0xFFFFFFFF, MBR commands which use
+ * flash will be unavailable and return @ref NRF_ERROR_NO_MEM.
+ *
+ * @param[in] param Pointer to a struct describing the command.
+ *
+ * @note For a complete set of return values, see ::sd_mbr_command_copy_sd_t,
+ * ::sd_mbr_command_copy_bl_t, ::sd_mbr_command_compare_t,
+ * ::sd_mbr_command_vector_table_base_set_t, ::sd_mbr_command_irq_forward_address_set_t
+ *
+ * @retval ::NRF_ERROR_NO_MEM No MBR parameter page provided
+ * @retval ::NRF_ERROR_INVALID_PARAM if an invalid command is given.
+*/
+SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_MBR_H__
+
+/**
+ @}
+*/
diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error.h new file mode 100755 index 0000000..6badee9 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** + @defgroup nrf_error SoftDevice Global Error Codes + @{ + + @brief Global Error definitions +*/ + +/* Header guard */ +#ifndef NRF_ERROR_H__ +#define NRF_ERROR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions + * @{ */ +#define NRF_ERROR_BASE_NUM (0x0) ///< Global error base +#define NRF_ERROR_SDM_BASE_NUM (0x1000) ///< SDM error base +#define NRF_ERROR_SOC_BASE_NUM (0x2000) ///< SoC error base +#define NRF_ERROR_STK_BASE_NUM (0x3000) ///< STK error base +/** @} */ + +#define NRF_SUCCESS (NRF_ERROR_BASE_NUM + 0) ///< Successful command +#define NRF_ERROR_SVC_HANDLER_MISSING (NRF_ERROR_BASE_NUM + 1) ///< SVC handler is missing +#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED (NRF_ERROR_BASE_NUM + 2) ///< SoftDevice has not been enabled +#define NRF_ERROR_INTERNAL (NRF_ERROR_BASE_NUM + 3) ///< Internal Error +#define NRF_ERROR_NO_MEM (NRF_ERROR_BASE_NUM + 4) ///< No Memory for operation +#define NRF_ERROR_NOT_FOUND (NRF_ERROR_BASE_NUM + 5) ///< Not found +#define NRF_ERROR_NOT_SUPPORTED (NRF_ERROR_BASE_NUM + 6) ///< Not supported +#define NRF_ERROR_INVALID_PARAM (NRF_ERROR_BASE_NUM + 7) ///< Invalid Parameter +#define NRF_ERROR_INVALID_STATE (NRF_ERROR_BASE_NUM + 8) ///< Invalid state, operation disallowed in this state +#define NRF_ERROR_INVALID_LENGTH (NRF_ERROR_BASE_NUM + 9) ///< Invalid Length +#define NRF_ERROR_INVALID_FLAGS (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags +#define NRF_ERROR_INVALID_DATA (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data +#define NRF_ERROR_DATA_SIZE (NRF_ERROR_BASE_NUM + 12) ///< Invalid Data size +#define NRF_ERROR_TIMEOUT (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out +#define NRF_ERROR_NULL (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer +#define NRF_ERROR_FORBIDDEN (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation +#define NRF_ERROR_INVALID_ADDR (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address +#define NRF_ERROR_BUSY (NRF_ERROR_BASE_NUM + 17) ///< Busy +#define NRF_ERROR_CONN_COUNT (NRF_ERROR_BASE_NUM + 18) ///< Maximum connection count exceeded. +#define NRF_ERROR_RESOURCES (NRF_ERROR_BASE_NUM + 19) ///< Not enough resources for operation + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h new file mode 100755 index 0000000..530959b --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error_sdm.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** + @addtogroup nrf_sdm_api + @{ + @defgroup nrf_sdm_error SoftDevice Manager Error Codes + @{ + + @brief Error definitions for the SDM API +*/ + +/* Header guard */ +#ifndef NRF_ERROR_SDM_H__ +#define NRF_ERROR_SDM_H__ + +#include "nrf_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN (NRF_ERROR_SDM_BASE_NUM + 0) ///< Unknown LFCLK source. +#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1) ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts). +#define NRF_ERROR_SDM_INCORRECT_CLENR0 (NRF_ERROR_SDM_BASE_NUM + 2) ///< Incorrect CLENR0 (can be caused by erroneous SoftDevice flashing). + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_SDM_H__ + +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error_soc.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error_soc.h new file mode 100755 index 0000000..1e784b8 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_error_soc.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @addtogroup nrf_soc_api + @{ + @defgroup nrf_soc_error SoC Library Error Codes + @{ + + @brief Error definitions for the SoC library + +*/ + +/* Header guard */ +#ifndef NRF_ERROR_SOC_H__ +#define NRF_ERROR_SOC_H__ + +#include "nrf_error.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* Mutex Errors */ +#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN (NRF_ERROR_SOC_BASE_NUM + 0) ///< Mutex already taken + +/* NVIC errors */ +#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE (NRF_ERROR_SOC_BASE_NUM + 1) ///< NVIC interrupt not available +#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2) ///< NVIC interrupt priority not allowed +#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 3) ///< NVIC should not return + +/* Power errors */ +#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 4) ///< Power mode unknown +#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 5) ///< Power POF threshold unknown +#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 6) ///< Power off should not return + +/* Rand errors */ +#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES (NRF_ERROR_SOC_BASE_NUM + 7) ///< RAND not enough values + +/* PPI errors */ +#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL (NRF_ERROR_SOC_BASE_NUM + 8) ///< Invalid PPI Channel +#define NRF_ERROR_SOC_PPI_INVALID_GROUP (NRF_ERROR_SOC_BASE_NUM + 9) ///< Invalid PPI Group + +#ifdef __cplusplus +} +#endif +#endif // NRF_ERROR_SOC_H__ +/** + @} + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_nvic.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_nvic.h new file mode 100755 index 0000000..1f79cc3 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_nvic.h @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup nrf_nvic_api SoftDevice NVIC API + * @{ + * + * @note In order to use this module, the following code has to be added to a .c file: + * \code + * nrf_nvic_state_t nrf_nvic_state = {0}; + * \endcode + * + * @note Definitions and declarations starting with __ (double underscore) in this header file are + * not intended for direct use by the application. + * + * @brief APIs for the accessing NVIC when using a SoftDevice. + * + */ + +#ifndef NRF_NVIC_H__ +#define NRF_NVIC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup NRF_NVIC_DEFINES Defines + * @{ */ + +/**@defgroup NRF_NVIC_ISER_DEFINES SoftDevice NVIC internal definitions + * @{ */ + +#define __NRF_NVIC_NVMC_IRQn (30) /**< The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK. */ + +#define __NRF_NVIC_ISER_COUNT (2) /**< The number of ISER/ICER registers in the NVIC that are used. */ + +/**@brief Interrupt priority levels used by the SoftDevice. */ +#define __NRF_NVIC_SD_IRQ_PRIOS ((uint8_t)( \ + (1U << 0) /**< Priority level high .*/ \ + | (1U << 1) /**< Priority level medium. */ \ + | (1U << 4) /**< Priority level low. */ \ + )) + +/**@brief Interrupt priority levels available to the application. */ +#define __NRF_NVIC_APP_IRQ_PRIOS ((uint8_t)~__NRF_NVIC_SD_IRQ_PRIOS) + +/**@brief Interrupts used by the SoftDevice, with IRQn in the range 0-31. */ +#define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \ + (1U << POWER_CLOCK_IRQn) \ + | (1U << RADIO_IRQn) \ + | (1U << RTC0_IRQn) \ + | (1U << TIMER0_IRQn) \ + | (1U << RNG_IRQn) \ + | (1U << ECB_IRQn) \ + | (1U << CCM_AAR_IRQn) \ + | (1U << TEMP_IRQn) \ + | (1U << __NRF_NVIC_NVMC_IRQn) \ + | (1U << (uint32_t)SWI5_IRQn) \ + )) + +/**@brief Interrupts used by the SoftDevice, with IRQn in the range 32-63. */ +#define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0) + +/**@brief Interrupts available for to application, with IRQn in the range 0-31. */ +#define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0) + +/**@brief Interrupts available for to application, with IRQn in the range 32-63. */ +#define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1) + +/**@} */ + +/**@} */ + +/**@addtogroup NRF_NVIC_VARIABLES Variables + * @{ */ + +/**@brief Type representing the state struct for the SoftDevice NVIC module. */ +typedef struct +{ + uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */ + uint32_t volatile __cr_flag; /**< Non-zero if already in a critical region */ +} nrf_nvic_state_t; + +/**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an + * application source file. */ +extern nrf_nvic_state_t nrf_nvic_state; + +/**@} */ + +/**@addtogroup NRF_NVIC_INTERNAL_FUNCTIONS SoftDevice NVIC internal functions + * @{ */ + +/**@brief Disables IRQ interrupts globally, including the SoftDevice's interrupts. + * + * @retval The value of PRIMASK prior to disabling the interrupts. + */ +__STATIC_INLINE int __sd_nvic_irq_disable(void); + +/**@brief Enables IRQ interrupts globally, including the SoftDevice's interrupts. + */ +__STATIC_INLINE void __sd_nvic_irq_enable(void); + +/**@brief Checks if IRQn is available to application + * @param[in] IRQn IRQ to check + * + * @retval 1 (true) if the IRQ to check is available to the application + */ +__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn); + +/**@brief Checks if priority is available to application + * @param[in] priority priority to check + * + * @retval 1 (true) if the priority to check is available to the application + */ +__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority); + +/**@} */ + +/**@addtogroup NRF_NVIC_FUNCTIONS SoftDevice NVIC public functions + * @{ */ + +/**@brief Enable External Interrupt. + * @note Corresponds to NVIC_EnableIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt was enabled. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn); + +/**@brief Disable External Interrupt. + * @note Corresponds to NVIC_DisableIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt was disabled. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn); + +/**@brief Get Pending Interrupt. + * @note Corresponds to NVIC_GetPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS. + * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ. + * + * @retval ::NRF_SUCCESS The interrupt is available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq); + +/**@brief Set Pending Interrupt. + * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt is set pending. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn); + +/**@brief Clear Pending Interrupt. + * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS. + * + * @retval ::NRF_SUCCESS The interrupt pending flag is cleared. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn); + +/**@brief Set Interrupt Priority. + * @note Corresponds to NVIC_SetPriority in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * @pre Priority is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS. + * @param[in] priority A valid IRQ priority for use by the application. + * + * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority); + +/**@brief Get Interrupt Priority. + * @note Corresponds to NVIC_GetPriority in CMSIS. + * + * @pre IRQn is valid and not reserved by the stack. + * + * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS. + * @param[out] p_priority Return value from NVIC_GetPriority. + * + * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. + * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application. + */ +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority); + +/**@brief System Reset. + * @note Corresponds to NVIC_SystemReset in CMSIS. + * + * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN + */ +__STATIC_INLINE uint32_t sd_nvic_SystemReset(void); + +/**@brief Enter critical region. + * + * @post Application interrupts will be disabled. + * @note sd_nvic_critical_region_enter() and ::sd_nvic_critical_region_exit() must be called in matching pairs inside each + * execution context + * @sa sd_nvic_critical_region_exit + * + * @param[out] p_is_nested_critical_region If 1, the application is now in a nested critical region. + * + * @retval ::NRF_SUCCESS + */ +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region); + +/**@brief Exit critical region. + * + * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter. + * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called. + * + * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter. + * + * @retval ::NRF_SUCCESS + */ +__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region); + +/**@} */ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE int __sd_nvic_irq_disable(void) +{ + int pm = __get_PRIMASK(); + __disable_irq(); + return pm; +} + +__STATIC_INLINE void __sd_nvic_irq_enable(void) +{ + __enable_irq(); +} + +__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn) +{ + if (IRQn < 32) + { + return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0; + } + else if (IRQn < 64) + { + return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0; + } + else + { + return 1; + } +} + +__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority) +{ + if( (priority >= (1 << __NVIC_PRIO_BITS)) + || (((1 << priority) & __NRF_NVIC_APP_IRQ_PRIOS) == 0) + ) + { + return 0; + } + return 1; +} + + +__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn))) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } + + if (nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); + } + else + { + NVIC_EnableIRQ(IRQn); + } + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F)); + } + else + { + NVIC_DisableIRQ(IRQn); + } + + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + *p_pending_irq = NVIC_GetPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + NVIC_SetPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + NVIC_ClearPendingIRQ(IRQn); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if (!__sd_nvic_app_accessible_irq(IRQn)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } + + if (!__sd_nvic_is_app_accessible_priority(priority)) + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; + } + + NVIC_SetPriority(IRQn, (uint32_t)priority); + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority) +{ + if (__sd_nvic_app_accessible_irq(IRQn)) + { + *p_priority = (NVIC_GetPriority(IRQn) & 0xFF); + return NRF_SUCCESS; + } + else + { + return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; + } +} + +__STATIC_INLINE uint32_t sd_nvic_SystemReset(void) +{ + NVIC_SystemReset(); + return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN; +} + +__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region) +{ + int was_masked = __sd_nvic_irq_disable(); + if (!nrf_nvic_state.__cr_flag) + { + nrf_nvic_state.__cr_flag = 1; + nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); + NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; + nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); + NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; + *p_is_nested_critical_region = 0; + } + else + { + *p_is_nested_critical_region = 1; + } + if (!was_masked) + { + __sd_nvic_irq_enable(); + } + return NRF_SUCCESS; +} + +__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) +{ + if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0)) + { + int was_masked = __sd_nvic_irq_disable(); + NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; + NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; + nrf_nvic_state.__cr_flag = 0; + if (!was_masked) + { + __sd_nvic_irq_enable(); + } + } + + return NRF_SUCCESS; +} + +#endif /* SUPPRESS_INLINE_IMPLEMENTATION */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_NVIC_H__ + +/**@} */ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_sdm.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_sdm.h new file mode 100755 index 0000000..5dfbb28 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_sdm.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + @defgroup nrf_sdm_api SoftDevice Manager API + @{ + + @brief APIs for SoftDevice management. + +*/ + +#ifndef NRF_SDM_H__ +#define NRF_SDM_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_sdm.h" +#include "nrf_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup NRF_SDM_DEFINES Defines + * @{ */ +#ifdef NRFSOC_DOXYGEN +/// Declared in nrf_mbr.h +#define MBR_SIZE 0 +#warning test +#endif + +/** @brief The major version for the SoftDevice binary distributed with this header file. */ +#define SD_MAJOR_VERSION (6) + +/** @brief The minor version for the SoftDevice binary distributed with this header file. */ +#define SD_MINOR_VERSION (1) + +/** @brief The bugfix version for the SoftDevice binary distributed with this header file. */ +#define SD_BUGFIX_VERSION (1) + +/** @brief The SoftDevice variant of this firmware. */ +#define SD_VARIANT_ID 140 + +/** @brief The full version number for the SoftDevice binary this header file was distributed + * with, as a decimal number in the form Mmmmbbb, where: + * - M is major version (one or more digits) + * - mmm is minor version (three digits) + * - bbb is bugfix version (three digits). */ +#define SD_VERSION (SD_MAJOR_VERSION * 1000000 + SD_MINOR_VERSION * 1000 + SD_BUGFIX_VERSION) + +/** @brief SoftDevice Manager SVC Base number. */ +#define SDM_SVC_BASE 0x10 + +/** @brief SoftDevice unique string size in bytes. */ +#define SD_UNIQUE_STR_SIZE 20 + +/** @brief Invalid info field. Returned when an info field does not exist. */ +#define SDM_INFO_FIELD_INVALID (0) + +/** @brief Defines the SoftDevice Information Structure location (address) as an offset from +the start of the SoftDevice (without MBR)*/ +#define SOFTDEVICE_INFO_STRUCT_OFFSET (0x2000) + +/** @brief Defines the absolute SoftDevice Information Structure location (address) when the + * SoftDevice is installed just above the MBR (the usual case). */ +#define SOFTDEVICE_INFO_STRUCT_ADDRESS (SOFTDEVICE_INFO_STRUCT_OFFSET + MBR_SIZE) + +/** @brief Defines the offset for the SoftDevice Information Structure size value relative to the + * SoftDevice base address. The size value is of type uint8_t. */ +#define SD_INFO_STRUCT_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET) + +/** @brief Defines the offset for the SoftDevice size value relative to the SoftDevice base address. + * The size value is of type uint32_t. */ +#define SD_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x08) + +/** @brief Defines the offset for FWID value relative to the SoftDevice base address. The FWID value + * is of type uint16_t. */ +#define SD_FWID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x0C) + +/** @brief Defines the offset for the SoftDevice ID relative to the SoftDevice base address. The ID + * is of type uint32_t. */ +#define SD_ID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x10) + +/** @brief Defines the offset for the SoftDevice version relative to the SoftDevice base address in + * the same format as @ref SD_VERSION, stored as an uint32_t. */ +#define SD_VERSION_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x14) + +/** @brief Defines the offset for the SoftDevice unique string relative to the SoftDevice base address. + * The SD_UNIQUE_STR is stored as an array of uint8_t. The size of array is @ref SD_UNIQUE_STR_SIZE. + */ +#define SD_UNIQUE_STR_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x18) + +/** @brief Defines a macro for retrieving the actual SoftDevice Information Structure size value + * from a given base address. Use @ref MBR_SIZE as the argument when the SoftDevice is + * installed just above the MBR (the usual case). */ +#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *) ((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET))) + +/** @brief Defines a macro for retrieving the actual SoftDevice size value from a given base + * address. Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above + * the MBR (the usual case). */ +#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET))) + +/** @brief Defines the amount of flash that is used by the SoftDevice. + * Add @ref MBR_SIZE to find the first available flash address when the SoftDevice is installed + * just above the MBR (the usual case). + */ +#define SD_FLASH_SIZE 0x25000 + +/** @brief Defines a macro for retrieving the actual FWID value from a given base address. Use + * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the usual + * case). */ +#define SD_FWID_GET(baseaddr) (*((uint16_t *) ((baseaddr) + SD_FWID_OFFSET))) + +/** @brief Defines a macro for retrieving the actual SoftDevice ID from a given base address. Use + * @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the + * usual case). */ +#define SD_ID_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_ID_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (*((uint32_t *) ((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/** @brief Defines a macro for retrieving the actual SoftDevice version from a given base address. + * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR + * (the usual case). */ +#define SD_VERSION_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_VERSION_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (*((uint32_t *) ((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/** @brief Defines a macro for retrieving the address of SoftDevice unique str based on a given base address. + * Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR + * (the usual case). */ +#define SD_UNIQUE_STR_ADDR_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_UNIQUE_STR_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \ + ? (((uint8_t *) ((baseaddr) + SD_UNIQUE_STR_OFFSET))) : SDM_INFO_FIELD_INVALID) + +/**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges + * @{ */ +#define NRF_FAULT_ID_SD_RANGE_START 0x00000000 /**< SoftDevice ID range start. */ +#define NRF_FAULT_ID_APP_RANGE_START 0x00001000 /**< Application ID range start. */ +/**@} */ + +/**@defgroup NRF_FAULT_IDS Fault ID types + * @{ */ +#define NRF_FAULT_ID_SD_ASSERT (NRF_FAULT_ID_SD_RANGE_START + 1) /**< SoftDevice assertion. The info parameter is reserved for future used. */ +#define NRF_FAULT_ID_APP_MEMACC (NRF_FAULT_ID_APP_RANGE_START + 1) /**< Application invalid memory access. The info parameter will contain 0x00000000, + in case of SoftDevice RAM access violation. In case of SoftDevice peripheral + register violation the info parameter will contain the sub-region number of + PREGION[0], on whose address range the disallowed write access caused the + memory access fault. */ +/**@} */ + +/** @} */ + +/** @addtogroup NRF_SDM_ENUMS Enumerations + * @{ */ + +/**@brief nRF SoftDevice Manager API SVC numbers. */ +enum NRF_SD_SVCS +{ + SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ + SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ + SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ + SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ + SVC_SDM_LAST /**< Placeholder for last SDM SVC */ +}; + +/** @} */ + +/** @addtogroup NRF_SDM_DEFINES Defines + * @{ */ + +/**@defgroup NRF_CLOCK_LF_ACCURACY Clock accuracy + * @{ */ + +#define NRF_CLOCK_LF_ACCURACY_250_PPM (0) /**< Default: 250 ppm */ +#define NRF_CLOCK_LF_ACCURACY_500_PPM (1) /**< 500 ppm */ +#define NRF_CLOCK_LF_ACCURACY_150_PPM (2) /**< 150 ppm */ +#define NRF_CLOCK_LF_ACCURACY_100_PPM (3) /**< 100 ppm */ +#define NRF_CLOCK_LF_ACCURACY_75_PPM (4) /**< 75 ppm */ +#define NRF_CLOCK_LF_ACCURACY_50_PPM (5) /**< 50 ppm */ +#define NRF_CLOCK_LF_ACCURACY_30_PPM (6) /**< 30 ppm */ +#define NRF_CLOCK_LF_ACCURACY_20_PPM (7) /**< 20 ppm */ +#define NRF_CLOCK_LF_ACCURACY_10_PPM (8) /**< 10 ppm */ +#define NRF_CLOCK_LF_ACCURACY_5_PPM (9) /**< 5 ppm */ +#define NRF_CLOCK_LF_ACCURACY_2_PPM (10) /**< 2 ppm */ +#define NRF_CLOCK_LF_ACCURACY_1_PPM (11) /**< 1 ppm */ + +/** @} */ + +/**@defgroup NRF_CLOCK_LF_SRC Possible LFCLK oscillator sources + * @{ */ + +#define NRF_CLOCK_LF_SRC_RC (0) /**< LFCLK RC oscillator. */ +#define NRF_CLOCK_LF_SRC_XTAL (1) /**< LFCLK crystal oscillator. */ +#define NRF_CLOCK_LF_SRC_SYNTH (2) /**< LFCLK Synthesized from HFCLK. */ + +/** @} */ + +/** @} */ + +/** @addtogroup NRF_SDM_TYPES Types + * @{ */ + +/**@brief Type representing LFCLK oscillator source. */ +typedef struct +{ + uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ + uint8_t rc_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second + units (nRF52: 1-32). + @note To avoid excessive clock drift, 0.5 degrees Celsius is the + maximum temperature change allowed in one calibration timer + interval. The interval should be selected to ensure this. + + @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC. */ + uint8_t rc_temp_ctiv; /**< Only for ::NRF_CLOCK_LF_SRC_RC: How often (in number of calibration + intervals) the RC oscillator shall be calibrated if the temperature + hasn't changed. + 0: Always calibrate even if the temperature hasn't changed. + 1: Only calibrate if the temperature has changed (legacy - nRF51 only). + 2-33: Check the temperature and only calibrate if it has changed, + however calibration will take place every rc_temp_ctiv + intervals in any case. + + @note Must be 0 if source is not ::NRF_CLOCK_LF_SRC_RC. + + @note For nRF52, the application must ensure calibration at least once + every 8 seconds to ensure +/-500 ppm clock stability. The + recommended configuration for ::NRF_CLOCK_LF_SRC_RC on nRF52 is + rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at + least once every 8 seconds and for temperature changes of 0.5 + degrees Celsius every 4 seconds. See the Product Specification + for the nRF52 device being used for more information.*/ + uint8_t accuracy; /**< External clock accuracy used in the LL to compute timing + windows, see @ref NRF_CLOCK_LF_ACCURACY.*/ +} nrf_clock_lf_cfg_t; + +/**@brief Fault Handler type. + * + * When certain unrecoverable errors occur within the application or SoftDevice the fault handler will be called back. + * The protocol stack will be in an undefined state when this happens and the only way to recover will be to + * perform a reset, using e.g. CMSIS NVIC_SystemReset(). + * If the application returns from the fault handler the SoftDevice will call NVIC_SystemReset(). + * + * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the fault callback. + * + * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. + * @param[in] pc The program counter of the instruction that triggered the fault. + * @param[in] info Optional additional information regarding the fault. Refer to each Fault identifier for details. + * + * @note When id is set to @ref NRF_FAULT_ID_APP_MEMACC, pc will contain the address of the instruction being executed at the time when + * the fault is detected by the CPU. The CPU program counter may have advanced up to 2 instructions (no branching) after the one that triggered the fault. + */ +typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info); + +/** @} */ + +/** @addtogroup NRF_SDM_FUNCTIONS Functions + * @{ */ + +/**@brief Enables the SoftDevice and by extension the protocol stack. + * + * @note Some care must be taken if a low frequency clock source is already running when calling this function: + * If the LF clock has a different source then the one currently running, it will be stopped. Then, the new + * clock source will be started. + * + * @note This function has no effect when returning with an error. + * + * @post If return code is ::NRF_SUCCESS + * - SoC library and protocol stack APIs are made available. + * - A portion of RAM will be unavailable (see relevant SDS documentation). + * - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation). + * - Interrupts will not arrive from protected peripherals or interrupts. + * - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the SoftDevice. + * - Interrupt latency may be affected by the SoftDevice (see relevant SDS documentation). + * - Chosen low frequency clock source will be running. + * + * @param p_clock_lf_cfg Low frequency clock source and accuracy. + If NULL the clock will be configured as an RC source with rc_ctiv = 16 and .rc_temp_ctiv = 2 + In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock. + * @param fault_handler Callback to be invoked in case of fault, cannot be NULL. + * + * @retval ::NRF_SUCCESS + * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied. + * @retval ::NRF_ERROR_INVALID_STATE SoftDevice is already enabled, and the clock source and fault handler cannot be updated. + * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDevice interrupt is already enabled, or an enabled interrupt has an illegal priority level. + * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected. + * @retval ::NRF_ERROR_INVALID_PARAM Invalid clock source configuration supplied in p_clock_lf_cfg. + */ +SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler)); + + +/**@brief Disables the SoftDevice and by extension the protocol stack. + * + * Idempotent function to disable the SoftDevice. + * + * @post SoC library and protocol stack APIs are made unavailable. + * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest). + * @post All peripherals used by the SoftDevice will be reset to default values. + * @post All of RAM become available. + * @post All interrupts are forwarded to the application. + * @post LFCLK source chosen in ::sd_softdevice_enable will be left running. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void)); + +/**@brief Check if the SoftDevice is enabled. + * + * @param[out] p_softdevice_enabled If the SoftDevice is enabled: 1 else 0. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled)); + +/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice + * + * This function is only intended to be called when a bootloader is enabled. + * + * @param[in] address The base address of the interrupt vector table for forwarded interrupts. + + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address)); + +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif // NRF_SDM_H__ + +/** + @} +*/ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_soc.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_soc.h new file mode 100755 index 0000000..beb4d3a --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_soc.h @@ -0,0 +1,1079 @@ +/* + * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup nrf_soc_api SoC Library API + * @{ + * + * @brief APIs for the SoC library. + * + */ + +#ifndef NRF_SOC_H__ +#define NRF_SOC_H__ + +#include <stdint.h> +#include "nrf.h" +#include "nrf_svc.h" +#include "nrf_error.h" +#include "nrf_error_soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@addtogroup NRF_SOC_DEFINES Defines + * @{ */ + +/**@brief The number of the lowest SVC number reserved for the SoC library. */ +#define SOC_SVC_BASE (0x20) /**< Base value for SVCs that are available when the SoftDevice is disabled. */ +#define SOC_SVC_BASE_NOT_AVAILABLE (0x2C) /**< Base value for SVCs that are not available when the SoftDevice is disabled. */ + +/**@brief Guaranteed time for application to process radio inactive notification. */ +#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US (62) + +/**@brief The minimum allowed timeslot extension time. */ +#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200) + +/**@brief The maximum processing time to handle a timeslot extension. */ +#define NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US (17) + +/**@brief The latest time before the end of a timeslot the timeslot can be extended. */ +#define NRF_RADIO_MIN_EXTENSION_MARGIN_US (79) + +#define SOC_ECB_KEY_LENGTH (16) /**< ECB key length. */ +#define SOC_ECB_CLEARTEXT_LENGTH (16) /**< ECB cleartext length. */ +#define SOC_ECB_CIPHERTEXT_LENGTH (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */ + +#define SD_EVT_IRQn (SWI2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */ +#define SD_EVT_IRQHandler (SWI2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. + The default interrupt priority for this handler is set to 6 */ +#define RADIO_NOTIFICATION_IRQn (SWI1_IRQn) /**< The radio notification IRQ number. */ +#define RADIO_NOTIFICATION_IRQHandler (SWI1_IRQHandler) /**< The radio notification IRQ handler. + The default interrupt priority for this handler is set to 6 */ +#define NRF_RADIO_LENGTH_MIN_US (100) /**< The shortest allowed radio timeslot, in microseconds. */ +#define NRF_RADIO_LENGTH_MAX_US (100000) /**< The longest allowed radio timeslot, in microseconds. */ + +#define NRF_RADIO_DISTANCE_MAX_US (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */ + +#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */ + +#define NRF_RADIO_START_JITTER_US (2) /**< The maximum jitter in @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */ + +/**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is disabled. */ +#define NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK ((uint32_t)(0)) + +/**@brief Mask of PPI channels reserved by the SoftDevice when the SoftDevice is enabled. */ +#define NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK ((uint32_t)( \ + (1U << 17) \ + | (1U << 18) \ + | (1U << 19) \ + | (1U << 20) \ + | (1U << 21) \ + | (1U << 22) \ + | (1U << 23) \ + | (1U << 24) \ + | (1U << 25) \ + | (1U << 26) \ + | (1U << 27) \ + | (1U << 28) \ + | (1U << 29) \ + | (1U << 30) \ + | (1U << 31) \ + )) + +/**@brief Mask of PPI channels available to the application when the SoftDevice is disabled. */ +#define NRF_SOC_APP_PPI_CHANNELS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_CHANNELS_SD_DISABLED_MSK) + +/**@brief Mask of PPI channels available to the application when the SoftDevice is enabled. */ +#define NRF_SOC_APP_PPI_CHANNELS_SD_ENABLED_MSK (~NRF_SOC_SD_PPI_CHANNELS_SD_ENABLED_MSK) + +/**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is disabled. */ +#define NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK ((uint32_t)(0)) + +/**@brief Mask of PPI groups reserved by the SoftDevice when the SoftDevice is enabled. */ +#define NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK ((uint32_t)( \ + (1U << 4) \ + | (1U << 5) \ + )) + +/**@brief Mask of PPI groups available to the application when the SoftDevice is disabled. */ +#define NRF_SOC_APP_PPI_GROUPS_SD_DISABLED_MSK (~NRF_SOC_SD_PPI_GROUPS_SD_DISABLED_MSK) + +/**@brief Mask of PPI groups available to the application when the SoftDevice is enabled. */ +#define NRF_SOC_APP_PPI_GROUPS_SD_ENABLED_MSK (~NRF_SOC_SD_PPI_GROUPS_SD_ENABLED_MSK) + +/**@} */ + +/**@addtogroup NRF_SOC_ENUMS Enumerations + * @{ */ + +/**@brief The SVC numbers used by the SVC functions in the SoC library. */ +enum NRF_SOC_SVCS +{ + SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE, + SD_PPI_CHANNEL_ENABLE_SET = SOC_SVC_BASE + 1, + SD_PPI_CHANNEL_ENABLE_CLR = SOC_SVC_BASE + 2, + SD_PPI_CHANNEL_ASSIGN = SOC_SVC_BASE + 3, + SD_PPI_GROUP_TASK_ENABLE = SOC_SVC_BASE + 4, + SD_PPI_GROUP_TASK_DISABLE = SOC_SVC_BASE + 5, + SD_PPI_GROUP_ASSIGN = SOC_SVC_BASE + 6, + SD_PPI_GROUP_GET = SOC_SVC_BASE + 7, + SD_FLASH_PAGE_ERASE = SOC_SVC_BASE + 8, + SD_FLASH_WRITE = SOC_SVC_BASE + 9, + SD_PROTECTED_REGISTER_WRITE = SOC_SVC_BASE + 11, + SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, + SD_MUTEX_ACQUIRE = SOC_SVC_BASE_NOT_AVAILABLE + 1, + SD_MUTEX_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 2, + SD_RAND_APPLICATION_POOL_CAPACITY_GET = SOC_SVC_BASE_NOT_AVAILABLE + 3, + SD_RAND_APPLICATION_BYTES_AVAILABLE_GET = SOC_SVC_BASE_NOT_AVAILABLE + 4, + SD_RAND_APPLICATION_VECTOR_GET = SOC_SVC_BASE_NOT_AVAILABLE + 5, + SD_POWER_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 6, + SD_POWER_SYSTEM_OFF = SOC_SVC_BASE_NOT_AVAILABLE + 7, + SD_POWER_RESET_REASON_GET = SOC_SVC_BASE_NOT_AVAILABLE + 8, + SD_POWER_RESET_REASON_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 9, + SD_POWER_POF_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 10, + SD_POWER_POF_THRESHOLD_SET = SOC_SVC_BASE_NOT_AVAILABLE + 11, + SD_POWER_POF_THRESHOLDVDDH_SET = SOC_SVC_BASE_NOT_AVAILABLE + 12, + SD_POWER_RAM_POWER_SET = SOC_SVC_BASE_NOT_AVAILABLE + 13, + SD_POWER_RAM_POWER_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 14, + SD_POWER_RAM_POWER_GET = SOC_SVC_BASE_NOT_AVAILABLE + 15, + SD_POWER_GPREGRET_SET = SOC_SVC_BASE_NOT_AVAILABLE + 16, + SD_POWER_GPREGRET_CLR = SOC_SVC_BASE_NOT_AVAILABLE + 17, + SD_POWER_GPREGRET_GET = SOC_SVC_BASE_NOT_AVAILABLE + 18, + SD_POWER_DCDC_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 19, + SD_POWER_DCDC0_MODE_SET = SOC_SVC_BASE_NOT_AVAILABLE + 20, + SD_APP_EVT_WAIT = SOC_SVC_BASE_NOT_AVAILABLE + 21, + SD_CLOCK_HFCLK_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 22, + SD_CLOCK_HFCLK_RELEASE = SOC_SVC_BASE_NOT_AVAILABLE + 23, + SD_CLOCK_HFCLK_IS_RUNNING = SOC_SVC_BASE_NOT_AVAILABLE + 24, + SD_RADIO_NOTIFICATION_CFG_SET = SOC_SVC_BASE_NOT_AVAILABLE + 25, + SD_ECB_BLOCK_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 26, + SD_ECB_BLOCKS_ENCRYPT = SOC_SVC_BASE_NOT_AVAILABLE + 27, + SD_RADIO_SESSION_OPEN = SOC_SVC_BASE_NOT_AVAILABLE + 28, + SD_RADIO_SESSION_CLOSE = SOC_SVC_BASE_NOT_AVAILABLE + 29, + SD_RADIO_REQUEST = SOC_SVC_BASE_NOT_AVAILABLE + 30, + SD_EVT_GET = SOC_SVC_BASE_NOT_AVAILABLE + 31, + SD_TEMP_GET = SOC_SVC_BASE_NOT_AVAILABLE + 32, + SD_POWER_USBPWRRDY_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 33, + SD_POWER_USBDETECTED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 34, + SD_POWER_USBREMOVED_ENABLE = SOC_SVC_BASE_NOT_AVAILABLE + 35, + SD_POWER_USBREGSTATUS_GET = SOC_SVC_BASE_NOT_AVAILABLE + 36, + SVC_SOC_LAST = SOC_SVC_BASE_NOT_AVAILABLE + 37 +}; + +/**@brief Possible values of a ::nrf_mutex_t. */ +enum NRF_MUTEX_VALUES +{ + NRF_MUTEX_FREE, + NRF_MUTEX_TAKEN +}; + +/**@brief Power modes. */ +enum NRF_POWER_MODES +{ + NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ + NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ +}; + + +/**@brief Power failure thresholds */ +enum NRF_POWER_THRESHOLDS +{ + NRF_POWER_THRESHOLD_V17 = 4UL, /**< 1.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V18, /**< 1.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V19, /**< 1.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V20, /**< 2.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V22, /**< 2.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V24, /**< 2.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V26, /**< 2.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLD_V28 /**< 2.8 Volts power failure threshold. */ +}; + +/**@brief Power failure thresholds for high voltage */ +enum NRF_POWER_THRESHOLDVDDHS +{ + NRF_POWER_THRESHOLDVDDH_V27, /**< 2.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V28, /**< 2.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V29, /**< 2.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V30, /**< 3.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V31, /**< 3.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V32, /**< 3.2 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V33, /**< 3.3 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V34, /**< 3.4 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V35, /**< 3.5 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V36, /**< 3.6 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V37, /**< 3.7 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V38, /**< 3.8 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V39, /**< 3.9 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V40, /**< 4.0 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V41, /**< 4.1 Volts power failure threshold. */ + NRF_POWER_THRESHOLDVDDH_V42 /**< 4.2 Volts power failure threshold. */ +}; + + +/**@brief DC/DC converter modes. */ +enum NRF_POWER_DCDC_MODES +{ + NRF_POWER_DCDC_DISABLE, /**< The DCDC is disabled. */ + NRF_POWER_DCDC_ENABLE /**< The DCDC is enabled. */ +}; + +/**@brief Radio notification distances. */ +enum NRF_RADIO_NOTIFICATION_DISTANCES +{ + NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ + NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ + NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ +}; + + +/**@brief Radio notification types. */ +enum NRF_RADIO_NOTIFICATION_TYPES +{ + NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ + NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ +}; + +/**@brief The Radio signal callback types. */ +enum NRF_RADIO_CALLBACK_SIGNAL_TYPE +{ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ + NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ +}; + +/**@brief The actions requested by the signal callback. + * + * This code gives the SOC instructions about what action to take when the signal callback has + * returned. + */ +enum NRF_RADIO_SIGNAL_CALLBACK_ACTION +{ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current + timeslot. Maximum execution time for this action: + @ref NRF_RADIO_MAX_EXTENSION_PROCESSING_TIME_US. + This action must be started at least + @ref NRF_RADIO_MIN_EXTENSION_MARGIN_US before + the end of the timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ + NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ +}; + +/**@brief Radio timeslot high frequency clock source configuration. */ +enum NRF_RADIO_HFCLK_CFG +{ + NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the + external crystal for the whole duration of the timeslot. This should be the + preferred option for events that use the radio or require high timing accuracy. + @note The SoftDevice will automatically turn on and off the external crystal, + at the beginning and end of the timeslot, respectively. The crystal may also + intentionally be left running after the timeslot, in cases where it is needed + by the SoftDevice shortly after the end of the timeslot. */ + NRF_RADIO_HFCLK_CFG_NO_GUARANTEE /**< This configuration allows for earlier and tighter scheduling of timeslots. + The RC oscillator may be the clock source in part or for the whole duration of the timeslot. + The RC oscillator's accuracy must therefore be taken into consideration. + @note If the application will use the radio peripheral in timeslots with this configuration, + it must make sure that the crystal is running and stable before starting the radio. */ +}; + +/**@brief Radio timeslot priorities. */ +enum NRF_RADIO_PRIORITY +{ + NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ + NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activities of the SoftDevice stack(s)). */ +}; + +/**@brief Radio timeslot request type. */ +enum NRF_RADIO_REQUEST_TYPE +{ + NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */ + NRF_RADIO_REQ_TYPE_NORMAL /**< Normal radio timeslot request. */ +}; + +/**@brief SoC Events. */ +enum NRF_SOC_EVTS +{ + NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ + NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ + NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ + NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ + NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ + NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ + NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */ + NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio timeslot session is idle. */ + NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio timeslot session is closed. */ + NRF_EVT_POWER_USB_POWER_READY, /**< Event indicating that a USB 3.3 V supply is ready. */ + NRF_EVT_POWER_USB_DETECTED, /**< Event indicating that voltage supply is detected on VBUS. */ + NRF_EVT_POWER_USB_REMOVED, /**< Event indicating that voltage supply is removed from VBUS. */ + NRF_EVT_NUMBER_OF_EVTS +}; + +/**@} */ + + +/**@addtogroup NRF_SOC_STRUCTURES Structures + * @{ */ + +/**@brief Represents a mutex for use with the nrf_mutex functions. + * @note Accessing the value directly is not safe, use the mutex functions! + */ +typedef volatile uint8_t nrf_mutex_t; + +/**@brief Parameters for a request for a timeslot as early as possible. */ +typedef struct +{ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ + uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ +} nrf_radio_request_earliest_t; + +/**@brief Parameters for a normal radio timeslot request. */ +typedef struct +{ + uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ + uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ + uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ + uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ +} nrf_radio_request_normal_t; + +/**@brief Radio timeslot request parameters. */ +typedef struct +{ + uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ + union + { + nrf_radio_request_earliest_t earliest; /**< Parameters for requesting a radio timeslot as early as possible. */ + nrf_radio_request_normal_t normal; /**< Parameters for requesting a normal radio timeslot. */ + } params; /**< Parameter union. */ +} nrf_radio_request_t; + +/**@brief Return parameters of the radio timeslot signal callback. */ +typedef struct +{ + uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ + union + { + struct + { + nrf_radio_request_t * p_next; /**< The request parameters for the next radio timeslot. */ + } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ + struct + { + uint32_t length_us; /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ + } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ + } params; /**< Parameter union. */ +} nrf_radio_signal_callback_return_param_t; + +/**@brief The radio timeslot signal callback type. + * + * @note In case of invalid return parameters, the radio timeslot will automatically end + * immediately after returning from the signal callback and the + * @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent. + * @note The returned struct pointer must remain valid after the signal callback + * function returns. For instance, this means that it must not point to a stack variable. + * + * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE. + * + * @return Pointer to structure containing action requested by the application. + */ +typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type); + +/**@brief AES ECB parameter typedefs */ +typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH]; /**< Encryption key type. */ +typedef uint8_t soc_ecb_cleartext_t[SOC_ECB_CLEARTEXT_LENGTH]; /**< Cleartext data type. */ +typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH]; /**< Ciphertext data type. */ + +/**@brief AES ECB data structure */ +typedef struct +{ + soc_ecb_key_t key; /**< Encryption key. */ + soc_ecb_cleartext_t cleartext; /**< Cleartext data. */ + soc_ecb_ciphertext_t ciphertext; /**< Ciphertext data. */ +} nrf_ecb_hal_data_t; + +/**@brief AES ECB block. Used to provide multiple blocks in a single call + to @ref sd_ecb_blocks_encrypt.*/ +typedef struct +{ + soc_ecb_key_t const * p_key; /**< Pointer to the Encryption key. */ + soc_ecb_cleartext_t const * p_cleartext; /**< Pointer to the Cleartext data. */ + soc_ecb_ciphertext_t * p_ciphertext; /**< Pointer to the Ciphertext data. */ +} nrf_ecb_hal_data_block_t; + +/**@} */ + +/**@addtogroup NRF_SOC_FUNCTIONS Functions + * @{ */ + +/**@brief Initialize a mutex. + * + * @param[in] p_mutex Pointer to the mutex to initialize. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex)); + +/**@brief Attempt to acquire a mutex. + * + * @param[in] p_mutex Pointer to the mutex to acquire. + * + * @retval ::NRF_SUCCESS The mutex was successfully acquired. + * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired. + */ +SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex)); + +/**@brief Release a mutex. + * + * @param[in] p_mutex Pointer to the mutex to release. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex)); + +/**@brief Query the capacity of the application random pool. + * + * @param[out] p_pool_capacity The capacity of the pool. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY_GET, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity)); + +/**@brief Get number of random bytes available to the application. + * + * @param[out] p_bytes_available The number of bytes currently available in the pool. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available)); + +/**@brief Get random bytes from the application pool. + * + * @param[out] p_buff Pointer to unit8_t buffer for storing the bytes. + * @param[in] length Number of bytes to take from pool and place in p_buff. + * + * @retval ::NRF_SUCCESS The requested bytes were written to p_buff. + * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available. +*/ +SVCALL(SD_RAND_APPLICATION_VECTOR_GET, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length)); + +/**@brief Gets the reset reason register. + * + * @param[out] p_reset_reason Contents of the NRF_POWER->RESETREAS register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason)); + +/**@brief Clears the bits of the reset reason register. + * + * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk)); + +/**@brief Sets the power mode when in CPU sleep. + * + * @param[in] power_mode The power mode to use when in CPU sleep, see @ref NRF_POWER_MODES. @sa sd_app_evt_wait + * + * @retval ::NRF_SUCCESS The power mode was set. + * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown. + */ +SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(uint8_t power_mode)); + +/**@brief Puts the chip in System OFF mode. + * + * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN + */ +SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void)); + +/**@brief Enables or disables the power-fail comparator. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] pof_enable True if the power-fail comparator should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable)); + +/**@brief Enables or disables the USB power ready event. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_POWER_READY) when a USB 3.3 V supply is ready. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] usbpwrrdy_enable True if the power ready event should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_USBPWRRDY_ENABLE, uint32_t, sd_power_usbpwrrdy_enable(uint8_t usbpwrrdy_enable)); + +/**@brief Enables or disables the power USB-detected event. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_DETECTED) when a voltage supply is detected on VBUS. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] usbdetected_enable True if the power ready event should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_USBDETECTED_ENABLE, uint32_t, sd_power_usbdetected_enable(uint8_t usbdetected_enable)); + +/**@brief Enables or disables the power USB-removed event. + * + * Enabling this will give a SoftDevice event (NRF_EVT_POWER_USB_REMOVED) when a voltage supply is removed from VBUS. + * The event can be retrieved with sd_evt_get(); + * + * @param[in] usbremoved_enable True if the power ready event should be enabled, false if it should be disabled. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_USBREMOVED_ENABLE, uint32_t, sd_power_usbremoved_enable(uint8_t usbremoved_enable)); + +/**@brief Get USB supply status register content. + * + * @param[out] usbregstatus The content of USBREGSTATUS register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_USBREGSTATUS_GET, uint32_t, sd_power_usbregstatus_get(uint32_t * usbregstatus)); + +/**@brief Sets the power failure comparator threshold value. + * + * @note: Power failure comparator threshold setting. This setting applies both for normal voltage + * mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to + * VDDH only). + * + * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDS. + * + * @retval ::NRF_SUCCESS The power failure threshold was set. + * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown. + */ +SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(uint8_t threshold)); + +/**@brief Sets the power failure comparator threshold value for high voltage. + * + * @note: Power failure comparator threshold setting for high voltage mode (supply connected to + * VDDH only). This setting does not apply for normal voltage mode (supply connected to both + * VDD and VDDH). + * + * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDVDDHS. + * + * @retval ::NRF_SUCCESS The power failure threshold was set. + * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown. + */ +SVCALL(SD_POWER_POF_THRESHOLDVDDH_SET, uint32_t, sd_power_pof_thresholdvddh_set(uint8_t threshold)); + +/**@brief Writes the NRF_POWER->RAM[index].POWERSET register. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWERSET register to write to. + * @param[in] ram_powerset Contains the word to write to the NRF_POWER->RAM[index].POWERSET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_SET, uint32_t, sd_power_ram_power_set(uint8_t index, uint32_t ram_powerset)); + +/**@brief Writes the NRF_POWER->RAM[index].POWERCLR register. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWERCLR register to write to. + * @param[in] ram_powerclr Contains the word to write to the NRF_POWER->RAM[index].POWERCLR register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_CLR, uint32_t, sd_power_ram_power_clr(uint8_t index, uint32_t ram_powerclr)); + +/**@brief Get contents of NRF_POWER->RAM[index].POWER register, indicates power status of RAM[index] blocks. + * + * @param[in] index Contains the index in the NRF_POWER->RAM[index].POWER register to read from. + * @param[out] p_ram_power Content of NRF_POWER->RAM[index].POWER register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_RAM_POWER_GET, uint32_t, sd_power_ram_power_get(uint8_t index, uint32_t * p_ram_power)); + +/**@brief Set bits in the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[in] gpregret_msk Bits to be set in the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_id, uint32_t gpregret_msk)); + +/**@brief Clear bits in the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[in] gpregret_msk Bits to be clear in the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_id, uint32_t gpregret_msk)); + +/**@brief Get contents of the general purpose retention registers (NRF_POWER->GPREGRET*). + * + * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2. + * @param[out] p_gpregret Contents of the GPREGRET register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t *p_gpregret)); + +/**@brief Enable or disable the DC/DC regulator for the regulator stage 1 (REG1). + * + * @param[in] dcdc_mode The mode of the DCDC, see @ref NRF_POWER_DCDC_MODES. + * + * @retval ::NRF_SUCCESS + * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid. + */ +SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(uint8_t dcdc_mode)); + +/**@brief Enable or disable the DC/DC regulator for the regulator stage 0 (REG0). + * + * For more details on the REG0 stage, please see product specification. + * + * @param[in] dcdc_mode The mode of the DCDC0, see @ref NRF_POWER_DCDC_MODES. + * + * @retval ::NRF_SUCCESS + * @retval ::NRF_ERROR_INVALID_PARAM The dcdc_mode is invalid. + */ +SVCALL(SD_POWER_DCDC0_MODE_SET, uint32_t, sd_power_dcdc0_mode_set(uint8_t dcdc_mode)); + +/**@brief Request the high frequency crystal oscillator. + * + * Will start the high frequency crystal oscillator, the startup time of the crystal varies + * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started. + * + * @see sd_clock_hfclk_is_running + * @see sd_clock_hfclk_release + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void)); + +/**@brief Releases the high frequency crystal oscillator. + * + * Will stop the high frequency crystal oscillator, this happens immediately. + * + * @see sd_clock_hfclk_is_running + * @see sd_clock_hfclk_request + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void)); + +/**@brief Checks if the high frequency crystal oscillator is running. + * + * @see sd_clock_hfclk_request + * @see sd_clock_hfclk_release + * + * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running)); + +/**@brief Waits for an application event. + * + * An application event is either an application interrupt or a pended interrupt when the interrupt + * is disabled. + * + * When the application waits for an application event by calling this function, an interrupt that + * is enabled will be taken immediately on pending since this function will wait in thread mode, + * then the execution will return in the application's main thread. + * + * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M + * MCU's System Control Register (SCR), CMSIS_SCB. In that case, when a disabled interrupt gets + * pended, this function will return to the application's main thread. + * + * @note The application must ensure that the pended flag is cleared using ::sd_nvic_ClearPendingIRQ + * in order to sleep using this function. This is only necessary for disabled interrupts, as + * the interrupt handler will clear the pending flag automatically for enabled interrupts. + * + * @note If an application interrupt has happened since the last time sd_app_evt_wait was + * called this function will return immediately and not go to sleep. This is to avoid race + * conditions that can occur when a flag is updated in the interrupt handler and processed + * in the main loop. + * + * @post An application interrupt has happened or a interrupt pending flag is set. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void)); + +/**@brief Get PPI channel enable register contents. + * + * @param[out] p_channel_enable The contents of the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable)); + +/**@brief Set PPI channel enable register. + * + * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk)); + +/**@brief Clear PPI channel enable register. + * + * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk)); + +/**@brief Assign endpoints to a PPI channel. + * + * @param[in] channel_num Number of the PPI channel to assign. + * @param[in] evt_endpoint Event endpoint of the PPI channel. + * @param[in] task_endpoint Task endpoint of the PPI channel. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)); + +/**@brief Task to enable a channel group. + * + * @param[in] group_num Number of the channel group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num)); + +/**@brief Task to disable a channel group. + * + * @param[in] group_num Number of the PPI group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num)); + +/**@brief Assign PPI channels to a channel group. + * + * @param[in] group_num Number of the channel group. + * @param[in] channel_msk Mask of the channels to assign to the group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk)); + +/**@brief Gets the PPI channels of a channel group. + * + * @param[in] group_num Number of the channel group. + * @param[out] p_channel_msk Mask of the channels assigned to the group. + * + * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk)); + +/**@brief Configures the Radio Notification signal. + * + * @note + * - The notification signal latency depends on the interrupt priority settings of SWI used + * for notification signal. + * - To ensure that the radio notification signal behaves in a consistent way, the radio + * notifications must be configured when there is no protocol stack or other SoftDevice + * activity in progress. It is recommended that the radio notification signal is + * configured directly after the SoftDevice has been enabled. + * - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice + * will interrupt the application to do Radio Event preparation. + * - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have + * to shorten the connection events to have time for the Radio Notification signals. + * + * @param[in] type Type of notification signal, see @ref NRF_RADIO_NOTIFICATION_TYPES. + * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio + * notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is + * recommended (but not required) to be used with + * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE. + * + * @param[in] distance Distance between the notification signal and start of radio activity, see @ref NRF_RADIO_NOTIFICATION_DISTANCES. + * This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or + * @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. + * + * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid. + * @retval ::NRF_ERROR_INVALID_STATE A protocol stack or other SoftDevice is running. Stop all + * running activities and retry. + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(uint8_t type, uint8_t distance)); + +/**@brief Encrypts a block according to the specified parameters. + * + * 128-bit AES encryption. + * + * @note: + * - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while + * the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application + * main or low interrupt level. + * + * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input + * parameters and one output parameter). + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data)); + +/**@brief Encrypts multiple data blocks provided as an array of data block structures. + * + * @details: Performs 128-bit AES encryption on multiple data blocks + * + * @note: + * - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while + * the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application + * main or low interrupt level. + * + * @param[in] block_count Count of blocks in the p_data_blocks array. + * @param[in,out] p_data_blocks Pointer to the first entry in a contiguous array of + * @ref nrf_ecb_hal_data_block_t structures. + * + * @retval ::NRF_SUCCESS + */ +SVCALL(SD_ECB_BLOCKS_ENCRYPT, uint32_t, sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks)); + +/**@brief Gets any pending events generated by the SoC API. + * + * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned. + * + * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending. + * + * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter. + * @retval ::NRF_ERROR_NOT_FOUND No pending events. + */ +SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id)); + +/**@brief Get the temperature measured on the chip + * + * This function will block until the temperature measurement is done. + * It takes around 50 us from call to return. + * + * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees Celsius. + * + * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp + */ +SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp)); + +/**@brief Flash Write +* +* Commands to write a buffer to flash +* +* If the SoftDevice is enabled: +* This call initiates the flash access command, and its completion will be communicated to the +* application with exactly one of the following events: +* - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. +* - @ref NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. +* +* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the + * write has been completed +* +* @note +* - This call takes control over the radio and the CPU during flash erase and write to make sure that +* they will not interfere with the flash access. This means that all interrupts will be blocked +* for a predictable time (depending on the NVMC specification in the device's Product Specification +* and the command parameters). +* - The data in the p_src buffer should not be modified before the @ref NRF_EVT_FLASH_OPERATION_SUCCESS +* or the @ref NRF_EVT_FLASH_OPERATION_ERROR have been received if the SoftDevice is enabled. +* - This call will make the SoftDevice trigger a hardfault when the page is written, if it is +* protected. +* +* +* @param[in] p_dst Pointer to start of flash location to be written. +* @param[in] p_src Pointer to buffer with data to be written. +* @param[in] size Number of 32-bit words to write. Maximum size is the number of words in one +* flash page. See the device's Product Specification for details. +* +* @retval ::NRF_ERROR_INVALID_ADDR Tried to write to a non existing flash address, or p_dst or p_src was unaligned. +* @retval ::NRF_ERROR_BUSY The previous command has not yet completed. +* @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or higher than the maximum allowed size. +* @retval ::NRF_ERROR_FORBIDDEN Tried to write to an address outside the application flash area. +* @retval ::NRF_SUCCESS The command was accepted. +*/ +SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * p_dst, uint32_t const * p_src, uint32_t size)); + + +/**@brief Flash Erase page +* +* Commands to erase a flash page +* If the SoftDevice is enabled: +* This call initiates the flash access command, and its completion will be communicated to the +* application with exactly one of the following events: +* - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. +* - @ref NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. +* +* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the +* erase has been completed +* +* @note +* - This call takes control over the radio and the CPU during flash erase and write to make sure that +* they will not interfere with the flash access. This means that all interrupts will be blocked +* for a predictable time (depending on the NVMC specification in the device's Product Specification +* and the command parameters). +* - This call will make the SoftDevice trigger a hardfault when the page is erased, if it is +* protected. +* +* +* @param[in] page_number Page number of the page to erase +* +* @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. +* @retval ::NRF_ERROR_INVALID_ADDR Tried to erase to a non existing flash page. +* @retval ::NRF_ERROR_BUSY The previous command has not yet completed. +* @retval ::NRF_ERROR_FORBIDDEN Tried to erase a page outside the application flash area. +* @retval ::NRF_SUCCESS The command was accepted. +*/ +SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)); + + + +/**@brief Opens a session for radio timeslot requests. + * + * @note Only one session can be open at a time. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot + * starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed + * by the application. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0 + * interrupt occurs. + * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO + * interrupt occurs. + * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This + * implies that none of the sd_* API calls can be used from p_radio_signal_callback(). + * + * @param[in] p_radio_signal_callback The signal callback. + * + * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer. + * @retval ::NRF_ERROR_BUSY If session cannot be opened. + * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); + +/**@brief Closes a session for radio timeslot requests. + * + * @note Any current radio timeslot will be finished before the session is closed. + * @note If a radio timeslot is scheduled when the session is closed, it will be canceled. + * @note The application cannot consider the session closed until the @ref NRF_EVT_RADIO_SESSION_CLOSED + * event is received. + * + * @retval ::NRF_ERROR_FORBIDDEN If session not opened. + * @retval ::NRF_ERROR_BUSY If session is currently being closed. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); + +/**@brief Requests a radio timeslot. + * + * @note The request type is determined by p_request->request_type, and can be one of @ref NRF_RADIO_REQ_TYPE_EARLIEST + * and @ref NRF_RADIO_REQ_TYPE_NORMAL. The first request in a session must always be of type @ref NRF_RADIO_REQ_TYPE_EARLIEST. + * @note For a normal request (@ref NRF_RADIO_REQ_TYPE_NORMAL), the start time of a radio timeslot is specified by + * p_request->distance_us and is given relative to the start of the previous timeslot. + * @note A too small p_request->distance_us will lead to a @ref NRF_EVT_RADIO_BLOCKED event. + * @note Timeslots scheduled too close will lead to a @ref NRF_EVT_RADIO_BLOCKED event. + * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths. + * @note If an opportunity for the first radio timeslot is not found before 100 ms after the call to this + * function, it is not scheduled, and instead a @ref NRF_EVT_RADIO_BLOCKED event is sent. + * The application may then try to schedule the first radio timeslot again. + * @note Successful requests will result in nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START). + * Unsuccessful requests will result in a @ref NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS. + * @note The jitter in the start time of the radio timeslots is +/- @ref NRF_RADIO_START_JITTER_US us. + * @note The nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the + * specified radio timeslot start, but this does not affect the actual start time of the timeslot. + * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency + * (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is + * guaranteed to be clocked from the external crystal. + * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral + * during the radio timeslot. + * + * @param[in] p_request Pointer to the request parameters. + * + * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE. + * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid. + * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid. + * @retval ::NRF_SUCCESS Otherwise. + */ + SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t const * p_request)); + +/**@brief Write register protected by the SoftDevice + * + * This function writes to a register that is write-protected by the SoftDevice. Please refer to your + * SoftDevice Specification for more details about which registers that are protected by SoftDevice. + * This function can write to the following protected peripheral: + * - ACL + * + * @note Protected registers may be read directly. + * @note Register that are write-once will return @ref NRF_SUCCESS on second set, even the value in + * the register has not changed. See the Product Specification for more details about register + * properties. + * + * @param[in] p_register Pointer to register to be written. + * @param[in] value Value to be written to the register. + * + * @retval ::NRF_ERROR_INVALID_ADDR This function can not write to the reguested register. + * @retval ::NRF_SUCCESS Value successfully written to register. + * + */ +SVCALL(SD_PROTECTED_REGISTER_WRITE, uint32_t, sd_protected_register_write(volatile uint32_t * p_register, uint32_t value)); + +/**@} */ + +#ifdef __cplusplus +} +#endif +#endif // NRF_SOC_H__ + +/**@} */ diff --git a/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_svc.h b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_svc.h new file mode 100755 index 0000000..292c692 --- /dev/null +++ b/arduino/cores/nRF5/nordic/softdevice/s140_nrf52_6.1.1_API/include/nrf_svc.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_SVC__ +#define NRF_SVC__ + +#include "stdint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SVCALL_AS_NORMAL_FUNCTION +#define SVCALL(number, return_type, signature) return_type signature +#else + +#ifndef SVCALL +#if defined (__CC_ARM) +#define SVCALL(number, return_type, signature) return_type __svc(number) signature +#elif defined (__GNUC__) +#ifdef __cplusplus +#define GCC_CAST_CPP (uint16_t) +#else +#define GCC_CAST_CPP +#endif +#define SVCALL(number, return_type, signature) \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ + __attribute__((naked)) \ + __attribute__((unused)) \ + static return_type signature \ + { \ + __asm( \ + "svc %0\n" \ + "bx r14" : : "I" (GCC_CAST_CPP number) : "r0" \ + ); \ + } \ + _Pragma("GCC diagnostic pop") + +#elif defined (__ICCARM__) +#define PRAGMA(x) _Pragma(#x) +#define SVCALL(number, return_type, signature) \ +PRAGMA(swi_number = (number)) \ + __swi return_type signature; +#else +#define SVCALL(number, return_type, signature) return_type signature +#endif +#endif // SVCALL + +#endif // SVCALL_AS_NORMAL_FUNCTION + +#ifdef __cplusplus +} +#endif +#endif // NRF_SVC__ |