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@ -39,7 +39,7 @@ ADCConversionGroup ADC::m_group_config = {
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.end_cb = ADC::conversionCallback,
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.error_cb = nullptr,
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.cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(13), /* TIM6_TRGO */
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.cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x
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.cfgr2 = 0,//ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x
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#if defined(TARGET_PLATFORM_H7)
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.ccr = 0,
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.pcsel = 0,
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@ -73,7 +73,7 @@ ADCConversionGroup ADC::m_group_config2 = {
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.end_cb = readAltCallback,
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.error_cb = nullptr,
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.cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(13), /* TIM6_TRGO */
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.cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x
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.cfgr2 = 0,//ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x
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#if defined(TARGET_PLATFORM_H7)
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.ccr = 0,
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.pcsel = 0,
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@ -182,13 +182,29 @@ void ADC::setRate(SClock::Rate rate)
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adcStart(m_driver, &m_config);
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#elif defined(TARGET_PLATFORM_L4)
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std::array<std::array<uint32_t, 3>, 6> m_rate_presets = {{
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// PLLSAI2 sources MSI of 4MHz, divided by PLLM of /1 = 4MHz.
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// 4MHz is then multiplied by PLLSAI2N (x8 to x86), with result
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// between 64 and 344 MHz.
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//
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// SAI2N MUST BE AT LEAST 16 TO MAKE 64MHz MINIMUM.
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//
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// That is then divided by PLLSAI2R:
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// R of 0 = /2; 1 = /4, 2 = /6, 3 = /8.
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// PLLSAI2 then feeds into the ADC, which has a prescaler of /10.
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// Finally, the ADC's SMP value produces the desired sample rate.
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//
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// 4MHz * N / R / 10 / SMP = sample rate.
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//
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// With oversampling, must create faster clock
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// (x2 oversampling requires x2 sample rate clock).
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//
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// Rate PLLSAI2N R SMPR
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{/* 8k */ 8, 1, ADC_SMPR_SMP_12P5},
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{/* 16k */ 16, 1, ADC_SMPR_SMP_12P5},
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{/* 20k */ 20, 1, ADC_SMPR_SMP_12P5},
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{/* 32k */ 32, 1, ADC_SMPR_SMP_12P5},
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{/* 48k */ 24, 0, ADC_SMPR_SMP_12P5},
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{/* 96k */ 73, 1, ADC_SMPR_SMP_6P5} // Technically 96.05263kS/s
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{/* 8k */ 16, 1, ADC_SMPR_SMP_12P5}, // R3=32k (min), R1=64k
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{/* 16k */ 16, 0, ADC_SMPR_SMP_12P5},
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{/* 20k */ 20, 0, ADC_SMPR_SMP_12P5},
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{/* 32k */ 32, 0, ADC_SMPR_SMP_12P5},
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{/* 48k */ 48, 0, ADC_SMPR_SMP_12P5},
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{/* 96k */ 73, 0, ADC_SMPR_SMP_6P5} // Technically 96.05263kS/s
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}};
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auto& preset = m_rate_presets[static_cast<int>(rate)];
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@ -205,9 +221,9 @@ void ADC::setRate(SClock::Rate rate)
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m_group_config.smpr[0] = ADC_SMPR1_SMP_AN5(smpr);
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// Set 2x oversampling
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m_group_config.cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_0 | ADC_CFGR2_OVSS_1;
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m_group_config2.cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_0 | ADC_CFGR2_OVSS_1;
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// 8x oversample
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m_group_config.cfgr2 = ADC_CFGR2_ROVSE | (2 << ADC_CFGR2_OVSR_Pos) | (3 << ADC_CFGR2_OVSS_Pos);
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m_group_config2.cfgr2 = ADC_CFGR2_ROVSE | (2 << ADC_CFGR2_OVSR_Pos) | (3 << ADC_CFGR2_OVSS_Pos);
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#endif
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}
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