diff options
| author | Clyne Sullivan <clyne@bitgloo.com> | 2021-01-23 09:59:11 -0500 |
|---|---|---|
| committer | Clyne Sullivan <clyne@bitgloo.com> | 2021-01-23 09:59:11 -0500 |
| commit | 564e20975b670d4bee1de525e9a25c33730fd7c2 (patch) | |
| tree | 52a61fc5cc67334e8fe257ddc375d78f3e3dfc77 /ChibiOS_20.3.2 | |
| parent | 74abc8d4b3ebabfac286cccc27ced565330eac4f (diff) | |
untested port cleanup; add sclock; up cpu to 480M
Diffstat (limited to 'ChibiOS_20.3.2')
| -rw-r--r-- | ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h index b1b9a42..af36372 100644 --- a/ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -1821,8 +1821,8 @@ /**
* @brief PLL1 DIVP field.
*/
-#if ((STM32_PLL1_DIVP_VALUE >= 2) && (STM32_PLL1_DIVP_VALUE <= 128) && \
- ((STM32_PLL1_DIVP_VALUE & 1U) == 0U)) || \
+#if ((STM32_PLL1_DIVP_VALUE >= 1) && (STM32_PLL1_DIVP_VALUE <= 128) && \
+ ((STM32_PLL1_DIVP_VALUE & 1U) == 0U || STM32_PLL1_DIVP_VALUE == 1)) || \
defined(__DOXYGEN__)
#define STM32_PLL1_DIVP ((STM32_PLL1_DIVP_VALUE - 1U) << 9U)
#else
|