upload initial port

3 files changed, 279 insertions, 160 deletions

diff --git a/cfg/chconf.h b/cfg/chconf.h
index faa8600..628d7e8 100644
--- a/cfg/chconf.h
+++ b/cfg/chconf.h
@@ -167,7 +167,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(CH_CFG_USE_REGISTRY)

-#define CH_CFG_USE_REGISTRY                 FALSE

+#define CH_CFG_USE_REGISTRY                 TRUE

 #endif

 

 /**

@@ -178,7 +178,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(CH_CFG_USE_WAITEXIT)

-#define CH_CFG_USE_WAITEXIT                 FALSE

+#define CH_CFG_USE_WAITEXIT                 TRUE

 #endif

 

 /**

@@ -235,7 +235,7 @@
  * @note    Requires @p CH_CFG_USE_MUTEXES.

  */

 #if !defined(CH_CFG_USE_CONDVARS)

-#define CH_CFG_USE_CONDVARS                 FALSE

+#define CH_CFG_USE_CONDVARS                 TRUE

 #endif

 

 /**

@@ -247,7 +247,7 @@
  * @note    Requires @p CH_CFG_USE_CONDVARS.

  */

 #if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)

-#define CH_CFG_USE_CONDVARS_TIMEOUT         FALSE

+#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE

 #endif

 

 /**

@@ -269,7 +269,7 @@
  * @note    Requires @p CH_CFG_USE_EVENTS.

  */

 #if !defined(CH_CFG_USE_EVENTS_TIMEOUT)

-#define CH_CFG_USE_EVENTS_TIMEOUT           FALSE

+#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE

 #endif

 

 /**

@@ -280,7 +280,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(CH_CFG_USE_MESSAGES)

-#define CH_CFG_USE_MESSAGES                 FALSE

+#define CH_CFG_USE_MESSAGES                 TRUE

 #endif

 

 /**

@@ -306,7 +306,7 @@
  * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.

  */

 #if !defined(CH_CFG_USE_DYNAMIC)

-#define CH_CFG_USE_DYNAMIC                  FALSE

+#define CH_CFG_USE_DYNAMIC                  TRUE

 #endif

 

 /** @} */

@@ -353,7 +353,7 @@
  * @note    Requires @p CH_CFG_USE_MEMCORE.

  */

 #if !defined(CH_CFG_MEMCORE_SIZE)

-#define CH_CFG_MEMCORE_SIZE                 (3 * 1024)

+#define CH_CFG_MEMCORE_SIZE                 0

 #endif

 

 /**

@@ -389,7 +389,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(CH_CFG_USE_OBJ_FIFOS)

-#define CH_CFG_USE_OBJ_FIFOS                FALSE

+#define CH_CFG_USE_OBJ_FIFOS                TRUE

 #endif

 

 /**

@@ -400,7 +400,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(CH_CFG_USE_PIPES)

-#define CH_CFG_USE_PIPES                    FALSE

+#define CH_CFG_USE_PIPES                    TRUE

 #endif

 

 /**

@@ -411,7 +411,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(CH_CFG_USE_OBJ_CACHES)

-#define CH_CFG_USE_OBJ_CACHES               FALSE

+#define CH_CFG_USE_OBJ_CACHES               TRUE

 #endif

 

 /**

@@ -422,7 +422,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(CH_CFG_USE_DELEGATES)

-#define CH_CFG_USE_DELEGATES                FALSE

+#define CH_CFG_USE_DELEGATES                TRUE

 #endif

 

 /**

@@ -433,7 +433,7 @@
  * @note    The default is @p TRUE.

  */

 #if !defined(CH_CFG_USE_JOBS)

-#define CH_CFG_USE_JOBS                     FALSE

+#define CH_CFG_USE_JOBS                     TRUE

 #endif

 

 /** @} */

@@ -453,7 +453,7 @@
  * @note    The default is @p FALSE.

  */

 #if !defined(CH_CFG_USE_FACTORY)

-#define CH_CFG_USE_FACTORY                  FALSE

+#define CH_CFG_USE_FACTORY                  TRUE

 #endif

 

 /**

@@ -469,42 +469,42 @@
  * @brief   Enables the registry of generic objects.

  */

 #if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)

-#define CH_CFG_FACTORY_OBJECTS_REGISTRY     FALSE

+#define CH_CFG_FACTORY_OBJECTS_REGISTRY     TRUE

 #endif

 

 /**

  * @brief   Enables factory for generic buffers.

  */

 #if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)

-#define CH_CFG_FACTORY_GENERIC_BUFFERS      FALSE

+#define CH_CFG_FACTORY_GENERIC_BUFFERS      TRUE

 #endif

 

 /**

  * @brief   Enables factory for semaphores.

  */

 #if !defined(CH_CFG_FACTORY_SEMAPHORES)

-#define CH_CFG_FACTORY_SEMAPHORES           FALSE

+#define CH_CFG_FACTORY_SEMAPHORES           TRUE

 #endif

 

 /**

  * @brief   Enables factory for mailboxes.

  */

 #if !defined(CH_CFG_FACTORY_MAILBOXES)

-#define CH_CFG_FACTORY_MAILBOXES            FALSE

+#define CH_CFG_FACTORY_MAILBOXES            TRUE

 #endif

 

 /**

  * @brief   Enables factory for objects FIFOs.

  */

 #if !defined(CH_CFG_FACTORY_OBJ_FIFOS)

-#define CH_CFG_FACTORY_OBJ_FIFOS            FALSE

+#define CH_CFG_FACTORY_OBJ_FIFOS            TRUE

 #endif

 

 /**

  * @brief   Enables factory for Pipes.

  */

 #if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)

-#define CH_CFG_FACTORY_PIPES                FALSE

+#define CH_CFG_FACTORY_PIPES                TRUE

 #endif

 

 /** @} */

@@ -533,7 +533,7 @@
  * @note    The default is @p FALSE.

  */

 #if !defined(CH_DBG_SYSTEM_STATE_CHECK)

-#define CH_DBG_SYSTEM_STATE_CHECK           FALSE

+#define CH_DBG_SYSTEM_STATE_CHECK           TRUE

 #endif

 

 /**

@@ -566,7 +566,7 @@
  * @note    The default is @p CH_DBG_TRACE_MASK_DISABLED.

  */

 #if !defined(CH_DBG_TRACE_MASK)

-#define CH_DBG_TRACE_MASK                   CH_DBG_TRACE_MASK_DISABLED

+#define CH_DBG_TRACE_MASK                   CH_DBG_TRACE_MASK_NONE

 #endif

 

 /**

@@ -751,9 +751,6 @@
 /* Port-specific settings (override port settings defaulted in chcore.h).    */

 /*===========================================================================*/

 

-// Enable syscall support

-#define PORT_USE_SYSCALL                    FALSE

-

 #endif  /* CHCONF_H */

 

 /** @} */

diff --git a/cfg/halconf.h b/cfg/halconf.h
index 24c6fde..1c77c25 100644
--- a/cfg/halconf.h
+++ b/cfg/halconf.h
@@ -230,7 +230,7 @@
  * @note    Disabling this option saves both code and data space.

  */

 #if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)

-#define ADC_USE_WAIT                        FALSE

+#define ADC_USE_WAIT                        TRUE

 #endif

 

 /**

@@ -238,7 +238,7 @@
  * @note    Disabling this option saves both code and data space.

  */

 #if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

-#define ADC_USE_MUTUAL_EXCLUSION            FALSE

+#define ADC_USE_MUTUAL_EXCLUSION            TRUE

 #endif

 

 /*===========================================================================*/

@@ -290,7 +290,7 @@
  * @note    Disabling this option saves both code and data space.

  */

 #if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)

-#define DAC_USE_WAIT                        FALSE

+#define DAC_USE_WAIT                        TRUE

 #endif

 

 /**

@@ -298,7 +298,7 @@
  * @note    Disabling this option saves both code and data space.

  */

 #if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

-#define DAC_USE_MUTUAL_EXCLUSION            FALSE

+#define DAC_USE_MUTUAL_EXCLUSION            TRUE

 #endif

 

 /*===========================================================================*/

diff --git a/cfg/mcuconf.h b/cfg/mcuconf.h
index caad802..98da3a7 100644
--- a/cfg/mcuconf.h
+++ b/cfg/mcuconf.h
@@ -14,8 +14,11 @@
     limitations under the License.

 */

 

+#ifndef MCUCONF_H

+#define MCUCONF_H

+

 /*

- * STM32L4xx drivers configuration.

+ * STM32H7xx drivers configuration.

  * The following settings override the default settings present in

  * the various device driver implementation headers.

  * Note that the settings for each driver only have effect if the whole

@@ -28,70 +31,138 @@
  * 0...3        Lowest...Highest.

  */

 

-#ifndef MCUCONF_H

-#define MCUCONF_H

-

-#define STM32L4xx_MCUCONF

-#define STM32L476_MCUCONF

-//#define STM32L432_MCUCONF

+#define STM32H7xx_MCUCONF

+#define STM32H725_MCUCONF

+//#define STM32H743_MCUCONF

 

 /*

- * HAL driver system settings.

+ * General settings.

  */

 #define STM32_NO_INIT                       FALSE

-#define STM32_VOS                           STM32_VOS_RANGE1

-#define STM32_PVD_ENABLE                    FALSE

-#define STM32_PLS                           STM32_PLS_LEV0

-#define STM32_HSI16_ENABLED                 FALSE

+#define STM32_TARGET_CORE                   1

+

+/*

+ * Memory attributes settings.

+ */

+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6

+#define STM32_NOCACHE_SRAM1_SRAM2           FALSE

+#define STM32_NOCACHE_SRAM3                 FALSE // keep

+#define STM32_NOCACHE_SRAM4                 TRUE

+

+/*

+ * PWR system settings.

+ * Reading STM32 Reference Manual is required, settings in PWR_CR3 are

+ * very critical.

+ * Register constants are taken from the ST header.

+ */

+#define STM32_VOS                           STM32_VOS_SCALE1

+#define STM32_PWR_CR1                       (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)

+#define STM32_PWR_CR2                       (PWR_CR2_BREN)

+#define STM32_PWR_CR3                       (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)

+#define STM32_PWR_CPUCR                     0

+

+/*

+ * Clock tree static settings.

+ * Reading STM32 Reference Manual is required.

+ */

+#define STM32_HSI_ENABLED                   TRUE

 #define STM32_LSI_ENABLED                   TRUE

+#define STM32_CSI_ENABLED                   FALSE

+#define STM32_HSI48_ENABLED                 TRUE

 #define STM32_HSE_ENABLED                   FALSE

 #define STM32_LSE_ENABLED                   FALSE

-#define STM32_MSIPLL_ENABLED                FALSE

-#define STM32_MSIRANGE                      STM32_MSIRANGE_8M

-#define STM32_MSISRANGE                     STM32_MSISRANGE_4M

-#define STM32_SW                            STM32_SW_PLL

-#define STM32_PLLSRC                        STM32_PLLSRC_MSI

-#define STM32_PLLM_VALUE                    2

-#define STM32_PLLN_VALUE                    72

-#define STM32_PLLP_VALUE                    7

-#define STM32_PLLQ_VALUE                    6

-#define STM32_PLLR_VALUE                    4

-#define STM32_HPRE                          STM32_HPRE_DIV1

-#define STM32_PPRE1                         STM32_PPRE1_DIV1

-#define STM32_PPRE2                         STM32_PPRE2_DIV1

-#define STM32_STOPWUCK                      STM32_STOPWUCK_MSI

-#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK

-#define STM32_MCOPRE                        STM32_MCOPRE_DIV1

-#define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK

-#define STM32_PLLSAI1N_VALUE                24

-#define STM32_PLLSAI1P_VALUE                7

-#define STM32_PLLSAI1Q_VALUE                2

-#define STM32_PLLSAI1R_VALUE                4

-#define STM32_PLLSAI2N_VALUE                24

-#define STM32_PLLSAI2P_VALUE                7

-#define STM32_PLLSAI2R_VALUE                8

+#define STM32_HSIDIV                        STM32_HSIDIV_DIV8 // 8

 

 /*

- * Peripherals clock sources.

+ * PLLs static settings.

+ * Reading STM32 Reference Manual is required.

  */

-#define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK

-#define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK

-#define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK

-#define STM32_UART4SEL                      STM32_UART4SEL_SYSCLK

-#define STM32_UART5SEL                      STM32_UART5SEL_SYSCLK

-#define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK

-#define STM32_I2C1SEL                       STM32_I2C1SEL_SYSCLK

-#define STM32_I2C2SEL                       STM32_I2C2SEL_SYSCLK

-#define STM32_I2C3SEL                       STM32_I2C3SEL_SYSCLK

+#define STM32_PLLSRC                        STM32_PLLSRC_HSI_CK

+#define STM32_PLLCFGR_MASK                  ~0

+#define STM32_PLL1_ENABLED                  TRUE

+#define STM32_PLL1_P_ENABLED                TRUE

+#define STM32_PLL1_Q_ENABLED                FALSE

+#define STM32_PLL1_R_ENABLED                FALSE

+#define STM32_PLL1_DIVM_VALUE               4   // 2

+#define STM32_PLL1_DIVN_VALUE               384 // 2(384)

+#define STM32_PLL1_FRACN_VALUE              0

+#define STM32_PLL1_DIVP_VALUE               2   // 384

+#define STM32_PLL1_DIVQ_VALUE               16

+#define STM32_PLL1_DIVR_VALUE               8

+#define STM32_PLL2_ENABLED                  TRUE

+#define STM32_PLL2_P_ENABLED                TRUE

+#define STM32_PLL2_Q_ENABLED                FALSE

+#define STM32_PLL2_R_ENABLED                FALSE

+#define STM32_PLL2_DIVM_VALUE               4

+#define STM32_PLL2_DIVN_VALUE               384

+#define STM32_PLL2_FRACN_VALUE              0

+#define STM32_PLL2_DIVP_VALUE               32

+#define STM32_PLL2_DIVQ_VALUE               8

+#define STM32_PLL2_DIVR_VALUE               8

+#define STM32_PLL3_ENABLED                  FALSE

+#define STM32_PLL3_P_ENABLED                FALSE

+#define STM32_PLL3_Q_ENABLED                FALSE

+#define STM32_PLL3_R_ENABLED                FALSE

+#define STM32_PLL3_DIVM_VALUE               4

+#define STM32_PLL3_DIVN_VALUE               400

+#define STM32_PLL3_FRACN_VALUE              0

+#define STM32_PLL3_DIVP_VALUE               8

+#define STM32_PLL3_DIVQ_VALUE               8

+#define STM32_PLL3_DIVR_VALUE               8

+

+/*

+ * Core clocks dynamic settings (can be changed at runtime).

+ * Reading STM32 Reference Manual is required.

+ */

+#define STM32_SW                            STM32_SW_PLL1_P_CK

+#define STM32_RTCSEL                        STM32_RTCSEL_LSI_CK

+#define STM32_D1CPRE                        STM32_D1CPRE_DIV1

+#define STM32_D1HPRE                        STM32_D1HPRE_DIV2

+#define STM32_D1PPRE3                       STM32_D1PPRE3_DIV2

+#define STM32_D2PPRE1                       STM32_D2PPRE1_DIV2 // 192

+#define STM32_D2PPRE2                       STM32_D2PPRE2_DIV2

+#define STM32_D3PPRE4                       STM32_D3PPRE4_DIV2

+

+/*

+ * Peripherals clocks static settings.

+ * Reading STM32 Reference Manual is required.

+ */

+#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI_CK

+#define STM32_MCO1PRE_VALUE                 4

+#define STM32_MCO2SEL                       STM32_MCO2SEL_SYS_CK

+#define STM32_MCO2PRE_VALUE                 4

+#define STM32_TIMPRE_ENABLE                 TRUE

+#define STM32_HRTIMSEL                      0

+#define STM32_STOPKERWUCK                   0

+#define STM32_STOPWUCK                      0

+#define STM32_RTCPRE_VALUE                  8

+#define STM32_CKPERSEL                      STM32_CKPERSEL_HSI_CK

+#define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL1_Q_CK

+//#define STM32_OCTOSPISEL                    STM32_OCTOSPISEL_HCLK

+//#define STM32_FMCSEL                        STM32_OCTOSPISEL_HCLK

+#define STM32_SWPSEL                        STM32_SWPSEL_PCLK1

+#define STM32_FDCANSEL                      STM32_FDCANSEL_HSE_CK

+#define STM32_DFSDM1SEL                     STM32_DFSDM1SEL_PCLK2

+#define STM32_SPDIFSEL                      STM32_SPDIFSEL_PLL1_Q_CK

+#define STM32_SPI45SEL                      STM32_SPI45SEL_PCLK2

+#define STM32_SPI123SEL                     STM32_SPI123SEL_PLL1_Q_CK

+//#define STM32_SAI23SEL                      STM32_SAI23SEL_PLL1_Q_CK

+#define STM32_SAI1SEL                       STM32_SAI1SEL_PLL1_Q_CK

 #define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1

-#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK1

-#define STM32_SAI1SEL                       STM32_SAI1SEL_OFF

-#define STM32_SAI2SEL                       STM32_SAI2SEL_OFF

-#define STM32_CLK48SEL                      STM32_CLK48SEL_PLLSAI1

-#define STM32_ADCSEL                        STM32_ADCSEL_PLLSAI2

-#define STM32_SWPMI1SEL                     STM32_SWPMI1SEL_PCLK1

-#define STM32_DFSDMSEL                      STM32_DFSDMSEL_PCLK2

-#define STM32_RTCSEL                        STM32_RTCSEL_LSI

+#define STM32_CECSEL                        STM32_CECSEL_LSE_CK

+#define STM32_USBSEL                        STM32_USBSEL_HSI48_CK

+#define STM32_I2C1235SEL                    STM32_I2C1235SEL_PCLK1

+#define STM32_RNGSEL                        STM32_RNGSEL_HSI48_CK

+#define STM32_USART16910SEL                 STM32_USART16910SEL_PCLK2

+#define STM32_USART234578SEL                STM32_USART234578SEL_PCLK1

+#define STM32_SPI6SEL                       STM32_SPI6SEL_PCLK4

+#define STM32_SAI4BSEL                      STM32_SAI4BSEL_PLL1_Q_CK

+#define STM32_SAI4ASEL                      STM32_SAI4ASEL_PLL1_Q_CK

+#define STM32_ADCSEL                        STM32_ADCSEL_PLL2_P_CK

+#define STM32_LPTIM345SEL                   STM32_LPTIM345SEL_PCLK4

+#define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK4

+#define STM32_I2C4SEL                       STM32_I2C4SEL_PCLK4

+#define STM32_LPUART1SEL                    STM32_LPUART1SEL_PCLK4

 

 /*

  * IRQ system settings.

@@ -103,15 +174,23 @@
 #define STM32_IRQ_EXTI4_PRIORITY            6

 #define STM32_IRQ_EXTI5_9_PRIORITY          6

 #define STM32_IRQ_EXTI10_15_PRIORITY        6

-#define STM32_IRQ_EXTI1635_38_PRIORITY      6

+#define STM32_IRQ_EXTI16_PRIORITY           6

+#define STM32_IRQ_EXTI17_PRIORITY           6

 #define STM32_IRQ_EXTI18_PRIORITY           6

 #define STM32_IRQ_EXTI19_PRIORITY           6

-#define STM32_IRQ_EXTI20_PRIORITY           6

-#define STM32_IRQ_EXTI21_22_PRIORITY        15

+#define STM32_IRQ_EXTI20_21_PRIORITY        6

+

+#define STM32_IRQ_FDCAN1_PRIORITY           10

+#define STM32_IRQ_FDCAN2_PRIORITY           10

 

-#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY   7

-#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY    7

-#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7

+#define STM32_IRQ_MDMA_PRIORITY             9

+

+#define STM32_IRQ_QUADSPI1_PRIORITY         10

+

+#define STM32_IRQ_SDMMC1_PRIORITY           9

+#define STM32_IRQ_SDMMC2_PRIORITY           9

+

+#define STM32_IRQ_TIM1_UP_PRIORITY          7

 #define STM32_IRQ_TIM1_CC_PRIORITY          7

 #define STM32_IRQ_TIM2_PRIORITY             7

 #define STM32_IRQ_TIM3_PRIORITY             7

@@ -119,14 +198,22 @@
 #define STM32_IRQ_TIM5_PRIORITY             7

 #define STM32_IRQ_TIM6_PRIORITY             7

 #define STM32_IRQ_TIM7_PRIORITY             7

-#define STM32_IRQ_TIM8_UP_PRIORITY          7

+#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY   7

+#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY    7

+#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7

 #define STM32_IRQ_TIM8_CC_PRIORITY          7

+#define STM32_IRQ_TIM15_PRIORITY            7

+#define STM32_IRQ_TIM16_PRIORITY            7

+#define STM32_IRQ_TIM17_PRIORITY            7

 

 #define STM32_IRQ_USART1_PRIORITY           12

 #define STM32_IRQ_USART2_PRIORITY           12

 #define STM32_IRQ_USART3_PRIORITY           12

 #define STM32_IRQ_UART4_PRIORITY            12

 #define STM32_IRQ_UART5_PRIORITY            12

+#define STM32_IRQ_USART6_PRIORITY           12

+#define STM32_IRQ_UART7_PRIORITY            12

+#define STM32_IRQ_UART8_PRIORITY            12

 #define STM32_IRQ_LPUART1_PRIORITY          12

 

 /*

@@ -134,43 +221,36 @@
  */

 #define STM32_ADC_DUAL_MODE                 FALSE

 #define STM32_ADC_COMPACT_SAMPLES           FALSE

-#define STM32_ADC_USE_ADC1                  TRUE

-#define STM32_ADC_USE_ADC2                  FALSE

-#define STM32_ADC_USE_ADC3                  FALSE 

-#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

-#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(1, 2)

-#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(1, 3)

-#define STM32_ADC_ADC1_DMA_PRIORITY         2

-#define STM32_ADC_ADC2_DMA_PRIORITY         2

+#define STM32_ADC_USE_ADC12                 FALSE

+#define STM32_ADC_USE_ADC3                  TRUE

+#define STM32_ADC_ADC12_DMA_STREAM          STM32_DMA_STREAM_ID_ANY

+#define STM32_ADC_ADC3_BDMA_STREAM          STM32_BDMA_STREAM_ID_ANY

+#define STM32_ADC_ADC12_DMA_PRIORITY        2

 #define STM32_ADC_ADC3_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

 #define STM32_ADC_ADC3_IRQ_PRIORITY         5

-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     5

-#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     5

-#define STM32_ADC_ADC123_CLOCK_MODE         ADC_CCR_CKMODE_ADCCK

-#define STM32_ADC_ADC123_PRESC              ADC_CCR_PRESC_DIV10

-

-//#define ADC123_PRESC_VALUE 1

+#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV4

+#define STM32_ADC_ADC3_CLOCK_MODE           ADC_CCR_CKMODE_ADCCK

+#define STM32_ADC_ADC3_PRESC                (5 << ADC_CCR_PRESC_Pos) // div10

 

 /*

  * CAN driver system settings.

  */

-#define STM32_CAN_USE_CAN1                  FALSE

-#define STM32_CAN_CAN1_IRQ_PRIORITY         11

+#define STM32_CAN_USE_FDCAN1                FALSE

+#define STM32_CAN_USE_FDCAN2                FALSE

 

 /*

  * DAC driver system settings.

  */

 #define STM32_DAC_DUAL_MODE                 FALSE

 #define STM32_DAC_USE_DAC1_CH1              TRUE

-#define STM32_DAC_USE_DAC1_CH2              TRUE

+#define STM32_DAC_USE_DAC1_CH2              FALSE

 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10

 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

-#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(2, 4)

-#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 4)

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

 

 /*

  * GPT driver system settings.

@@ -181,8 +261,11 @@
 #define STM32_GPT_USE_TIM4                  FALSE

 #define STM32_GPT_USE_TIM5                  FALSE

 #define STM32_GPT_USE_TIM6                  TRUE

-#define STM32_GPT_USE_TIM7                  TRUE

+#define STM32_GPT_USE_TIM7                  FALSE

 #define STM32_GPT_USE_TIM8                  FALSE

+#define STM32_GPT_USE_TIM12                 FALSE

+#define STM32_GPT_USE_TIM13                 FALSE

+#define STM32_GPT_USE_TIM14                 FALSE

 #define STM32_GPT_USE_TIM15                 FALSE

 #define STM32_GPT_USE_TIM16                 FALSE

 #define STM32_GPT_USE_TIM17                 FALSE

@@ -193,19 +276,24 @@
 #define STM32_I2C_USE_I2C1                  FALSE

 #define STM32_I2C_USE_I2C2                  FALSE

 #define STM32_I2C_USE_I2C3                  FALSE

+#define STM32_I2C_USE_I2C4                  FALSE

 #define STM32_I2C_BUSY_TIMEOUT              50

-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)

-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

-#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

-#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C4_RX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

+#define STM32_I2C_I2C4_TX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

 #define STM32_I2C_I2C1_IRQ_PRIORITY         5

 #define STM32_I2C_I2C2_IRQ_PRIORITY         5

 #define STM32_I2C_I2C3_IRQ_PRIORITY         5

+#define STM32_I2C_I2C4_IRQ_PRIORITY         5

 #define STM32_I2C_I2C1_DMA_PRIORITY         3

 #define STM32_I2C_I2C2_DMA_PRIORITY         3

 #define STM32_I2C_I2C3_DMA_PRIORITY         3

+#define STM32_I2C_I2C4_DMA_PRIORITY         3

 #define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

 

 /*

@@ -217,11 +305,25 @@
 #define STM32_ICU_USE_TIM4                  FALSE

 #define STM32_ICU_USE_TIM5                  FALSE

 #define STM32_ICU_USE_TIM8                  FALSE

+#define STM32_ICU_USE_TIM12                 FALSE

+#define STM32_ICU_USE_TIM13                 FALSE

+#define STM32_ICU_USE_TIM14                 FALSE

 #define STM32_ICU_USE_TIM15                 FALSE

 #define STM32_ICU_USE_TIM16                 FALSE

 #define STM32_ICU_USE_TIM17                 FALSE

 

 /*

+ * MAC driver system settings.

+ */

+#define STM32_MAC_TRANSMIT_BUFFERS          2

+#define STM32_MAC_RECEIVE_BUFFERS           4

+#define STM32_MAC_BUFFERS_SIZE              1522

+#define STM32_MAC_PHY_TIMEOUT               100

+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE

+#define STM32_MAC_ETH1_IRQ_PRIORITY         13

+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0

+

+/*

  * PWM driver system settings.

  */

 #define STM32_PWM_USE_ADVANCED              FALSE

@@ -231,6 +333,9 @@
 #define STM32_PWM_USE_TIM4                  FALSE

 #define STM32_PWM_USE_TIM5                  FALSE

 #define STM32_PWM_USE_TIM8                  FALSE

+#define STM32_PWM_USE_TIM12                 FALSE

+#define STM32_PWM_USE_TIM13                 FALSE

+#define STM32_PWM_USE_TIM14                 FALSE

 #define STM32_PWM_USE_TIM15                 FALSE

 #define STM32_PWM_USE_TIM16                 FALSE

 #define STM32_PWM_USE_TIM17                 FALSE

@@ -247,29 +352,24 @@
  * SDC driver system settings.

  */

 #define STM32_SDC_USE_SDMMC1                FALSE

+#define STM32_SDC_USE_SDMMC2                FALSE

 #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT   TRUE

-#define STM32_SDC_SDMMC_WRITE_TIMEOUT       1000

-#define STM32_SDC_SDMMC_READ_TIMEOUT        1000

+#define STM32_SDC_SDMMC_WRITE_TIMEOUT       1000000

+#define STM32_SDC_SDMMC_READ_TIMEOUT        1000000

 #define STM32_SDC_SDMMC_CLOCK_DELAY         10

-#define STM32_SDC_SDMMC1_DMA_PRIORITY       3

-#define STM32_SDC_SDMMC1_IRQ_PRIORITY       9

-#define STM32_SDC_SDMMC1_DMA_STREAM         STM32_DMA_STREAM_ID(2, 4)

+#define STM32_SDC_SDMMC_PWRSAV              TRUE

 

 /*

  * SERIAL driver system settings.

  */

 #define STM32_SERIAL_USE_USART1             FALSE

-#define STM32_SERIAL_USE_USART2             TRUE

+#define STM32_SERIAL_USE_USART2             FALSE

 #define STM32_SERIAL_USE_USART3             FALSE

 #define STM32_SERIAL_USE_UART4              FALSE

 #define STM32_SERIAL_USE_UART5              FALSE

-#define STM32_SERIAL_USE_LPUART1            FALSE

-#define STM32_SERIAL_USART1_PRIORITY        12

-#define STM32_SERIAL_USART2_PRIORITY        12

-#define STM32_SERIAL_USART3_PRIORITY        12

-#define STM32_SERIAL_UART4_PRIORITY         12

-#define STM32_SERIAL_UART5_PRIORITY         12

-#define STM32_SERIAL_LPUART1_PRIORITY       12

+#define STM32_SERIAL_USE_USART6             FALSE

+#define STM32_SERIAL_USE_UART7              FALSE

+#define STM32_SERIAL_USE_UART8              FALSE

 

 /*

  * SPI driver system settings.

@@ -277,18 +377,33 @@
 #define STM32_SPI_USE_SPI1                  FALSE

 #define STM32_SPI_USE_SPI2                  FALSE

 #define STM32_SPI_USE_SPI3                  FALSE

-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 3)

-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 4)

-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)

-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)

+#define STM32_SPI_USE_SPI4                  FALSE

+#define STM32_SPI_USE_SPI5                  FALSE

+#define STM32_SPI_USE_SPI6                  FALSE

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI4_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI4_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI5_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI5_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI6_RX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

+#define STM32_SPI_SPI6_TX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

 #define STM32_SPI_SPI1_DMA_PRIORITY         1

 #define STM32_SPI_SPI2_DMA_PRIORITY         1

 #define STM32_SPI_SPI3_DMA_PRIORITY         1

+#define STM32_SPI_SPI4_DMA_PRIORITY         1

+#define STM32_SPI_SPI5_DMA_PRIORITY         1

+#define STM32_SPI_SPI6_DMA_PRIORITY         1

 #define STM32_SPI_SPI1_IRQ_PRIORITY         10

 #define STM32_SPI_SPI2_IRQ_PRIORITY         10

 #define STM32_SPI_SPI3_IRQ_PRIORITY         10

+#define STM32_SPI_SPI4_IRQ_PRIORITY         10

+#define STM32_SPI_SPI5_IRQ_PRIORITY         10

+#define STM32_SPI_SPI6_IRQ_PRIORITY         10

 #define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

 

 /*

@@ -310,41 +425,45 @@
 #define STM32_UART_USE_USART3               FALSE

 #define STM32_UART_USE_UART4                FALSE

 #define STM32_UART_USE_UART5                FALSE

-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 6)

-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)

-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)

-#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)

-#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)

-#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 2)

-#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 1)

-#define STM32_UART_USART1_IRQ_PRIORITY      12

-#define STM32_UART_USART2_IRQ_PRIORITY      12

-#define STM32_UART_USART3_IRQ_PRIORITY      12

-#define STM32_UART_UART4_IRQ_PRIORITY       12

-#define STM32_UART_UART5_IRQ_PRIORITY       12

+#define STM32_UART_USE_USART6               FALSE

+#define STM32_UART_USE_UART7                FALSE

+#define STM32_UART_USE_UART8                FALSE

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART7_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART7_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART8_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART8_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

 #define STM32_UART_USART1_DMA_PRIORITY      0

 #define STM32_UART_USART2_DMA_PRIORITY      0

 #define STM32_UART_USART3_DMA_PRIORITY      0

 #define STM32_UART_UART4_DMA_PRIORITY       0

 #define STM32_UART_UART5_DMA_PRIORITY       0

+#define STM32_UART_USART6_DMA_PRIORITY      0

+#define STM32_UART_UART7_DMA_PRIORITY       0

+#define STM32_UART_UART8_DMA_PRIORITY       0

 #define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

 

 /*

  * USB driver system settings.

  */

-#ifdef STM32L476_MCUCONF

-#define STM32_USB_USE_OTG1                  TRUE

+#define STM32_USB_USE_OTG1                  FALSE

+#define STM32_USB_USE_OTG2                  TRUE

 #define STM32_USB_OTG1_IRQ_PRIORITY         14

+#define STM32_USB_OTG2_IRQ_PRIORITY         14

 #define STM32_USB_OTG1_RX_FIFO_SIZE         512

-#else

-#define STM32_USB_USE_USB1                  TRUE

-#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE

-#define STM32_USB_USB1_HP_IRQ_PRIORITY      13

-#define STM32_USB_USB1_LP_IRQ_PRIORITY      14

-#endif // STM32L476_MCUCONF

+#define STM32_USB_OTG2_RX_FIFO_SIZE         1024

+#define STM32_USB_HOST_WAKEUP_DURATION      2

 

 /*

  * WDG driver system settings.

@@ -355,6 +474,9 @@
  * WSPI driver system settings.

  */

 #define STM32_WSPI_USE_QUADSPI1             FALSE

-#define STM32_WSPI_QUADSPI1_DMA_STREAM      STM32_DMA_STREAM_ID(2, 7)

+#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1

+#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY

+#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1

+#define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")

 

 #endif /* MCUCONF_H */