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230 lines
6.4 KiB
C++
230 lines
6.4 KiB
C++
/**
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* @file adc.cpp
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* @brief Manages signal reading through the ADC.
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*
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* Copyright (C) 2021 Clyne Sullivan
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*
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* Distributed under the GNU GPL v3 or later. You should have received a copy of
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* the GNU General Public License along with this program.
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* If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "adc.hpp"
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#if defined(TARGET_PLATFORM_L4)
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ADCDriver *ADC::m_driver = &ADCD1;
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ADCDriver *ADC::m_driver2 = &ADCD3;
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#else
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ADCDriver *ADC::m_driver = &ADCD3;
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//ADCDriver *ADC::m_driver2 = &ADCD1; // TODO
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#endif
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const ADCConfig ADC::m_config = {
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.difsel = 0,
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#if defined(TARGET_PLATFORM_H7)
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.calibration = 0,
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#endif
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};
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const ADCConfig ADC::m_config2 = {
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.difsel = 0,
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#if defined(TARGET_PLATFORM_H7)
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.calibration = 0,
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#endif
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};
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ADCConversionGroup ADC::m_group_config = {
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.circular = true,
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.num_channels = 1,
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.end_cb = ADC::conversionCallback,
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.error_cb = nullptr,
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.cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(13), /* TIM6_TRGO */
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.cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x
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#if defined(TARGET_PLATFORM_H7)
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.ccr = 0,
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.pcsel = 0,
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.ltr1 = 0, .htr1 = 4095,
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.ltr2 = 0, .htr2 = 4095,
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.ltr3 = 0, .htr3 = 4095,
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#else
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.tr1 = ADC_TR(0, 4095),
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.tr2 = ADC_TR(0, 4095),
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.tr3 = ADC_TR(0, 4095),
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.awd2cr = 0,
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.awd3cr = 0,
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#endif
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.smpr = {
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ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_12P5), 0
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},
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.sqr = {
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ADC_SQR1_SQ1_N(ADC_CHANNEL_IN5),
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0, 0, 0
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},
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};
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static bool readAltDone = false;
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static void readAltCallback(ADCDriver *)
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{
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readAltDone = true;
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}
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ADCConversionGroup ADC::m_group_config2 = {
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.circular = false,
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.num_channels = 2,
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.end_cb = readAltCallback,
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.error_cb = nullptr,
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.cfgr = ADC_CFGR_EXTEN_RISING | ADC_CFGR_EXTSEL_SRC(13), /* TIM6_TRGO */
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.cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSS_0, // Oversampling 2x
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#if defined(TARGET_PLATFORM_H7)
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.ccr = 0,
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.pcsel = 0,
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.ltr1 = 0, .htr1 = 4095,
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.ltr2 = 0, .htr2 = 4095,
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.ltr3 = 0, .htr3 = 4095,
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#else
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.tr1 = ADC_TR(0, 4095),
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.tr2 = ADC_TR(0, 4095),
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.tr3 = ADC_TR(0, 4095),
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.awd2cr = 0,
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.awd3cr = 0,
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#endif
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.smpr = {
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ADC_SMPR1_SMP_AN1(ADC_SMPR_SMP_2P5) | ADC_SMPR1_SMP_AN2(ADC_SMPR_SMP_2P5), 0
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},
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.sqr = {
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ADC_SQR1_SQ1_N(ADC_CHANNEL_IN1) | ADC_SQR1_SQ2_N(ADC_CHANNEL_IN2),
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0, 0, 0
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},
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};
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adcsample_t *ADC::m_current_buffer = nullptr;
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size_t ADC::m_current_buffer_size = 0;
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ADC::Operation ADC::m_operation = nullptr;
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void ADC::begin()
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{
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#if defined(TARGET_PLATFORM_H7)
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palSetPadMode(GPIOF, 3, PAL_MODE_INPUT_ANALOG);
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#else
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palSetPadMode(GPIOA, 0, PAL_MODE_INPUT_ANALOG); // Algorithm in
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palSetPadMode(GPIOC, 0, PAL_MODE_INPUT_ANALOG); // Potentiometer 1
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palSetPadMode(GPIOC, 1, PAL_MODE_INPUT_ANALOG); // Potentiometer 2
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#endif
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adcStart(m_driver, &m_config);
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adcStart(m_driver2, &m_config2);
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}
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void ADC::start(adcsample_t *buffer, size_t count, Operation operation)
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{
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m_current_buffer = buffer;
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m_current_buffer_size = count;
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m_operation = operation;
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adcStartConversion(m_driver, &m_group_config, buffer, count);
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SClock::start();
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}
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void ADC::stop()
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{
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SClock::stop();
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adcStopConversion(m_driver);
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m_current_buffer = nullptr;
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m_current_buffer_size = 0;
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m_operation = nullptr;
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}
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adcsample_t ADC::readAlt(unsigned int id)
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{
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if (id > 1)
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return 0;
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static adcsample_t result[16] = {};
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readAltDone = false;
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adcStartConversion(m_driver2, &m_group_config2, result, 8);
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while (!readAltDone);
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//__WFI();
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adcStopConversion(m_driver2);
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return result[id];
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}
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void ADC::setRate(SClock::Rate rate)
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{
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#if defined(TARGET_PLATFORM_H7)
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std::array<std::array<uint32_t, 2>, 6> m_rate_presets = {{
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// Rate PLL N PLL P
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{/* 8k */ 80, 20},
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{/* 16k */ 80, 10},
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{/* 20k */ 80, 8},
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{/* 32k */ 80, 5},
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{/* 48k */ 96, 4},
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{/* 96k */ 288, 10}
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}};
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auto& preset = m_rate_presets[static_cast<unsigned int>(rate)];
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auto pllbits = (preset[0] << RCC_PLL2DIVR_N2_Pos) |
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(preset[1] << RCC_PLL2DIVR_P2_Pos);
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adcStop(m_driver);
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// Adjust PLL2
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RCC->CR &= ~(RCC_CR_PLL2ON);
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while ((RCC->CR & RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY);
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auto pll2divr = RCC->PLL2DIVR &
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~(RCC_PLL2DIVR_N2_Msk | RCC_PLL2DIVR_P2_Msk);
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pll2divr |= pllbits;
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RCC->PLL2DIVR = pll2divr;
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RCC->CR |= RCC_CR_PLL2ON;
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while ((RCC->CR & RCC_CR_PLL2RDY) != RCC_CR_PLL2RDY);
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m_group_config.smpr[0] = rate != SClock::Rate::R96K ? ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_12P5)
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: ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_2P5);
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adcStart(m_driver, &m_config);
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#elif defined(TARGET_PLATFORM_L4)
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std::array<std::array<uint32_t, 3>, 6> m_rate_presets = {{
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// Rate PLLSAI2N R SMPR
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{/* 8k */ 8, 1, ADC_SMPR_SMP_12P5},
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{/* 16k */ 16, 1, ADC_SMPR_SMP_12P5},
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{/* 20k */ 20, 1, ADC_SMPR_SMP_12P5},
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{/* 32k */ 32, 1, ADC_SMPR_SMP_12P5},
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{/* 48k */ 24, 0, ADC_SMPR_SMP_12P5},
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{/* 96k */ 73, 1, ADC_SMPR_SMP_6P5} // Technically 96.05263kS/s
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}};
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auto& preset = m_rate_presets[static_cast<int>(rate)];
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auto pllnr = (preset[0] << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
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(preset[1] << RCC_PLLSAI2CFGR_PLLSAI2R_Pos);
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auto smpr = preset[2];
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// Adjust PLLSAI2
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RCC->CR &= ~(RCC_CR_PLLSAI2ON);
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while ((RCC->CR & RCC_CR_PLLSAI2RDY) == RCC_CR_PLLSAI2RDY);
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RCC->PLLSAI2CFGR = (RCC->PLLSAI2CFGR & ~(RCC_PLLSAI2CFGR_PLLSAI2N_Msk | RCC_PLLSAI2CFGR_PLLSAI2R_Msk)) | pllnr;
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RCC->CR |= RCC_CR_PLLSAI2ON;
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while ((RCC->CR & RCC_CR_PLLSAI2RDY) != RCC_CR_PLLSAI2RDY);
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m_group_config.smpr[0] = ADC_SMPR1_SMP_AN5(smpr);
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// Set 2x oversampling
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m_group_config.cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_0 | ADC_CFGR2_OVSS_1;
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m_group_config2.cfgr2 = ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR_0 | ADC_CFGR2_OVSS_1;
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#endif
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}
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void ADC::setOperation(ADC::Operation operation)
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{
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m_operation = operation;
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}
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void ADC::conversionCallback(ADCDriver *driver)
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{
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if (m_operation != nullptr) {
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auto half_size = m_current_buffer_size / 2;
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if (adcIsBufferComplete(driver))
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m_operation(m_current_buffer + half_size, half_size);
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else
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m_operation(m_current_buffer, half_size);
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}
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}
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