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409 lines
13 KiB
ArmAsm
409 lines
13 KiB
ArmAsm
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC56ECxx/boot.s
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* @brief SPC56ECxx boot-related code.
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*
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* @addtogroup PPC_BOOT
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* @{
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*/
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#include "boot.h"
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#if defined(__HIGHTEC__)
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#define se_bge bge
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#define se_bne bne
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#endif
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#if !defined(__DOXYGEN__)
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/* BAM record.*/
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.section .boot, "ax"
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#if BOOT_USE_VLE
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.long 0x015A0000
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#else
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.long 0x005A0000
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#endif
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.long _reset_address
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.align 2
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.globl _reset_address
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.type _reset_address, @function
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_reset_address:
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#if BOOT_PERFORM_CORE_INIT
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e_bl _coreinit
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#endif
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e_bl _ivinit
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#if BOOT_RELOCATE_IN_RAM
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/*
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* Image relocation in RAM.
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*/
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e_lis r4, __ram_reloc_start__@h
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e_or2i r4, __ram_reloc_start__@l
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e_lis r5, __ram_reloc_dest__@h
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e_or2i r5, __ram_reloc_dest__@l
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e_lis r6, __ram_reloc_end__@h
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e_or2i r6, r6, __ram_reloc_end__@l
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.relloop:
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se_cmpl r4, r6
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se_bge .relend
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se_lwz r7, 0(r4)
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se_addi r4, 4
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se_stw r7, 0(r5)
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se_addi r5, 4
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se_b .relloop
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.relend:
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e_lis r3, _boot_address@h
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e_or2i r3, _boot_address@l
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mtctr r3
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se_bctrl
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#else
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e_b _boot_address
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#endif
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#if BOOT_PERFORM_CORE_INIT
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.align 2
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_ramcode:
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tlbwe
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se_isync
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se_blr
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.align 2
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_coreinit:
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/*
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* Invalidating all TLBs except TLB0.
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*/
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e_lis r3, 0
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mtspr 625, r3 /* MAS1 */
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mtspr 626, r3 /* MAS2 */
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mtspr 627, r3 /* MAS3 */
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
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mtspr 624, r3 /* MAS0 */
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tlbwe
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/*
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* TLB1 allocated to internal RAM.
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*/
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e_lis r3, TLB1_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB1_MAS1@h
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e_or2i r3, TLB1_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB1_MAS2@h
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e_or2i r3, TLB1_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB1_MAS3@h
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e_or2i r3, TLB1_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/*
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* TLB2 allocated to internal Peripherals Bridge A.
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*/
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e_lis r3, TLB2_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB2_MAS1@h
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e_or2i r3, TLB2_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB2_MAS2@h
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e_or2i r3, TLB2_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB2_MAS3@h
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e_or2i r3, TLB2_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/*
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* TLB3 allocated to internal Peripherals Bridge B.
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*/
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e_lis r3, TLB3_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB3_MAS1@h
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e_or2i r3, TLB3_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB3_MAS2@h
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e_or2i r3, TLB3_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB3_MAS3@h
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e_or2i r3, TLB3_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/*
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* TLB4 allocated to on-platform peripherals.
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*/
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e_lis r3, TLB4_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB4_MAS1@h
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e_or2i r3, TLB4_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB4_MAS2@h
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e_or2i r3, TLB4_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB4_MAS3@h
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e_or2i r3, TLB4_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/*
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* TLB5 allocated to on-platform peripherals.
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*/
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e_lis r3, TLB5_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB5_MAS1@h
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e_or2i r3, TLB5_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB5_MAS2@h
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e_or2i r3, TLB5_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB5_MAS3@h
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e_or2i r3, TLB5_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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* slow down the startup but there is no way around.
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*/
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xor r0, r0, r0
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xor r1, r1, r1
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xor r2, r2, r2
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xor r3, r3, r3
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xor r4, r4, r4
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xor r5, r5, r5
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xor r6, r6, r6
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xor r7, r7, r7
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xor r8, r8, r8
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xor r9, r9, r9
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xor r10, r10, r10
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xor r11, r11, r11
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xor r12, r12, r12
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xor r13, r13, r13
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xor r14, r14, r14
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xor r15, r15, r15
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xor r16, r16, r16
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xor r17, r17, r17
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xor r18, r18, r18
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xor r19, r19, r19
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xor r20, r20, r20
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xor r21, r21, r21
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xor r22, r22, r22
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xor r23, r23, r23
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xor r24, r24, r24
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xor r25, r25, r25
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xor r26, r26, r26
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xor r27, r27, r27
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xor r28, r28, r28
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xor r29, r29, r29
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xor r30, r30, r30
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xor r31, r31, r31
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e_lis r4, __ram_start__@h
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e_or2i r4, __ram_start__@l
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e_lis r5, __ram_end__@h
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e_or2i r5, __ram_end__@l
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.cleareccloop:
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se_cmpl r4, r5
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se_bge .cleareccend
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e_stmw r16, 0(r4)
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e_addi r4, r4, 64
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se_b .cleareccloop
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.cleareccend:
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/*
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* Special function registers clearing, required in order to avoid
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* possible problems with lockstep mode.
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*/
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mtcrf 0xFF, r31
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mtspr 9, r31 /* CTR */
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mtspr 22, r31 /* DEC */
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mtspr 26, r31 /* SRR0-1 */
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mtspr 27, r31
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mtspr 54, r31 /* DECAR */
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mtspr 58, r31 /* CSRR0-1 */
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mtspr 59, r31
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mtspr 61, r31 /* DEAR */
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mtspr 256, r31 /* USPRG0 */
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mtspr 272, r31 /* SPRG1-7 */
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mtspr 273, r31
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mtspr 274, r31
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mtspr 275, r31
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mtspr 276, r31
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mtspr 277, r31
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mtspr 278, r31
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mtspr 279, r31
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mtspr 285, r31 /* TBU */
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mtspr 284, r31 /* TBL */
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#if 0
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mtspr 318, r31 /* DVC1-2 */
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mtspr 319, r31
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#endif
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mtspr 562, r31 /* DBCNT */
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mtspr 570, r31 /* MCSRR0 */
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mtspr 571, r31 /* MCSRR1 */
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mtspr 604, r31 /* SPRG8-9 */
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mtspr 605, r31
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/*
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* *Finally* the TLB0 is re-allocated to flash, note, the final phase
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* is executed from RAM.
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*/
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e_lis r3, TLB0_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB0_MAS1@h
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e_or2i r3, TLB0_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB0_MAS2@h
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e_or2i r3, TLB0_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB0_MAS3@h
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e_or2i r3, TLB0_MAS3@l
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mtspr 627, r3 /* MAS3 */
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mflr r4
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e_lis r6, _ramcode@h
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e_or2i r6, _ramcode@l
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e_lis r7, 0x40010000@h
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mtctr r7
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se_lwz r3, 0(r6)
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se_stw r3, 0(r7)
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se_lwz r3, 4(r6)
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se_stw r3, 4(r7)
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se_lwz r3, 8(r6)
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se_stw r3, 8(r7)
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se_bctrl
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mtlr r4
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/*
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* Branch prediction enabled.
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*/
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e_li r3, BOOT_BUCSR_DEFAULT
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mtspr 1013, r3 /* BUCSR */
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/*
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* Cache invalidated and then enabled.
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*/
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e_li r3, LICSR1_ICINV
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mtspr 1011, r3 /* LICSR1 */
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.inv: mfspr r3, 1011 /* LICSR1 */
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e_and2i. r3, LICSR1_ICINV
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se_bne .inv
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e_lis r3, BOOT_LICSR1_DEFAULT@h
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e_or2i r3, BOOT_LICSR1_DEFAULT@l
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mtspr 1011, r3 /* LICSR1 */
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se_blr
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#endif /* BOOT_PERFORM_CORE_INIT */
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/*
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* Exception vectors initialization.
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*/
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.align 2
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_ivinit:
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/* MSR initialization.*/
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e_lis r3, BOOT_MSR_DEFAULT@h
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e_or2i r3, BOOT_MSR_DEFAULT@l
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mtMSR r3
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/* IVPR initialization.*/
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e_lis r3, __ivpr_base__@h
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e_or2i r3, __ivpr_base__@l
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mtIVPR r3
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/* IVORs initialization.*/
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e_lis r3, _unhandled_exception@h
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e_or2i r3, _unhandled_exception@l
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mtspr 400, r3 /* IVOR0-15 */
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mtspr 401, r3
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mtspr 402, r3
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mtspr 403, r3
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mtspr 404, r3
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mtspr 405, r3
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mtspr 406, r3
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mtspr 407, r3
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mtspr 408, r3
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mtspr 409, r3
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mtspr 410, r3
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mtspr 411, r3
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mtspr 412, r3
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mtspr 413, r3
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mtspr 414, r3
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mtspr 415, r3
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mtspr 528, r3 /* IVOR32-34 */
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mtspr 529, r3
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mtspr 530, r3
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se_blr
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.section .handlers, "ax"
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/*
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* Unhandled exceptions handler.
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*/
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.weak _unhandled_exception
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.type _unhandled_exception, @function
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_unhandled_exception:
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se_b _unhandled_exception
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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