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779 lines
29 KiB
C
779 lines
29 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32H7xx/stm32_registry.h
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* @brief STM32H7xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef STM32_REGISTRY_H
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#define STM32_REGISTRY_H
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/* Cores.*/
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#if defined(STM32H750xx) || defined(STM32H742xx) || \
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defined(STM32H743xx) || defined(STM32H753xx) || \
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defined(STM32H723xx)
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#define STM32_HAS_M7 TRUE
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#define STM32_HAS_M4 FALSE
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#else
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#define STM32_HAS_M7 TRUE
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#define STM32_HAS_M4 TRUE
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#endif
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/**
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* @name STM32H7xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* Common. */
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/*===========================================================================*/
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/* RNG attributes.*/
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#define STM32_HAS_RNG1 TRUE
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/* I2C attributes.*/
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#define STM32_I2C4_USE_BDMA TRUE
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/*===========================================================================*/
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/* STM32H743xx, STM32H753xx, STM32H745xx, STM32H755xx, STM32H747xx, */
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/* STM32H757xx. */
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/*===========================================================================*/
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#if defined(STM32H743xx) || defined(STM32H753xx) || \
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defined(STM32H745xx) || defined(STM32H755xx) || \
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defined(STM32H747xx) || defined(STM32H757xx) || \
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defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 TRUE
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_FDCAN1 TRUE
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#define STM32_HAS_FDCAN2 TRUE
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#define STM32_HAS_FDCAN3 FALSE
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#define STM32_FDCAN_FLS_NBR 128U
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#define STM32_FDCAN_FLE_NBR 128U
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#define STM32_FDCAN_RF0_NBR 64U
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#define STM32_FDCAN_RF1_NBR 64U
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#define STM32_FDCAN_RB_NBR 64U
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#define STM32_FDCAN_TEF_NBR 32U
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#define STM32_FDCAN_TB_NBR 32U
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#define STM32_FDCAN_TM_NBR 64U
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* BDMA attributes.*/
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#define STM32_HAS_BDMA1 TRUE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX TRUE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 TRUE
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/* MDMA attributes.*/
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#define STM32_HAS_MDMA1 TRUE
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/* ETH attributes.*/
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#define STM32_HAS_ETH TRUE
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/* EXTI attributes.*/
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#define STM32_EXTI_ENHANCED
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#define STM32_EXTI_NUM_LINES 34
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#define STM32_EXTI_IMR1_MASK 0x1F800000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOI TRUE
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#define STM32_HAS_GPIOJ TRUE
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#define STM32_HAS_GPIOK TRUE
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#define STM32_GPIO_EN_MASK (RCC_AHB4ENR_GPIOAEN | \
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RCC_AHB4ENR_GPIOBEN | \
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RCC_AHB4ENR_GPIOCEN | \
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RCC_AHB4ENR_GPIODEN | \
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RCC_AHB4ENR_GPIOEEN | \
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RCC_AHB4ENR_GPIOFEN | \
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RCC_AHB4ENR_GPIOGEN | \
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RCC_AHB4ENR_GPIOHEN | \
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RCC_AHB4ENR_GPIOIEN | \
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RCC_AHB4ENR_GPIOJEN | \
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RCC_AHB4ENR_GPIOKEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_I2C3 TRUE
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#define STM32_HAS_I2C4 TRUE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 TRUE
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#define STM32_HAS_QUADSPI2 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 TRUE
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#define STM32_HAS_SDMMC2 TRUE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S TRUE
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#define STM32_SPI1_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_SPI2_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_SPI3_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI5 TRUE
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#define STM32_SPI5_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI6 TRUE
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#define STM32_SPI6_SUPPORTS_I2S FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM12 TRUE
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#define STM32_TIM12_IS_32BITS FALSE
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#define STM32_TIM12_CHANNELS 2
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#define STM32_HAS_TIM13 TRUE
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#define STM32_TIM13_IS_32BITS FALSE
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#define STM32_TIM13_CHANNELS 1
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 FALSE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 FALSE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 1
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#define STM32_HAS_TIM17 FALSE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 1
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 TRUE
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#define STM32_HAS_UART5 TRUE
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#define STM32_HAS_USART6 TRUE
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#define STM32_HAS_UART7 TRUE
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#define STM32_HAS_UART8 TRUE
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#define STM32_HAS_LPUART1 TRUE
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/* USB attributes.*/
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#define STM32_OTG_STEPPING 2
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#define STM32_HAS_OTG1 TRUE
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#define STM32_OTG1_ENDPOINTS 8
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#define STM32_HAS_OTG2 TRUE
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#define STM32_OTG2_ENDPOINTS 8
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#define STM32_HAS_USB FALSE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC TRUE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D TRUE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC TRUE
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#define STM32_FSMC_IS_FMC TRUE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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/* DCMI attributes.*/
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#define STM32_HAS_DCMI TRUE
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#endif /* defined(STM32H743xx) || defined(STM32H753xx) */
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/** @} */
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/*===========================================================================*/
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/* STM32H750xx. */
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/*===========================================================================*/
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#if defined(STM32H750xx) || \
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defined(__DOXYGEN__)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_FDCAN1 TRUE
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#define STM32_HAS_FDCAN2 TRUE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 TRUE
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#define STM32_HAS_DAC1_CH2 TRUE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* BDMA attributes.*/
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#define STM32_HAS_BDMA1 TRUE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX TRUE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 TRUE
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/* MDMA attributes.*/
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#define STM32_HAS_MDMA1 TRUE
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/* ETH attributes.*/
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#define STM32_HAS_ETH TRUE
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/* EXTI attributes.*/
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#define STM32_EXTI_ENHANCED
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#define STM32_EXTI_NUM_LINES 34
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#define STM32_EXTI_IMR1_MASK 0x1F800000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOH TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOI TRUE
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#define STM32_HAS_GPIOJ TRUE
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#define STM32_HAS_GPIOK TRUE
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#define STM32_GPIO_EN_MASK (RCC_AHB4ENR_GPIOAEN | \
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RCC_AHB4ENR_GPIOBEN | \
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RCC_AHB4ENR_GPIOCEN | \
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RCC_AHB4ENR_GPIODEN | \
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RCC_AHB4ENR_GPIOEEN | \
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RCC_AHB4ENR_GPIOFEN | \
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RCC_AHB4ENR_GPIOGEN | \
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RCC_AHB4ENR_GPIOHEN | \
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RCC_AHB4ENR_GPIOIEN | \
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RCC_AHB4ENR_GPIOJEN | \
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RCC_AHB4ENR_GPIOKEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_HAS_I2C2 TRUE
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#define STM32_HAS_I2C3 TRUE
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#define STM32_HAS_I2C4 TRUE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 TRUE
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#define STM32_HAS_QUADSPI2 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 TRUE
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#define STM32_HAS_SDMMC2 TRUE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S TRUE
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#define STM32_SPI1_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_SUPPORTS_I2S TRUE
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#define STM32_SPI2_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_SUPPORTS_I2S TRUE
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#define STM32_SPI3_I2S_FULLDUPLEX TRUE
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI5 TRUE
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#define STM32_SPI5_SUPPORTS_I2S FALSE
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#define STM32_HAS_SPI6 TRUE
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#define STM32_SPI6_SUPPORTS_I2S FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM12 TRUE
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#define STM32_TIM12_IS_32BITS FALSE
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#define STM32_TIM12_CHANNELS 2
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#define STM32_HAS_TIM13 TRUE
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#define STM32_TIM13_IS_32BITS FALSE
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#define STM32_TIM13_CHANNELS 1
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 FALSE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 FALSE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 1
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#define STM32_HAS_TIM17 FALSE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 1
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_HAS_USART2 TRUE
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#define STM32_HAS_USART3 TRUE
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#define STM32_HAS_UART4 TRUE
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#define STM32_HAS_UART5 TRUE
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#define STM32_HAS_USART6 TRUE
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#define STM32_HAS_UART7 TRUE
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#define STM32_HAS_UART8 TRUE
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#define STM32_HAS_LPUART1 TRUE
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/* USB attributes.*/
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#define STM32_OTG_STEPPING 2
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#define STM32_HAS_OTG1 TRUE
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#define STM32_OTG1_ENDPOINTS 8
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#define STM32_HAS_OTG2 TRUE
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#define STM32_OTG2_ENDPOINTS 8
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#define STM32_HAS_USB FALSE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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|
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC TRUE
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|
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D TRUE
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|
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC TRUE
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#define STM32_FSMC_IS_FMC TRUE
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|
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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|
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/* DCMI attributes.*/
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#define STM32_HAS_DCMI TRUE
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#endif /* defined(STM32H750xx) */
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/*===========================================================================*/
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/* STM32H723xx. */
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/*===========================================================================*/
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#if defined(STM32H723xx) || defined(__DOXYGEN__)
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/* ADC attributes.*/
|
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 TRUE
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#define STM32_HAS_ADC3 TRUE
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#define STM32_HAS_ADC4 FALSE
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|
|
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_HAS_SDADC3 FALSE
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|
|
|
/* CAN attributes.*/
|
|
#define STM32_HAS_FDCAN1 TRUE
|
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#define STM32_HAS_FDCAN2 TRUE
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#define STM32_HAS_FDCAN3 FALSE
|
|
#define STM32_FDCAN_FLS_NBR 128U
|
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#define STM32_FDCAN_FLE_NBR 128U
|
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#define STM32_FDCAN_RF0_NBR 64U
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#define STM32_FDCAN_RF1_NBR 64U
|
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#define STM32_FDCAN_RB_NBR 64U
|
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#define STM32_FDCAN_TEF_NBR 32U
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#define STM32_FDCAN_TB_NBR 32U
|
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#define STM32_FDCAN_TM_NBR 64U
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|
|
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/* DAC attributes.*/
|
|
#define STM32_HAS_DAC1_CH1 TRUE
|
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#define STM32_HAS_DAC1_CH2 TRUE
|
|
#define STM32_HAS_DAC2_CH1 FALSE
|
|
#define STM32_HAS_DAC2_CH2 FALSE
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|
|
|
/* BDMA attributes.*/
|
|
#define STM32_HAS_BDMA1 TRUE
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|
|
|
/* DMA attributes.*/
|
|
#define STM32_ADVANCED_DMA TRUE
|
|
#define STM32_DMA_SUPPORTS_DMAMUX TRUE
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|
|
|
#define STM32_HAS_DMA1 TRUE
|
|
#define STM32_HAS_DMA2 TRUE
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|
|
|
/* MDMA attributes.*/
|
|
#define STM32_HAS_MDMA1 TRUE
|
|
|
|
/* ETH attributes.*/
|
|
#define STM32_HAS_ETH TRUE
|
|
|
|
/* EXTI attributes.*/
|
|
#define STM32_EXTI_ENHANCED
|
|
#define STM32_EXTI_NUM_LINES 34
|
|
#define STM32_EXTI_IMR1_MASK 0x1F800000U
|
|
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
|
|
|
/* GPIO attributes.*/
|
|
#define STM32_HAS_GPIOA TRUE
|
|
#define STM32_HAS_GPIOB TRUE
|
|
#define STM32_HAS_GPIOC TRUE
|
|
#define STM32_HAS_GPIOD TRUE
|
|
#define STM32_HAS_GPIOE TRUE
|
|
#define STM32_HAS_GPIOH TRUE
|
|
#define STM32_HAS_GPIOF TRUE
|
|
#define STM32_HAS_GPIOG TRUE
|
|
#define STM32_HAS_GPIOI FALSE
|
|
#define STM32_HAS_GPIOJ TRUE
|
|
#define STM32_HAS_GPIOK TRUE
|
|
#define STM32_GPIO_EN_MASK (RCC_AHB4ENR_GPIOAEN | \
|
|
RCC_AHB4ENR_GPIOBEN | \
|
|
RCC_AHB4ENR_GPIOCEN | \
|
|
RCC_AHB4ENR_GPIODEN | \
|
|
RCC_AHB4ENR_GPIOEEN | \
|
|
RCC_AHB4ENR_GPIOFEN | \
|
|
RCC_AHB4ENR_GPIOGEN | \
|
|
RCC_AHB4ENR_GPIOHEN | \
|
|
RCC_AHB4ENR_GPIOJEN | \
|
|
RCC_AHB4ENR_GPIOKEN)
|
|
|
|
/* I2C attributes.*/
|
|
#define STM32_HAS_I2C1 TRUE
|
|
#define STM32_HAS_I2C2 TRUE
|
|
#define STM32_HAS_I2C3 TRUE
|
|
#define STM32_HAS_I2C4 TRUE
|
|
#define STM32_HAS_I2C5 TRUE
|
|
|
|
/* QUADSPI attributes.*/
|
|
#define STM32_HAS_QUADSPI1 FALSE
|
|
#define STM32_HAS_QUADSPI2 FALSE
|
|
|
|
/* OCTOSPI attributes.*/
|
|
#define STM32_HAS_OCTOSPI1 TRUE
|
|
#define STM32_HAS_OCTOSPI2 TRUE
|
|
|
|
/* RTC attributes.*/
|
|
#define STM32_HAS_RTC TRUE
|
|
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
|
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
|
#define STM32_RTC_NUM_ALARMS 2
|
|
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
|
|
|
/* SDMMC attributes.*/
|
|
#define STM32_HAS_SDMMC1 TRUE
|
|
#define STM32_HAS_SDMMC2 TRUE
|
|
|
|
/* SPI attributes.*/
|
|
#define STM32_HAS_SPI1 TRUE
|
|
#define STM32_SPI1_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI1_I2S_FULLDUPLEX TRUE
|
|
|
|
#define STM32_HAS_SPI2 TRUE
|
|
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
|
|
|
#define STM32_HAS_SPI3 TRUE
|
|
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
|
|
|
#define STM32_HAS_SPI4 TRUE
|
|
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
|
|
|
#define STM32_HAS_SPI5 TRUE
|
|
#define STM32_SPI5_SUPPORTS_I2S FALSE
|
|
|
|
#define STM32_HAS_SPI6 TRUE
|
|
#define STM32_SPI6_SUPPORTS_I2S TRUE
|
|
#define STM32_SPI6_I2S_FULLDUPLEX TRUE
|
|
|
|
/* TIM attributes.*/
|
|
#define STM32_TIM_MAX_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM1 TRUE
|
|
#define STM32_TIM1_IS_32BITS FALSE
|
|
#define STM32_TIM1_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM2 TRUE
|
|
#define STM32_TIM2_IS_32BITS TRUE
|
|
#define STM32_TIM2_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM3 TRUE
|
|
#define STM32_TIM3_IS_32BITS FALSE
|
|
#define STM32_TIM3_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM4 TRUE
|
|
#define STM32_TIM4_IS_32BITS FALSE
|
|
#define STM32_TIM4_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM5 TRUE
|
|
#define STM32_TIM5_IS_32BITS TRUE
|
|
#define STM32_TIM5_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM6 TRUE
|
|
#define STM32_TIM6_IS_32BITS FALSE
|
|
#define STM32_TIM6_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM7 TRUE
|
|
#define STM32_TIM7_IS_32BITS FALSE
|
|
#define STM32_TIM7_CHANNELS 0
|
|
|
|
#define STM32_HAS_TIM8 TRUE
|
|
#define STM32_TIM8_IS_32BITS FALSE
|
|
#define STM32_TIM8_CHANNELS 6
|
|
|
|
#define STM32_HAS_TIM12 TRUE
|
|
#define STM32_TIM12_IS_32BITS FALSE
|
|
#define STM32_TIM12_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM13 TRUE
|
|
#define STM32_TIM13_IS_32BITS FALSE
|
|
#define STM32_TIM13_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM14 TRUE
|
|
#define STM32_TIM14_IS_32BITS FALSE
|
|
#define STM32_TIM14_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM15 TRUE
|
|
#define STM32_TIM15_IS_32BITS FALSE
|
|
#define STM32_TIM15_CHANNELS 2
|
|
|
|
#define STM32_HAS_TIM16 TRUE
|
|
#define STM32_TIM16_IS_32BITS FALSE
|
|
#define STM32_TIM16_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM17 TRUE
|
|
#define STM32_TIM17_IS_32BITS FALSE
|
|
#define STM32_TIM17_CHANNELS 1
|
|
|
|
#define STM32_HAS_TIM23 TRUE
|
|
#define STM32_TIM23_IS_32BITS TRUE
|
|
#define STM32_TIM23_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM24 TRUE
|
|
#define STM32_TIM24_IS_32BITS TRUE
|
|
#define STM32_TIM24_CHANNELS 4
|
|
|
|
#define STM32_HAS_TIM9 FALSE
|
|
#define STM32_HAS_TIM10 FALSE
|
|
#define STM32_HAS_TIM11 FALSE
|
|
#define STM32_HAS_TIM18 FALSE
|
|
#define STM32_HAS_TIM19 FALSE
|
|
#define STM32_HAS_TIM20 FALSE
|
|
#define STM32_HAS_TIM21 FALSE
|
|
#define STM32_HAS_TIM22 FALSE
|
|
|
|
/* USART attributes.*/
|
|
#define STM32_HAS_USART1 TRUE
|
|
#define STM32_HAS_USART2 TRUE
|
|
#define STM32_HAS_USART3 TRUE
|
|
#define STM32_HAS_UART4 TRUE
|
|
#define STM32_HAS_UART5 TRUE
|
|
#define STM32_HAS_USART6 TRUE
|
|
#define STM32_HAS_UART7 TRUE
|
|
#define STM32_HAS_UART8 TRUE
|
|
#define STM32_HAS_UART9 TRUE
|
|
#define STM32_HAS_USART10 TRUE
|
|
#define STM32_HAS_LPUART1 TRUE
|
|
|
|
/* USB attributes.*/
|
|
#define STM32_OTG_STEPPING 2
|
|
#define STM32_HAS_OTG1 TRUE
|
|
#define STM32_OTG1_ENDPOINTS 8
|
|
|
|
#define STM32_HAS_OTG2 TRUE
|
|
#define STM32_OTG2_ENDPOINTS 8
|
|
|
|
#define STM32_HAS_USB FALSE
|
|
|
|
/* IWDG attributes.*/
|
|
#define STM32_HAS_IWDG TRUE
|
|
#define STM32_IWDG_IS_WINDOWED TRUE
|
|
|
|
/* LTDC attributes.*/
|
|
#define STM32_HAS_LTDC TRUE
|
|
|
|
/* DMA2D attributes.*/
|
|
#define STM32_HAS_DMA2D TRUE
|
|
|
|
/* FSMC attributes.*/
|
|
#define STM32_HAS_FSMC TRUE
|
|
#define STM32_FSMC_IS_FMC TRUE
|
|
|
|
/* CRC attributes.*/
|
|
#define STM32_HAS_CRC TRUE
|
|
#define STM32_CRC_PROGRAMMABLE TRUE
|
|
|
|
/* DCMI attributes.*/
|
|
#define STM32_HAS_DCMI TRUE
|
|
|
|
#endif /* defined(STM32H723xx) */
|
|
/** @} */
|
|
|
|
#endif /* STM32_REGISTRY_H */
|
|
|
|
/** @} */
|