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authorClyne Sullivan <tullivan99@gmail.com>2018-10-02 21:26:48 -0400
committerClyne Sullivan <tullivan99@gmail.com>2018-10-02 21:26:48 -0400
commitc66410f6319284b94e21758539ac25bfb4694d3a (patch)
tree73c1ac0da5c6507d4111cf967549184c964552c9 /src/clock.c
parent231c796f50ac4dc277978a6568e8083412c765e0 (diff)
folder restructure
Diffstat (limited to 'src/clock.c')
-rw-r--r--src/clock.c72
1 files changed, 0 insertions, 72 deletions
diff --git a/src/clock.c b/src/clock.c
deleted file mode 100644
index c94695b..0000000
--- a/src/clock.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/**
- * @file clock.c
- * Basic clock utilities
- *
- * Copyright (C) 2018 Clyne Sullivan
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <https://www.gnu.org/licenses/>.
- */
-
-#include <clock.h>
-#include <stm32l476xx.h>
-
-// ticks since init
-volatile uint32_t ticks = 0;
-
-void clock_init(void)
-{
- // turn on HSI (16MHz)
- RCC->CR |= RCC_CR_HSION;
- while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY);
-
- // get PLLR to 80MHz (max)
- // VCO = C * (N/M) -> 16 * (10/1) = 160
- // SCLK = VCO / R = 160 / 2 = 80 MHz
- RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC);
- RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSI;
- RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM);
- RCC->PLLCFGR |= 10 << RCC_PLLCFGR_PLLN_Pos;
- RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLQ); // /2
- RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLQEN;
-
- // start PLL
- RCC->CR |= RCC_CR_PLLON;
- while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
-
- // set system clock to PLL
- RCC->CFGR &= ~(RCC_CFGR_SW);
- RCC->CFGR &= ~(RCC_CFGR_HPRE_Msk);
- RCC->CFGR |= RCC_CFGR_SW_PLL;
- while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
-
- // SysTick init. 80MHz / 80000 = 1kHz, ms precision
- SysTick->LOAD = 80000;
- SysTick->CTRL |= 0x07; // no div, interrupt, enable
-}
-
-void delay(uint32_t count)
-{
- uint32_t target = ticks + count;
- while (ticks < target);
-}
-
-void SysTick_Handler(void)
-{
- // just keep counting
- ticks++;
-
- if (!(ticks & 3))
- SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
-}
-