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authorClyne Sullivan <clyne@bitgloo.com>2025-01-29 21:34:25 -0500
committerClyne Sullivan <clyne@bitgloo.com>2025-01-29 21:34:25 -0500
commit5b81bc8ccbd342b8566d88fc9f17a73aec03b5b6 (patch)
treecc57486912cfa74c6440d8b97c28f451ec787d78 /Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c
initial commit
Diffstat (limited to 'Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c')
-rw-r--r--Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c129
1 files changed, 129 insertions, 0 deletions
diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c
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+++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c
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+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_xor_u32.c
+ * Description: uint32_t bitwise exclusive OR
+ *
+ * $Date: 23 April 2021
+ * $Revision: V1.9.0
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "dsp/basic_math_functions.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup Xor
+ @{
+ */
+
+/**
+ @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ @param[in] pSrcA points to input vector A
+ @param[in] pSrcB points to input vector B
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_xor_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
+ uint32x4_t vecSrcA, vecSrcB;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2;
+
+ while (blkCnt > 0U)
+ {
+ vecSrcA = vld1q(pSrcA);
+ vecSrcB = vld1q(pSrcB);
+
+ vst1q(pDst, veorq_u32(vecSrcA, vecSrcB) );
+
+ pSrcA += 4;
+ pSrcB += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 3;
+
+ if (blkCnt > 0U)
+ {
+ mve_pred16_t p0 = vctp32q(blkCnt);
+ vecSrcA = vld1q(pSrcA);
+ vecSrcB = vld1q(pSrcB);
+ vstrwq_p(pDst, veorq_u32(vecSrcA, vecSrcB), p0);
+ }
+#else
+#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE)
+ uint32x4_t vecA, vecB;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ vecA = vld1q_u32(pSrcA);
+ vecB = vld1q_u32(pSrcB);
+
+ vst1q_u32(pDst, veorq_u32(vecA, vecB) );
+
+ pSrcA += 4;
+ pSrcB += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 3;
+#else
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+#endif
+
+ while (blkCnt > 0U)
+ {
+ *pDst++ = (*pSrcA++)^(*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+#endif /* if defined(ARM_MATH_MVEI) */
+}
+
+/**
+ @} end of Xor group
+ */