diff options
Diffstat (limited to 'Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates')
16 files changed, 3087 insertions, 0 deletions
diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u031xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u031xx.s new file mode 100644 index 0000000..43ef086 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u031xx.s @@ -0,0 +1,248 @@ +;****************************************************************************** +;* File Name : startup_stm32u031xx.s +;* Author : MCD Application Team +;* Description : STM32U031xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IWDG_IRQHandler ; Window WatchDog / Independent Watchdog Interrupt + DCD PVD_PVM_IRQHandler ; PVD through EXTI line detection + DCD RTC_TAMP_IRQHandler ; RTC/TAMP through the EXTI line + DCD FLASH_ECC_IRQHandler ; FLASH / ECC + DCD RCC_CRS_IRQHandler ; RCC / CRS + DCD EXTI0_1_IRQHandler ; EXTI Line[0:1] + DCD EXTI2_3_IRQHandler ; EXTI Line[2:3] + DCD EXTI4_15_IRQHandler ; EXTI Line[4:15] + DCD 0 ; + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel1 interrupt + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel2/Channel3 interrupt + DCD DMA1_Ch4_7_DMAMUX_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX overrun + DCD ADC_COMP1_IRQHandler ; ADC and COMP1 interrupts + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 break, update, trigger, commutation, error, direction change and index interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6 / DAC1&3 / LPTIM1 global interrupt + DCD TIM7_LPTIM2_IRQHandler ; TIM7 / LPTIM2 global interrupt + DCD TIM15_IRQHandler ; TIM15 global interrupt + DCD TIM16_IRQHandler ; TIM16 + DCD TSC_IRQHandler ; TSC global interrupt + DCD 0 ; + DCD I2C1_IRQHandler ; I2C1 global interrupt + DCD I2C2_3_IRQHandler ; I2C2 / I2C3 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_LPUART2_IRQHandler ; USART2, LPUART 2 global interrupt + DCD USART3_LPUART1_IRQHandler ; USART3, LPUART 1 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD RNG_IRQHandler ; RNG global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_ECC_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMAMUX_OVR_IRQHandler [WEAK] + EXPORT ADC_COMP1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK] + EXPORT TIM7_LPTIM2_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_LPUART2_IRQHandler [WEAK] + EXPORT USART3_LPUART1_IRQHandler [WEAK] + EXPORT USART4_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + + +WWDG_IWDG_IRQHandler +PVD_PVM_IRQHandler +RTC_TAMP_IRQHandler +FLASH_ECC_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMAMUX_OVR_IRQHandler +ADC_COMP1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_LPTIM1_IRQHandler +TIM7_LPTIM2_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TSC_IRQHandler +I2C1_IRQHandler +I2C2_3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_LPUART2_IRQHandler +USART3_LPUART1_IRQHandler +USART4_IRQHandler +RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u073xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u073xx.s new file mode 100644 index 0000000..1acd3f8 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u073xx.s @@ -0,0 +1,252 @@ +;****************************************************************************** +;* File Name : startup_stm32u073xx.s +;* Author : MCD Application Team +;* Description : STM32U073xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IWDG_IRQHandler ; Window WatchDog / Independent Watchdog Interrupt + DCD PVD_PVM_IRQHandler ; PVD through EXTI line detection + DCD RTC_TAMP_IRQHandler ; RTC/TAMP through the EXTI line + DCD FLASH_ECC_IRQHandler ; FLASH / ECC + DCD RCC_CRS_IRQHandler ; RCC / CRS + DCD EXTI0_1_IRQHandler ; EXTI Line[0:1] + DCD EXTI2_3_IRQHandler ; EXTI Line[2:3] + DCD EXTI4_15_IRQHandler ; EXTI Line[4:15] + DCD USB_DRD_FS_IRQHandler ; USB global interrupt through EXTI line detection + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel1 interrupt + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel2/Channel3 interrupt + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMA2 Channel 1 to Channel 5, DMAMUX overrun + DCD ADC_COMP1_2_IRQHandler ; ADC and COMP1/COMP2 interrupts + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 break, update, trigger, commutation, error, direction change and index interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6 / DAC1&3 / LPTIM1 global interrupt + DCD TIM7_LPTIM2_IRQHandler ; TIM7 / LPTIM2 global interrupt + DCD TIM15_LPTIM3_IRQHandler ; TIM15 / LPTIM3 global interrupt + DCD TIM16_IRQHandler ; TIM16 + DCD TSC_IRQHandler ; TSC global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD I2C1_IRQHandler ; I2C1 global interrupt + DCD I2C2_3_4_IRQHandler ; I2C2 / I2C3 / I2C4 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_3_IRQHandler ; SPI2 /SPI3 global interrupt + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_LPUART2_IRQHandler ; USART2, LPUART 2 global interrupt + DCD USART3_LPUART1_IRQHandler ; USART3, LPUART 1 global interrupt + DCD USART4_LPUART3_IRQHandler ; USART4, LPUART 3 global interrupt + DCD RNG_CRYP_IRQHandler ; RNG, CRYPTO global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_ECC_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT USB_DRD_FS_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler [WEAK] + EXPORT ADC_COMP1_2_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK] + EXPORT TIM7_LPTIM2_IRQHandler [WEAK] + EXPORT TIM15_LPTIM3_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_3_4_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_3_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_LPUART2_IRQHandler [WEAK] + EXPORT USART3_LPUART1_IRQHandler [WEAK] + EXPORT USART4_LPUART3_IRQHandler [WEAK] + EXPORT RNG_CRYP_IRQHandler [WEAK] + + +WWDG_IWDG_IRQHandler +PVD_PVM_IRQHandler +RTC_TAMP_IRQHandler +FLASH_ECC_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +USB_DRD_FS_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler +ADC_COMP1_2_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_LPTIM1_IRQHandler +TIM7_LPTIM2_IRQHandler +TIM15_LPTIM3_IRQHandler +TIM16_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +I2C1_IRQHandler +I2C2_3_4_IRQHandler +SPI1_IRQHandler +SPI2_3_IRQHandler +USART1_IRQHandler +USART2_LPUART2_IRQHandler +USART3_LPUART1_IRQHandler +USART4_LPUART3_IRQHandler +RNG_CRYP_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u083xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u083xx.s new file mode 100644 index 0000000..142a78e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/arm/startup_stm32u083xx.s @@ -0,0 +1,252 @@ +;****************************************************************************** +;* File Name : startup_stm32u083xx.s +;* Author : MCD Application Team +;* Description : STM32U083xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IWDG_IRQHandler ; Window WatchDog / Independent Watchdog Interrupt + DCD PVD_PVM_IRQHandler ; PVD through EXTI line detection + DCD RTC_TAMP_IRQHandler ; RTC/TAMP through the EXTI line + DCD FLASH_ECC_IRQHandler ; FLASH / ECC + DCD RCC_CRS_IRQHandler ; RCC / CRS + DCD EXTI0_1_IRQHandler ; EXTI Line[0:1] + DCD EXTI2_3_IRQHandler ; EXTI Line[2:3] + DCD EXTI4_15_IRQHandler ; EXTI Line[4:15] + DCD USB_DRD_FS_IRQHandler ; USB global interrupt through EXTI line detection + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel1 interrupt + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel2/Channel3 interrupt + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMA2 Channel 1 to Channel 5, DMAMUX overrun + DCD ADC_COMP1_2_IRQHandler ; ADC and COMP1/COMP2 interrupts + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 break, update, trigger, commutation, error, direction change and index interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6 / DAC1&3 / LPTIM1 global interrupt + DCD TIM7_LPTIM2_IRQHandler ; TIM7 / LPTIM2 global interrupt + DCD TIM15_LPTIM3_IRQHandler ; TIM15 / LPTIM3 global interrupt + DCD TIM16_IRQHandler ; TIM16 + DCD TSC_IRQHandler ; TSC global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD I2C1_IRQHandler ; I2C1 global interrupt + DCD I2C2_3_4_IRQHandler ; I2C2 / I2C3 / I2C4 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_3_IRQHandler ; SPI2 /SPI3 global interrupt + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_LPUART2_IRQHandler ; USART2, LPUART 2 global interrupt + DCD USART3_LPUART1_IRQHandler ; USART3, LPUART 1 global interrupt + DCD USART4_LPUART3_IRQHandler ; USART4, LPUART 3 global interrupt + DCD RNG_CRYP_IRQHandler ; RNG, CRYPTO global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_ECC_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT USB_DRD_FS_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler [WEAK] + EXPORT ADC_COMP1_2_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK] + EXPORT TIM7_LPTIM2_IRQHandler [WEAK] + EXPORT TIM15_LPTIM3_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_3_4_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_3_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_LPUART2_IRQHandler [WEAK] + EXPORT USART3_LPUART1_IRQHandler [WEAK] + EXPORT USART4_LPUART3_IRQHandler [WEAK] + EXPORT RNG_CRYP_IRQHandler [WEAK] + + +WWDG_IWDG_IRQHandler +PVD_PVM_IRQHandler +RTC_TAMP_IRQHandler +FLASH_ECC_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +USB_DRD_FS_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler +ADC_COMP1_2_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_LPTIM1_IRQHandler +TIM7_LPTIM2_IRQHandler +TIM15_LPTIM3_IRQHandler +TIM16_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +I2C1_IRQHandler +I2C2_3_4_IRQHandler +SPI1_IRQHandler +SPI2_3_IRQHandler +USART1_IRQHandler +USART2_LPUART2_IRQHandler +USART3_LPUART1_IRQHandler +USART4_LPUART3_IRQHandler +RNG_CRYP_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u031xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u031xx.s new file mode 100644 index 0000000..18f45fc --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u031xx.s @@ -0,0 +1,293 @@ +/** + ****************************************************************************** + * @file startup_stm32u031xx.s + * @author Auto-generated by STM32CubeIDE + * @brief STM32U031xx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32U031xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IWDG_IRQHandler /* Window watchdog interrupt */ + .word PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3 interrupt (combined with EXTI lines 16 and 19 and 20 and 21) */ + .word RTC_TAMP_IRQHandler /* RTC and TAMP interrupts(combined EXTI lines 19 and 21) */ + .word FLASH_ECC_IRQHandler /* FLASH global interrupt */ + .word RCC_CRS_IRQHandler /* RCC and CRS global interrupt */ + .word EXTI0_1_IRQHandler /* EXTI lines 0 and 1 interrupt */ + .word EXTI2_3_IRQHandler /* EXTI lines 2 and 3 interrupt */ + .word EXTI4_15_IRQHandler /* EXTI lines 4 to 15 interrupt */ + .word 0 /* */ + .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 channel 2 and 3 interrupts */ + .word DMA1_Ch4_7_DMAMUX_OVR_IRQHandler /* DMA1 channel 4, 5, 6, 7, DMAMUX overrun interrupts */ + .word ADC_COMP1_IRQHandler /* ADC and COMP1 interrupts (ADC combined with EXTI lines 17 and 18) */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 break, update, trigger and commutation interrupts */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM3_IRQHandler /* TIM3 global interrupt */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, LPTIM1 and DAC global interrupt (combined with EXTI line 29) */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 global interrupt (combined with EXTI line 30) */ + .word TIM15_IRQHandler /* TIM15 global interrupt (combined with EXTI line 29) */ + .word TIM16_IRQHandler /* TIM16 global interrupt */ + .word TSC_IRQHandler /* TSC global interrupt */ + .word 0 /* LCD global interrupt (combined with EXTI line 32) */ + .word I2C1_IRQHandler /* I2C1 global interrupt (combined with EXTI line 23) */ + .word I2C2_3_IRQHandler /* I2C2/3 global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_IRQHandler /* SPI2 global interrupt */ + .word USART1_IRQHandler /* USART1 global interrupt (combined with EXTI line 25) */ + .word USART2_LPUART2_IRQHandler /* USART2 and LPUART2 global interrupt (combined with EXTI lines 26 and 35) */ + .word USART3_LPUART1_IRQHandler /* USART3 and LPUART1 global interrupt (combined with EXTI lines 24 and 28) */ + .word USART4_IRQHandler /* USART4 and LPUART3 global interrupt (combined with EXTI lines 20 and 34) */ + .word RNG_IRQHandler /* RNG global interrupts */ + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IWDG_IRQHandler + .thumb_set WWDG_IWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_ECC_IRQHandler + .thumb_set FLASH_ECC_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMAMUX_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMAMUX_OVR_IRQHandler,Default_Handler + + .weak ADC_COMP1_IRQHandler + .thumb_set ADC_COMP1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_3_IRQHandler + .thumb_set I2C2_3_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_LPUART2_IRQHandler + .thumb_set USART2_LPUART2_IRQHandler,Default_Handler + + .weak USART3_LPUART1_IRQHandler + .thumb_set USART3_LPUART1_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak SystemInit diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u073xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u073xx.s new file mode 100644 index 0000000..f35d975 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u073xx.s @@ -0,0 +1,299 @@ +/** + ****************************************************************************** + * @file startup_stm32u073xx.s + * @author Auto-generated by STM32CubeIDE + * @brief STM32U073xx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32U073xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IWDG_IRQHandler /* Window watchdog interrupt */ + .word PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3 interrupt (combined with EXTI lines 16 and 19 and 20 and 21) */ + .word RTC_TAMP_IRQHandler /* RTC and TAMP interrupts(combined EXTI lines 19 and 21) */ + .word FLASH_ECC_IRQHandler /* FLASH global interrupt */ + .word RCC_CRS_IRQHandler /* RCC and CRS global interrupt */ + .word EXTI0_1_IRQHandler /* EXTI lines 0 and 1 interrupt */ + .word EXTI2_3_IRQHandler /* EXTI lines 2 and 3 interrupt */ + .word EXTI4_15_IRQHandler /* EXTI lines 4 to 15 interrupt */ + .word USB_DRD_FS_IRQHandler /* USB global interrupt (combined with EXTI line 33) */ + .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 channel 2 and 3 interrupts */ + .word DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler /* DMA1 channel 4, 5, 6, 7, DMAMUX, DMA2 channel 1, 2, 3, 4, 5 interrupts */ + .word ADC_COMP1_2_IRQHandler /* ADC and COMP interrupts (ADC combined with EXTI lines 17 and 18) */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler/* TIM1 break, update, trigger and commutation interrupts */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM3_IRQHandler /* TIM3 global interrupt */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, LPTIM1 and DAC global interrupt (combined with EXTI line 29) */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 global interrupt (combined with EXTI line 30) */ + .word TIM15_LPTIM3_IRQHandler /* TIM15 and LPTIM3 global interrupt (combined with EXTI line 29) */ + .word TIM16_IRQHandler /* TIM16 global interrupt */ + .word TSC_IRQHandler /* TSC global interrupt */ + .word LCD_IRQHandler /* LCD global interrupt (combined with EXTI line 32) */ + .word I2C1_IRQHandler /* I2C1 global interrupt (combined with EXTI line 23) */ + .word I2C2_3_4_IRQHandler /* I2C2/3/4 global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_3_IRQHandler /* SPI2/3 global interrupt */ + .word USART1_IRQHandler /* USART1 global interrupt (combined with EXTI line 25) */ + .word USART2_LPUART2_IRQHandler /* USART2 and LPUART2 global interrupt (combined with EXTI lines 26 and 35) */ + .word USART3_LPUART1_IRQHandler /* USART3 and LPUART1 global interrupt (combined with EXTI lines 24 and 28) */ + .word USART4_LPUART3_IRQHandler /* USART4 and LPUART3 global interrupt (combined with EXTI lines 20 and 34) */ + .word RNG_CRYP_IRQHandler /* RNG and CRYPTO global interrupts */ + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IWDG_IRQHandler + .thumb_set WWDG_IWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_ECC_IRQHandler + .thumb_set FLASH_ECC_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler,Default_Handler + + .weak ADC_COMP1_2_IRQHandler + .thumb_set ADC_COMP1_2_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_LPTIM3_IRQHandler + .thumb_set TIM15_LPTIM3_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_3_4_IRQHandler + .thumb_set I2C2_3_4_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_3_IRQHandler + .thumb_set SPI2_3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_LPUART2_IRQHandler + .thumb_set USART2_LPUART2_IRQHandler,Default_Handler + + .weak USART3_LPUART1_IRQHandler + .thumb_set USART3_LPUART1_IRQHandler,Default_Handler + + .weak USART4_LPUART3_IRQHandler + .thumb_set USART4_LPUART3_IRQHandler,Default_Handler + + .weak RNG_CRYP_IRQHandler + .thumb_set RNG_CRYP_IRQHandler,Default_Handler + + .weak SystemInit diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u083xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u083xx.s new file mode 100644 index 0000000..1272d12 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/startup_stm32u083xx.s @@ -0,0 +1,299 @@ +/** + ****************************************************************************** + * @file startup_stm32u083xx.s + * @author Auto-generated by STM32CubeIDE + * @brief STM32U083xx device vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + .size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32U083xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IWDG_IRQHandler /* Window watchdog interrupt */ + .word PVD_PVM_IRQHandler /* PVD/PVM1/PVM2/PVM3 interrupt (combined with EXTI lines 16 and 19 and 20 and 21) */ + .word RTC_TAMP_IRQHandler /* RTC and TAMP interrupts(combined EXTI lines 19 and 21) */ + .word FLASH_ECC_IRQHandler /* FLASH global interrupt */ + .word RCC_CRS_IRQHandler /* RCC and CRS global interrupt */ + .word EXTI0_1_IRQHandler /* EXTI lines 0 and 1 interrupt */ + .word EXTI2_3_IRQHandler /* EXTI lines 2 and 3 interrupt */ + .word EXTI4_15_IRQHandler /* EXTI lines 4 to 15 interrupt */ + .word USB_DRD_FS_IRQHandler /* USB global interrupt (combined with EXTI line 33) */ + .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 channel 2 and 3 interrupts */ + .word DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler /* DMA1 channel 4, 5, 6, 7, DMAMUX overrun, DMA2 channel 1, 2, 3, 4, 5 interrupts */ + .word ADC_COMP1_2_IRQHandler /* ADC and COMP interrupts (ADC combined with EXTI lines 17 and 18) */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler/* TIM1 break, update, trigger and commutation interrupts */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ + .word TIM2_IRQHandler /* TIM2 global interrupt */ + .word TIM3_IRQHandler /* TIM3 global interrupt */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, LPTIM1 and DAC global interrupt (combined with EXTI line 29) */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 global interrupt (combined with EXTI line 30) */ + .word TIM15_LPTIM3_IRQHandler /* TIM15 and LPTIM3 global interrupt (combined with EXTI line 29) */ + .word TIM16_IRQHandler /* TIM16 global interrupt */ + .word TSC_IRQHandler /* TSC global interrupt */ + .word LCD_IRQHandler /* LCD global interrupt (combined with EXTI line 32) */ + .word I2C1_IRQHandler /* I2C1 global interrupt (combined with EXTI line 23) */ + .word I2C2_3_4_IRQHandler /* I2C2/3/4 global interrupt */ + .word SPI1_IRQHandler /* SPI1 global interrupt */ + .word SPI2_3_IRQHandler /* SPI2/3 global interrupt */ + .word USART1_IRQHandler /* USART1 global interrupt (combined with EXTI line 25) */ + .word USART2_LPUART2_IRQHandler /* USART2 and LPUART2 global interrupt (combined with EXTI lines 26 and 35) */ + .word USART3_LPUART1_IRQHandler /* USART3 and LPUART1 global interrupt (combined with EXTI lines 24 and 28) */ + .word USART4_LPUART3_IRQHandler /* USART4 and LPUART3 global interrupt (combined with EXTI lines 20 and 34) */ + .word RNG_CRYP_IRQHandler /* RNG and CRYPTO global interrupts */ + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IWDG_IRQHandler + .thumb_set WWDG_IWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_ECC_IRQHandler + .thumb_set FLASH_ECC_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak USB_DRD_FS_IRQHandler + .thumb_set USB_DRD_FS_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler,Default_Handler + + .weak ADC_COMP1_2_IRQHandler + .thumb_set ADC_COMP1_2_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM15_LPTIM3_IRQHandler + .thumb_set TIM15_LPTIM3_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_3_4_IRQHandler + .thumb_set I2C2_3_4_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_3_IRQHandler + .thumb_set SPI2_3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_LPUART2_IRQHandler + .thumb_set USART2_LPUART2_IRQHandler,Default_Handler + + .weak USART3_LPUART1_IRQHandler + .thumb_set USART3_LPUART1_IRQHandler,Default_Handler + + .weak USART4_LPUART3_IRQHandler + .thumb_set USART4_LPUART3_IRQHandler,Default_Handler + + .weak RNG_CRYP_IRQHandler + .thumb_set RNG_CRYP_IRQHandler,Default_Handler + + .weak SystemInit diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u031xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u031xx_flash.icf new file mode 100644 index 0000000..47cf7a3 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u031xx_flash.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u031xx_sram.icf b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u031xx_sram.icf new file mode 100644 index 0000000..3bf1e61 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u031xx_sram.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x20001FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20002FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u073xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u073xx_flash.icf new file mode 100644 index 0000000..349f0d0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u073xx_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u073xx_sram.icf b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u073xx_sram.icf new file mode 100644 index 0000000..6268e00 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u073xx_sram.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x20007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20008000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u083xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u083xx_flash.icf new file mode 100644 index 0000000..349f0d0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u083xx_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u083xx_sram.icf b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u083xx_sram.icf new file mode 100644 index 0000000..6268e00 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/linker/stm32u083xx_sram.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x20007FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20008000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20009FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u031xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u031xx.s new file mode 100644 index 0000000..c9c3966 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u031xx.s @@ -0,0 +1,295 @@ +;******************************************************************************** +;* File Name : startup_stm32u031xx.s +;* Author : MCD Application Team +;* Description : STM32U031xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IWDG_IRQHandler ; Window WatchDog / Independent Watchdog Interrupt + DCD PVD_PVM_IRQHandler ; PVD through EXTI line detection + DCD RTC_TAMP_IRQHandler ; RTC/TAMP through the EXTI line + DCD FLASH_ECC_IRQHandler ; FLASH / ECC + DCD RCC_CRS_IRQHandler ; RCC / CRS + DCD EXTI0_1_IRQHandler ; EXTI Line[0:1] + DCD EXTI2_3_IRQHandler ; EXTI Line[2:3] + DCD EXTI4_15_IRQHandler ; EXTI Line[4:15] + DCD 0 ; + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel1 interrupt + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel2/Channel3 interrupt + DCD DMA1_Ch4_7_DMAMUX_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX overrun + DCD ADC_COMP1_IRQHandler ; ADC and COMP1 interrupts + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 break, update, trigger, commutation, error, direction change and index interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6 / DAC1&3 / LPTIM1 global interrupt + DCD TIM7_LPTIM2_IRQHandler ; TIM7 / LPTIM2 global interrupt + DCD TIM15_IRQHandler ; TIM15 global interrupt + DCD TIM16_IRQHandler ; TIM16 + DCD TSC_IRQHandler ; TSC global interrupt + DCD 0 ; + DCD I2C1_IRQHandler ; I2C1 global interrupt + DCD I2C2_3_IRQHandler ; I2C2 / I2C3 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_IRQHandler ; SPI2 global interrupt + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_LPUART2_IRQHandler ; USART2, LPUART 2 global interrupt + DCD USART3_LPUART1_IRQHandler ; USART3, LPUART 1 global interrupt + DCD USART4_IRQHandler ; USART4 global interrupt + DCD RNG_IRQHandler ; RNG global interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IWDG_IRQHandler + B WWDG_IWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_ECC_IRQHandler + B FLASH_ECC_IRQHandler + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMAMUX_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMAMUX_OVR_IRQHandler + B DMA1_Ch4_7_DMAMUX_OVR_IRQHandler + + PUBWEAK ADC_COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_COMP1_IRQHandler + B ADC_COMP1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM6_DAC_LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_LPTIM1_IRQHandler + B TIM6_DAC_LPTIM1_IRQHandler + + PUBWEAK TIM7_LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_LPTIM2_IRQHandler + B TIM7_LPTIM2_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_3_IRQHandler + B I2C2_3_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_LPUART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_LPUART2_IRQHandler + B USART2_LPUART2_IRQHandler + + PUBWEAK USART3_LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_LPUART1_IRQHandler + B USART3_LPUART1_IRQHandler + + PUBWEAK USART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART4_IRQHandler + B USART4_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + END
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u073xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u073xx.s new file mode 100644 index 0000000..944b0a4 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u073xx.s @@ -0,0 +1,305 @@ +;******************************************************************************** +;* File Name : startup_stm32u073xx.s +;* Author : MCD Application Team +;* Description : STM32U073xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IWDG_IRQHandler ; Window WatchDog / Independent Watchdog Interrupt + DCD PVD_PVM_IRQHandler ; PVD through EXTI line detection + DCD RTC_TAMP_IRQHandler ; RTC/TAMP through the EXTI line + DCD FLASH_ECC_IRQHandler ; FLASH / ECC + DCD RCC_CRS_IRQHandler ; RCC / CRS + DCD EXTI0_1_IRQHandler ; EXTI Line[0:1] + DCD EXTI2_3_IRQHandler ; EXTI Line[2:3] + DCD EXTI4_15_IRQHandler ; EXTI Line[4:15] + DCD USB_DRD_FS_IRQHandler ; USB global interrupt through EXTI line detection + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel1 interrupt + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel2/Channel3 interrupt + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMA2 Channel 1 to Channel 5, DMAMUX overrun + DCD ADC_COMP1_2_IRQHandler ; ADC and COMP1/COMP2 interrupts + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 break, update, trigger, commutation, error, direction change and index interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6 / DAC1&3 / LPTIM1 global interrupt + DCD TIM7_LPTIM2_IRQHandler ; TIM7 / LPTIM2 global interrupt + DCD TIM15_LPTIM3_IRQHandler ; TIM15 / LPTIM3 global interrupt + DCD TIM16_IRQHandler ; TIM16 + DCD TSC_IRQHandler ; TSC global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD I2C1_IRQHandler ; I2C1 global interrupt + DCD I2C2_3_4_IRQHandler ; I2C2 / I2C3 / I2C4 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_3_IRQHandler ; SPI2 /SPI3 global interrupt + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_LPUART2_IRQHandler ; USART2, LPUART 2 global interrupt + DCD USART3_LPUART1_IRQHandler ; USART3, LPUART 1 global interrupt + DCD USART4_LPUART3_IRQHandler ; USART4, LPUART 3 global interrupt + DCD RNG_CRYP_IRQHandler ; RNG, CRYPTO global interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IWDG_IRQHandler + B WWDG_IWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_ECC_IRQHandler + B FLASH_ECC_IRQHandler + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK USB_DRD_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_DRD_FS_IRQHandler + B USB_DRD_FS_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + B DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + + PUBWEAK ADC_COMP1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_COMP1_2_IRQHandler + B ADC_COMP1_2_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM6_DAC_LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_LPTIM1_IRQHandler + B TIM6_DAC_LPTIM1_IRQHandler + + PUBWEAK TIM7_LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_LPTIM2_IRQHandler + B TIM7_LPTIM2_IRQHandler + + PUBWEAK TIM15_LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_LPTIM3_IRQHandler + B TIM15_LPTIM3_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_3_4_IRQHandler + B I2C2_3_4_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_3_IRQHandler + B SPI2_3_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_LPUART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_LPUART2_IRQHandler + B USART2_LPUART2_IRQHandler + + PUBWEAK USART3_LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_LPUART1_IRQHandler + B USART3_LPUART1_IRQHandler + + PUBWEAK USART4_LPUART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART4_LPUART3_IRQHandler + B USART4_LPUART3_IRQHandler + + PUBWEAK RNG_CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_CRYP_IRQHandler + B RNG_CRYP_IRQHandler + + END
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u083xx.s b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u083xx.s new file mode 100644 index 0000000..ce45d76 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/iar/startup_stm32u083xx.s @@ -0,0 +1,305 @@ +;******************************************************************************** +;* File Name : startup_stm32u083xx.s +;* Author : MCD Application Team +;* Description : STM32U083xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2023 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IWDG_IRQHandler ; Window WatchDog / Independent Watchdog Interrupt + DCD PVD_PVM_IRQHandler ; PVD through EXTI line detection + DCD RTC_TAMP_IRQHandler ; RTC/TAMP through the EXTI line + DCD FLASH_ECC_IRQHandler ; FLASH / ECC + DCD RCC_CRS_IRQHandler ; RCC / CRS + DCD EXTI0_1_IRQHandler ; EXTI Line[0:1] + DCD EXTI2_3_IRQHandler ; EXTI Line[2:3] + DCD EXTI4_15_IRQHandler ; EXTI Line[4:15] + DCD USB_DRD_FS_IRQHandler ; USB global interrupt through EXTI line detection + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel1 interrupt + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel2/Channel3 interrupt + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMA2 Channel 1 to Channel 5, DMAMUX overrun + DCD ADC_COMP1_2_IRQHandler ; ADC and COMP1/COMP2 interrupts + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 break, update, trigger, commutation, error, direction change and index interrupts + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6 / DAC1&3 / LPTIM1 global interrupt + DCD TIM7_LPTIM2_IRQHandler ; TIM7 / LPTIM2 global interrupt + DCD TIM15_LPTIM3_IRQHandler ; TIM15 / LPTIM3 global interrupt + DCD TIM16_IRQHandler ; TIM16 + DCD TSC_IRQHandler ; TSC global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD I2C1_IRQHandler ; I2C1 global interrupt + DCD I2C2_3_4_IRQHandler ; I2C2 / I2C3 / I2C4 global interrupt + DCD SPI1_IRQHandler ; SPI1 global interrupt + DCD SPI2_3_IRQHandler ; SPI2 /SPI3 global interrupt + DCD USART1_IRQHandler ; USART1 global interrupt + DCD USART2_LPUART2_IRQHandler ; USART2, LPUART 2 global interrupt + DCD USART3_LPUART1_IRQHandler ; USART3, LPUART 1 global interrupt + DCD USART4_LPUART3_IRQHandler ; USART4, LPUART 3 global interrupt + DCD RNG_CRYP_IRQHandler ; RNG, CRYPTO global interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IWDG_IRQHandler + B WWDG_IWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_ECC_IRQHandler + B FLASH_ECC_IRQHandler + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK USB_DRD_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_DRD_FS_IRQHandler + B USB_DRD_FS_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + B DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX_OVR_IRQHandler + + PUBWEAK ADC_COMP1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_COMP1_2_IRQHandler + B ADC_COMP1_2_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM6_DAC_LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_LPTIM1_IRQHandler + B TIM6_DAC_LPTIM1_IRQHandler + + PUBWEAK TIM7_LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_LPTIM2_IRQHandler + B TIM7_LPTIM2_IRQHandler + + PUBWEAK TIM15_LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_LPTIM3_IRQHandler + B TIM15_LPTIM3_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_3_4_IRQHandler + B I2C2_3_4_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_3_IRQHandler + B SPI2_3_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_LPUART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_LPUART2_IRQHandler + B USART2_LPUART2_IRQHandler + + PUBWEAK USART3_LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_LPUART1_IRQHandler + B USART3_LPUART1_IRQHandler + + PUBWEAK USART4_LPUART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART4_LPUART3_IRQHandler + B USART4_LPUART3_IRQHandler + + PUBWEAK RNG_CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_CRYP_IRQHandler + B RNG_CRYP_IRQHandler + + END diff --git a/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c new file mode 100644 index 0000000..0222b0f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/system_stm32u0xx.c @@ -0,0 +1,346 @@ +/** + ****************************************************************************** + * @file system_stm32u0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32u0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32u0xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32u0xx_system + * @{ + */ + +/** @addtogroup STM32U0xx_System_Private_Includes + * @{ + */ + +#include "stm32u0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE (32000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (MSI_VALUE) +#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE (32000UL) /*!< Value of the Internal oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32U0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U0xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +//#define VECT_TAB_SRAM +#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +/*!< Comment the following line if you would like to disable the software + workaround related to debug access in case RDP=1 and Boot_Lock=1 */ +#define ENABLE_DBG_SWEN /*!< Enable the debugger read access. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32U0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U0xx_System_Private_Variables + * @{ + */ +/* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. +*/ +uint32_t SystemCoreClock = 4000000U; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ + 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U + }; + +/** + * @} + */ + +/** @addtogroup STM32U0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ +#ifdef ENABLE_DBG_SWEN +uint32_t tmp_seccr; +uint32_t tmp_optr; +#endif /* ENABLE_DBG_SWEN */ + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif /* VECT_TAB_SRAM */ + +/* Software workaround added to keep Debug enabled after Boot_Lock activation and RDP=1 */ +#ifdef ENABLE_DBG_SWEN + tmp_seccr = FLASH->SECR; + tmp_optr = FLASH->OPTR; + if (((tmp_seccr & FLASH_SECR_BOOT_LOCK) == FLASH_SECR_BOOT_LOCK) \ + && (((tmp_optr & FLASH_OPTR_RDP) != 0xCCU) \ + && ((tmp_optr & FLASH_OPTR_RDP) != 0xAAU))) + { + FLASH->ACR |= FLASH_ACR_DBG_SWEN; /* Debug access software enabled to avoid the chip + to be locked when RDP=1 and Boot_Lock=1 */ + } +#endif /* ENABLE_DBG_SWEN */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32u0xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32u0xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32u0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr; + + /* Get MSI Range frequency--------------------------------------------------*/ + if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U) + { + /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISTBYRG) >> 8U; + } + else + { + /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; + } + /* MSI frequency range in HZ*/ + if (msirange > 11U) + { + msirange = 0U; + } + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case RCC_CFGR_SWS_0: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case RCC_CFGR_SWS_1: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_2: /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; + + case (RCC_CFGR_SWS_2 | RCC_CFGR_SWS_0): /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; + + case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + + switch (pllsource) + { + case RCC_PLLCFGR_PLLSRC_0: /* MSI used as PLL clock source */ + pllvco = (msirange / pllm); + break; + + case RCC_PLLCFGR_PLLSRC_1: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm); + break; + + case (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0): /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm); + break; + + default: /* no clock used as PLL clock source */ + pllvco = 0x0U; + break; + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + SystemCoreClock = pllvco / pllr; + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + |