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347 lines
12 KiB
C
347 lines
12 KiB
C
/**
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******************************************************************************
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* @file system_stm32u0xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32u0xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the MSI (4 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32u0xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* This file configures the system clock as follows:
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*=============================================================================
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*-----------------------------------------------------------------------------
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* System Clock source | MSI
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 4000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 4000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB Prescaler | 1
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*-----------------------------------------------------------------------------
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* HSI Division factor | 1
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*-----------------------------------------------------------------------------
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* PLL_M | 1
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*-----------------------------------------------------------------------------
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* PLL_N | 8
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*-----------------------------------------------------------------------------
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* PLL_P | 7
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*-----------------------------------------------------------------------------
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* PLL_Q | 2
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*-----------------------------------------------------------------------------
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* PLL_R | 2
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*-----------------------------------------------------------------------------
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* Require 48MHz for RNG | Disabled
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*-----------------------------------------------------------------------------
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*=============================================================================
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32u0xx_system
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* @{
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*/
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/** @addtogroup STM32U0xx_System_Private_Includes
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* @{
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*/
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#include "stm32u0xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE (32000000U) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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#if !defined (MSI_VALUE)
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#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
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#endif /* MSI_VALUE */
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#if !defined (LSI_VALUE)
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#define LSI_VALUE (32000UL) /*!< Value of the Internal oscillator in Hz */
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#endif /* LSI_VALUE */
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#if !defined (LSE_VALUE)
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#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz */
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#endif /* LSE_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32U0xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32U0xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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//#define VECT_TAB_SRAM
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#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/*!< Comment the following line if you would like to disable the software
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workaround related to debug access in case RDP=1 and Boot_Lock=1 */
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#define ENABLE_DBG_SWEN /*!< Enable the debugger read access. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32U0xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32U0xx_System_Private_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 4000000U;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
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4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U
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};
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/**
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* @}
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*/
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/** @addtogroup STM32U0xx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32U0xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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#ifdef ENABLE_DBG_SWEN
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uint32_t tmp_seccr;
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uint32_t tmp_optr;
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#endif /* ENABLE_DBG_SWEN */
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif /* VECT_TAB_SRAM */
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/* Software workaround added to keep Debug enabled after Boot_Lock activation and RDP=1 */
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#ifdef ENABLE_DBG_SWEN
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tmp_seccr = FLASH->SECR;
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tmp_optr = FLASH->OPTR;
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if (((tmp_seccr & FLASH_SECR_BOOT_LOCK) == FLASH_SECR_BOOT_LOCK) \
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&& (((tmp_optr & FLASH_OPTR_RDP) != 0xCCU) \
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&& ((tmp_optr & FLASH_OPTR_RDP) != 0xAAU)))
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{
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FLASH->ACR |= FLASH_ACR_DBG_SWEN; /* Debug access software enabled to avoid the chip
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to be locked when RDP=1 and Boot_Lock=1 */
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}
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#endif /* ENABLE_DBG_SWEN */
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) MSI_VALUE is a constant defined in stm32u0xx_hal.h file (default value
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* 4 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSI_VALUE is a constant defined in stm32u0xx_hal.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***) HSE_VALUE is a constant defined in stm32u0xx_hal.h file (default value
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
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/* Get MSI Range frequency--------------------------------------------------*/
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if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
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{
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/* MSISRANGE from RCC_CSR applies */
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msirange = (RCC->CSR & RCC_CSR_MSISTBYRG) >> 8U;
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}
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else
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{
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/* MSIRANGE from RCC_CR applies */
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msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
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}
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/* MSI frequency range in HZ*/
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if (msirange > 11U)
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{
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msirange = 0U;
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}
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msirange = MSIRangeTable[msirange];
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case 0x00: /* MSI used as system clock source */
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SystemCoreClock = msirange;
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break;
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case RCC_CFGR_SWS_0: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case RCC_CFGR_SWS_1: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case RCC_CFGR_SWS_2: /* LSI used as system clock */
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SystemCoreClock = LSI_VALUE;
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break;
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case (RCC_CFGR_SWS_2 | RCC_CFGR_SWS_0): /* LSE used as system clock */
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SystemCoreClock = LSE_VALUE;
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break;
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case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
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switch (pllsource)
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{
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case RCC_PLLCFGR_PLLSRC_0: /* MSI used as PLL clock source */
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pllvco = (msirange / pllm);
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break;
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case RCC_PLLCFGR_PLLSRC_1: /* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm);
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break;
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case (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0): /* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm);
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break;
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default: /* no clock used as PLL clock source */
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pllvco = 0x0U;
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break;
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}
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
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SystemCoreClock = pllvco / pllr;
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break;
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default:
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SystemCoreClock = msirange;
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos) & 0xFU];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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