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1649 lines
56 KiB
C
1649 lines
56 KiB
C
/**
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******************************************************************************
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* @file stm32u0xx_hal_rcc.c
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* @author MCD Application Team
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* @brief RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Reset and Clock Control (RCC) peripheral:
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* + Initialization and de-initialization functions
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* + Peripheral Control functions
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*
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@verbatim
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==============================================================================
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##### RCC specific features #####
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==============================================================================
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[..]
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After reset the device is running from Multiple Speed Internal oscillator
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(4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
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and I-Cache are disabled, and all peripherals are off except internal
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SRAM, Flash and JTAG.
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(+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
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all peripherals mapped on these busses are running at MSI speed.
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(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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(+) All GPIOs are in analog mode, except the JTAG pins which
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are assigned to be used for debug purpose.
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[..]
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Once the device started from reset, the user application has to:
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(+) Configure the clock source to be used to drive the System clock
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(if the application needs higher frequency/performance)
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(+) Configure the System clock frequency and Flash settings
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(+) Configure the AHB and APB busses prescalers
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(+) Enable the clock for the peripheral(s) to be used
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(+) Configure the clock source(s) for peripherals which clocks are not
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derived from the System clock (RTC, ADC, USB FS/RNG)
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@endverbatim
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32u0xx_hal.h"
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/** @addtogroup STM32U0xx_HAL_Driver
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* @{
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*/
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/** @defgroup RCC RCC
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* @brief RCC HAL module driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup RCC_Private_Constants RCC Private Constants
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* @{
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*/
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#define LSI_TIMEOUT_VALUE ((uint32_t)17UL) /* 17 ms (LSI maximum timeout is LSI startup time +
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LSI_VALUE/128 when LSI prediv is used) */
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#if defined(RCC_CRRCR_HSI48ON)
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#define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
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#endif /* RCC_CRRCR_HSI48ON */
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#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
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#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/** @defgroup RCC_Private_Macros RCC Private Macros
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* @{
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*/
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#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK)
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#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
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#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
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#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) \
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(((IOPORT_BASE) + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX((__RCC_MCOx__)))))
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#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
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(MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup RCC_Private_Functions RCC Private Functions
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* @{
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*/
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static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange);
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup RCC_Exported_Functions RCC Exported Functions
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* @{
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*/
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/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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This section provides functions allowing to configure the internal and external oscillators
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(HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB).
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[..] Internal/external clock and PLL configuration
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(+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
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the PLL as System clock source.
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(+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
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It can be used to generate the clock for the USB OTG FS (48 MHz).
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The number of flash wait states is automatically adjusted when MSI range is updated with
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HAL_RCC_OscConfig() and the MSI is used as System clock source.
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(+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
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clock source.
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(+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or
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through the PLL as System clock source. Can be used also optionally as RTC clock source.
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(+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source.
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(+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
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(++) The first output is used to generate the high speed system clock (up to 80MHz).
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(++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
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the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
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(++) The third output is used to generate an accurate clock to achieve
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high-quality audio performance on SAI interface.
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(+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
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(HSE used directly or through PLL as System clock source), the System clock
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is automatically switched to HSI and an interrupt is generated if enabled.
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The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
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exception vector.
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(+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or
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main PLL clock (through a configurable prescaler) on PA8 pin.
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[..] System, AHB and APB busses clocks configuration
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(+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
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HSE and main PLL.
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The AHB clock (HCLK) is derived from System clock through configurable
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prescaler and used to clock the CPU, memory and peripherals mapped
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on AHB bus (DMA, GPIO...). APB (PCLK) clocks are derived
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from AHB clock through configurable prescalers and used to clock
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the peripherals mapped on these busses. You can use
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"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
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-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
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(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
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divided by 2 to 31.
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You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
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to configure this clock.
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(+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz
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to work correctly, while the RNG peripherals require a frequency
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equal or lower than to 48 MHz. This clock is derived of the main PLL
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through PLLQ divider. You have to enable the peripheral clock and use
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HAL_RCCEx_PeriphCLKConfig() function to configure this clock.
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(+@) IWDG clock which is always the LSI clock.
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(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 48 MHz.
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The clock source frequency should be adapted depending on the device voltage range
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as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
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@endverbatim
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Table 1. HCLK clock frequency for other STM32U0 devices
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+-------------------------------------------------------+
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| Latency | HCLK clock frequency (MHz) |
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| |-------------------------------------|
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| | voltage range 1 | voltage range 2 |
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| | 1.2 V | 1.0 V |
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|-----------------|------------------|------------------|
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|0WS(1 CPU cycles)| HCLK <= 24 | 0 < HCLK <= 8 |
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|-----------------|------------------|------------------|
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|1WS(2 CPU cycles)| < HCLK <= 48 | 8 < HCLK <= 16 |
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|-----------------|------------------|------------------|
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|2WS(3 CPU cycles)| HCLK <= 56 | 16 < HCLK <= 18 |
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+-------------------------------------------------------+
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* @{
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*/
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/**
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* @brief Reset the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - MSI ON and used as system clock source
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* - HSE, HSI and PLL OFF
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* - AHB, APB prescaler set to 1.
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* - CSS, MCO OFF
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* - All interrupts disabled
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* @note This function doesn't modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @retval None
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*/
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HAL_StatusTypeDef HAL_RCC_DeInit(void)
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{
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uint32_t tickstart;
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/* Get start tick*/
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tickstart = HAL_GetTick();
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/* Set MSION bit */
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SET_BIT(RCC->CR, RCC_CR_MSION);
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/* Insure MSIRDY bit is set before writing default MSISRANGE value */
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while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
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{
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if ((HAL_GetTick() - tickstart) > RCC_MSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Set MSIRANGE default value */
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MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6);
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/* Reset CFGR register (MSI is selected as system clock source) */
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CLEAR_REG(RCC->CFGR);
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/* Update the SystemCoreClock global variable for MSI as system clock source */
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SystemCoreClock = MSI_VALUE;
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/* Configure the source of time base considering new system clock settings */
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if (HAL_InitTick(uwTickPrio) != HAL_OK)
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{
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return HAL_ERROR;
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}
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/* Insure MSI selected as system clock source */
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/* Get start tick */
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tickstart = HAL_GetTick();
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/* Wait till clock switch is ready */
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while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U)
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{
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if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON bits */
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CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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/* Reset HSEBYP bits */
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CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till PLL is disabled */
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while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
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{
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if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Reset PLLCFGR register */
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CLEAR_REG(RCC->PLLCFGR);
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SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4);
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/* Disable all interrupts */
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CLEAR_REG(RCC->CIER);
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/* Clear all interrupts flags */
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CLEAR_REG(RCC->CICR);
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/* Reset all CSR flags */
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SET_BIT(RCC->CSR, RCC_CSR_RMVF);
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/* Update the SystemCoreClock global variable */
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SystemCoreClock = MSI_VALUE;
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/* Adapt Systick interrupt period */
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if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
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{
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return HAL_ERROR;
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}
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else
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{
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return HAL_OK;
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}
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}
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/**
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* @brief Initialize the RCC Oscillators according to the specified parameters in the
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* RCC_OscInitTypeDef.
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* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
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* contains the configuration information for the RCC Oscillators.
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* @note The PLL is not disabled when used as system clock.
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* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
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* supported by this macro. User should request a transition to LSE Off
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* first and then LSE On or LSE Bypass.
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* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
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* supported by this macro. User should request a transition to HSE Off
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* first and then HSE On or HSE Bypass.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
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{
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uint32_t tickstart;
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HAL_StatusTypeDef status;
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uint32_t sysclk_source;
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uint32_t pll_config;
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/* Check the parameters */
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assert_param(RCC_OscInitStruct != NULL);
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assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
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sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
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pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
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/*----------------------------- MSI Configuration --------------------------*/
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if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
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{
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/* Check the parameters */
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assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
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assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
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assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
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/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
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if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
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((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
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{
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if ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
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{
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return HAL_ERROR;
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}
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/* Otherwise, just the calibration and MSI range change are allowed */
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else
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{
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/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
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must be correctly programmed according to the frequency of the CPU clock
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(HCLK) and the supply voltage of the device. */
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if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
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{
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/* First increase number of wait states update if necessary */
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if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
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{
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return HAL_ERROR;
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}
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/* Selects the Multiple Speed oscillator (MSI) clock range .*/
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__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
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/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
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__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
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}
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else
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{
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/* Else, keep current flash latency while decreasing applies */
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/* Selects the Multiple Speed oscillator (MSI) clock range .*/
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__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
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/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
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__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
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/* Decrease number of wait states update if necessary */
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/* Only possible when MSI is the System clock source */
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if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
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{
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if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
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{
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return HAL_ERROR;
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}
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}
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}
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/* Update the SystemCoreClock global variable */
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SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) \
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>> RCC_CFGR_HPRE_Pos] & 0x1FU);
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|
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/* Configure the source of time base considering new system clocks settings*/
|
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status = HAL_InitTick(uwTickPrio);
|
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if (status != HAL_OK)
|
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{
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return status;
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}
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}
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}
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else
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{
|
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/* Check the MSI State */
|
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if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
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{
|
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/* Enable the Internal High Speed oscillator (MSI). */
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__HAL_RCC_MSI_ENABLE();
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|
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/* Get timeout */
|
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tickstart = HAL_GetTick();
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|
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/* Wait till MSI is ready */
|
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while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
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{
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if ((HAL_GetTick() - tickstart) > RCC_MSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
|
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}
|
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}
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
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__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
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/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
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__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
|
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}
|
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else
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{
|
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/* Disable the Internal High Speed oscillator (MSI). */
|
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__HAL_RCC_MSI_DISABLE();
|
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|
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/* Get timeout */
|
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tickstart = HAL_GetTick();
|
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|
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/* Wait till MSI is ready */
|
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while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
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{
|
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if ((HAL_GetTick() - tickstart) > RCC_MSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
|
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}
|
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}
|
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}
|
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}
|
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}
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
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if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
{
|
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/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
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/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
|
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((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
{
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
/* Wait till HSE is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) ||
|
|
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSI is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
{
|
|
/* Apply prescaler value */
|
|
if (RCC_OscInitStruct->LSIDiv == RCC_LSI_DIV1)
|
|
{
|
|
CLEAR_BIT(RCC->CSR, RCC_CSR_LSIPREDIV);
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(RCC->CSR, RCC_CSR_LSIPREDIV);
|
|
}
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (HAL_IS_BIT_CLR(RCC->APBENR1, RCC_APBENR1_PWREN))
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
pwrclkchanged = SET;
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
if ((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U)
|
|
{
|
|
if ((RCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U)
|
|
{
|
|
/* LSE oscillator bypass enable */
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
}
|
|
else
|
|
{
|
|
/* LSE oscillator enable */
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
}
|
|
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till LSE is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Enable LSESYS additionally if requested */
|
|
if ((RCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSEN) != 0U)
|
|
{
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
|
|
/* Wait till LSESYS is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Make sure LSESYSEN/LSESYSRDY are reset */
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
|
|
/* Wait till LSESYSRDY is cleared */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN) != 0U)
|
|
{
|
|
/* Reset LSESYSEN once LSE is disabled */
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
|
|
/* Wait till LSESYSRDY is cleared */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
}
|
|
}
|
|
#if defined(RCC_CRRCR_HSI48ON)
|
|
/*------------------------------ HSI48 Configuration -----------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
|
|
|
|
/* Check the HSI48 State */
|
|
if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_ENABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSI48 is ready */
|
|
while (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSI48 is disabled */
|
|
while (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif /* RCC_CRRCR_HSI48ON */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
{
|
|
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_DIVM_VALUE(RCC_OscInitStruct->PLL.PLLM));
|
|
assert_param(IS_RCC_PLL_MULN_VALUE(RCC_OscInitStruct->PLL.PLLN));
|
|
assert_param(IS_RCC_PLL_DIVP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLL_DIVQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLL_DIVR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
RCC_OscInitStruct->PLL.PLLM,
|
|
RCC_OscInitStruct->PLL.PLLN,
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
|
|
/* Enable PLL System Clock output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_DIVR);
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
}
|
|
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
HAL_StatusTypeDef halstatus;
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(RCC_ClkInitStruct != NULL);
|
|
assert_param(IS_RCC_CLOCKTYPE((uint8_t)RCC_ClkInitStruct->ClockType));
|
|
assert_param(IS_FLASH_LATENCY(FLatency));
|
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/* LSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
|
|
{
|
|
/* Check the LSI ready flag */
|
|
if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/* LSE is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the LSE ready flag */
|
|
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
}
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
{
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) \
|
|
>> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
halstatus = HAL_InitTick(TICK_INT_PRIORITY);
|
|
|
|
return halstatus;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
|
|
* @brief RCC clocks control functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Peripheral Control functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to:
|
|
|
|
(+) Output clock to MCO pin.
|
|
(+) Retrieve current clock frequencies.
|
|
(+) Enable the Clock Security System.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Select the clock source to output on MCO pin(PA8).
|
|
* @note PA8 should be configured in alternate function mode.
|
|
* @param RCC_MCOx specifies the output direction for the clock source.
|
|
* For STM32U0xx family this parameter can have these values:
|
|
* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
|
|
* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA9).
|
|
* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PF2).
|
|
* @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA10).
|
|
* @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PC2).
|
|
* @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA8).
|
|
* @param RCC_MCOSource specifies the clock source to output.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
|
|
* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLLR main PLL clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source
|
|
* @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO output disabled, no clock on MCO
|
|
* @arg @ref RCC_MCO2SOURCE_SYSCLK system clock selected as MCO source
|
|
* @arg @ref RCC_MCO2SOURCE_MSI MSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO source
|
|
* @arg @ref RCC_MCO2SOURCE_PLLR main PLL clock selected as MCO source
|
|
* @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO source
|
|
* @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO source
|
|
* @param RCC_MCODiv specifies the MCO prescaler.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCO1DIV_1 division by 1 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_2 division by 2 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_4 division by 4 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_8 division by 8 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_16 division by 16 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_32 division by 32 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_64 division by 64 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_128 division by 128 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_256 division by 256 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_512 division by 512 applied to MCO clock
|
|
* @arg @ref RCC_MCO1DIV_1024 division by 1024 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_1 division by 1 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_2 division by 2 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_4 division by 4 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_8 division by 8 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_16 division by 16 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_32 division by 32 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_64 division by 64 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_128 division by 128 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_256 division by 256 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_512 division by 512 applied to MCO clock
|
|
* @arg @ref RCC_MCO2DIV_1024 division by 1024 applied to MCO clock
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
|
|
{
|
|
GPIO_InitTypeDef GPIO_InitStruct;
|
|
uint32_t mcoindex;
|
|
uint32_t mco_gpio_index;
|
|
GPIO_TypeDef *mco_gpio_port;
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_MCO(RCC_MCOx));
|
|
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
|
/* Get MCOx selection */
|
|
mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK;
|
|
|
|
/* Get MCOx GPIO Port */
|
|
mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
|
|
/* MCOx Clock Enable */
|
|
mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
|
|
SET_BIT(RCC->IOPENR, (1UL << mco_gpio_index));
|
|
|
|
/* Configure the MCOx pin in alternate function mode */
|
|
GPIO_InitStruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
|
|
GPIO_InitStruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
|
|
HAL_GPIO_Init(mco_gpio_port, &GPIO_InitStruct);
|
|
|
|
if (mcoindex == RCC_MCO1_INDEX)
|
|
{
|
|
assert_param(IS_RCC_MCO1DIV(RCC_MCODiv));
|
|
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
|
|
|
|
/* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */
|
|
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1SEL | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
|
|
}
|
|
else if (mcoindex == RCC_MCO2_INDEX)
|
|
{
|
|
assert_param(IS_RCC_MCO2DIV(RCC_MCODiv));
|
|
assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
|
|
|
|
/* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */
|
|
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), (RCC_MCOSource | RCC_MCODiv));
|
|
}
|
|
else
|
|
{
|
|
/* unexpected case: added to resolve MISRA 15.7 rule */
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Return the SYSCLK frequency.
|
|
*
|
|
* @note The system frequency computed by this function is not the real
|
|
* frequency in the chip. It is calculated based on the predefined
|
|
* constant and the selected clock source:
|
|
* @note If SYSCLK source is MSI, function returns values based on MSI
|
|
* Value as defined by the MSI range.
|
|
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
|
|
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
|
|
* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
|
|
* HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
|
|
* @note (*) HSI_VALUE is a constant defined in stm32u0xx_hal_conf.h file (default value
|
|
* 16 MHz) but the real value may vary depending on the variations
|
|
* in voltage and temperature.
|
|
* @note (**) HSE_VALUE is a constant defined in stm32u0xx_hal_conf.h file (default value
|
|
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
|
* frequency of the crystal used. Otherwise, this function may
|
|
* have wrong result.
|
|
*
|
|
* @note The result of this function could be not correct when using fractional
|
|
* value for HSE crystal.
|
|
*
|
|
* @note This function can be used by the user application to compute the
|
|
* baudrate for the communication peripherals or configure other parameters.
|
|
*
|
|
* @note Each time SYSCLK changes, this function must be called to update the
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
uint32_t msirange = 0U;
|
|
uint32_t sysclockfreq = 0U;
|
|
uint32_t pllvco;
|
|
uint32_t pllsource;
|
|
uint32_t pllr;
|
|
uint32_t pllm;
|
|
uint32_t sysclk_source;
|
|
uint32_t pll_oscsource;
|
|
uint32_t pllsourcefreq;
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
|
|
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
|
|
{
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
|
|
/* Get SYSCLK source */
|
|
if (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
|
|
{
|
|
/* MSISRANGE from RCC_CSR applies */
|
|
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISTBYRG) >> RCC_CSR_MSISTBYRG_Pos;
|
|
}
|
|
else
|
|
{
|
|
/* MSIRANGE from RCC_CR applies */
|
|
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
|
|
}
|
|
/*MSI frequency range in HZ*/
|
|
if (msirange > 11U)
|
|
{
|
|
msirange = 0U;
|
|
}
|
|
msirange = MSIRangeTable[msirange];
|
|
|
|
if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
|
|
{
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = msirange;
|
|
}
|
|
}
|
|
else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
}
|
|
else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
}
|
|
else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_LSI)
|
|
{
|
|
/* LSI used as system clock source */
|
|
sysclockfreq = LSI_VALUE;
|
|
}
|
|
else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_LSE)
|
|
{
|
|
/* LSE used as system clock source */
|
|
sysclockfreq = LSE_VALUE;
|
|
}
|
|
else
|
|
{
|
|
/* unexpected case: sysclockfreq at 0 */
|
|
}
|
|
|
|
if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
{
|
|
/* PLL used as system clock source */
|
|
/* The allowed input (pllinput/M) frequency range is from 2.66 to 16 MHZ */
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
|
|
switch (pllsource)
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllsourcefreq = HSI_VALUE;
|
|
break;
|
|
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllsourcefreq = HSE_VALUE;
|
|
break;
|
|
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllsourcefreq = msirange;
|
|
break;
|
|
}
|
|
pllvco = (pllsourcefreq * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm ;
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
|
|
sysclockfreq = pllvco / pllr;
|
|
}
|
|
|
|
return sysclockfreq;
|
|
}
|
|
|
|
/**
|
|
* @brief Return the HCLK frequency.
|
|
* @note Each time HCLK changes, this function must be called to update the
|
|
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
return SystemCoreClock;
|
|
}
|
|
|
|
/**
|
|
* @brief Return the PCLK frequency.
|
|
* @note Each time PCLK changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos] & 0x1FU));
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the RCC_OscInitStruct according to the internal
|
|
* RCC configuration registers.
|
|
* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
|
|
* will be configured.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
uint32_t regval;
|
|
|
|
/* Check the parameters */
|
|
assert_param(RCC_OscInitStruct != NULL);
|
|
#if defined(RCC_CRRCR_HSI48ON)
|
|
/* Set all possible values for the Oscillator type parameter ---------------*/
|
|
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
|
|
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
|
|
#else
|
|
/* Set all possible values for the Oscillator type parameter ---------------*/
|
|
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
|
|
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
|
|
#endif /* RCC_CRRCR_HSI48ON */
|
|
/* Get the HSE configuration -----------------------------------------------*/
|
|
if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
|
|
}
|
|
else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
|
|
}
|
|
|
|
/* Get the HSI configuration -----------------------------------------------*/
|
|
if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
|
|
{
|
|
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
|
|
}
|
|
RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
|
|
|
|
/* Get the MSI configuration -----------------------------------------------*/
|
|
if ((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
|
|
{
|
|
RCC_OscInitStruct->MSIState = RCC_MSI_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
|
|
}
|
|
|
|
RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos;
|
|
RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE);
|
|
|
|
/* Get the LSE configuration -----------------------------------------------*/
|
|
/* Get BDCR register */
|
|
regval = RCC->BDCR;
|
|
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
|
|
{
|
|
if (((regval & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
|
|
&& ((regval & RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN))
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_RTC_ONLY;
|
|
}
|
|
}
|
|
else if (READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
|
|
{
|
|
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN) == RCC_BDCR_LSESYSEN)
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_ON_RTC_ONLY;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
|
|
}
|
|
|
|
/* Get the LSI configuration -----------------------------------------------*/
|
|
if (READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION)
|
|
{
|
|
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
|
|
}
|
|
|
|
if ((RCC->CSR & RCC_CSR_LSIPREDIV) == RCC_CSR_LSIPREDIV)
|
|
{
|
|
RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV128;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSIDiv = RCC_LSI_DIV1;
|
|
}
|
|
#if defined(RCC_CRRCR_HSI48ON)
|
|
/* Get the HSI48 configuration ---------------------------------------------*/
|
|
if (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
|
|
{
|
|
RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
|
|
}
|
|
#endif /* RCC_CRRCR_HSI48ON */
|
|
/* Get the PLL configuration -----------------------------------------------*/
|
|
if (READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON)
|
|
{
|
|
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
|
|
}
|
|
RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
|
|
RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
|
|
RCC_OscInitStruct->PLL.PLLQ = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)));
|
|
RCC_OscInitStruct->PLL.PLLR = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)));
|
|
RCC_OscInitStruct->PLL.PLLP = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)));
|
|
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the RCC_ClkInitStruct according to the internal
|
|
* RCC configuration registers.
|
|
* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
|
|
* will be configured.
|
|
* @param pFLatency Pointer on the Flash Latency.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(RCC_ClkInitStruct != NULL);
|
|
assert_param(pFLatency != NULL);
|
|
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
|
|
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
|
}
|
|
|
|
/**
|
|
* @brief Enables the Clock Security System.
|
|
* @note If a failure is detected on the HSE oscillator clock, this oscillator
|
|
* is automatically disabled and an interrupt is generated to inform the
|
|
* software about the failure (Clock Security System Interrupt, CSSI),
|
|
* allowing the MCU to perform rescue operations. The CSSI is linked to
|
|
* the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_EnableCSS(void)
|
|
{
|
|
SET_BIT(RCC->CR, RCC_CR_CSSON) ;
|
|
}
|
|
|
|
/* * @brief Handle the RCC Clock Security System interrupt request.
|
|
* @note This API should be called under the NMI_Handler().
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_NMI_IRQHandler(void)
|
|
{
|
|
/* Check RCC CSSF interrupt flag */
|
|
if (__HAL_RCC_GET_IT(RCC_IT_CSS))
|
|
{
|
|
/* RCC Clock Security System interrupt user callback */
|
|
HAL_RCC_CSSCallback();
|
|
|
|
/* Clear RCC CSS pending bit */
|
|
__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief RCC Clock Security System interrupt callback.
|
|
* @retval none
|
|
*/
|
|
__weak void HAL_RCC_CSSCallback(void)
|
|
{
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_RCC_CSSCallback should be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Get and clear reset flags
|
|
* @note Once reset flags are retrieved, this API is clearing them in order
|
|
* to isolate next reset reason.
|
|
* @retval can be a combination of @ref RCC_Reset_Flag
|
|
*/
|
|
uint32_t HAL_RCC_GetResetSource(void)
|
|
{
|
|
uint32_t reset;
|
|
|
|
/* Get all reset flags */
|
|
reset = RCC->CSR & RCC_RESET_FLAG_ALL;
|
|
|
|
/* Clear Reset flags */
|
|
RCC->CSR |= RCC_CSR_RMVF;
|
|
|
|
return reset;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private function prototypes -----------------------------------------------*/
|
|
/** @addtogroup RCC_Private_Functions
|
|
* @{
|
|
*/
|
|
/**
|
|
* @brief Update number of Flash wait states in line with MSI range and current
|
|
voltage range.
|
|
* @param msirange MSI range value from RCC_MSISRANGE_0 to RCC_MSISRANGE_15
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
|
{
|
|
uint32_t vos;
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
|
|
if (__HAL_RCC_PWR_IS_CLK_ENABLED())
|
|
{
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
}
|
|
else
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
}
|
|
|
|
if (vos == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
{
|
|
if (msirange > RCC_MSIRANGE_8)
|
|
{
|
|
/* MSI > 16Mhz */
|
|
if (msirange > RCC_MSIRANGE_11)
|
|
{
|
|
/* MSI 48Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
}
|
|
else if (msirange > RCC_MSIRANGE_9)
|
|
{
|
|
/* MSI 24Mhz or 32Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
}
|
|
else
|
|
{
|
|
/* MSI 16Mhz */
|
|
latency = FLASH_LATENCY_0; /* 0WS */
|
|
}
|
|
}
|
|
/* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */
|
|
}
|
|
else
|
|
{
|
|
if (msirange >= RCC_MSIRANGE_8)
|
|
{
|
|
/* MSI > 16Mhz */
|
|
latency = FLASH_LATENCY_2; /* 3WS */
|
|
}
|
|
else if (msirange == RCC_MSIRANGE_7)
|
|
{
|
|
/* MSI 8Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
}
|
|
else
|
|
{
|
|
/* MSI 16Mhz */
|
|
latency = FLASH_LATENCY_0; /* 0WS */
|
|
}
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if ((FLASH->ACR & FLASH_ACR_LATENCY) != latency)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|