1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
|
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_svm_linear_predict_f16.c
* Description: SVM Linear Classifier
*
* $Date: 23 April 2021
* $Revision: V1.9.0
*
* Target Processor: Cortex-M and Cortex-A cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "dsp/svm_functions_f16.h"
#if defined(ARM_FLOAT16_SUPPORTED)
#include <limits.h>
#include <math.h>
/**
* @addtogroup linearsvm
* @{
*/
/**
* @brief SVM linear prediction
* @param[in] S Pointer to an instance of the linear SVM structure.
* @param[in] in Pointer to input vector
* @param[out] pResult Decision value
* @return none.
*
*/
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
#include "arm_helium_utils.h"
void arm_svm_linear_predict_f16(
const arm_svm_linear_instance_f16 *S,
const float16_t * in,
int32_t * pResult)
{
/* inlined Matrix x Vector function interleaved with dot prod */
uint32_t numRows = S->nbOfSupportVectors;
uint32_t numCols = S->vectorDimension;
const float16_t *pSupport = S->supportVectors;
const float16_t *pSrcA = pSupport;
const float16_t *pInA0;
const float16_t *pInA1;
uint32_t row;
uint32_t blkCnt; /* loop counters */
const float16_t *pDualCoef = S->dualCoefficients;
_Float16 sum = S->intercept;
row = numRows;
/*
* compute 4 rows in parrallel
*/
while (row >= 4)
{
const float16_t *pInA2, *pInA3;
float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec;
f16x8_t vecIn, acc0, acc1, acc2, acc3;
float16_t const *pSrcVecPtr = in;
/*
* Initialize the pointers to 4 consecutive MatrixA rows
*/
pInA0 = pSrcA;
pInA1 = pInA0 + numCols;
pInA2 = pInA1 + numCols;
pInA3 = pInA2 + numCols;
/*
* Initialize the vector pointer
*/
pInVec = pSrcVecPtr;
/*
* reset accumulators
*/
acc0 = vdupq_n_f16(0.0f);
acc1 = vdupq_n_f16(0.0f);
acc2 = vdupq_n_f16(0.0f);
acc3 = vdupq_n_f16(0.0f);
pSrcA0Vec = pInA0;
pSrcA1Vec = pInA1;
pSrcA2Vec = pInA2;
pSrcA3Vec = pInA3;
blkCnt = numCols >> 3;
while (blkCnt > 0U) {
f16x8_t vecA;
vecIn = vld1q(pInVec);
pInVec += 8;
vecA = vld1q(pSrcA0Vec);
pSrcA0Vec += 8;
acc0 = vfmaq(acc0, vecIn, vecA);
vecA = vld1q(pSrcA1Vec);
pSrcA1Vec += 8;
acc1 = vfmaq(acc1, vecIn, vecA);
vecA = vld1q(pSrcA2Vec);
pSrcA2Vec += 8;
acc2 = vfmaq(acc2, vecIn, vecA);
vecA = vld1q(pSrcA3Vec);
pSrcA3Vec += 8;
acc3 = vfmaq(acc3, vecIn, vecA);
blkCnt--;
}
/*
* tail
* (will be merged thru tail predication)
*/
blkCnt = numCols & 7;
if (blkCnt > 0U) {
mve_pred16_t p0 = vctp16q(blkCnt);
f16x8_t vecA;
vecIn = vldrhq_z_f16(pInVec, p0);
vecA = vldrhq_z_f16(pSrcA0Vec, p0);
acc0 = vfmaq(acc0, vecIn, vecA);
vecA = vldrhq_z_f16(pSrcA1Vec, p0);
acc1 = vfmaq(acc1, vecIn, vecA);
vecA = vldrhq_z_f16(pSrcA2Vec, p0);
acc2 = vfmaq(acc2, vecIn, vecA);
vecA = vldrhq_z_f16(pSrcA3Vec, p0);
acc3 = vfmaq(acc3, vecIn, vecA);
}
/*
* Sum the partial parts
*/
acc0 = vmulq_n_f16(acc0,*pDualCoef++);
acc0 = vfmaq_n_f16(acc0,acc1,*pDualCoef++);
acc0 = vfmaq_n_f16(acc0,acc2,*pDualCoef++);
acc0 = vfmaq_n_f16(acc0,acc3,*pDualCoef++);
sum += (_Float16)vecAddAcrossF16Mve(acc0);
pSrcA += numCols * 4;
/*
* Decrement the row loop counter
*/
row -= 4;
}
/*
* compute 2 rows in parallel
*/
if (row >= 2) {
float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec;
f16x8_t vecIn, acc0, acc1;
float16_t const *pSrcVecPtr = in;
/*
* Initialize the pointers to 2 consecutive MatrixA rows
*/
pInA0 = pSrcA;
pInA1 = pInA0 + numCols;
/*
* Initialize the vector pointer
*/
pInVec = pSrcVecPtr;
/*
* reset accumulators
*/
acc0 = vdupq_n_f16(0.0f);
acc1 = vdupq_n_f16(0.0f);
pSrcA0Vec = pInA0;
pSrcA1Vec = pInA1;
blkCnt = numCols >> 3;
while (blkCnt > 0U) {
f16x8_t vecA;
vecIn = vld1q(pInVec);
pInVec += 8;
vecA = vld1q(pSrcA0Vec);
pSrcA0Vec += 8;
acc0 = vfmaq(acc0, vecIn, vecA);
vecA = vld1q(pSrcA1Vec);
pSrcA1Vec += 8;
acc1 = vfmaq(acc1, vecIn, vecA);
blkCnt--;
}
/*
* tail
* (will be merged thru tail predication)
*/
blkCnt = numCols & 7;
if (blkCnt > 0U) {
mve_pred16_t p0 = vctp16q(blkCnt);
f16x8_t vecA;
vecIn = vldrhq_z_f16(pInVec, p0);
vecA = vldrhq_z_f16(pSrcA0Vec, p0);
acc0 = vfmaq(acc0, vecIn, vecA);
vecA = vldrhq_z_f16(pSrcA1Vec, p0);
acc1 = vfmaq(acc1, vecIn, vecA);
}
/*
* Sum the partial parts
*/
acc0 = vmulq_n_f16(acc0,*pDualCoef++);
acc0 = vfmaq_n_f16(acc0,acc1,*pDualCoef++);
sum += (_Float16)vecAddAcrossF16Mve(acc0);
pSrcA += numCols * 2;
row -= 2;
}
if (row >= 1) {
f16x8_t vecIn, acc0;
float16_t const *pSrcA0Vec, *pInVec;
float16_t const *pSrcVecPtr = in;
/*
* Initialize the pointers to last MatrixA row
*/
pInA0 = pSrcA;
/*
* Initialize the vector pointer
*/
pInVec = pSrcVecPtr;
/*
* reset accumulators
*/
acc0 = vdupq_n_f16(0.0f);
pSrcA0Vec = pInA0;
blkCnt = numCols >> 3;
while (blkCnt > 0U) {
f16x8_t vecA;
vecIn = vld1q(pInVec);
pInVec += 8;
vecA = vld1q(pSrcA0Vec);
pSrcA0Vec += 8;
acc0 = vfmaq(acc0, vecIn, vecA);
blkCnt--;
}
/*
* tail
* (will be merged thru tail predication)
*/
blkCnt = numCols & 7;
if (blkCnt > 0U) {
mve_pred16_t p0 = vctp16q(blkCnt);
f16x8_t vecA;
vecIn = vldrhq_z_f16(pInVec, p0);
vecA = vldrhq_z_f16(pSrcA0Vec, p0);
acc0 = vfmaq(acc0, vecIn, vecA);
}
/*
* Sum the partial parts
*/
sum += (_Float16)*pDualCoef++ * (_Float16)vecAddAcrossF16Mve(acc0);
}
*pResult = S->classes[STEP(sum)];
}
#else
void arm_svm_linear_predict_f16(
const arm_svm_linear_instance_f16 *S,
const float16_t * in,
int32_t * pResult)
{
_Float16 sum=S->intercept;
_Float16 dot=0;
uint32_t i,j;
const float16_t *pSupport = S->supportVectors;
for(i=0; i < S->nbOfSupportVectors; i++)
{
dot=0;
for(j=0; j < S->vectorDimension; j++)
{
dot = (_Float16)dot + (_Float16)in[j]* (_Float16)*pSupport++;
}
sum += (_Float16)S->dualCoefficients[i] * (_Float16)dot;
}
*pResult=S->classes[STEP(sum)];
}
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
/**
* @} end of linearsvm group
*/
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */
|