diff options
| author | Clyne Sullivan <tullivan99@gmail.com> | 2016-11-11 15:02:17 -0500 |
|---|---|---|
| committer | Clyne Sullivan <tullivan99@gmail.com> | 2016-11-11 15:02:17 -0500 |
| commit | 7772ea4579a45bcf63ebd5e68be66ba1a9c72dfa (patch) | |
| tree | 9e1ce52ea97102d3513e519a77d999eac228820b /ChibiOS_16.1.5/community/os/hal/ports/KINETIS | |
| parent | 02b3ff42cccf32617c88c0ca65436b8c9d4f61eb (diff) | |
chibios!
Diffstat (limited to 'ChibiOS_16.1.5/community/os/hal/ports/KINETIS')
31 files changed, 10173 insertions, 0 deletions
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.c new file mode 100644 index 0000000..e6eeed8 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.c @@ -0,0 +1,234 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/hal_lld.c
+ * @brief HAL Driver subsystem low level driver source template.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#ifdef __CC_ARM
+__attribute__ ((section(".ARM.__at_0x400")))
+#else
+__attribute__ ((used,section(".cfmconfig")))
+#endif
+const uint8_t _cfm[0x10] = {
+ 0xFF, /* NV_BACKKEY3: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY2: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY1: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY0: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY7: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY6: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY5: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY4: KEY=0xFF */
+ 0xFF, /* NV_FPROT3: PROT=0xFF */
+ 0xFF, /* NV_FPROT2: PROT=0xFF */
+ 0xFF, /* NV_FPROT1: PROT=0xFF */
+ 0xFF, /* NV_FPROT0: PROT=0xFF */
+ 0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+ 0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
+ NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+ 0xFF,
+ 0xFF
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ * @todo Use a macro to define the system clock frequency.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+}
+
+/**
+ * @brief K20x clock initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function is meant to be invoked early during the system
+ * initialization, it is usually invoked from the file
+ * @p board.c.
+ * @todo This function needs to be more generic.
+ *
+ * @special
+ */
+void k20x_clock_init(void) {
+#if !KINETIS_NO_INIT
+
+ /* Disable the watchdog */
+ WDOG->UNLOCK = 0xC520;
+ WDOG->UNLOCK = 0xD928;
+ WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
+
+ SIM->SCGC5 |= SIM_SCGC5_PORTA |
+ SIM_SCGC5_PORTB |
+ SIM_SCGC5_PORTC |
+ SIM_SCGC5_PORTD |
+ SIM_SCGC5_PORTE;
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+ /* This is the default mode at reset. */
+
+ /* Configure FEI mode */
+ MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+ (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
+
+ /* Set clock dividers */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ uint8_t i;
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] = 0;
+ PORTA->PCR[19] = 0;
+
+ /*
+ * Start in FEI mode
+ */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+ /* TODO: need to add more flexible calculation, specially regarding
+ * divisors which may not be available depending on the XTAL
+ * frequency, which would required other registers to be modified.
+ */
+ /* Enable OSC, low power mode */
+ MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
+ if (KINETIS_XTAL_FREQUENCY > 8000000UL)
+ MCG->C2 |= MCG_C2_RANGE0(2);
+ else
+ MCG->C2 |= MCG_C2_RANGE0(1);
+
+ frdiv = 7;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
+ for (i = 0; i < ratio_quantity; ++i) {
+ if (ratio == ratios[i]) {
+ frdiv = i;
+ break;
+ }
+ }
+
+ /* Switch to crystal as clock source, FLL input of 31.25 KHz */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
+
+ /* Wait for crystal oscillator to begin */
+ while (!(MCG->S & MCG_S_OSCINIT0));
+
+ /* Wait for the FLL to use the oscillator */
+ while (MCG->S & MCG_S_IREFST);
+
+ /* Wait for the MCGOUTCLK to use the oscillator */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
+
+ /*
+ * Now in FBE mode
+ */
+ #define KINETIS_PLLIN_FREQUENCY 2000000UL
+ /*
+ * Config PLL input for 2 MHz
+ * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
+ */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
+
+ /*
+ * Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+ * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
+ */
+ for(i = 24; i < 56; i++)
+ {
+ if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
+ {
+ /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+ break;
+ }
+ }
+
+ if(i>=56) /* Config PLL for 96 MHz output as default setting */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
+ /* Wait for PLL to start using crystal as its input, and to lock */
+ while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
+
+ /*
+ * Now in PBE mode
+ */
+ /* Set the PLL dividers for the different clocks */
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+ SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
+
+ /* Switch to PLL as clock source */
+ MCG->C1 = MCG_C1_CLKS(0);
+
+ /* Wait for PLL clock to be used */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
+
+ /*
+ * Now in PEE mode
+ */
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.h new file mode 100644 index 0000000..b7f6b46 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_lld.h @@ -0,0 +1,302 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x/hal_lld.h
+ * @brief Kinetis K20x HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H_
+#define HAL_LLD_H_
+
+#include "kinetis_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "Kinetis"
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT FALSE
+#endif
+
+/**
+ * @brief MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#endif
+
+/**
+ * @brief MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#endif
+
+/**
+ * @brief Clock divider for core/system clocks (OUTDIV1).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz system clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+ #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV1 2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for bus clock (OUTDIV2).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 48 MHz bus clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
+ #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV2 KINETIS_CLKDIV1_OUTDIV1
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV2 2
+ #endif
+#endif
+
+/**
+ * @brief Clock divider for flash clock (OUTDIV4).
+ * @note The allowed range is 1..16
+ * @note The default value is calculated for a 24 MHz flash clock
+ * from a 96 MHz PLL output
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+ #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
+ #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 (KINETIS_CLKDIV1_OUTDIV1*2)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV4 4
+ #endif
+#endif
+
+/**
+ * @brief FLL DCO tuning enable for 32.768 kHz reference.
+ * @note Set to 1 for fine-tuning DCO for maximum frequency with
+ * a 32.768 kHz reference.
+ * @note The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32 1
+#endif
+
+/**
+ * @brief FLL DCO range selection.
+ * @note The allowed range is 0...3.
+ * @note The default value is calculated for 48 MHz FLL output
+ * from a 32.768 kHz external crystal.
+ * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS 2
+#endif
+
+/**
+ * @brief MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
+#endif
+
+/**
+ * @brief MCU bus clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
+#endif
+
+/**
+ * @brief MCU flash clock frequency.
+ */
+#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_FLASHCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+ #error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+ #error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+ #error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+ #error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !defined(KINETIS_FLASHCLK_FREQUENCY)
+ #error KINETIS_FLASHCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
+ #error KINETIS_FLASHCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+ KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+ #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
+ KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * DWT_CYCCNT register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value() 0
+
+/**
+ * @brief Realtime counter frequency.
+ * @note The DWT_CYCCNT register is incremented directly by the system
+ * clock so this function returns STM32_HCLK.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() 0
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void k20x_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c new file mode 100644 index 0000000..f5a8d96 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c @@ -0,0 +1,390 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x/pwm_lld.c
+ * @brief KINETIS PWM subsystem low level driver source.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the timer FTM0 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the timer FTM1 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the timer FTM2 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+ uint32_t sr;
+
+ sr = pwmp->ftm->SC;
+ pwmp->ftm->SC = sr&(~FTM_SC_TOF);
+
+ if (((sr & FTM_SC_TOF) != 0) && /* Timer Overflow */
+ ((sr & FTM_SC_TOIE) != 0) &&
+ (pwmp->config->callback != NULL)) {
+ pwmp->config->callback(pwmp);
+ }
+
+ uint8_t n=0;
+ for(n=0;n<pwmp->channels;n++) {
+ sr = pwmp->ftm->CHANNEL[n].CnSC;
+ pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF);
+ if (((sr & FTM_CnSC_CHF) != 0) &&
+ ((sr & FTM_CnSC_CHIE) != 0) &&
+ (pwmp->config->channels[n].callback != NULL)) {
+ pwmp->config->channels[n].callback(pwmp);
+ }
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0
+/**
+ * @brief FTM0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM0 */
+
+#if KINETIS_PWM_USE_FTM1
+/**
+ * @brief FTM1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM1 */
+
+#if KINETIS_PWM_USE_FTM2
+/**
+ * @brief FTM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM2 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if KINETIS_PWM_USE_FTM0
+ pwmObjectInit(&PWMD1);
+ PWMD1.channels = KINETIS_FTM0_CHANNELS;
+ PWMD1.ftm = FTM0;
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ pwmObjectInit(&PWMD2);
+ PWMD2.channels = KINETIS_FTM1_CHANNELS;
+ PWMD2.ftm = FTM1;
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ pwmObjectInit(&PWMD3);
+ PWMD3.channels = KINETIS_FTM2_CHANNELS;
+ PWMD3.ftm = FTM2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+ uint16_t psc;
+ uint8_t i=0;
+
+ if (pwmp->state == PWM_STOP) {
+ /* Clock activation and timer reset.*/
+#if KINETIS_PWM_USE_FTM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_FTM0;
+ nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_FTM1;
+ nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC3 |= SIM_SCGC3_FTM2;
+ nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY);
+ }
+#endif
+ }
+ pwmp->ftm->MODE = FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK;
+ pwmp->ftm->SYNC = FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK
+ |FTM_SYNC_SWSYNC_MASK;
+ pwmp->ftm->COMBINE = FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK
+ | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK;
+ pwmp->ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK;
+
+ pwmp->ftm->CNTIN = 0x0000;
+ //~ pwmp->ftm->SC = 0; /* Disable FTM counter.*/
+ pwmp->ftm->CNT = 0x0000; /* Clear count register.*/
+
+ /* Prescaler value calculation.*/
+ psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
+ //~ /* Prescaler must be power of two between 1 and 128.*/
+ osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
+ //~ /* Prescaler register value determination.
+ //~ Prescaler register value conveniently corresponds to bit position,
+ //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
+ for (i = 0; i < 8; i++) {
+ if (psc == (unsigned)(1 << i)) {
+ break;
+ }
+ }
+
+ /* Set prescaler and clock mode.
+ This also sets the following:
+ CPWMS up-counting mode
+ Timer overflow interrupt disabled
+ DMA disabled.*/
+ pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i);
+ /* Configure period */
+ pwmp->ftm->MOD = pwmp->period-1;
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+ /* If in ready state then disables the PWM clock.*/
+ if (pwmp->state == PWM_READY) {
+#if KINETIS_PWM_USE_FTM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_FTM0;
+ nvicDisableVector(FTM0_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_FTM1;
+ nvicDisableVector(FTM1_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC3 &= ~SIM_SCGC3_FTM2;
+ nvicDisableVector(FTM2_IRQn);
+ }
+#endif
+ /* Disable FTM counter.*/
+ pwmp->ftm->SC = 0;
+ pwmp->ftm->MOD = 0;
+ }
+}
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note The function has effect at the next cycle start.
+ * @note Channel notification is not enabled.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+ uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/
+
+ switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_HIGH:
+ mode |= FTM_CnSC_ELSB;
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+ mode |= FTM_CnSC_ELSA;
+ break;
+ }
+
+ if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE)
+ mode |= FTM_CnSC_CHIE;
+
+ pwmp->ftm->CHANNEL[channel].CnSC = mode;
+ pwmp->ftm->CHANNEL[channel].CnV = width;
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief Disables a PWM channel and its notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ pwmp->ftm->CHANNEL[channel].CnSC = 0;
+ pwmp->ftm->CHANNEL[channel].CnV = 0;
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->ftm->SC |= FTM_SC_TOIE;
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+ pwmp->ftm->SC &= ~FTM_SC_TOIE;
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE;
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+ pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE;
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.h new file mode 100644 index 0000000..ccc100f --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_pwm_lld.h @@ -0,0 +1,270 @@ +/*
+ ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x7/pwm_lld.h
+ * @brief KINETIS PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef HAL_PWM_LLD_H_
+#define HAL_PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS 8
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_PWM_USE_FTM0)
+ #define KINETIS_PWM_USE_FTM0 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM1)
+ #define KINETIS_PWM_USE_FTM1 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM2)
+ #define KINETIS_PWM_USE_FTM2 FALSE
+#endif
+
+/**
+ * @brief FTM0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM0_PRIORITY 12
+#endif
+
+/**
+ * @brief FTM1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM1_PRIORITY 12
+#endif
+
+/**
+ * @brief FTM2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM2_PRIORITY 12
+#endif
+
+/** @} */
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief If advanced timer features switch.
+ * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
+ * enabled.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
+#define KINETIS_PWM_USE_ADVANCED FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks. */
+/*===========================================================================*/
+
+#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2
+#error "PWM driver activated but no FTM peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief Type of a PWM driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief Structure representing a PWM driver.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief Current driver configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the FTM registers block.
+ */
+ FTM_TypeDef *ftm;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period) \
+ do { \
+ (pwmp)->ftm->MOD = ((period) - 1); \
+ pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\
+ } while(0)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* HAL_PWM_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.c new file mode 100644 index 0000000..29ab4e8 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.c @@ -0,0 +1,539 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/spi_lld.c
+ * @brief KINETIS SPI subsystem low level driver source.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY 8
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI0_RX_DMAMUX_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMA_CHANNEL)
+#define KINETIS_SPI0_RX_DMA_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI0_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI0_TX_DMAMUX_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI0_TX_DMA_CHANNEL)
+#define KINETIS_SPI0_TX_DMA_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY 8
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_RX_DMAMUX_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL)
+#define KINETIS_SPI1_RX_DMA_CHANNEL 0
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_TX_DMAMUX_CHANNEL 1
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL)
+#define KINETIS_SPI1_TX_DMA_CHANNEL 1
+#endif
+
+#if KINETIS_SPI_USE_SPI0
+#define DMAMUX_SPI_RX_SOURCE 16
+#define DMAMUX_SPI_TX_SOURCE 17
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+#define DMAMUX_SPI_RX_SOURCE 18
+#define DMAMUX_SPI_TX_SOURCE 19
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief SPI0 driver identifier.*/
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+SPIDriver SPID1;
+#endif
+
+/** @brief SPI1 driver identifier.*/
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/* Use a dummy byte as the source/destination when a buffer is not provided */
+/* Note: The MMC driver relies on 0xFF being sent for dummy bytes. */
+static volatile uint16_t dmaRxDummy;
+static uint16_t dmaTxDummy = 0xFFFF;
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void spi_start_xfer(SPIDriver *spip, bool polling)
+{
+ /*
+ * Enable the DSPI peripheral in master mode.
+ * Clear the TX and RX FIFOs.
+ * */
+ spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_CLR_TXF | SPIx_MCR_CLR_RXF;
+
+ /* If we are not polling then enable DMA */
+ if (!polling) {
+
+ /* Enable receive dma and transmit dma */
+ spip->spi->RSER = SPIx_RSER_RFDF_DIRS | SPIx_RSER_RFDF_RE |
+ SPIx_RSER_TFFF_RE | SPIx_RSER_TFFF_DIRS;
+
+ /* Configure RX DMA */
+ if (spip->rxbuf) {
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)spip->rxbuf;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = spip->word_size;
+ } else {
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)&dmaRxDummy;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = 0;
+ }
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
+
+ /* Enable Request Register (ERQ) for RX by writing 0 to SERQ */
+ DMA->SERQ = KINETIS_SPI0_RX_DMA_CHANNEL;
+
+ /* Configure TX DMA */
+ if (spip->txbuf) {
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)spip->txbuf;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = spip->word_size;
+ } else {
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR = (uint32_t)&dmaTxDummy;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = 0;
+ }
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
+
+ /* Enable Request Register (ERQ) for TX by writing 1 to SERQ */
+ DMA->SERQ = KINETIS_SPI0_TX_DMA_CHANNEL;
+ }
+}
+
+static void spi_stop_xfer(SPIDriver *spip)
+{
+ /* Halt the DSPI peripheral */
+ spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_HALT;
+
+ /* Clear all the flags which are currently set. */
+ spip->spi->SR |= spip->spi->SR;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+ DMA->CINT = KINETIS_SPI0_RX_DMA_CHANNEL;
+
+ spi_stop_xfer(&SPID1);
+
+ _spi_isr_code(&SPID1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+ DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL;
+
+ spi_stop_xfer(&SPID2);
+
+ _spi_isr_code(&SPID2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SPI driver initialization.
+ *
+ * @notapi
+ */
+void spi_lld_init(void) {
+#if KINETIS_SPI_USE_SPI0
+ spiObjectInit(&SPID1);
+#endif
+#if KINETIS_SPI_USE_SPI1
+ spiObjectInit(&SPID2);
+#endif
+}
+
+/**
+ * @brief Configures and activates the SPI peripheral.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_start(SPIDriver *spip) {
+
+ /* If in stopped state then enables the SPI and DMA clocks.*/
+ if (spip->state == SPI_STOP) {
+
+#if KINETIS_SPI_USE_SPI0
+ if (&SPID1 == spip) {
+
+ /* Enable the clock for SPI0 */
+ SIM->SCGC6 |= SIM_SCGC6_SPI0;
+
+ SPID1.spi = SPI0;
+
+ if (spip->config->tar0) {
+ spip->spi->CTAR[0] = spip->config->tar0;
+ } else {
+ spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+ }
+ }
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ if (&SPID2 == spip) {
+
+ /* Enable the clock for SPI0 */
+ SIM->SCGC6 |= SIM_SCGC6_SPI1;
+
+ SPID2.spi = SPI1;
+
+ if (spip->config->tar0) {
+ spip->spi->CTAR[0] = spip->config->tar0;
+ } else {
+ spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+ }
+ }
+#endif
+
+ nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
+
+ SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
+ SIM->SCGC7 |= SIM_SCGC7_DMA;
+
+ /* Clear DMA error flags */
+ DMA->ERR = 0x0F;
+
+#if KINETIS_SPI_USE_SPI0
+ /* Rx, select SPI Rx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+ /* Tx, select SPI Tx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI0_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+ /* Extract the frame size from the TAR */
+ uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+ SPIx_CTARn_FMSZ_MASK) + 1;
+
+ /* DMA transfer size is 16 bits for a frame size > 8 bits */
+ uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+ /* DMA word size is 2 for a 16 bit frame size */
+ spip->word_size = frame_size > 8 ? 2 : 1;
+
+ /* configure DMA RX fixed values */
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI0->POPR;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SOFF = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+ DMA_CSR_INTMAJOR_MASK;
+
+ /* configure DMA TX fixed values */
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI0->PUSHR;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DOFF = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ /* Rx, select SPI Rx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+ /* Tx, select SPI Tx FIFO */
+ DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+ DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+ /* Extract the frame size from the TAR */
+ uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+ SPIx_CTARn_FMSZ_MASK) + 1;
+
+ /* DMA transfer size is 16 bits for a frame size > 8 bits */
+ uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+ /* DMA word size is 2 for a 16 bit frame size */
+ spip->word_size = frame_size > 8 ? 2 : 1;
+
+ /* configure DMA RX fixed values */
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+ DMA_CSR_INTMAJOR_MASK;
+
+ /* configure DMA TX fixed values */
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+ DMA_ATTR_DSIZE(dma_size);
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+ DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
+ }
+}
+
+/**
+ * @brief Deactivates the SPI peripheral.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_stop(SPIDriver *spip) {
+
+ /* If in ready state then disables the SPI clock.*/
+ if (spip->state == SPI_READY) {
+
+ nvicDisableVector(DMA0_IRQn);
+
+ SIM->SCGC7 &= ~SIM_SCGC7_DMA;
+ SIM->SCGC6 &= ~SIM_SCGC6_DMAMUX;
+
+#if KINETIS_SPI_USE_SPI0
+ if (&SPID1 == spip) {
+ /* SPI halt.*/
+ spip->spi->MCR |= SPIx_MCR_HALT;
+ }
+
+ /* Disable the clock for SPI0 */
+ SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+ if (&SPID2 == spip) {
+ /* SPI halt.*/
+ spip->spi->MCR |= SPIx_MCR_HALT;
+ }
+
+ /* Disable the clock for SPI1 */
+ SIM->SCGC6 &= ~SIM_SCGC6_SPI1;
+#endif
+ }
+}
+
+/**
+ * @brief Asserts the slave select signal and prepares for transfers.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_select(SPIDriver *spip) {
+
+ palClearPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_unselect(SPIDriver *spip) {
+
+ palSetPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief Ignores data on the SPI bus.
+ * @details This asynchronous function starts the transmission of a series of
+ * idle words on the SPI bus and ignores the received data.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be ignored
+ *
+ * @notapi
+ */
+void spi_lld_ignore(SPIDriver *spip, size_t n) {
+
+ spip->count = n;
+ spip->rxbuf = NULL;
+ spip->txbuf = NULL;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Exchanges data on the SPI bus.
+ * @details This asynchronous function starts a simultaneous transmit/receive
+ * operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ * @param[in] txbuf the pointer to the transmit buffer
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_exchange(SPIDriver *spip, size_t n,
+ const void *txbuf, void *rxbuf) {
+
+ spip->count = n;
+ spip->rxbuf = rxbuf;
+ spip->txbuf = txbuf;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Sends data over the SPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+
+ spip->count = n;
+ spip->rxbuf = NULL;
+ spip->txbuf = (void *)txbuf;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Receives data from the SPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to receive
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+
+ spip->count = n;
+ spip->rxbuf = rxbuf;
+ spip->txbuf = NULL;
+
+ spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief Exchanges one frame using a polled wait.
+ * @details This synchronous function exchanges one frame using a polled
+ * synchronization method. This function is useful when exchanging
+ * small amount of data on high speed channels, usually in this
+ * situation is much more efficient just wait for completion using
+ * polling than suspending the thread waiting for an interrupt.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] frame the data frame to send over the SPI bus
+ * @return The received data frame from the SPI bus.
+ */
+uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
+
+ spi_start_xfer(spip, true);
+
+ spip->spi->PUSHR = SPIx_PUSHR_TXDATA(frame);
+
+ while ((spip->spi->SR & SPIx_SR_RFDF) == 0)
+ ;
+
+ frame = spip->spi->POPR;
+
+ spi_stop_xfer(spip);
+
+ return frame;
+}
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.h new file mode 100644 index 0000000..0cf108e --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/hal_spi_lld.h @@ -0,0 +1,261 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/spi_lld.h
+ * @brief KINETIS SPI subsystem low level driver header.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef HAL_SPI_LLD_H_
+#define HAL_SPI_LLD_H_
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SPI0 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI0) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI0 FALSE
+#endif
+
+/**
+ * @brief SPI0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI0_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief SPI1 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI1 FALSE
+#endif
+
+/**
+ * @brief SPI1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI1_IRQ_PRIORITY 10
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
+#error "SPI0 not present in the selected device"
+#endif
+
+#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1
+#error "Only one SPI peripheral can be enabled"
+#endif
+
+#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1)
+#error "SPI driver activated but no SPI peripheral assigned"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI0"
+#endif
+
+#if KINETIS_SPI_USE_SPI1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an SPI driver.
+ */
+typedef struct SPIDriver SPIDriver;
+
+/**
+ * @brief SPI notification callback type.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object triggering the
+ * callback
+ */
+typedef void (*spicallback_t)(SPIDriver *spip);
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Operation complete callback or @p NULL.
+ */
+ spicallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief The chip select line port - when not using pcs.
+ */
+ ioportid_t ssport;
+ /**
+ * @brief The chip select line pad number - when not using pcs.
+ */
+ uint16_t sspad;
+ /**
+ * @brief SPI initialization data.
+ */
+ uint32_t tar0;
+} SPIConfig;
+
+/**
+ * @brief Structure representing a SPI driver.
+ */
+struct SPIDriver {
+ /**
+ * @brief Driver state.
+ */
+ spistate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const SPIConfig *config;
+#if SPI_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif /* SPI_USE_WAIT */
+#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if defined(SPI_DRIVER_EXT_FIELDS)
+ SPI_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the SPIx registers block.
+ */
+ SPI_TypeDef *spi;
+ /**
+ * @brief Number of bytes/words of data to transfer.
+ */
+ size_t count;
+ /**
+ * @brief Word size in bytes.
+ */
+ size_t word_size;
+ /**
+ * @brief Pointer to the buffer with data to send.
+ */
+ const uint8_t *txbuf;
+ /**
+ * @brief Pointer to the buffer to put received data.
+ */
+ uint8_t *rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/* TAR settings for n bits at SYSCLK / 2 */
+#define KINETIS_SPI_TAR_SYSCLK_DIV_2(n)\
+ SPIx_CTARn_FMSZ((n) - 1) | \
+ SPIx_CTARn_CPOL | \
+ SPIx_CTARn_CPHA | \
+ SPIx_CTARn_DBR | \
+ SPIx_CTARn_PBR(0) | \
+ SPIx_CTARn_BR(0) | \
+ SPIx_CTARn_CSSCK(0) | \
+ SPIx_CTARn_ASC(0) | \
+ SPIx_CTARn_DT(0)
+
+/* TAR settings for n bits at SYSCLK / 4096 for debugging */
+#define KINETIS_SPI_TAR_SYSCLK_DIV_4096(n) \
+ SPIx_CTARn_FMSZ(((n) - 1)) | \
+ SPIx_CTARn_CPOL | \
+ SPIx_CTARn_CPHA | \
+ SPIx_CTARn_PBR(0) | \
+ SPIx_CTARn_BR(0xB) | \
+ SPIx_CTARn_CSSCK(0xB) | \
+ SPIx_CTARn_ASC(0x7) | \
+ SPIx_CTARn_DT(0xB)
+
+#define KINETIS_SPI_TAR_8BIT_FAST KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+#define KINETIS_SPI_TAR_8BIT_SLOW KINETIS_SPI_TAR_SYSCLK_DIV_4096(8)
+
+#define KINETIS_SPI_TAR0_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+#define KINETIS_SPI_TAR1_DEFAULT KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 && !defined(__DOXYGEN__)
+extern SPIDriver SPID1;
+#endif
+
+#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void spi_lld_init(void);
+ void spi_lld_start(SPIDriver *spip);
+ void spi_lld_stop(SPIDriver *spip);
+ void spi_lld_select(SPIDriver *spip);
+ void spi_lld_unselect(SPIDriver *spip);
+ void spi_lld_ignore(SPIDriver *spip, size_t n);
+ void spi_lld_exchange(SPIDriver *spip, size_t n,
+ const void *txbuf, void *rxbuf);
+ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
+ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
+ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* HAL_SPI_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/kinetis_registry.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/kinetis_registry.h new file mode 100644 index 0000000..d2eea6f --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/kinetis_registry.h @@ -0,0 +1,258 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file K20x/kinetis_registry.h
+ * @brief K20x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef KINETIS_REGISTRY_H_
+#define KINETIS_REGISTRY_H_
+
+#if !defined(K20x) || defined(__DOXYGEN__)
+#define K20x
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name K20x capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* K20x5 */
+/*===========================================================================*/
+#if defined(K20x5) || defined(__DOXYGEN__)
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX 25000000L
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR Vector98
+#define KINETIS_HAS_ADC1 FALSE
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 FALSE
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector50
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorE0
+#define KINETIS_PORTB_IRQ_VECTOR VectorE4
+#define KINETIS_PORTC_IRQ_VECTOR VectorE8
+#define KINETIS_PORTD_IRQ_VECTOR VectorEC
+#define KINETIS_PORTE_IRQ_VECTOR VectorF0
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR Vector6C
+#define KINETIS_HAS_I2C1 FALSE
+
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR Vector80
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR Vector88
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector90
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR Vector84
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR Vector8C
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR Vector94
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR Vector70
+#define KINETIS_HAS_SPI1 FALSE
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+
+#define KINETIS_FTM0_IRQ_VECTOR VectorA4
+#define KINETIS_FTM1_IRQ_VECTOR VectorA8
+#define KINETIS_HAS_FTM2 FALSE
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_PIT0_IRQ_VECTOR VectorB8
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_PIT1_IRQ_VECTOR VectorBC
+#define KINETIS_HAS_PIT2 TRUE
+#define KINETIS_PIT2_IRQ_VECTOR VectorC0
+#define KINETIS_HAS_PIT3 TRUE
+#define KINETIS_PIT3_IRQ_VECTOR VectorC4
+#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR VectorCC
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR VectorDC
+
+/*===========================================================================*/
+/* K20x7 */
+/*===========================================================================*/
+#elif defined(K20x7)
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 72000000L
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 50000000L
+
+/**
+ * @brief Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX 25000000L
+
+/**
+ * @name K20x7 attributes
+ * @{
+ */
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR Vector124
+#define KINETIS_HAS_ADC1 TRUE
+#define KINETIS_ADC1_IRQ_VECTOR Vector128
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR Vector184
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector50
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR Vector19C
+#define KINETIS_PORTB_IRQ_VECTOR Vector1A0
+#define KINETIS_PORTC_IRQ_VECTOR Vector1A4
+#define KINETIS_PORTD_IRQ_VECTOR Vector1A8
+#define KINETIS_PORTE_IRQ_VECTOR Vector1AC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN TRUE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR VectorA0
+#define KINETIS_HAS_I2C1 TRUE
+#define KINETIS_I2C1_IRQ_VECTOR VectorA4
+
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR VectorF4
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR VectorFC
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector104
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorF8
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR Vector100
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR Vector108
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR VectorA8
+#define KINETIS_HAS_SPI1 TRUE
+#define KINETIS_SPI1_IRQ_VECTOR VectorAC
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+#define KINETIS_FTM2_CHANNELS 2
+
+#define KINETIS_FTM0_IRQ_VECTOR Vector138
+#define KINETIS_FTM1_IRQ_VECTOR Vector13C
+#define KINETIS_HAS_FTM2 TRUE
+#define KINETIS_FTM2_IRQ_VECTOR Vector140
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_PIT0_IRQ_VECTOR Vector150
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_PIT1_IRQ_VECTOR Vector154
+#define KINETIS_HAS_PIT2 TRUE
+#define KINETIS_PIT2_IRQ_VECTOR Vector158
+#define KINETIS_HAS_PIT3 TRUE
+#define KINETIS_PIT3_IRQ_VECTOR Vector15C
+#define KINETIS_HAS_PIT FALSE
+#define KINETIS_PIT_CHANNELS 4
+#define KINETIS_HAS_PIT_COMMON_IRQ FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR Vector164
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR Vector194
+
+#endif /* K20xY */
+
+/** @} */
+
+#endif /* KINETIS_REGISTRY_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.dox b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.dox new file mode 100644 index 0000000..3fb142d --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.dox @@ -0,0 +1,365 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/* TODO Still need to edit this entire file */
+
+/**
+ * @defgroup MK20D5_DRIVERS MK20D5 Drivers
+ * @details This section describes all the supported drivers on the MK20D5
+ * platform and the implementation details of the single drivers.
+ *
+ * @ingroup platforms
+ */
+
+/**
+ * @defgroup MK20D5_HAL MK20D5 Initialization Support
+ * @details The MK20D5 HAL support is responsible for system initialization.
+ *
+ * @section mk20d5_hal_1 Supported HW resources
+ * - PLL1.
+ * - PLL2.
+ * - RCC.
+ * - Flash.
+ * .
+ * @section mk20d5_hal_2 MK20D5 HAL driver implementation features
+ * - PLL startup and stabilization.
+ * - Clock tree initialization.
+ * - Clock source selection.
+ * - Flash wait states initialization based on the selected clock options.
+ * - SYSTICK initialization based on current clock and kernel required rate.
+ * - DMA support initialization.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_ADC MK20D5 ADC Support
+ * @details The MK20D5 ADC driver supports the ADC peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk20d5_adc_1 Supported HW resources
+ * - ADC1.
+ * - ADC2.
+ * - ADC3.
+ * - DMA2.
+ * .
+ * @section mk20d5_adc_2 MK20D5 ADC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Streaming conversion using DMA for maximum performance.
+ * - Programmable ADC interrupt priority level.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - DMA and ADC errors detection.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_CAN MK20D5 CAN Support
+ * @details The MK20D5 CAN driver uses the CAN peripherals.
+ *
+ * @section mk20d5_can_1 Supported HW resources
+ * - bxCAN1.
+ * .
+ * @section mk20d5_can_2 MK20D5 CAN driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Support for bxCAN sleep mode.
+ * - Programmable bxCAN interrupts priority level.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_EXT MK20D5 EXT Support
+ * @details The MK20D5 EXT driver uses the EXTI peripheral.
+ *
+ * @section mk20d5_ext_1 Supported HW resources
+ * - EXTI.
+ * .
+ * @section mk20d5_ext_2 MK20D5 EXT driver implementation features
+ * - Each EXTI channel can be independently enabled and programmed.
+ * - Programmable EXTI interrupts priority level.
+ * - Capability to work as event sources (WFE) rather than interrupt sources.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_GPT MK20D5 GPT Support
+ * @details The MK20D5 GPT driver uses the TIMx peripherals.
+ *
+ * @section mk20d5_gpt_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk20d5_gpt_2 MK20D5 GPT driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_ICU MK20D5 ICU Support
+ * @details The MK20D5 ICU driver uses the TIMx peripherals.
+ *
+ * @section mk20d5_icu_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk20d5_icu_2 MK20D5 ICU driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_MAC MK20D5 MAC Support
+ * @details The MK20D5 MAC driver supports the ETH peripheral.
+ *
+ * @section mk20d5_mac_1 Supported HW resources
+ * - ETH.
+ * - PHY (external).
+ * .
+ * @section mk20d5_mac_2 MK20D5 MAC driver implementation features
+ * - Dedicated DMA operations.
+ * - Support for checksum off-loading.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_PAL MK20D5 PAL Support
+ * @details The MK20D5 PAL driver uses the GPIO peripherals.
+ *
+ * @section mk20d5_pal_1 Supported HW resources
+ * - GPIOA.
+ * - GPIOB.
+ * - GPIOC.
+ * - GPIOD.
+ * - GPIOE.
+ * - GPIOF.
+ * - GPIOG.
+ * - GPIOH.
+ * - GPIOI.
+ * .
+ * @section mk20d5_pal_2 MK20D5 PAL driver implementation features
+ * The PAL driver implementation fully supports the following hardware
+ * capabilities:
+ * - 16 bits wide ports.
+ * - Atomic set/reset functions.
+ * - Atomic set+reset function (atomic bus operations).
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * @section mk20d5_pal_3 Supported PAL setup modes
+ * The MK20D5 PAL driver supports the following I/O modes:
+ * - @p PAL_MODE_RESET.
+ * - @p PAL_MODE_UNCONNECTED.
+ * - @p PAL_MODE_INPUT.
+ * - @p PAL_MODE_INPUT_PULLUP.
+ * - @p PAL_MODE_INPUT_PULLDOWN.
+ * - @p PAL_MODE_INPUT_ANALOG.
+ * - @p PAL_MODE_OUTPUT_PUSHPULL.
+ * - @p PAL_MODE_OUTPUT_OPENDRAIN.
+ * - @p PAL_MODE_ALTERNATE (non standard).
+ * .
+ * Any attempt to setup an invalid mode is ignored.
+ *
+ * @section mk20d5_pal_4 Suboptimal behavior
+ * The MK20D5 GPIO is less than optimal in several areas, the limitations
+ * should be taken in account while using the PAL driver:
+ * - Pad/port toggling operations are not atomic.
+ * - Pad/group mode setup is not atomic.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_PWM MK20D5 PWM Support
+ * @details The MK20D5 PWM driver uses the TIMx peripherals.
+ *
+ * @section mk20d5_pwm_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk20d5_pwm_2 MK20D5 PWM driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Four independent PWM channels per timer.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_SDC MK20D5 SDC Support
+ * @details The MK20D5 SDC driver uses the SDIO peripheral.
+ *
+ * @section mk20d5_sdc_1 Supported HW resources
+ * - SDIO.
+ * - DMA2.
+ * .
+ * @section mk20d5_sdc_2 MK20D5 SDC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Programmable interrupt priority.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_SERIAL MK20D5 Serial Support
+ * @details The MK20D5 Serial driver uses the USART/UART peripherals in a
+ * buffered, interrupt driven, implementation.
+ *
+ * @section mk20d5_serial_1 Supported HW resources
+ * The serial driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3.
+ * - UART4.
+ * - UART5.
+ * - USART6.
+ * .
+ * @section mk20d5_serial_2 MK20D5 Serial driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Fully interrupt driven.
+ * - Programmable priority levels for each UART/USART.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_SPI MK20D5 SPI Support
+ * @details The SPI driver supports the MK20D5 SPI peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk20d5_spi_1 Supported HW resources
+ * - SPI1.
+ * - SPI2.
+ * - SPI3.
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk20d5_spi_2 MK20D5 SPI driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each SPI can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each SPI.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_UART MK20D5 UART Support
+ * @details The UART driver supports the MK20D5 USART peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section mk20d5_uart_1 Supported HW resources
+ * The UART driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3.
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk20d5_uart_2 MK20D5 UART driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each UART/USART.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_PLATFORM_DRIVERS MK20D5 Platform Drivers
+ * @details Platform support drivers. Platform drivers do not implement HAL
+ * standard driver templates, their role is to support platform
+ * specific functionalities.
+ *
+ * @ingroup MK20D5_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_DMA MK20D5 DMA Support
+ * @details This DMA helper driver is used by the other drivers in order to
+ * access the shared DMA resources in a consistent way.
+ *
+ * @section mk20d5_dma_1 Supported HW resources
+ * The DMA driver can support any of the following hardware resources:
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk20d5_dma_2 MK20D5 DMA driver implementation features
+ * - Exports helper functions/macros to the other drivers that share the
+ * DMA resource.
+ * - Automatic DMA clock stop when not in use by any driver.
+ * - DMA streams and interrupt vectors sharing among multiple drivers.
+ * .
+ * @ingroup MK20D5_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_ISR MK20D5 ISR Support
+ * @details This ISR helper driver is used by the other drivers in order to
+ * map ISR names to physical vector names.
+ *
+ * @ingroup MK20D5_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup MK20D5_RCC MK20D5 RCC Support
+ * @details This RCC helper driver is used by the other drivers in order to
+ * access the shared RCC resources in a consistent way.
+ *
+ * @section mk20d5_rcc_1 Supported HW resources
+ * - RCC.
+ * .
+ * @section mk20d5_rcc_2 MK20D5 RCC driver implementation features
+ * - Peripherals reset.
+ * - Peripherals clock enable.
+ * - Peripherals clock disable.
+ * .
+ * @ingroup MK20D5_PLATFORM_DRIVERS
+ */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.mk new file mode 100644 index 0000000..beee336 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/K20x/platform.mk @@ -0,0 +1,18 @@ +# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_spi_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x/hal_pwm_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K20x \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.c new file mode 100644 index 0000000..77addf0 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.c @@ -0,0 +1,472 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/hal_lld.c
+ * @brief Kinetis KL2x HAL Driver subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#ifdef __CC_ARM
+__attribute__ ((section(".ARM.__at_0x400")))
+#else
+__attribute__ ((used,section(".cfmconfig")))
+#endif
+const uint8_t _cfm[0x10] = {
+ 0xFF, /* NV_BACKKEY3: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY2: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY1: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY0: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY7: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY6: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY5: KEY=0xFF */
+ 0xFF, /* NV_BACKKEY4: KEY=0xFF */
+ 0xFF, /* NV_FPROT3: PROT=0xFF */
+ 0xFF, /* NV_FPROT2: PROT=0xFF */
+ 0xFF, /* NV_FPROT1: PROT=0xFF */
+ 0xFF, /* NV_FPROT0: PROT=0xFF */
+#if defined(KINETIS_NV_FSEC_BYTE)
+ #warning Please triple check your FSEC setting: KEYEN!=b10, MEEN==b10, SEC!=b10 leads to an unmodifiable chip.
+ KINETIS_NV_FSEC_BYTE,
+#else /* KINETIS_NV_FSEC_BYTE */
+ 0x7E, /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+#endif /* KINETIS_NV_FSEC_BYTE */
+#if defined(KINETIS_NV_FOPT_BYTE)
+ KINETIS_NV_FOPT_BYTE,
+#else /* KINETIS_NV_FOPT_BYTE */
+ 0xFF, /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
+ NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+ /* on KL27: bit7-6:BOOTSRC_SEL=0b11 (11=from ROM; 00=from FLASH)
+ bit1:BOOTPIN_OPT=1 (NMI pin not sampled at boot) */
+#endif /* KINETIS_NV_FOPT_BYTE */
+ 0xFF,
+ 0xFF
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+}
+
+/**
+ * @brief KL2x clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void kl2x_clock_init(void) {
+#if !KINETIS_NO_INIT
+
+ /* Disable COP watchdog */
+ SIM->COPC = 0;
+
+ /* Enable PORTA */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA;
+
+ /* --- MCG mode: FEI (default out of reset) ---
+ f_MCGOUTCLK = f_int * F
+ F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits.
+ Typical f_MCGOUTCLK = 21 MHz immediately after reset.
+ C4[DMX32]=0 and C4[DRST_DRS]=00 => FLL factor=640.
+ C3[SCTRIM] and C4[SCFTRIM] factory trim values apply to f_int. */
+
+ /* System oscillator drives 32 kHz clock (OSC32KSEL=0) */
+ SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
+
+#if KINETIS_HAS_MCG_LITE
+/* MCU only has MCG_Lite */
+
+#if KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_LIRC8M
+ /* Out of reset, the MCU is in LIRC8M mode. */
+ /* Except when coming out of the ROM bootloader, then
+ * the MCU is in HIRC mode; so better set it explicitly here. */
+
+ /* Switching to LIRC8M mode, page 414 of the KL27Z manual. */
+
+ /* (1) Write 1b to MCG_C2[IRCS] to select LIRC 8M. */
+ MCG->C2 |= MCG_C2_IRCS;
+
+ /* (2) Write 1b to MCG_C1[IRCLKEN] to enable LIRC clock (optional). */
+ MCG->C1 |= MCG_C1_IRCLKEN;
+
+ /* (2) Write 01b to MCG_C1[CLKS] to select LIRC clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_LIRC;
+
+ /* (3) Check MCG_S[CLKST] to confirm LIRC clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_LIRC )
+ ;
+
+#elif KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_HIRC
+ /* Switching to HIRC mode, page 413 of the KL27Z manual. */
+
+ /* (1) Write 1b to MCG_MC[HIRCEN] to enable HIRC (optional). */
+ MCG->MC |= MCG_MC_HIRCEN;
+
+ /* (2) Write 00b to MCG_C1[CLKS] to select HIRC clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_HIRC;
+
+ /* (3) Check MCG_S[CLKST] to confirm HIRC clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_HIRC )
+ ;
+
+#elif KINETIS_MCGLITE_MODE == KINETIS_MCGLITE_MODE_EXT
+ /* Assuming we have an external crystal, frequency
+ * specified with KINETIS_XTAL_FREQUENCY.
+ *
+ * Note: Except with 32768 kHz crystal (low-freq mode),
+ * external load capacitors and a feedback resistor
+ * are *required*. Additionally, a series resistor is
+ * required in the high-gain mode, and forbidden in
+ * the low-power mode.
+ * In this case, the internal caps can be configured
+ * via KINETIS_BOARD_OSCILLATOR_SETTING.
+ * (Page 420 of the KL27 manual.) */
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+ /* Switching to EXT mode, page 413 of the KL27 manual. */
+
+ /* (1) Configure MCG_C2[EREFS0] for external clock source selection. */
+ #if KINETIS_XTAL_FREQUENCY == 32768 /* low range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(0);
+ #elif (KINETIS_XTAL_FREQUENCY >= 1000000 && \
+ KINETIS_XTAL_FREQUENCY <= 8000000) /* high range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(1);
+ #elif (KINETIS_XTAL_FREQUENCY > 8000000 && \
+ KINETIS_XTAL_FREQUENCY <= 32000000) /* very high range */
+ MCG->C2 = (MCG->C2 & ~MCG_C2_RANGE0_MASK) | MCG_C2_RANGE0(2);
+ #else /* KINETIS_XTAL_FREQUENCY == */
+ #error KINETIS_XTAL_FREQUENCY not in allowed range
+ #endif /* KINETIS_XTAL_FREQUENCY == */
+
+ #if defined(KINETIS_XTAL_HIGH_GAIN) && KINETIS_XTAL_HIGH_GAIN
+ MCG->C2 |= MCG_C2_HGO0;
+ #endif /* KINETIS_XTAL_HIGH_GAIN */
+
+ /* Oscillator requested. */
+ MCG->C2 |= MCG_C2_EREFS0;
+
+ /* (2) Write 10b to MCG_C1[CLKS] to select external clock source. */
+ MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS_EXT;
+
+ /* (3) Check MCG_S[CLKST] to confirm external clock source is selected. */
+ while( (MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT )
+ ;
+
+#else /* KINETIS_MCGLITE_MODE */
+#error Unimplemented KINETIS_MCGLITE_MODE
+#endif /* KINETIS_MCGLITE_MODE */
+
+#else /* KINETIS_HAS_MCG_LITE */
+/* MCU has full blown MCG */
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+ /* This is the default mode at reset. */
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock) */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+
+ /* Configure FEI mode */
+ MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+ (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEE
+ /* TODO: check this, for generality */
+ /*
+ * FLL Enabled External (FEE) MCG Mode
+ * 24 MHz core, 12 MHz bus - using 32.768 kHz crystal with FLL.
+ * f_MCGOUTCLK = (f_ext / FLL_R) * F
+ * = (32.768 kHz ) *
+ * FLL_R is the reference divider selected by C1[FRDIV]
+ * F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32].
+ *
+ * Then the core/system and bus/flash clocks are divided:
+ * f_SYS = f_MCGOUTCLK / OUTDIV1 = 48 MHz / 1 = 48 MHz
+ * f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = MHz / 4 = 24 MHz
+ */
+
+ SIM->SOPT2 =
+ SIM_SOPT2_TPMSRC(1); /* MCGFLLCLK clock or MCGPLLCLK/2 */
+ /* PLLFLLSEL=0 -> MCGFLLCLK */
+
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock) */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1 - 1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4 - 1);
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+ /* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
+ /* To change from FEI mode to FEE mode: */
+ /* (1) Select the external clock source in C2 register.
+ Use low-power OSC mode (HGO0=0) which enables internal feedback
+ resistor, for 32.768 kHz crystal configuration. */
+ MCG->C2 =
+ MCG_C2_RANGE0(0) | /* low frequency range (<= 40 kHz) */
+ MCG_C2_EREFS0; /* external reference (using a crystal) */
+ /* (2) Write to C1 to select the clock mode. */
+ MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
+ MCG_C1_CLKS_FLLPLL | /* Use FLL for system clock, MCGCLKOUT. */
+ MCG_C1_FRDIV(0); /* Don't divide 32kHz ERCLK FLL reference. */
+ MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
+
+ /* Loop until S[OSCINIT0] is 1, indicating the
+ crystal selected by C2[EREFS0] has been initialized. */
+ while ((MCG->S & MCG_S_OSCINIT0) == 0)
+ ;
+ /* Loop until S[IREFST] is 0, indicating the
+ external reference is the current reference clock source. */
+ while ((MCG->S & MCG_S_IREFST) != 0)
+ ; /* Wait until external reference clock is FLL reference. */
+ /* (1)(e) Loop until S[CLKST] indicates FLL feeds MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_FLL)
+ ; /* Wait until FLL has been selected. */
+
+ /* --- MCG mode: FEE --- */
+ /* Set frequency range for DCO output (MCGFLLCLK). */
+ MCG->C4 = (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0) |
+ MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS);
+
+ /* Wait for the FLL lock time; t[fll_acquire][max] = 1 ms */
+ /* TODO - not implemented - is it required? Freescale example code
+ seems to omit it. */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+ uint32_t ratio, frdiv;
+ uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+ uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+ uint8_t i;
+
+ /*
+ * PLL Enabled External (PEE) MCG Mode
+ * Uses external crystal (KINETIS_XTAL_FREQUENCY) with PLL.
+ * f_MCGOUTCLK = (OSCCLK / PLL_R) * M
+ * OSCCLK = KINETIS_XTAL_FREQUENCY
+ * PLL_R is the reference divider selected by C5[PRDIV0]
+ * (OSCCLK/PLL_R must be between 2 and 4 MHz)
+ * M is the multiplier selected by C6[VDIV0]
+ *
+ * Running from PLL, so assuming PLLCLK = MCGOUTCLK.
+ *
+ * Then the core/system and bus/flash clocks are divided:
+ * f_SYS = f_MCGOUTCLK / OUTDIV1 = 96 MHz / 2 = 48 MHz
+ * f_BUS = f_MCGOUTCLK / OUTDIV1 / OUTDIV4 = 96 MHz / 4 = 24 MHz
+ */
+
+ /* EXTAL0 and XTAL0 */
+ PORTA->PCR[18] &= ~0x01000700; /* Set PA18 to analog (default) */
+ PORTA->PCR[19] &= ~0x01000700; /* Set PA19 to analog (default) */
+
+ /* Start in FEI mode */
+
+ /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+ OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+ /* Disable the internal capacitors */
+ OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+ /* From KL25P80M48SF0RM section 24.5.1.1 "Initializing the MCG". */
+ /* To change from FEI mode to FBE mode: */
+ /* (1) Select the external clock source in C2 register.
+ Use low-power OSC mode (HGO0=0) which enables internal feedback
+ resistor since FRDM-KL25Z has feedback resistor R25 unpopulated.
+ Use high-gain mode by setting C2[HGO0] instead if external
+ feedback resistor Rf is installed. */
+ MCG->C2 = MCG_C2_EREFS0; /* external reference (using a crystal) */
+ if (KINETIS_XTAL_FREQUENCY > 8000000UL)
+ MCG->C2 |= MCG_C2_RANGE0(2);
+ else
+ MCG->C2 |= MCG_C2_RANGE0(1);
+ /* (2) Write to C1 to select the clock mode. */
+ frdiv = 7;
+ ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
+ for (i = 0; i < ratio_quantity; ++i) {
+ if (ratio == ratios[i]) {
+ frdiv = i;
+ break;
+ }
+ }
+
+ /* Switch to crystal as clock source, FLL input of 31.25 KHz */
+ MCG->C1 = /* Clear the IREFS bit to switch to the external reference. */
+ MCG_C1_CLKS_ERCLK | /* Use Ext Ref Clock for system clock, MCGCLKOUT. */
+ MCG_C1_FRDIV(frdiv); /* Divide ERCLK / 256 for FLL reference. */
+ /* Note: FLL reference frequency must be 31.25 kHz to 39.0625 kHz. */
+
+ MCG->C4 &= ~(MCG_C4_DMX32 | MCG_C4_DRST_DRS_MASK);
+ MCG->C6 = 0; /* PLLS=0: Select FLL as MCG source, not PLL */
+
+ /* (3) Once configuration is set, wait for MCG mode change. */
+
+ /* From KL25P80M48SF0RM section 24.5.31: */
+ /* (1)(c) Loop until S[OSCINIT0] is 1, indicating the
+ crystal selected by C2[EREFS0] has been initialized. */
+ while ((MCG->S & MCG_S_OSCINIT0) == 0)
+ ;
+ /* (1)(d) Loop until S[IREFST] is 0, indicating the
+ external reference is the current reference clock source. */
+ while ((MCG->S & MCG_S_IREFST) != 0)
+ ; /* Wait until external reference clock is FLL reference. */
+ /* (1)(e) Loop until S[CLKST] is 2'b10, indicating
+ the external reference clock is selected to feed MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_ERCLK)
+ ; /* Wait until external reference clock has been selected. */
+
+ /* --- MCG mode: FBE (FLL bypassed, external crystal) ---
+ Now the MCG is in FBE mode.
+ Although the FLL is bypassed, it is still on. */
+
+ /* (2) Then configure C5[PRDIV0] to generate the
+ correct PLL reference frequency. */
+ #define KINETIS_PLLIN_FREQUENCY 2000000UL
+ /* TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz */
+ /* PLL External Reference Divide by ... */
+ MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
+ /* (3) Then from FBE transition to PBE mode. */
+ /* (3)(b) C6[PLLS]=1 to select PLL. */
+ /* (3)(b) C6[VDIV0]= PLLIN MHz * i = PLLCLK MHz. */
+ /* Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+ * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match */
+ for(i = 24; i < 56; i++) {
+ if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY)) {
+ /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+ break;
+ }
+ }
+ if(i>=56) /* Config PLL for 96 MHz output as default setting */
+ MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
+ /* (3)(d) Loop until S[PLLST], indicating PLL
+ is the PLLS clock source. */
+ while ((MCG->S & MCG_S_PLLST) == 0)
+ ; /* wait until PLL is the PLLS clock source. */
+ /* (3)(e) Loop until S[LOCK0] is set, indicating the PLL has acquired lock. */
+ /* PLL selected as MCG source. VDIV0=00000 (Multiply=24). */
+ while ((MCG->S & MCG_S_LOCK0) == 0)
+ ; /* wait until PLL locked */
+
+ /* --- MCG mode: PBE (PLL bypassed, external crystal) --- */
+
+ /* Set the PLL dividers for the different clocks */
+ /* The MCGOUTCLK is divided by OUTDIV1 and OUTDIV4:
+ * OUTDIV1 (divider for core/system and bus/flash clock)
+ * OUTDIV4 (additional divider for bus/flash clock)
+ * - these are computed in .h */
+ SIM->CLKDIV1 =
+ SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+ SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+
+ SIM->SOPT2 =
+ SIM_SOPT2_TPMSRC(1) | /* MCGFLLCLK clock or MCGPLLCLK/2 */
+ SIM_SOPT2_PLLFLLSEL; /* PLLFLLSEL=MCGPLLCLK/2 */
+
+ /* (4) Transition from PBE mode to PEE mode. */
+ /* (4)(a) C1[CLKS] = 2'b00 to select PLL output as system clock source. */
+ // Switch to PEE mode
+ // Select PLL output (CLKS=0)
+ // FLL external reference divider (FRDIV) already set
+ // External reference clock for FLL (IREFS=0)
+ MCG->C1 = MCG_C1_CLKS(0);
+ /* (4)(b) Loop until S[CLKST] are 2'b11, indicating the PLL output is selected for MCGOUTCLK. */
+ while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
+ ; /* wait until clock switched to PLL output */
+
+ /* --- MCG mode: PEE (PLL enabled, external crystal) --- */
+
+#else /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE != KINETIS_MCG_MODE_PEE */
+
+#endif /* KINETIS_HAS_MCG_LITE */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/**
+ * @brief Platform early initialization.
+ * @note All the involved constants come from the file @p board.h.
+ * @note This function is meant to be invoked early during the system
+ * initialization, it is usually invoked from the file
+ * @p board.c.
+ *
+ * @special
+ */
+void platform_early_init(void) {
+
+}
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.h new file mode 100644 index 0000000..d16e13f --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_lld.h @@ -0,0 +1,316 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/hal_lld.h
+ * @brief Kinetis KL2x HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H_
+#define HAL_LLD_H_
+
+#include "kl2xz.h"
+#include "kinetis_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "Kinetis"
+/** @} */
+
+#if KINETIS_HAS_MCG_LITE
+/* MCU only has MCG_Lite */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define KINETIS_HIRC 48000000 /**< High-frequency internal reference clock (USB recovery). */
+#define KINETIS_LIRC_8 8000000 /**< Low-frequency internal reference clock (faster). */
+#define KINETIS_LIRC_2 2000000 /**< Low-frequency internal reference clock (slower). */
+/** @} */
+
+/**
+ * @name MCG modes of operation
+ * @{
+ */
+#define KINETIS_MCGLITE_MODE_LIRC8M 1 /**< Low frequency internal reference mode (8MHz). */
+#define KINETIS_MCGLITE_MODE_LIRC2M 2 /**< Low frequency internal reference mode (2MHz). */
+#define KINETIS_MCGLITE_MODE_HIRC 3 /**< High frequency internal reference mode (with optional USB recovery). */
+#define KINETIS_MCGLITE_MODE_EXT 4 /**< External reference mode. */
+/** @} */
+
+#else /* KINETIS_HAS_MCG_LITE */
+/* MCU has full blown MCG */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F 4000000 /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S 32768 /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+/**
+ * @name MCG modes of operation
+ * @{
+ */
+#define KINETIS_MCG_MODE_FEI 1 /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE 2 /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI 3 /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE 4 /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE 5 /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE 6 /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI 7 /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE 8 /**< Bypassed Low Power External. */
+/** @} */
+
+#endif /* KINETIS_HAS_MCG_LITE */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT FALSE
+#endif
+
+/**
+ * @brief MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
+#endif
+
+#if !defined(KINETIS_MCGLITE_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_HIRC
+#endif
+
+/**
+ * @brief MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY 96000000UL
+#endif
+
+/**
+ * @brief Clock divider for core/system and bus/flash clocks (OUTDIV1).
+ * @note The allowed range is 1...16.
+ * @note The default value is calculated for a 48 MHz system clock
+ * from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+ #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV1 (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV1 2
+ #endif
+#endif
+
+/**
+ * @brief Additional clock divider bus/flash clocks (OUTDIV4).
+ * @note The allowed range is 1...8.
+ * @note This divider is on top of the OUTDIV1 divider.
+ * @note The default value is calculated for 24 MHz bus/flash clocks
+ * from a 96 MHz PLL output and 48 MHz core/system clock.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+ #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+ #define KINETIS_CLKDIV1_OUTDIV4 ((KINETIS_PLLCLK_FREQUENCY/KINETIS_CLKDIV1_OUTDIV1)/KINETIS_BUSCLK_FREQUENCY)
+ #else
+ #define KINETIS_CLKDIV1_OUTDIV4 2
+ #endif
+#endif
+
+/**
+ * @brief FLL DCO tuning enable for 32.768 kHz reference.
+ * @note Set to 1 for fine-tuning DCO for maximum frequency with
+ * a 32.768 kHz reference.
+ * @note The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32 1
+#endif
+
+/**
+ * @brief FLL DCO range selection.
+ * @note The allowed range is 0...3.
+ * @note The default value is calculated for 48 MHz FLL output
+ * from a 32.768 kHz external crystal.
+ * (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS 2
+#endif
+
+/**
+ * @brief MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
+#endif
+
+/**
+ * @brief MCU bus/flash clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY (KINETIS_SYSCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
+#endif
+
+/**
+ * @brief UART0 clock frequency.
+ * @note The default value is based on 96 MHz PLL/2 source.
+ * If you use a different source, such as the FLL,
+ * you must set this properly.
+ */
+#if !defined(KINETIS_UART0_CLOCK_FREQ) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_FREQ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+/**
+ * @brief UART0 clock source.
+ * @note The default value is to use PLL/2 or FLL source.
+ */
+#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_SRC 1
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+#error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+#error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+#error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+#error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+ #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+ KINETIS_SYSCLK_FREQUENCY
+#endif
+
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+ KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+ #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+ KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * DWT_CYCCNT register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value() 0
+
+/**
+ * @brief Realtime counter frequency.
+ * @note The DWT_CYCCNT register is incremented directly by the system
+ * clock so this function returns STM32_HCLK.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() 0
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void kl2x_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c new file mode 100644 index 0000000..2f56216 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c @@ -0,0 +1,388 @@ +/*
+ ChibiOS - Copyright (C) 2014 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/pwm_lld.c
+ * @brief KINETIS PWM subsystem low level driver source.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PWMD1 driver identifier.
+ * @note The driver PWMD1 allocates the timer TPM0 when enabled.
+ */
+#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief PWMD2 driver identifier.
+ * @note The driver PWMD2 allocates the timer TPM1 when enabled.
+ */
+#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief PWMD3 driver identifier.
+ * @note The driver PWMD3 allocates the timer TPM2 when enabled.
+ */
+#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+ uint32_t sr;
+
+ sr = pwmp->tpm->STATUS;
+ pwmp->tpm->STATUS = 0xFFFFFFFF;
+
+ if (((sr & TPMx_STATUS_TOF) != 0) &&
+ (pwmp->config->callback != NULL))
+ pwmp->config->callback(pwmp);
+ if (((sr & TPMx_STATUS_CH0F) != 0) &&
+ (pwmp->config->channels[0].callback != NULL))
+ pwmp->config->channels[0].callback(pwmp);
+ if (((sr & TPMx_STATUS_CH1F) != 0) &&
+ (pwmp->config->channels[1].callback != NULL))
+ pwmp->config->channels[1].callback(pwmp);
+ if (((sr & TPMx_STATUS_CH2F) != 0) &&
+ (pwmp->config->channels[2].callback != NULL))
+ pwmp->config->channels[2].callback(pwmp);
+ if (((sr & TPMx_STATUS_CH3F) != 0) &&
+ (pwmp->config->channels[3].callback != NULL))
+ pwmp->config->channels[3].callback(pwmp);
+ if (((sr & TPMx_STATUS_CH4F) != 0) &&
+ (pwmp->config->channels[4].callback != NULL))
+ pwmp->config->channels[4].callback(pwmp);
+ if (((sr & TPMx_STATUS_CH5F) != 0) &&
+ (pwmp->config->channels[5].callback != NULL))
+ pwmp->config->channels[5].callback(pwmp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_TPM0
+/**
+ * @brief TPM0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_TPM0_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_TPM0 */
+
+#if KINETIS_PWM_USE_TPM1
+/**
+ * @brief TPM1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_TPM1_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_TPM1 */
+
+#if KINETIS_PWM_USE_TPM2
+/**
+ * @brief TPM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_TPM2_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ pwm_lld_serve_interrupt(&PWMD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_TPM2 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if KINETIS_PWM_USE_TPM0
+ pwmObjectInit(&PWMD1);
+ PWMD1.channels = KINETIS_TPM0_CHANNELS;
+ PWMD1.tpm = TPM0;
+#endif
+
+#if KINETIS_PWM_USE_TPM1
+ pwmObjectInit(&PWMD2);
+ PWMD2.channels = KINETIS_TPM1_CHANNELS;
+ PWMD2.tpm = TPM1;
+#endif
+
+#if KINETIS_PWM_USE_TPM2
+ pwmObjectInit(&PWMD3);
+ PWMD3.channels = KINETIS_TPM2_CHANNELS;
+ PWMD3.tpm = TPM2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the PWM peripheral.
+ * @note Starting a driver that is already in the @p PWM_READY state
+ * disables all the active channels.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+ uint32_t psc;
+ int i;
+
+ if (pwmp->state == PWM_STOP) {
+ /* Clock activation and timer reset.*/
+#if KINETIS_PWM_USE_TPM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_TPM0;
+ nvicEnableVector(TPM0_IRQn, KINETIS_PWM_TPM0_IRQ_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_TPM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_TPM1;
+ nvicEnableVector(TPM1_IRQn, KINETIS_PWM_TPM1_IRQ_PRIORITY);
+ }
+#endif
+
+#if KINETIS_PWM_USE_TPM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC6 |= SIM_SCGC6_TPM2;
+ nvicEnableVector(TPM2_IRQn, KINETIS_PWM_TPM2_IRQ_PRIORITY);
+ }
+#endif
+ }
+
+ /* Disable LPTPM counter.*/
+ pwmp->tpm->SC = 0;
+ /* Clear count register.*/
+ pwmp->tpm->CNT = 0;
+
+ /* Prescaler value calculation.*/
+ psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
+ /* Prescaler must be power of two between 1 and 128.*/
+ osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
+ /* Prescaler register value determination.
+ Prescaler register value conveniently corresponds to bit position,
+ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
+ for (i = 0; i < 8; i++) {
+ if (psc == (1UL << i)) {
+ break;
+ }
+ }
+ /* Set prescaler and clock mode.
+ This also sets the following:
+ CPWM up-counting mode
+ Timer overflow interrupt disabled
+ DMA disabled.*/
+ pwmp->tpm->SC = TPMx_SC_CMOD_LPTPM_CLK | i;
+ /* Configure period.*/
+ pwmp->tpm->MOD = pwmp->period - 1;
+}
+
+/**
+ * @brief Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+ /* If in ready state then disables the PWM clock.*/
+ if (pwmp->state == PWM_READY) {
+#if KINETIS_PWM_USE_TPM0
+ if (&PWMD1 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_TPM0;
+ nvicDisableVector(TPM0_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_TPM1
+ if (&PWMD2 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_TPM1;
+ nvicDisableVector(TPM1_IRQn);
+ }
+#endif
+
+#if KINETIS_PWM_USE_TPM2
+ if (&PWMD3 == pwmp) {
+ SIM->SCGC6 &= ~SIM_SCGC6_TPM2;
+ nvicDisableVector(TPM2_IRQn);
+ }
+#endif
+ /* Disable LPTPM counter.*/
+ pwmp->tpm->SC = 0;
+ pwmp->tpm->MOD = 0;
+ }
+}
+
+
+/**
+ * @brief Enables a PWM channel.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is active using the specified configuration.
+ * @note The function has effect at the next cycle start.
+ * @note Channel notification is not enabled.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ * @param[in] width PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width) {
+ uint32_t mode = TPMx_CnSC_MSB; /* Edge-aligned PWM mode.*/
+
+ switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
+ case PWM_OUTPUT_ACTIVE_HIGH:
+ mode |= TPMx_CnSC_ELSB;
+ break;
+ case PWM_OUTPUT_ACTIVE_LOW:
+ mode |= TPMx_CnSC_ELSA;
+ break;
+ }
+
+ if (pwmp->tpm->C[channel].SC & TPMx_CnSC_CHIE)
+ mode |= TPMx_CnSC_CHIE;
+
+ pwmp->tpm->C[channel].SC = mode;
+ pwmp->tpm->C[channel].V = width;
+}
+
+/**
+ * @brief Disables a PWM channel and its notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The channel is disabled and its output line returned to the
+ * idle state.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+ pwmp->tpm->C[channel].SC = 0;
+ pwmp->tpm->C[channel].V = 0;
+}
+
+/**
+ * @brief Enables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+
+ pwmp->tpm->SC |= TPMx_SC_TOIE;
+}
+
+/**
+ * @brief Disables the periodic activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+
+ pwmp->tpm->SC &= ~TPMx_SC_TOIE;
+}
+
+/**
+ * @brief Enables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+
+ pwmp->tpm->C[channel].SC |= TPMx_CnSC_CHIE;
+}
+
+/**
+ * @brief Disables a channel de-activation edge notification.
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @pre The channel must have been activated using @p pwmEnableChannel().
+ * @note If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] channel PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel) {
+
+ pwmp->tpm->C[channel].SC &= ~TPMx_CnSC_CHIE;
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.h new file mode 100644 index 0000000..64ff9ee --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.h @@ -0,0 +1,305 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Adam J. Porter
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/pwm_lld.h
+ * @brief KINETIS PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef HAL_PWM_LLD_H_
+#define HAL_PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#if !defined(KINETIS_PWM_USE_TPM0)
+#define KINETIS_PWM_USE_TPM0 FALSE
+#endif
+#if !defined(KINETIS_PWM_USE_TPM1)
+#define KINETIS_PWM_USE_TPM1 FALSE
+#endif
+#if !defined(KINETIS_PWM_USE_TPM2)
+#define KINETIS_PWM_USE_TPM2 FALSE
+#endif
+
+/**
+ * @brief Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS 6
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief If advanced timer features switch.
+ * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
+ * enabled.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
+#define KINETIS_PWM_USE_ADVANCED FALSE
+#endif
+
+/**
+ * @brief TPM0 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM0_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief TPM1 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM1_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM1_IRQ_PRIORITY 2
+#endif
+
+/**
+ * @brief TPM2 interrupt priority level setting.
+ * @note The default is 2.
+ */
+#if !defined(KINETIS_PWM_TPM2_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_PWM_TPM2_IRQ_PRIORITY 2
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_TPM0 && !KINETIS_HAS_TPM0
+#error "TPM0 not present in the selected device"
+#endif
+
+#if KINETIS_PWM_USE_TPM1 && !KINETIS_HAS_TPM1
+#error "TPM1 not present in the selected device"
+#endif
+
+#if KINETIS_PWM_USE_TPM2 && !KINETIS_HAS_TPM2
+#error "TPM2 not present in the selected device"
+#endif
+
+#if !KINETIS_PWM_USE_TPM0 && !KINETIS_PWM_USE_TPM1 && !KINETIS_PWM_USE_TPM2
+#error "PWM driver activated but no TPM peripheral assigned"
+#endif
+
+#if KINETIS_PWM_USE_TPM0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM0_IRQ_PRIORITY"
+#endif
+
+#if KINETIS_PWM_USE_TPM1 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM1_IRQ_PRIORITY"
+#endif
+
+#if KINETIS_PWM_USE_TPM2 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_PWM_TPM2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_PWM_TPM2_IRQ_PRIORITY"
+#endif
+
+#if !defined(KINETIS_TPM0_IRQ_VECTOR)
+#error "KINETIS_TPM0_IRQ_VECTOR not defined"
+#endif
+
+#if !defined(KINETIS_TPM1_IRQ_VECTOR)
+#error "KINETIS_TPM1_IRQ_VECTOR not defined"
+#endif
+
+#if !defined(KINETIS_TPM2_IRQ_VECTOR)
+#error "KINETIS_TPM2_IRQ_VECTOR not defined"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel active logic level.
+ */
+ pwmmode_t mode;
+ /**
+ * @brief Channel callback pointer.
+ * @note This callback is invoked on the channel compare event. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief Type of a PWM driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ uint32_t frequency;
+ /**
+ * @brief PWM period in ticks.
+ * @note The low level can use assertions in order to catch invalid
+ * period specifications.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Periodic callback pointer.
+ * @note This callback is invoked on PWM counter reset. If set to
+ * @p NULL then the callback is disabled.
+ */
+ pwmcallback_t callback;
+ /**
+ * @brief Channels configurations.
+ */
+ PWMChannelConfig channels[PWM_CHANNELS];
+ /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief Structure representing a PWM driver.
+ */
+struct PWMDriver {
+ /**
+ * @brief Driver state.
+ */
+ pwmstate_t state;
+ /**
+ * @brief Current driver configuration data.
+ */
+ const PWMConfig *config;
+ /**
+ * @brief Current PWM period in ticks.
+ */
+ pwmcnt_t period;
+ /**
+ * @brief Mask of the enabled channels.
+ */
+ pwmchnmsk_t enabled;
+ /**
+ * @brief Number of channels in this instance.
+ */
+ pwmchannel_t channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+ PWM_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the TPM registers block.
+ */
+ TPM_TypeDef *tpm;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ * been activated using @p pwmStart().
+ * @pre The PWM unit must have been activated using @p pwmStart().
+ * @post The PWM unit period is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ * @note If a period is specified that is shorter than the pulse width
+ * programmed in one of the channels then the behavior is not
+ * guaranteed.
+ *
+ * @param[in] pwmp pointer to a @p PWMDriver object
+ * @param[in] period new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period) \
+ ((pwmp)->tpm->MOD = ((period) - 1))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_TPM0 || defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+#if KINETIS_PWM_USE_TPM1 || defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+#if KINETIS_PWM_USE_TPM2 || defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void pwm_lld_init(void);
+ void pwm_lld_start(PWMDriver *pwmp);
+ void pwm_lld_stop(PWMDriver *pwmp);
+ void pwm_lld_enable_channel(PWMDriver *pwmp,
+ pwmchannel_t channel,
+ pwmcnt_t width);
+ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+ void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+ pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* HAL_PWM_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/kinetis_registry.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/kinetis_registry.h new file mode 100644 index 0000000..49b1ec8 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/kinetis_registry.h @@ -0,0 +1,258 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+ (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/kinetis_registry.h
+ * @brief KL2x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef KINETIS_REGISTRY_H_
+#define KINETIS_REGISTRY_H_
+
+#if !defined(KL2x) || defined(__DOXYGEN__)
+#define KL2x
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name KL2x capabilities
+ * @{
+ */
+
+/*===========================================================================*/
+/* Common features */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX 48000000
+
+/**
+ * @brief Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX 24000000
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0 TRUE
+#define KINETIS_ADC0_IRQ_VECTOR Vector7C
+#define KINETIS_HAS_ADC1 FALSE
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR Vector40
+#define KINETIS_DMA1_IRQ_VECTOR Vector44
+#define KINETIS_DMA2_IRQ_VECTOR Vector48
+#define KINETIS_DMA3_IRQ_VECTOR Vector4C
+#define KINETIS_HAS_DMA_ERROR_IRQ FALSE
+
+/* GPT attributes.*/
+#define KINETIS_PIT_IRQ_VECTOR Vector98
+#define KINETIS_HAS_PIT_COMMON_IRQ TRUE
+#define KINETIS_HAS_PIT0 TRUE
+#define KINETIS_HAS_PIT1 TRUE
+#define KINETIS_HAS_PIT2 FALSE
+#define KINETIS_HAS_PIT3 FALSE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0 TRUE
+#define KINETIS_I2C0_IRQ_VECTOR Vector60
+#define KINETIS_HAS_I2C1 TRUE
+#define KINETIS_I2C1_IRQ_VECTOR Vector64
+
+/* Serial attributes */
+#define KINETIS_HAS_SERIAL0 TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR Vector70
+#define KINETIS_HAS_SERIAL1 TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR Vector74
+#define KINETIS_HAS_SERIAL2 TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR Vector78
+#define KINETIS_HAS_SERIAL_ERROR_IRQ FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0 TRUE
+#define KINETIS_SPI0_IRQ_VECTOR Vector68
+#define KINETIS_HAS_SPI1 TRUE
+#define KINETIS_SPI1_IRQ_VECTOR Vector6C
+
+/* TPM attributes.*/
+#define KINETIS_HAS_TPM0 TRUE
+#define KINETIS_TPM0_CHANNELS 6
+#define KINETIS_TPM0_IRQ_VECTOR Vector84
+#define KINETIS_HAS_TPM1 TRUE
+#define KINETIS_TPM1_CHANNELS 2
+#define KINETIS_TPM1_IRQ_VECTOR Vector88
+#define KINETIS_HAS_TPM2 TRUE
+#define KINETIS_TPM2_CHANNELS 2
+#define KINETIS_TPM2_IRQ_VECTOR Vector8C
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB TRUE
+#define KINETIS_USB_IRQ_VECTOR VectorA0
+
+/* FTFA attributes.*/
+#define KINETIS_FTFA_IRQ_VECTOR Vector54
+
+/* LPTMR attributes */
+#define KINETIS_LPTMR0_IRQ_VECTOR VectorB0
+
+/*===========================================================================*/
+/* KL25 */
+/*===========================================================================*/
+#if defined(KL25) || defined(__DOXYGEN__)
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 FALSE
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE FALSE
+
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP TRUE
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/*===========================================================================*/
+/* KL26 */
+/*===========================================================================*/
+#elif defined(KL26) /* defined(KL25) */
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTC and PORTD */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ TRUE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 TRUE
+#define KINETIS_I2S0_IRQ_VECTOR Vector9C
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE FALSE
+
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP TRUE
+#define KINETIS_SERIAL0_IS_LPUART FALSE
+#define KINETIS_SERIAL1_IS_LPUART FALSE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY FALSE
+
+/*===========================================================================*/
+/* KL27 */
+/*===========================================================================*/
+#elif defined(KL27Zxxx) || defined(KL27Zxx) /* defined(KL26) */
+
+#if !defined(KL27)
+#define KL27
+#endif
+
+/* MCG attributes.*/
+#define KINETIS_HAS_MCG_LITE TRUE
+
+/* Note: on this device, SERIAL2 IRQ is alternatively FlexIO IRQ. */
+/* Serial attributes */
+#define KINETIS_SERIAL0_IS_UARTLP FALSE
+#define KINETIS_SERIAL0_IS_LPUART TRUE
+#define KINETIS_SERIAL1_IS_LPUART TRUE
+
+/* USB attributes.*/
+#define KINETIS_USB0_IS_USBOTG FALSE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
+
+/*===========================================================================*/
+/* KL27Zxxx (MKL27Z128* and MKL27Z256*) specific */
+/*===========================================================================*/
+#if defined(KL27Zxxx)
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 TRUE
+#define KINTEIS_DAC0_IRQ_VECTOR VectorA4
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTC and PORTD */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ TRUE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 TRUE
+#define KINETIS_I2S0_IRQ_VECTOR Vector9C
+
+/*===========================================================================*/
+/* KL27Zxx (MKL27Z32* and MKL27Z264*) specific */
+/*===========================================================================*/
+#elif defined(KL27Zxx) /* defined(KL27Zxxx) */
+
+/* Has CRC module */
+/* Does not have USB voltage regulator */
+/* Does have KEEP_ALIVE USB feature */
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0 FALSE
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR VectorB8
+/* Common IRQ vector for PORTB to PORTE */
+#define KINETIS_PORTD_IRQ_VECTOR VectorBC
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ TRUE
+#define KINETIS_GPIO_HAS_OPENDRAIN FALSE
+
+/* I2S attributes.*/
+#define KINETIS_HAS_I2S0 FALSE
+
+#endif /* defined(KL27Zxx) */
+
+#else /* ! (KL25 || KL26 || KL27) */
+#error MCU type not described in kinetis_registry
+#endif /* KL2Y */
+
+/** @} */
+
+#endif /* KINETIS_REGISTRY_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/platform.mk b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/platform.mk new file mode 100644 index 0000000..dda7a6d --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/KL2x/platform.mk @@ -0,0 +1,17 @@ +# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x/hal_pwm_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/KL2x \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.c new file mode 100644 index 0000000..56ae4c3 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.c @@ -0,0 +1,259 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/adc_lld.c
+ * @brief KINETIS ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define ADC_CHANNEL_MASK 0x1f
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if KINETIS_ADC_USE_ADC0 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void calibrate(ADCDriver *adcp) {
+
+ /* Clock Divide by 8, Use Bus Clock Div 2 */
+ /* At 48MHz this results in ADCCLK of 48/8/2 == 3MHz */
+ adcp->adc->CFG1 = ADCx_CFG1_ADIV(ADCx_CFG1_ADIV_DIV_8) |
+ ADCx_CFG1_ADICLK(ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2);
+
+ /* Use software trigger and disable DMA etc. */
+ adcp->adc->SC2 = 0;
+
+ /* Enable Hardware Average, Average 32 Samples, Calibrate */
+ adcp->adc->SC3 = ADCx_SC3_AVGE |
+ ADCx_SC3_AVGS(ADCx_SC3_AVGS_AVERAGE_32_SAMPLES) |
+ ADCx_SC3_CAL;
+
+ /* FIXME: May take several ms. Use an interrupt instead of busy wait */
+ /* Wait for calibration completion */
+ while (!(adcp->adc->SC1A & ADCx_SC1n_COCO))
+ ;
+
+ uint16_t gain = ((adcp->adc->CLP0 + adcp->adc->CLP1 + adcp->adc->CLP2 +
+ adcp->adc->CLP3 + adcp->adc->CLP4 + adcp->adc->CLPS) / 2) | 0x8000;
+ adcp->adc->PG = gain;
+
+ gain = ((adcp->adc->CLM0 + adcp->adc->CLM1 + adcp->adc->CLM2 +
+ adcp->adc->CLM3 + adcp->adc->CLM4 + adcp->adc->CLMS) / 2) | 0x8000;
+ adcp->adc->MG = gain;
+
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_ADC_USE_ADC0 || defined(__DOXYGEN__)
+/**
+ * @brief ADC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_ADC0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ ADCDriver *adcp = &ADCD1;
+
+ /* Disable Interrupt, Disable Channel */
+ adcp->adc->SC1A = ADCx_SC1n_ADCH(ADCx_SC1n_ADCH_DISABLED);
+
+ /* Read the sample into the buffer */
+ adcp->samples[adcp->current_index++] = adcp->adc->RA;
+
+ bool more = true;
+
+ /* At the end of the buffer then we may be finished */
+ if (adcp->current_index == adcp->number_of_samples) {
+ /* We are never finished in circular mode */ + more = ADCD1.grpp->circular; + + _adc_isr_full_code(&ADCD1);
+
+ adcp->current_index = 0;
+
+ }
+
+ if (more) {
+
+ /* Signal half completion in circular mode. */
+ if (ADCD1.grpp->circular &&
+ (adcp->current_index == (adcp->number_of_samples / 2))) {
+
+ _adc_isr_half_code(&ADCD1);
+ }
+
+ /* Skip to the next channel */
+ do {
+ adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
+ } while (((1 << adcp->current_channel) & adcp->grpp->channel_mask) == 0);
+
+ /* Enable Interrupt, Select the Channel */
+ adcp->adc->SC1A = ADCx_SC1n_AIEN | ADCx_SC1n_ADCH(adcp->current_channel);
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if KINETIS_ADC_USE_ADC0
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD1);
+#endif
+
+ /* The shared vector is initialized on driver initialization and never
+ disabled.*/
+ nvicEnableVector(ADC0_IRQn, KINETIS_ADC_IRQ_PRIORITY);
+}
+
+/**
+ * @brief Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+ /* If in stopped state then enables the ADC clock.*/
+ if (adcp->state == ADC_STOP) {
+ SIM->SCGC6 |= SIM_SCGC6_ADC0;
+
+#if KINETIS_ADC_USE_ADC0
+ if (&ADCD1 == adcp) {
+ adcp->adc = ADC0;
+ if (adcp->config->calibrate) {
+ calibrate(adcp);
+ }
+ }
+#endif /* KINETIS_ADC_USE_ADC0 */
+ }
+}
+
+/**
+ * @brief Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+ /* If in ready state then disables the ADC clock.*/
+ if (adcp->state == ADC_READY) {
+ SIM->SCGC6 &= ~SIM_SCGC6_ADC0;
+
+#if KINETIS_ADC_USE_ADC0
+ if (&ADCD1 == adcp) {
+ /* Disable Interrupt, Disable Channel */
+ adcp->adc->SC1A = ADCx_SC1n_ADCH(ADCx_SC1n_ADCH_DISABLED);
+ }
+#endif
+ }
+}
+
+/**
+ * @brief Starts an ADC conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+ const ADCConversionGroup *grpp = adcp->grpp;
+
+ /* Enable the Bandgap Buffer if channel mask includes BANDGAP */
+ if (grpp->channel_mask & ADC_BANDGAP) {
+ PMC->REGSC |= PMC_REGSC_BGBE;
+ }
+
+ adcp->number_of_samples = adcp->depth * grpp->num_channels;
+ adcp->current_index = 0;
+
+ /* Skip to the next channel */
+ adcp->current_channel = 0;
+ while (((1 << adcp->current_channel) & grpp->channel_mask) == 0) {
+ adcp->current_channel = (adcp->current_channel + 1) & ADC_CHANNEL_MASK;
+ }
+
+ /* Set clock speed and conversion size */
+ adcp->adc->CFG1 = grpp->cfg1;
+
+ /* Set averaging */
+ adcp->adc->SC3 = grpp->sc3;
+
+ /* Enable Interrupt, Select Channel */
+ adcp->adc->SC1A = ADCx_SC1n_AIEN | ADCx_SC1n_ADCH(adcp->current_channel);
+}
+
+/**
+ * @brief Stops an ongoing conversion.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+ const ADCConversionGroup *grpp = adcp->grpp;
+
+ /* Disable the Bandgap buffer if channel mask includes BANDGAP */
+ if (grpp->channel_mask & ADC_BANDGAP) {
+ /* Clear BGBE, ACKISO is w1c, avoid setting */
+ PMC->REGSC &= ~(PMC_REGSC_BGBE | PMC_REGSC_ACKISO);
+ }
+
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.h new file mode 100644 index 0000000..c4edbd6 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_adc_lld.h @@ -0,0 +1,360 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/adc_lld.h
+ * @brief KINETIS ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef HAL_ADC_LLD_H_
+#define HAL_ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Minimum ADC clock frequency.
+ */
+#define KINETIS_ADCCLK_MIN 600000
+
+/**
+ * @brief Maximum ADC clock frequency.
+ */
+#define KINETIS_ADCCLK_MAX 36000000
+
+#define ADCx_SC3_AVGS_AVERAGE_4_SAMPLES 0
+#define ADCx_SC3_AVGS_AVERAGE_8_SAMPLES 1
+#define ADCx_SC3_AVGS_AVERAGE_16_SAMPLES 2
+#define ADCx_SC3_AVGS_AVERAGE_32_SAMPLES 3
+
+#define ADCx_CFG1_ADIV_DIV_1 0
+#define ADCx_CFG1_ADIV_DIV_2 1
+#define ADCx_CFG1_ADIV_DIV_4 2
+#define ADCx_CFG1_ADIV_DIV_8 3
+
+#define ADCx_CFG1_ADIVCLK_BUS_CLOCK 0
+#define ADCx_CFG1_ADIVCLK_BUS_CLOCK_DIV_2 1
+#define ADCx_CFG1_ADIVCLK_BUS_ALTCLK 2
+#define ADCx_CFG1_ADIVCLK_BUS_ADACK 3
+
+#define ADCx_CFG1_MODE_8_OR_9_BITS 0
+#define ADCx_CFG1_MODE_12_OR_13_BITS 1
+#define ADCx_CFG1_MODE_10_OR_11_BITS 2
+#define ADCx_CFG1_MODE_16_BITS 3
+
+#define ADCx_SC1n_ADCH_DAD0 0
+#define ADCx_SC1n_ADCH_DAD1 1
+#define ADCx_SC1n_ADCH_DAD2 2
+#define ADCx_SC1n_ADCH_DAD3 3
+#define ADCx_SC1n_ADCH_DADP0 0
+#define ADCx_SC1n_ADCH_DADP1 1
+#define ADCx_SC1n_ADCH_DADP2 2
+#define ADCx_SC1n_ADCH_DADP3 3
+#define ADCx_SC1n_ADCH_AD4 4
+#define ADCx_SC1n_ADCH_AD5 5
+#define ADCx_SC1n_ADCH_AD6 6
+#define ADCx_SC1n_ADCH_AD7 7
+#define ADCx_SC1n_ADCH_AD8 8
+#define ADCx_SC1n_ADCH_AD9 9
+#define ADCx_SC1n_ADCH_AD10 10
+#define ADCx_SC1n_ADCH_AD11 11
+#define ADCx_SC1n_ADCH_AD12 12
+#define ADCx_SC1n_ADCH_AD13 13
+#define ADCx_SC1n_ADCH_AD14 14
+#define ADCx_SC1n_ADCH_AD15 15
+#define ADCx_SC1n_ADCH_AD16 16
+#define ADCx_SC1n_ADCH_AD17 17
+#define ADCx_SC1n_ADCH_AD18 18
+#define ADCx_SC1n_ADCH_AD19 19
+#define ADCx_SC1n_ADCH_AD20 20
+#define ADCx_SC1n_ADCH_AD21 21
+#define ADCx_SC1n_ADCH_AD22 22
+#define ADCx_SC1n_ADCH_AD23 23
+#define ADCx_SC1n_ADCH_TEMP_SENSOR 26
+#define ADCx_SC1n_ADCH_BANDGAP 27
+#define ADCx_SC1n_ADCH_VREFSH 29
+#define ADCx_SC1n_ADCH_VREFSL 30
+#define ADCx_SC1n_ADCH_DISABLED 31
+
+#define ADC_DAD0 (1 << ADCx_SC1n_ADCH_DAD0)
+#define ADC_DAD1 (1 << ADCx_SC1n_ADCH_DAD1)
+#define ADC_DAD2 (1 << ADCx_SC1n_ADCH_DAD2)
+#define ADC_DAD3 (1 << ADCx_SC1n_ADCH_DAD3)
+#define ADC_DADP0 (1 << ADCx_SC1n_ADCH_DADP0)
+#define ADC_DADP1 (1 << ADCx_SC1n_ADCH_DADP1)
+#define ADC_DADP2 (1 << ADCx_SC1n_ADCH_DADP2)
+#define ADC_DADP3 (1 << ADCx_SC1n_ADCH_DADP3)
+#define ADC_AD4 (1 << ADCx_SC1n_ADCH_AD4)
+#define ADC_AD5 (1 << ADCx_SC1n_ADCH_AD5)
+#define ADC_AD6 (1 << ADCx_SC1n_ADCH_AD6)
+#define ADC_AD7 (1 << ADCx_SC1n_ADCH_AD7)
+#define ADC_AD8 (1 << ADCx_SC1n_ADCH_AD8)
+#define ADC_AD9 (1 << ADCx_SC1n_ADCH_AD9)
+#define ADC_AD10 (1 << ADCx_SC1n_ADCH_AD10)
+#define ADC_AD11 (1 << ADCx_SC1n_ADCH_AD11)
+#define ADC_AD12 (1 << ADCx_SC1n_ADCH_AD12)
+#define ADC_AD13 (1 << ADCx_SC1n_ADCH_AD13)
+#define ADC_AD14 (1 << ADCx_SC1n_ADCH_AD14)
+#define ADC_AD15 (1 << ADCx_SC1n_ADCH_AD15)
+#define ADC_AD16 (1 << ADCx_SC1n_ADCH_AD16)
+#define ADC_AD17 (1 << ADCx_SC1n_ADCH_AD17)
+#define ADC_AD18 (1 << ADCx_SC1n_ADCH_AD18)
+#define ADC_AD19 (1 << ADCx_SC1n_ADCH_AD19)
+#define ADC_AD20 (1 << ADCx_SC1n_ADCH_AD20)
+#define ADC_AD21 (1 << ADCx_SC1n_ADCH_AD21)
+#define ADC_AD22 (1 << ADCx_SC1n_ADCH_AD22)
+#define ADC_AD23 (1 << ADCx_SC1n_ADCH_AD23)
+#define ADC_TEMP_SENSOR (1 << ADCx_SC1n_ADCH_TEMP_SENSOR)
+#define ADC_BANDGAP (1 << ADCx_SC1n_ADCH_BANDGAP)
+#define ADC_VREFSH (1 << ADCx_SC1n_ADCH_VREFSH)
+#define ADC_VREFSL (1 << ADCx_SC1n_ADCH_VREFSL)
+#define ADC_DISABLED (1 << ADCx_SC1n_ADCH_DISABLED)
+
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+
+/**
+ * @brief ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_ADC_USE_ADC0) || defined(__DOXYGEN__)
+#define KINETIS_ADC_USE_ADC0 FALSE
+#endif
+
+/**
+ * @brief ADC interrupt priority level setting.
+ */
+#if !defined(KINETIS_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_ADC_IRQ_PRIORITY 5
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_ADC_USE_ADC0 && !KINETIS_HAS_ADC0
+#error "ADC1 not present in the selected device"
+#endif
+
+#if !KINETIS_ADC_USE_ADC0
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief Possible ADC failure causes.
+ * @note Error codes are architecture dependent and should not relied
+ * upon.
+ */
+typedef enum {
+ ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
+ ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
+} adcerror_t;
+
+/**
+ * @brief Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief ADC notification callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] buffer pointer to the most recent samples data
+ * @param[in] n number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief ADC error callback type.
+ *
+ * @param[in] adcp pointer to the @p ADCDriver object triggering the
+ * callback
+ * @param[in] err ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ * operation.
+ */
+typedef struct {
+ /**
+ * @brief Enables the circular buffer mode for the group.
+ */
+ bool circular;
+ /**
+ * @brief Number of the analog channels belonging to the conversion group.
+ */
+ adc_channels_num_t num_channels;
+ /**
+ * @brief Callback function associated to the group or @p NULL.
+ */
+ adccallback_t end_cb;
+ /**
+ * @brief Error callback or @p NULL.
+ */
+ adcerrorcallback_t error_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Bitmask of channels for ADC conversion.
+ */
+ uint32_t channel_mask;
+ /**
+ * @brief ADC CFG1 register initialization data.
+ * @note All the required bits must be defined into this field.
+ */
+ uint32_t cfg1;
+ /**
+ * @brief ADC SC3 register initialization data.
+ * @note All the required bits must be defined into this field.
+ */
+ uint32_t sc3;
+} ADCConversionGroup;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /* Perform first time calibration */
+ bool calibrate;
+} ADCConfig;
+
+/**
+ * @brief Structure representing an ADC driver.
+ */
+struct ADCDriver {
+ /**
+ * @brief Driver state.
+ */
+ adcstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const ADCConfig *config;
+ /**
+ * @brief Current samples buffer pointer or @p NULL.
+ */
+ adcsample_t *samples;
+ /**
+ * @brief Current samples buffer depth or @p 0.
+ */
+ size_t depth;
+ /**
+ * @brief Current conversion group pointer or @p NULL.
+ */
+ const ADCConversionGroup *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+ ADC_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the ADCx registers block.
+ */
+ ADC_TypeDef *adc;
+ /**
+ * @brief Number of samples expected.
+ */
+ size_t number_of_samples;
+ /**
+ * @brief Current position in the buffer.
+ */
+ size_t current_index;
+ /**
+ * @brief Current channel index into group channel_mask.
+ */
+ size_t current_channel;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_ADC_USE_ADC0 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void adc_lld_init(void);
+ void adc_lld_start(ADCDriver *adcp);
+ void adc_lld_stop(ADCDriver *adcp);
+ void adc_lld_start_conversion(ADCDriver *adcp);
+ void adc_lld_stop_conversion(ADCDriver *adcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* HAL_ADC_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.c new file mode 100644 index 0000000..21bb6e0 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.c @@ -0,0 +1,434 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/ext_lld.c
+ * @brief KINETIS EXT subsystem low level driver source.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define PCR_IRQC_DISABLED 0x0
+#define PCR_IRQC_DMA_RISING_EDGE 0x1
+#define PCR_IRQC_DMA_FALLING_EDGE 0x2
+#define PCR_IRQC_DMA_EITHER_EDGE 0x3
+
+#define PCR_IRQC_LOGIC_ZERO 0x8
+#define PCR_IRQC_RISING_EDGE 0x9
+#define PCR_IRQC_FALLING_EDGE 0xA
+#define PCR_IRQC_EITHER_EDGE 0xB
+#define PCR_IRQC_LOGIC_ONE 0xC
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTD1 driver identifier.
+ */
+EXTDriver EXTD1;
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/* A channel map for each channel.
+ *
+ * The index is the pin number.
+ * The result is the channel for that pin.
+ */
+#if KINETIS_EXT_PORTA_WIDTH > 0
+uint8_t porta_channel_map[KINETIS_EXT_PORTA_WIDTH];
+#endif
+#if KINETIS_EXT_PORTB_WIDTH > 0
+uint8_t portb_channel_map[KINETIS_EXT_PORTB_WIDTH];
+#endif
+#if KINETIS_EXT_PORTC_WIDTH > 0
+uint8_t portc_channel_map[KINETIS_EXT_PORTC_WIDTH];
+#endif
+#if KINETIS_EXT_PORTD_WIDTH > 0
+uint8_t portd_channel_map[KINETIS_EXT_PORTD_WIDTH];
+#endif
+#if KINETIS_EXT_PORTE_WIDTH > 0
+uint8_t porte_channel_map[KINETIS_EXT_PORTE_WIDTH];
+#endif
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+static void ext_lld_exti_irq_enable(void) {
+
+#if KINETIS_EXT_PORTA_WIDTH > 0
+ nvicEnableVector(PINA_IRQn, KINETIS_EXT_PORTA_IRQ_PRIORITY);
+#endif
+
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+#if (KINETIS_EXT_PORTB_WIDTH > 0) || (KINETIS_EXT_PORTC_WIDTH > 0) \
+ || (KINETIS_EXT_PORTD_WIDTH > 0) || (KINETIS_EXT_PORTE_WIDTH > 0)
+ nvicEnableVector(PINBCDE_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
+#endif
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+#if (KINETIS_EXT_PORTC_WIDTH > 0) || (KINETIS_EXT_PORTD_WIDTH > 0)
+ nvicEnableVector(PINCD_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
+#endif
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
+#if KINETIS_EXT_PORTB_WIDTH > 0
+ nvicEnableVector(PINB_IRQn, KINETIS_EXT_PORTB_IRQ_PRIORITY);
+#endif
+#if KINETIS_EXT_PORTC_WIDTH > 0
+ nvicEnableVector(PINC_IRQn, KINETIS_EXT_PORTC_IRQ_PRIORITY);
+#endif
+#if KINETIS_EXT_PORTD_WIDTH > 0
+ nvicEnableVector(PIND_IRQn, KINETIS_EXT_PORTD_IRQ_PRIORITY);
+#endif
+#if KINETIS_EXT_PORTE_WIDTH > 0
+ nvicEnableVector(PINE_IRQn, KINETIS_EXT_PORTE_IRQ_PRIORITY);
+#endif
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+static void ext_lld_exti_irq_disable(void) {
+
+#if KINETIS_EXT_PORTA_WIDTH > 0
+ nvicDisableVector(PINA_IRQn);
+#endif
+
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+#if (KINETIS_EXT_PORTB_WIDTH > 0) || (KINETIS_EXT_PORTC_WIDTH > 0) \
+ || (KINETIS_EXT_PORTD_WIDTH > 0) || (KINETIS_EXT_PORTE_WIDTH > 0)
+ nvicDisableVector(PINBCDE_IRQn);
+#endif
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+#if (KINETIS_EXT_PORTC_WIDTH > 0) || (KINETIS_EXT_PORTD_WIDTH > 0)
+ nvicDisableVector(PINCD_IRQn);
+#endif
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
+#if KINETIS_EXT_PORTB_WIDTH > 0
+ nvicDisableVector(PINB_IRQn);
+#endif
+#if KINETIS_EXT_PORTC_WIDTH > 0
+ nvicDisableVector(PINC_IRQn);
+#endif
+#if KINETIS_EXT_PORTD_WIDTH > 0
+ nvicDisableVector(PIND_IRQn);
+#endif
+#if KINETIS_EXT_PORTE_WIDTH > 0
+ nvicDisableVector(PINE_IRQn);
+#endif
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*
+ * Generic interrupt handler.
+ */
+static inline void irq_handler(PORT_TypeDef * const port, const unsigned port_width, const uint8_t *channel_map) {
+ unsigned pin;
+ uint32_t isfr = port->ISFR;
+
+ /* Clear all pending interrupts on this port. */
+ port->ISFR = 0xFFFFFFFF;
+
+ for (pin = 0; pin < port_width; pin++) {
+ if (isfr & (1 << pin)) {
+ expchannel_t channel = channel_map[pin];
+ EXTD1.config->channels[channel].cb(&EXTD1, channel);
+ }
+ }
+}
+
+/**
+ * @brief PORTA interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTA_IRQ_VECTOR) && KINETIS_EXT_PORTA_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTA_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTA, KINETIS_EXT_PORTA_WIDTH, porta_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTA_WIDTH > 0 */
+
+#if KINETIS_EXT_HAS_COMMON_BCDE_IRQ
+
+#if defined(KINETIS_PORTD_IRQ_VECTOR)
+OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+#if (KINETIS_EXT_PORTB_WIDTH > 0)
+ irq_handler(PORTB, KINETIS_EXT_PORTB_WIDTH, portb_channel_map);
+#endif
+#if (KINETIS_EXT_PORTC_WIDTH > 0)
+ irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
+#endif
+#if (KINETIS_EXT_PORTD_WIDTH > 0)
+ irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
+#endif
+#if (KINETIS_EXT_PORTE_WIDTH > 0)
+ irq_handler(PORTE, KINETIS_EXT_PORTE_WIDTH, porte_channel_map);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(KINETIS_PORTD_IRQ_VECTOR) */
+
+#elif KINETIS_EXT_HAS_COMMON_CD_IRQ /* KINETIS_EXT_HAS_COMMON_BCDE_IRQ */
+
+#if defined(KINETIS_PORTD_IRQ_VECTOR)
+OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+#if (KINETIS_EXT_PORTC_WIDTH > 0)
+ irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
+#endif
+#if (KINETIS_EXT_PORTD_WIDTH > 0)
+ irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* defined(KINETIS_PORTD_IRQ_VECTOR) */
+
+
+#else /* KINETIS_EXT_HAS_COMMON_CD_IRQ */
+
+/**
+ * @brief PORTB interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTB_IRQ_VECTOR) && KINETIS_EXT_PORTB_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTB_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTB, KINETIS_EXT_PORTB_WIDTH, portb_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTB_WIDTH > 0 */
+
+/**
+ * @brief PORTC interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTC_IRQ_VECTOR) && KINETIS_EXT_PORTC_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTC_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTC, KINETIS_EXT_PORTC_WIDTH, portc_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTC_WIDTH > 0 */
+
+/**
+ * @brief PORTD interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTD_IRQ_VECTOR) && KINETIS_EXT_PORTD_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTD_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTD, KINETIS_EXT_PORTD_WIDTH, portd_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTD_WIDTH > 0 */
+
+/**
+ * @brief PORTE interrupt handler.
+ *
+ * @isr
+ */
+#if defined(KINETIS_PORTE_IRQ_VECTOR) && KINETIS_EXT_PORTE_WIDTH > 0
+OSAL_IRQ_HANDLER(KINETIS_PORTE_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+
+ irq_handler(PORTE, KINETIS_EXT_PORTE_WIDTH, porte_channel_map);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_EXT_PORTE_WIDTH > 0 */
+
+#endif /* !KINETIS_EXT_HAS_COMMON_CD_IRQ */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level EXT driver initialization.
+ *
+ * @notapi
+ */
+void ext_lld_init(void) {
+
+ /* Driver initialization.*/
+ extObjectInit(&EXTD1);
+}
+
+/**
+ * @brief Configures and activates the EXT peripheral.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_start(EXTDriver *extp) {
+ expchannel_t channel;
+
+ if (extp->state == EXT_STOP)
+ ext_lld_exti_irq_enable();
+
+ /* Configuration of automatic channels.*/
+ for (channel = 0; channel < EXT_MAX_CHANNELS; channel++) {
+
+ uint32_t mode = extp->config->channels[channel].mode;
+ PORT_TypeDef *port = extp->config->channels[channel].port;
+ uint32_t pin = extp->config->channels[channel].pin;
+
+ /* Initialize the channel map */
+#if KINETIS_EXT_PORTA_WIDTH > 0
+ if (port == PORTA)
+ porta_channel_map[pin] = channel;
+ else
+#endif
+#if KINETIS_EXT_PORTB_WIDTH > 0
+ if (port == PORTB)
+ portb_channel_map[pin] = channel;
+ else
+#endif
+#if KINETIS_EXT_PORTC_WIDTH > 0
+ if (port == PORTC)
+ portc_channel_map[pin] = channel;
+ else
+#endif
+#if KINETIS_EXT_PORTD_WIDTH > 0
+ if (port == PORTD)
+ portd_channel_map[pin] = channel;
+ else
+#endif
+#if KINETIS_EXT_PORTE_WIDTH > 0
+ if (port == PORTE)
+ porte_channel_map[pin] = channel;
+ else
+#endif
+ {}
+
+ if (mode & EXT_CH_MODE_AUTOSTART)
+ ext_lld_channel_enable(extp, channel);
+ else if (port != NULL)
+ ext_lld_channel_disable(extp, channel);
+ }
+}
+
+/**
+ * @brief Deactivates the EXT peripheral.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ *
+ * @notapi
+ */
+void ext_lld_stop(EXTDriver *extp) {
+
+ if (extp->state == EXT_ACTIVE)
+ ext_lld_exti_irq_disable();
+}
+
+/**
+ * @brief Enables an EXT channel.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ * @param[in] channel channel to be enabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
+
+ uint32_t irqc;
+ uint32_t mode = extp->config->channels[channel].mode;
+ if (mode & EXT_CH_MODE_RISING_EDGE)
+ irqc = PCR_IRQC_RISING_EDGE;
+ else if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE)
+ irqc = PCR_IRQC_FALLING_EDGE;
+ else if (extp->config->channels[channel].mode & EXT_CH_MODE_BOTH_EDGES)
+ irqc = PCR_IRQC_EITHER_EDGE;
+ else
+ irqc = PCR_IRQC_DISABLED;
+
+ PORT_TypeDef *port = extp->config->channels[channel].port;
+ uint32_t pin = extp->config->channels[channel].pin;
+
+ uint32_t pcr = port->PCR[pin];
+
+ /* Clear all the IRQC bits */
+ pcr &= ~PORTx_PCRn_IRQC_MASK;
+ /* Set the required IRQC bits */
+ pcr |= PORTx_PCRn_IRQC(irqc);
+
+ port->PCR[pin] = pcr;
+}
+
+/**
+ * @brief Disables an EXT channel.
+ *
+ * @param[in] extp pointer to the @p EXTDriver object
+ * @param[in] channel channel to be disabled
+ *
+ * @notapi
+ */
+void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
+
+ PORT_TypeDef *port = extp->config->channels[channel].port;
+ uint32_t pin = extp->config->channels[channel].pin;
+ port->PCR[pin] |= PORTx_PCRn_IRQC(PCR_IRQC_DISABLED);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.h new file mode 100644 index 0000000..bcd9cb0 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_ext_lld.h @@ -0,0 +1,188 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/ext_lld.h
+ * @brief KINETIS EXT subsystem low level driver header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef HAL_EXT_LLD_H_
+#define HAL_EXT_LLD_H_
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of EXT channels required.
+ */
+#define EXT_MAX_CHANNELS KINETIS_EXTI_NUM_CHANNELS
+
+/**
+ * @name KINETIS-specific EXT channel modes
+ * @{
+ */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief PORTA interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTA_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief PORTB interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTB_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTB_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief PORTC interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTC_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief PORTD interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTD_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTD_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief PORTE interrupt priority level setting.
+ */
+#if !defined(KINETIS_EXT_PORTE_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_EXT_PORTE_IRQ_PRIORITY 3
+#endif
+/** @} */
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief EXT channel identifier.
+ */
+typedef uint32_t expchannel_t;
+
+/**
+ * @brief Type of an EXT generic notification callback.
+ *
+ * @param[in] extp pointer to the @p EXPDriver object triggering the
+ * callback
+ */
+typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
+
+/**
+ * @brief Channel configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief Channel mode.
+ */
+ uint32_t mode;
+ /**
+ * @brief Channel callback.
+ */
+ extcallback_t cb;
+
+ /**
+ * @brief Port.
+ */
+ PORT_TypeDef *port;
+
+ /**
+ * @brief Pin.
+ */
+ uint32_t pin;
+} EXTChannelConfig;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Channel configurations.
+ */
+ EXTChannelConfig channels[EXT_MAX_CHANNELS];
+ /* End of the mandatory fields.*/
+} EXTConfig;
+
+/**
+ * @brief Structure representing an EXT driver.
+ */
+struct EXTDriver {
+ /**
+ * @brief Driver state.
+ */
+ extstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const EXTConfig *config;
+ /* End of the mandatory fields.*/
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern EXTDriver EXTD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_init(void);
+ void ext_lld_start(EXTDriver *extp);
+ void ext_lld_stop(EXTDriver *extp);
+ void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
+ void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* HAL_EXT_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c new file mode 100644 index 0000000..6e88f88 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c @@ -0,0 +1,391 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/gpt_lld.c
+ * @brief KINETIS GPT subsystem low level driver source.
+ *
+ * @addtogroup GPT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_GPT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief GPTD1 driver identifier.
+ * @note The driver GPTD1 allocates the complex timer PIT0 when enabled.
+ */
+#if KINETIS_GPT_USE_PIT0 || defined(__DOXYGEN__)
+GPTDriver GPTD1;
+#endif
+
+/**
+ * @brief GPTD2 driver identifier.
+ * @note The driver GPTD2 allocates the timer PIT1 when enabled.
+ */
+#if KINETIS_GPT_USE_PIT1 || defined(__DOXYGEN__)
+GPTDriver GPTD2;
+#endif
+
+/**
+ * @brief GPTD3 driver identifier.
+ * @note The driver GPTD3 allocates the timer PIT2 when enabled.
+ */
+#if KINETIS_GPT_USE_PIT2 || defined(__DOXYGEN__)
+GPTDriver GPTD3;
+#endif
+
+/**
+ * @brief GPTD4 driver identifier.
+ * @note The driver GPTD4 allocates the timer PIT3 when enabled.
+ */
+#if KINETIS_GPT_USE_PIT3 || defined(__DOXYGEN__)
+GPTDriver GPTD4;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#if KINETIS_HAS_PIT_COMMON_IRQ
+static uint8_t active_channels = 0;
+#endif /* KINETIS_HAS_PIT_COMMON_IRQ */
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Shared IRQ handler.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ */
+static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
+
+ /* Clear the interrupt */
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
+
+ if (gptp->state == GPT_ONESHOT) {
+ gptp->state = GPT_READY; /* Back in GPT_READY state. */
+ gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */
+ }
+ gptp->config->callback(gptp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if !KINETIS_HAS_PIT_COMMON_IRQ
+
+#if KINETIS_GPT_USE_PIT0
+/**
+ * @brief PIT1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ gpt_lld_serve_interrupt(&GPTD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_GPT_USE_PIT0 */
+
+#if KINETIS_GPT_USE_PIT1
+/**
+ * @brief PIT1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT1_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ gpt_lld_serve_interrupt(&GPTD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_GPT_USE_PIT1 */
+
+#if KINETIS_GPT_USE_PIT2
+/**
+ * @brief PIT2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT2_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ gpt_lld_serve_interrupt(&GPTD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_GPT_USE_PIT2 */
+
+#if KINETIS_GPT_USE_PIT3
+/**
+ * @brief PIT3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT3_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ gpt_lld_serve_interrupt(&GPTD4);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_GPT_USE_PIT3 */
+
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+/**
+ * @brief Common PIT interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_PIT_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+#if KINETIS_GPT_USE_PIT0
+ if(GPTD1.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD1);
+#endif /* KINETIS_GPT_USE_PIT0 */
+#if KINETIS_GPT_USE_PIT1
+ if(GPTD2.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD2);
+#endif /* KINETIS_GPT_USE_PIT1 */
+#if KINETIS_GPT_USE_PIT2
+ if(GPTD3.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD3);
+#endif /* KINETIS_GPT_USE_PIT2 */
+#if KINETIS_GPT_USE_PIT3
+ if(GPTD4.channel->TFLG & PIT_TFLGn_TIF)
+ gpt_lld_serve_interrupt(&GPTD4);
+#endif /* KINETIS_GPT_USE_PIT3 */
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level GPT driver initialization.
+ *
+ * @notapi
+ */
+void gpt_lld_init(void) {
+
+#if KINETIS_GPT_USE_PIT0
+ /* Driver initialization.*/
+ GPTD1.channel = &PIT->CHANNEL[0];
+ gptObjectInit(&GPTD1);
+#endif
+
+#if KINETIS_GPT_USE_PIT1
+ /* Driver initialization.*/
+ GPTD2.channel = &PIT->CHANNEL[1];
+ gptObjectInit(&GPTD2);
+#endif
+
+#if KINETIS_GPT_USE_PIT2
+ /* Driver initialization.*/
+ GPTD3.channel = &PIT->CHANNEL[2];
+ gptObjectInit(&GPTD3);
+#endif
+
+#if KINETIS_GPT_USE_PIT3
+ /* Driver initialization.*/
+ GPTD4.channel = &PIT->CHANNEL[3];
+ gptObjectInit(&GPTD4);
+#endif
+}
+
+/**
+ * @brief Configures and activates the GPT peripheral.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_start(GPTDriver *gptp) {
+ uint16_t psc;
+
+ if (gptp->state == GPT_STOP) {
+ /* Clock activation.*/
+ SIM->SCGC6 |= SIM_SCGC6_PIT;
+ gptp->clock = KINETIS_SYSCLK_FREQUENCY;
+
+#if !KINETIS_HAS_PIT_COMMON_IRQ
+
+#if KINETIS_GPT_USE_PIT0
+ if (&GPTD1 == gptp) {
+ nvicEnableVector(PITChannel0_IRQn, KINETIS_GPT_PIT0_IRQ_PRIORITY);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT1
+ if (&GPTD2 == gptp) {
+ nvicEnableVector(PITChannel1_IRQn, KINETIS_GPT_PIT1_IRQ_PRIORITY);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT2
+ if (&GPTD3 == gptp) {
+ nvicEnableVector(PITChannel2_IRQn, KINETIS_GPT_PIT2_IRQ_PRIORITY);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT3
+ if (&GPTD4 == gptp) {
+ nvicEnableVector(PITChannel3_IRQn, KINETIS_GPT_PIT3_IRQ_PRIORITY);
+ }
+#endif
+
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+ nvicEnableVector(PIT_IRQn, KINETIS_GPT_PIT_IRQ_PRIORITY);
+ active_channels++;
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
+ }
+
+ /* Prescaler value calculation.*/
+ psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
+ osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
+ "invalid frequency");
+
+ /* Enable the PIT */
+ PIT->MCR = 0;
+}
+
+/**
+ * @brief Deactivates the GPT peripheral.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_stop(GPTDriver *gptp) {
+
+ if (gptp->state == GPT_READY) {
+ SIM->SCGC6 &= ~SIM_SCGC6_PIT;
+
+ /* Disable the channel */
+ gptp->channel->TCTRL = 0;
+
+ /* Clear pending interrupts */
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
+
+#if !KINETIS_HAS_PIT_COMMON_IRQ
+
+#if KINETIS_GPT_USE_PIT0
+ if (&GPTD1 == gptp) {
+ nvicDisableVector(PITChannel0_IRQn);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT1
+ if (&GPTD2 == gptp) {
+ nvicDisableVector(PITChannel1_IRQn);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT2
+ if (&GPTD3 == gptp) {
+ nvicDisableVector(PITChannel2_IRQn);
+ }
+#endif
+#if KINETIS_GPT_USE_PIT3
+ if (&GPTD4 == gptp) {
+ nvicDisableVector(PITChannel3_IRQn);
+ }
+#endif
+
+#else /* !KINETIS_HAS_PIT_COMMON_IRQ */
+ if(--active_channels == 0)
+ nvicDisableVector(PIT_IRQn);
+#endif /* !KINETIS_HAS_PIT_COMMON_IRQ */
+ }
+}
+
+/**
+ * @brief Starts the timer in continuous mode.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ * @param[in] interval period in ticks
+ *
+ * @notapi
+ */
+void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
+
+ /* Clear pending interrupts */
+ gptp->channel->TFLG |= PIT_TFLGn_TIF;
+
+ /* Set the interval */
+ gpt_lld_change_interval(gptp, interval);
+
+ /* Start the timer */
+ gptp->channel->TCTRL |= PIT_TCTRLn_TIE | PIT_TCTRLn_TEN;
+}
+
+/**
+ * @brief Stops the timer.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_stop_timer(GPTDriver *gptp) {
+
+ /* Stop the timer */
+ gptp->channel->TCTRL = 0;
+}
+
+/**
+ * @brief Starts the timer in one shot mode and waits for completion.
+ * @details This function specifically polls the timer waiting for completion
+ * in order to not have extra delays caused by interrupt servicing,
+ * this function is only recommended for short delays.
+ *
+ * @param[in] gptp pointer to the @p GPTDriver object
+ * @param[in] interval time interval in ticks
+ *
+ * @notapi
+ */
+void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
+ struct PIT_CHANNEL *channel = gptp->channel;
+
+ /* Disable timer and disable interrupts */
+ channel->TCTRL = 0;
+
+ /* Clear the interrupt flag */
+ channel->TFLG |= PIT_TFLGn_TIF;
+
+ /* Set the interval */
+ channel->LDVAL = (gptp->clock / gptp->config->frequency) * interval;
+
+ /* Enable Timer but keep interrupts disabled */
+ channel->TCTRL = PIT_TCTRLn_TEN;
+
+ /* Wait for the interrupt flag to be set */
+ while (!(channel->TFLG & PIT_TFLGn_TIF))
+ ;
+
+ /* Disable timer and disable interrupts */
+ channel->TCTRL = 0;
+}
+
+#endif /* HAL_USE_GPT */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.h new file mode 100644 index 0000000..1b9e5ef --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_gpt_lld.h @@ -0,0 +1,333 @@ +/*
+ ChibiOS - Copyright (C) 2014 Derek Mulcahy
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/gpt_lld.h
+ * @brief KINETIS GPT subsystem low level driver header.
+ *
+ * @addtogroup GPT
+ * @{
+ */
+
+#ifndef HAL_GPT_LLD_H_
+#define HAL_GPT_LLD_H_
+
+#if HAL_USE_GPT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief GPTD1 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_GPT_USE_PIT0) || defined(__DOXYGEN__)
+#define KINETIS_GPT_USE_PIT0 FALSE
+#endif
+
+/**
+ * @brief GPTD2 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_GPT_USE_PIT1) || defined(__DOXYGEN__)
+#define KINETIS_GPT_USE_PIT1 FALSE
+#endif
+
+/**
+ * @brief GPTD3 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD3 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_GPT_USE_PIT2) || defined(__DOXYGEN__)
+#define KINETIS_GPT_USE_PIT2 FALSE
+#endif
+
+/**
+ * @brief GPTD4 driver enable switch.
+ * @details If set to @p TRUE the support for GPTD4 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_GPT_USE_PIT3) || defined(__DOXYGEN__)
+#define KINETIS_GPT_USE_PIT3 FALSE
+#endif
+
+/**
+ * @brief GPTD1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_GPT_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT0_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief GPTD2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_GPT_PIT1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT1_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief GPTD3 interrupt priority level setting.
+ */
+#if !defined(KINETIS_GPT_PIT2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT2_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief GPTD4 interrupt priority level setting.
+ */
+#if !defined(KINETIS_GPT_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT3_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief GPTD* common interrupt priority level setting.
+ */
+#if (KINETIS_HAS_PIT_COMMON_IRQ && !defined(KINETIS_GPT_PIT_IRQ_PRIORITY)) \
+ || defined(__DOXYGEN__)
+#define KINETIS_GPT_PIT_IRQ_PRIORITY 2
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_GPT_USE_PIT0 && !KINETIS_HAS_PIT0
+#error "PIT0 not present in the selected device"
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && !KINETIS_HAS_PIT1
+#error "PIT1 not present in the selected device"
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && !KINETIS_HAS_PIT2
+#error "PIT2 not present in the selected device"
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && !KINETIS_HAS_PIT3
+#error "PIT3 not present in the selected device"
+#endif
+
+#if !KINETIS_GPT_USE_PIT0 && !KINETIS_GPT_USE_PIT1 && \
+ !KINETIS_GPT_USE_PIT2 && !KINETIS_GPT_USE_PIT3
+#error "GPT driver activated but no PIT peripheral assigned"
+#endif
+
+#if KINETIS_GPT_USE_PIT0 && !KINETIS_HAS_PIT_COMMON_IRQ && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT0"
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && !KINETIS_HAS_PIT_COMMON_IRQ && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT1"
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && !KINETIS_HAS_PIT_COMMON_IRQ && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT2"
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && !KINETIS_HAS_PIT_COMMON_IRQ && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT3"
+#endif
+
+#if KINETIS_HAS_PIT_COMMON_IRQ && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_GPT_PIT_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to PIT"
+#endif
+
+#if KINETIS_GPT_USE_PIT0 && !defined(KINETIS_PIT0_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT0_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && !defined(KINETIS_PIT1_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT1_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && !defined(KINETIS_PIT2_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT2_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && !defined(KINETIS_PIT3_IRQ_VECTOR) && \
+ !KINETIS_HAS_PIT_COMMON_IRQ
+#error "KINETIS_PIT3_IRQ_VECTOR not defined"
+#endif
+
+#if KINETIS_HAS_PIT_COMMON_IRQ && !defined(KINETIS_PIT_IRQ_VECTOR)
+#error "KINETIS_PIT_IRQ_VECTOR not defined"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief GPT frequency type.
+ */
+typedef uint32_t gptfreq_t;
+
+/**
+ * @brief GPT counter type.
+ */
+typedef uint32_t gptcnt_t;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Timer clock in Hz.
+ * @note The low level can use assertions in order to catch invalid
+ * frequency specifications.
+ */
+ gptfreq_t frequency;
+ /**
+ * @brief Timer callback pointer.
+ * @note This callback is invoked on GPT counter events.
+ * @note This callback can be set to @p NULL but in that case the
+ * one-shot mode cannot be used.
+ */
+ gptcallback_t callback;
+ /* End of the mandatory fields.*/
+} GPTConfig;
+
+/**
+ * @brief Structure representing a GPT driver.
+ */
+struct GPTDriver {
+ /**
+ * @brief Driver state.
+ */
+ gptstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const GPTConfig *config;
+#if defined(GPT_DRIVER_EXT_FIELDS)
+ GPT_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Timer base clock.
+ */
+ uint32_t clock;
+ /**
+ * @brief Channel structure in PIT registers block.
+ */
+ struct PIT_CHANNEL *channel;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Changes the interval of GPT peripheral.
+ * @details This function changes the interval of a running GPT unit.
+ * @pre The GPT unit must be running in continuous mode.
+ * @post The GPT unit interval is changed to the new value.
+ * @note The function has effect at the next cycle start.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @param[in] interval new cycle time in timer ticks
+ *
+ * @notapi
+ */
+#define gpt_lld_change_interval(gptp, interval) \
+ ((gptp)->channel->LDVAL = (uint32_t)( \
+ ( (gptp)->clock / (gptp)->config->frequency ) * \
+ ( interval ) ))
+
+/**
+ * @brief Returns the interval of GPT peripheral.
+ * @pre The GPT unit must be running in continuous mode.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @return The current interval.
+ *
+ * @notapi
+ */
+#define gpt_lld_get_interval(gptp) \
+ ((uint32_t)( ( (uint64_t)(gptp)->channel->LDVAL * (gptp)->config->frequency ) / \
+ ( (uint32_t)(gptp)->clock ) ))
+
+/**
+ * @brief Returns the counter value of GPT peripheral.
+ * @pre The GPT unit must be running in continuous mode.
+ * @note The nature of the counter is not defined, it may count upward
+ * or downward, it could be continuously running or not.
+ *
+ * @param[in] gptp pointer to a @p GPTDriver object
+ * @return The current counter value.
+ *
+ * @notapi
+ */
+#define gpt_lld_get_counter(gptp) ((gptcnt_t)(gptp)->pit->CHANNEL[gptp->channel].CVAL)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_GPT_USE_PIT0 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD1;
+#endif
+
+#if KINETIS_GPT_USE_PIT1 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD2;
+#endif
+
+#if KINETIS_GPT_USE_PIT2 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD3;
+#endif
+
+#if KINETIS_GPT_USE_PIT3 && !defined(__DOXYGEN__)
+extern GPTDriver GPTD4;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void gpt_lld_init(void);
+ void gpt_lld_start(GPTDriver *gptp);
+ void gpt_lld_stop(GPTDriver *gptp);
+ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
+ void gpt_lld_stop_timer(GPTDriver *gptp);
+ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_GPT */
+
+#endif /* HAL_GPT_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c new file mode 100644 index 0000000..c6b3d11 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -0,0 +1,583 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/i2c_lld.c
+ * @brief KINETIS I2C subsystem low level driver source.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief I2C0 driver identifier.
+ */
+#if KINETIS_I2C_USE_I2C0 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/**
+ * @brief I2C1 driver identifier.
+ */
+#if KINETIS_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+void config_frequency(I2CDriver *i2cp) {
+
+ /* Each index in the table corresponds to a a frequency
+ * divider used to generate the SCL clock from the main
+ * system clock.
+ */
+ const uint16_t icr_table[] = {
+ /* 0x00 - 0x0F */
+ 20,22,24,26,28,30,34,40,28,32,36,40,44,48,56,68,
+ /* 0x10 - 0x1F */
+ 48,56,64,72,80,88,104,128,80,96,112,128,144,160,192,240,
+ /* 0x20 - 0x2F */
+ 160,192,224,256,288,320,384,480,320,384,448,512,576,640,768,960,
+ /* 0x30 - 0x3F */
+ 640,768,896,1024,1152,1280,1536,1920,1280,1536,1792,2048,2304,2560,3072,3840,
+ };
+
+ int length = sizeof(icr_table) / sizeof(icr_table[0]);
+ uint16_t divisor;
+ uint8_t i = 0, index = 0;
+ uint16_t best, diff;
+
+ if (i2cp->config != NULL)
+ divisor = KINETIS_BUSCLK_FREQUENCY / i2cp->config->clock;
+ else
+ divisor = KINETIS_BUSCLK_FREQUENCY / 100000;
+
+ best = ~0;
+ index = 0;
+ /* Tries to find the SCL clock which is the closest
+ * approximation to the clock passed in config. To
+ * stay on the safe side, only values that generate
+ * lower frequency are used.
+ */
+ for (i = 0; i < length; i++) {
+ if (icr_table[i] >= divisor) {
+ diff = icr_table[i] - divisor;
+ if (diff < best) {
+ best = diff;
+ index = i;
+ }
+ }
+ }
+
+ i2cp->i2c->F = index;
+}
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] i2cp pointer to an I2CDriver
+ */
+static void serve_interrupt(I2CDriver *i2cp) {
+
+ I2C_TypeDef *i2c = i2cp->i2c;
+ intstate_t state = i2cp->intstate;
+
+ /* check if we're master or slave */
+ if (i2c->C1 & I2Cx_C1_MST) {
+ /* master */
+
+ if (i2c->S & I2Cx_S_ARBL) {
+ /* check if we lost arbitration */
+ i2cp->errors |= I2C_ARBITRATION_LOST;
+ i2c->S |= I2Cx_S_ARBL;
+ /* TODO: may need to do more here, reset bus? */
+ /* Perhaps clear MST? */
+ }
+
+#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
+ else if ((i2cp->rsta_workaround == RSTA_WORKAROUND_ON) && (i2cp->i2c->FLT & I2Cx_FLT_STARTF)) {
+ i2cp->rsta_workaround = RSTA_WORKAROUND_OFF;
+ /* clear+disable STARTF/STOPF interrupts and wake up the thread */
+ i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF;
+ i2cp->i2c->FLT &= ~I2Cx_FLT_SSIE;
+ i2c->S |= I2Cx_S_IICIF;
+ _i2c_wakeup_isr(i2cp);
+ }
+#endif /* KL27Z RST workaround */
+
+ else if (i2c->S & I2Cx_S_TCF) {
+ /* just completed byte transfer */
+ if (i2c->C1 & I2Cx_C1_TX) {
+ /* the byte was transmitted */
+
+ if (state == STATE_SEND) {
+ /* currently sending stuff */
+
+ if (i2c->S & I2Cx_S_RXAK) {
+ /* slave did not ACK */
+ i2cp->errors |= I2C_ACK_FAILURE;
+ /* the thread will be woken up at the end of ISR and release the bus */
+
+ } else if (i2cp->txbuf != NULL && i2cp->txidx < i2cp->txbytes) {
+ /* slave ACK'd and we want to send more */
+ i2c->D = i2cp->txbuf[i2cp->txidx++];
+ } else {
+ /* slave ACK'd and we are done sending */
+ i2cp->intstate = STATE_STOP;
+ /* this wakes up the waiting thread at the end of ISR */
+ }
+
+ } else if (state == STATE_RECV) {
+ /* should be receiving stuff, so we've just sent the address */
+
+ if (i2c->S & I2Cx_S_RXAK) {
+ /* slave did not ACK */
+ i2cp->errors |= I2C_ACK_FAILURE;
+ /* the thread will be woken up and release the bus */
+
+ } else {
+ /* slave ACK'd, we should be receiving next */
+ i2c->C1 &= ~I2Cx_C1_TX;
+
+ if (i2cp->rxbytes > 1) {
+ /* multi-byte read, send ACK after next transfer */
+ i2c->C1 &= ~I2Cx_C1_TXAK;
+ } else {
+ /* only 1 byte remaining, send NAK */
+ i2c->C1 |= I2Cx_C1_TXAK;
+ }
+
+ (void) i2c->D; /* dummy read; triggers next receive */
+ }
+
+ } /* possibly check other states here - should not happen! */
+
+ } else {
+ /* the byte was received */
+
+ if (state == STATE_RECV) {
+ /* currently receiving stuff */
+ /* the received byte is now in D */
+
+ if (i2cp->rxbytes > 1) {
+ /* expecting at least one byte after this one */
+ if (i2cp->rxidx == (i2cp->rxbytes - 2)) {
+ /* expecting exactly one byte after this one, NAK that one */
+ i2c->C1 |= I2Cx_C1_TXAK;
+ } else {
+ /* expecting more than one after this one, respond with ACK */
+ i2c->C1 &= ~I2Cx_C1_TXAK;
+ }
+ }
+
+ if (i2cp->rxidx == i2cp->rxbytes - 1) {
+ /* D is the last byte we're expecting */
+ /* release bus: switch to RX mode, send STOP */
+ /* need to do it now otherwise the I2C module will wait for another byte */
+ // delayMicroseconds(1);
+ i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
+ i2cp->intstate = STATE_STOP;
+ /* this wakes up the waiting thread at the end of ISR */
+ }
+
+ /* get the data from D; this triggers the next receive */
+ i2cp->rxbuf[i2cp->rxidx++] = i2c->D;
+
+ // if (i2cp->rxidx == i2cp->rxbytes) {
+ /* done receiving */
+ // }
+ } /* possibly check other states here - should not happen! */
+ }
+
+ } /* possibly check other interrupt flags here */
+ } else {
+ /* slave */
+
+ /* Not implemented yet */
+ }
+
+ /* Reset other interrupt sources */
+#if defined(I2Cx_FLT_STOPF) /* extra flags on KL26Z and KL27Z */
+ i2cp->i2c->FLT |= I2Cx_FLT_STOPF;
+#endif
+#if defined(I2Cx_FLT_STARTF) /* extra flags on KL27Z */
+ i2cp->i2c->FLT |= I2Cx_FLT_STARTF;
+#endif
+ /* Reset interrupt flag */
+ i2c->S |= I2Cx_S_IICIF;
+
+ if (i2cp->errors != I2C_NO_ERROR)
+ _i2c_wakeup_error_isr(i2cp);
+
+ if (i2cp->intstate == STATE_STOP)
+ _i2c_wakeup_isr(i2cp);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_I2C_USE_I2C0 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_I2C0_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&I2CD1);
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+#if KINETIS_I2C_USE_I2C1 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_I2C1_IRQ_VECTOR) {
+
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&I2CD2);
+ OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2C driver initialization.
+ *
+ * @notapi
+ */
+void i2c_lld_init(void) {
+
+#if KINETIS_I2C_USE_I2C0
+ i2cObjectInit(&I2CD1);
+ I2CD1.thread = NULL;
+ I2CD1.i2c = I2C0;
+#endif
+
+#if KINETIS_I2C_USE_I2C1
+ i2cObjectInit(&I2CD2);
+ I2CD2.thread = NULL;
+ I2CD2.i2c = I2C1;
+#endif
+
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+
+ if (i2cp->state == I2C_STOP) {
+
+ /* TODO:
+ * The PORT must be enabled somewhere. The PIN multiplexer
+ * will map the I2C functionality to some PORT which must
+ * than be enabled. The easier way is enabling all PORTs at
+ * startup, which is currently being done in __early_init.
+ */
+
+#if KINETIS_I2C_USE_I2C0
+ if (&I2CD1 == i2cp) {
+ SIM->SCGC4 |= SIM_SCGC4_I2C0;
+ nvicEnableVector(I2C0_IRQn, KINETIS_I2C_I2C0_PRIORITY);
+ }
+#endif
+
+#if KINETIS_I2C_USE_I2C1
+ if (&I2CD2 == i2cp) {
+ SIM->SCGC4 |= SIM_SCGC4_I2C1;
+ nvicEnableVector(I2C1_IRQn, KINETIS_I2C_I2C1_PRIORITY);
+ }
+#endif
+
+ }
+
+ config_frequency(i2cp);
+ i2cp->i2c->C1 = I2Cx_C1_IICEN | I2Cx_C1_IICIE; // reset I2C, enable interrupts
+ i2cp->i2c->S = I2Cx_S_IICIF | I2Cx_S_ARBL; // clear status flags just in case
+ i2cp->intstate = STATE_STOP; // internal state
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+
+ if (i2cp->state != I2C_STOP) {
+
+ i2cp->i2c->C1 &= ~(I2Cx_C1_IICEN | I2Cx_C1_IICIE);
+
+#if KINETIS_I2C_USE_I2C0
+ if (&I2CD1 == i2cp) {
+ SIM->SCGC4 &= ~SIM_SCGC4_I2C0;
+ nvicDisableVector(I2C0_IRQn);
+ }
+#endif
+
+#if KINETIS_I2C_USE_I2C1
+ if (&I2CD2 == i2cp) {
+ SIM->SCGC4 &= ~SIM_SCGC4_I2C1;
+ nvicDisableVector(I2C1_IRQn);
+ }
+#endif
+
+ }
+}
+
+static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ msg_t msg;
+ systime_t start, end;
+
+ uint8_t op = (i2cp->intstate == STATE_SEND) ? 0 : 1;
+
+ i2cp->errors = I2C_NO_ERROR;
+ i2cp->addr = addr;
+
+ i2cp->txbuf = txbuf;
+ i2cp->txbytes = txbytes;
+ i2cp->txidx = 0;
+
+ i2cp->rxbuf = rxbuf;
+ i2cp->rxbytes = rxbytes;
+ i2cp->rxidx = 0;
+
+#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
+ i2cp->rsta_workaround = RSTA_WORKAROUND_OFF;
+#endif /* KL27Z RST workaround */
+
+ /* clear status flags */
+#if defined(I2Cx_FLT_STOPF) /* extra flags on KL26Z and KL27Z */
+ i2cp->i2c->FLT |= I2Cx_FLT_STOPF;
+#endif
+#if defined(I2Cx_FLT_STARTF) /* extra flags on KL27Z */
+ i2cp->i2c->FLT |= I2Cx_FLT_STARTF;
+#endif
+ i2cp->i2c->S = I2Cx_S_IICIF|I2Cx_S_ARBL;
+
+ /* acquire the bus */
+ /* check to see if we already have the bus */
+ if(i2cp->i2c->C1 & I2Cx_C1_MST) {
+
+#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
+ /* need to wait for STARTF interrupt after issuing repeated start,
+ * otherwise the double buffering mechanism sends the last sent byte
+ * instead of the slave address.
+ * https://community.freescale.com/thread/377611
+ */
+ i2cp->rsta_workaround = RSTA_WORKAROUND_ON;
+ /* clear any interrupt bits and enable STARTF/STOPF interrupts */
+ i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF;
+ i2cp->i2c->S |= I2Cx_S_IICIF|I2Cx_S_ARBL;
+ i2cp->i2c->FLT |= I2Cx_FLT_SSIE;
+#endif /* KL27Z RST workaround */
+
+ /* send repeated start */
+ i2cp->i2c->C1 |= I2Cx_C1_RSTA | I2Cx_C1_TX;
+
+#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
+ /* wait for the STARTF interrupt */
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+ /* abort if this didn't go well (timed out) */
+ if (msg != MSG_OK) {
+ /* release bus - RX mode, send STOP */
+ i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
+ return msg;
+ }
+#endif /* KL27Z RST workaround */
+
+ } else {
+ /* unlock during the wait, so that tasks with
+ * higher priority can get attention */
+ osalSysUnlock();
+
+ /* wait until the bus is released */
+ /* Calculating the time window for the timeout on the busy bus condition.*/
+ start = osalOsGetSystemTimeX();
+ end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
+
+ while(true) {
+ osalSysLock();
+ /* If the bus is not busy then the operation can continue, note, the
+ loop is exited in the locked state.*/
+ if(!(i2cp->i2c->S & I2Cx_S_BUSY))
+ break;
+ /* If the system time went outside the allowed window then a timeout
+ condition is returned.*/
+ if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) {
+ return MSG_TIMEOUT;
+ }
+ osalSysUnlock();
+ }
+
+ /* send START */
+ i2cp->i2c->C1 |= I2Cx_C1_MST|I2Cx_C1_TX;
+ }
+
+ /* send slave address */
+ i2cp->i2c->D = addr << 1 | op;
+
+ /* wait for the ISR to signal that the transmission (or receive if no transmission) phase is complete */
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+
+ /* FIXME */
+ //if (i2cp->i2c->S & I2Cx_S_RXAK)
+ // i2cp->errors |= I2C_ACK_FAILURE;
+
+ /* the transmitting (or receiving if no transmission) phase has finished,
+ * do we expect to receive something? */
+ if (msg == MSG_OK && rxbuf != NULL && rxbytes > 0 && i2cp->rxidx < rxbytes) {
+
+#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
+ /* the same KL27Z RST workaround as above */
+ i2cp->rsta_workaround = RSTA_WORKAROUND_ON;
+ /* clear any interrupt bits and enable STARTF/STOPF interrupts */
+ i2cp->i2c->FLT |= I2Cx_FLT_STOPF|I2Cx_FLT_STARTF;
+ i2cp->i2c->S |= I2Cx_S_IICIF|I2Cx_S_ARBL;
+ i2cp->i2c->FLT |= I2Cx_FLT_SSIE;
+#endif /* KL27Z RST workaround */
+
+ /* send repeated start */
+ i2cp->i2c->C1 |= I2Cx_C1_RSTA;
+
+#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
+ /* wait for the STARTF interrupt */
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+ /* abort if this didn't go well (timed out) */
+ if (msg != MSG_OK) {
+ /* release bus - RX mode, send STOP */
+ i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
+ return msg;
+ }
+#endif /* KL27Z RST workaround */
+
+ /* FIXME */
+ // while (!(i2cp->i2c->S & I2Cx_S_BUSY));
+
+ i2cp->intstate = STATE_RECV;
+ i2cp->i2c->D = i2cp->addr << 1 | 1;
+
+ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout);
+ }
+
+ /* release bus - RX mode, send STOP */
+ // other kinetis I2C drivers wait here for 1us. is this needed?
+ i2cp->i2c->C1 &= ~(I2Cx_C1_TX | I2Cx_C1_MST);
+ /* FIXME */
+ // while (i2cp->i2c->S & I2Cx_S_BUSY);
+
+ return msg;
+}
+
+/**
+ * @brief Receives data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ i2cp->intstate = STATE_RECV;
+ return _i2c_txrx_timeout(i2cp, addr, NULL, 0, rxbuf, rxbytes, timeout);
+}
+
+/**
+ * @brief Transmits data via the I2C bus as master.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ * @param[in] addr slave device address
+ * @param[in] txbuf pointer to the transmit buffer
+ * @param[in] txbytes number of bytes to be transmitted
+ * @param[out] rxbuf pointer to the receive buffer
+ * @param[in] rxbytes number of bytes to be received
+ * @param[in] timeout the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The operation status.
+ * @retval MSG_OK if the function succeeded.
+ * @retval MSG_RESET if one or more I2C errors occurred, the errors can
+ * be retrieved using @p i2cGetErrors().
+ * @retval MSG_TIMEOUT if a timeout occurred before operation end. <b>After a
+ * timeout the driver must be stopped and restarted
+ * because the bus is in an uncertain state</b>.
+ *
+ * @notapi
+ */
+msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout) {
+
+ i2cp->intstate = STATE_SEND;
+ return _i2c_txrx_timeout(i2cp, addr, txbuf, txbytes, rxbuf, rxbytes, timeout);
+}
+
+#endif /* HAL_USE_I2C */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h new file mode 100644 index 0000000..bfc5008 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_i2c_lld.h @@ -0,0 +1,247 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/i2c_lld.h
+ * @brief KINETIS I2C subsystem low level driver header.
+ *
+ * @addtogroup I2C
+ * @{
+ */
+
+#ifndef HAL_I2C_LLD_H_
+#define HAL_I2C_LLD_H_
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define STATE_STOP 0x00
+#define STATE_SEND 0x01
+#define STATE_RECV 0x02
+
+#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
+#define RSTA_WORKAROUND_OFF 0x00
+#define RSTA_WORKAROUND_ON 0x01
+#endif /* KL27Z RST workaround */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief I2C0 driver enable switch.
+ * @details If set to @p TRUE the support for I2C0 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_I2C_USE_I2C0) || defined(__DOXYGEN__)
+#define KINETIS_I2C_USE_I2C0 FALSE
+#endif
+
+/**
+ * @brief I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note The default is @p FALSE.
+ */
+#if !defined(KINETIS_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define KINETIS_I2C_USE_I2C1 FALSE
+#endif
+/** @} */
+
+/**
+ * @brief I2C0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_I2C_I2C0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_I2C_I2C0_PRIORITY 12
+#endif
+
+/**
+ * @brief I2C1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_I2C_I2C1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_I2C_I2C1_PRIORITY 12
+#endif
+
+/**
+ * @brief Timeout for external clearing BUSY bus (in ms).
+ */
+#if !defined(KINETIS_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
+#define KINETIS_I2C_BUSY_TIMEOUT 50
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/** @brief error checks */
+#if KINETIS_I2C_USE_I2C0 && !KINETIS_HAS_I2C0
+#error "I2C0 not present in the selected device"
+#endif
+
+#if KINETIS_I2C_USE_I2C1 && !KINETIS_HAS_I2C1
+#error "I2C1 not present in the selected device"
+#endif
+
+
+#if !(KINETIS_I2C_USE_I2C0 || KINETIS_I2C_USE_I2C1)
+#error "I2C driver activated but no I2C peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/* @brief Type representing I2C address. */
+typedef uint8_t i2caddr_t;
+
+/* @brief Type of I2C Driver condition flags. */
+typedef uint32_t i2cflags_t;
+
+/* @brief Type used to control the ISR state machine. */
+typedef uint8_t intstate_t;
+
+/**
+ * @brief Driver configuration structure.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+
+ /* @brief Clock to be used for the I2C bus. */
+ uint32_t clock;
+
+} I2CConfig;
+
+/**
+ * @brief Type of a structure representing an I2C driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2cstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2CConfig *config;
+ /**
+ * @brief Error flags.
+ */
+ i2cflags_t errors;
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the bus.
+ */
+ mutex_t mutex;
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+#if defined(I2C_DRIVER_EXT_FIELDS)
+ I2C_DRIVER_EXT_FIELDS
+#endif
+ /* @brief Thread waiting for I/O completion. */
+ thread_reference_t thread;
+ /* @brief Current slave address without R/W bit. */
+ i2caddr_t addr;
+
+ /* End of the mandatory fields.*/
+
+ /* @brief Pointer to the buffer with data to send. */
+ const uint8_t *txbuf;
+ /* @brief Number of bytes of data to send. */
+ size_t txbytes;
+ /* @brief Current index in buffer when sending data. */
+ size_t txidx;
+ /* @brief Pointer to the buffer to put received data. */
+ uint8_t *rxbuf;
+ /* @brief Number of bytes of data to receive. */
+ size_t rxbytes;
+ /* @brief Current index in buffer when receiving data. */
+ size_t rxidx;
+ /* @brief Tracks current ISR state. */
+ intstate_t intstate;
+ /* @brief Low-level register access. */
+ I2C_TypeDef *i2c;
+#if defined(KL27Zxxx) || defined(KL27Zxx) /* KL27Z RST workaround */
+ /* @brief Auxiliary variable for KL27Z repeated start workaround. */
+ intstate_t rsta_workaround;
+#endif /* KL27Z RST workaround */
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Get errors from I2C driver.
+ *
+ * @param[in] i2cp pointer to the @p I2CDriver object
+ *
+ * @notapi
+ */
+#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+
+#if KINETIS_I2C_USE_I2C0
+extern I2CDriver I2CD1;
+#endif
+
+#if KINETIS_I2C_USE_I2C1
+extern I2CDriver I2CD2;
+#endif
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2c_lld_init(void);
+ void i2c_lld_start(I2CDriver *i2cp);
+ void i2c_lld_stop(I2CDriver *i2cp);
+ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ const uint8_t *txbuf, size_t txbytes,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout);
+ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
+ uint8_t *rxbuf, size_t rxbytes,
+ systime_t timeout);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2C */
+
+#endif /* HAL_I2C_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.c new file mode 100644 index 0000000..51f8a2e --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.c @@ -0,0 +1,245 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/pal_lld.c
+ * @brief PAL subsystem low level driver.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+uint8_t _pal_lld_readpad(ioportid_t port,
+ uint8_t pad) {
+
+ return (port->PDIR & ((uint32_t) 1 << pad)) ? PAL_HIGH : PAL_LOW;
+}
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+void _pal_lld_writepad(ioportid_t port,
+ uint8_t pad,
+ uint8_t bit) {
+
+ if (bit == PAL_HIGH)
+ port->PDOR |= ((uint32_t) 1 << pad);
+ else
+ port->PDOR &= ~((uint32_t) 1 << pad);
+}
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+void _pal_lld_setpadmode(ioportid_t port,
+ uint8_t pad,
+ iomode_t mode) {
+
+ PORT_TypeDef *portcfg = NULL;
+
+ osalDbgAssert(pad < PADS_PER_PORT, "pal_lld_setpadmode() #1, invalid pad");
+
+ if (mode == PAL_MODE_OUTPUT_PUSHPULL)
+ port->PDDR |= ((uint32_t) 1 << pad);
+ else
+ port->PDDR &= ~((uint32_t) 1 << pad);
+
+ if (port == IOPORT1)
+ portcfg = PORTA;
+ else if (port == IOPORT2)
+ portcfg = PORTB;
+ else if (port == IOPORT3)
+ portcfg = PORTC;
+ else if (port == IOPORT4)
+ portcfg = PORTD;
+ else if (port == IOPORT5)
+ portcfg = PORTE;
+
+ osalDbgAssert(portcfg != NULL, "pal_lld_setpadmode() #2, invalid port");
+
+ switch (mode) {
+ case PAL_MODE_RESET:
+ case PAL_MODE_INPUT:
+ case PAL_MODE_OUTPUT_PUSHPULL:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);
+ break;
+#if KINETIS_GPIO_HAS_OPENDRAIN
+ case PAL_MODE_OUTPUT_OPENDRAIN:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
+ PORTx_PCRn_ODE;
+ break;
+#else
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+#endif
+ case PAL_MODE_INPUT_PULLUP:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
+ PORTx_PCRn_PE |
+ PORTx_PCRn_PS;
+ break;
+ case PAL_MODE_INPUT_PULLDOWN:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1) |
+ PORTx_PCRn_PE;
+ break;
+ case PAL_MODE_UNCONNECTED:
+ case PAL_MODE_INPUT_ANALOG:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(0);
+ break;
+ case PAL_MODE_ALTERNATIVE_1:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(1);
+ break;
+ case PAL_MODE_ALTERNATIVE_2:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(2);
+ break;
+ case PAL_MODE_ALTERNATIVE_3:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(3);
+ break;
+ case PAL_MODE_ALTERNATIVE_4:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(4);
+ break;
+ case PAL_MODE_ALTERNATIVE_5:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(5);
+ break;
+ case PAL_MODE_ALTERNATIVE_6:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(6);
+ break;
+ case PAL_MODE_ALTERNATIVE_7:
+ portcfg->PCR[pad] = PIN_MUX_ALTERNATIVE(7);
+ break;
+ }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Kinetis I/O ports configuration.
+ * @details Ports A-E clocks enabled.
+ *
+ * @param[in] config the Kinetis ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+
+ int i, j;
+
+ /* Enable clocking on all Ports */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA |
+ SIM_SCGC5_PORTB |
+ SIM_SCGC5_PORTC |
+ SIM_SCGC5_PORTD |
+ SIM_SCGC5_PORTE;
+
+ /* Initial PORT and GPIO setup */
+ for (i = 0; i < TOTAL_PORTS; i++) {
+ for (j = 0; j < PADS_PER_PORT; j++) {
+ pal_lld_setpadmode(config->ports[i].port,
+ j,
+ config->ports[i].pads[j]);
+ }
+ }
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode) {
+
+ int i;
+
+ (void)mask;
+
+ for (i = 0; i < PADS_PER_PORT; i++) {
+ pal_lld_setpadmode(port, i, mode);
+ }
+}
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.h new file mode 100644 index 0000000..833d95e --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_pal_lld.h @@ -0,0 +1,423 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/pal_lld.h
+ * @brief PAL subsystem low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef HAL_PAL_LLD_H_
+#define HAL_PAL_LLD_H_
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+#define PAL_MODE_ALTERNATIVE_1 0x10
+#define PAL_MODE_ALTERNATIVE_2 0x11
+#define PAL_MODE_ALTERNATIVE_3 0x12
+#define PAL_MODE_ALTERNATIVE_4 0x13
+#define PAL_MODE_ALTERNATIVE_5 0x14
+#define PAL_MODE_ALTERNATIVE_6 0x15
+#define PAL_MODE_ALTERNATIVE_7 0x16
+
+#define PIN_MUX_ALTERNATIVE(x) PORTx_PCRn_MUX(x)
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+#define TOTAL_PORTS 5
+#define PADS_PER_PORT 32
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 32
+
+/**
+ * @brief Whole port mask.
+ * @brief This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief Digital I/O modes.
+ */
+typedef uint32_t iomode_t;
+
+/**
+ * @brief Type of an I/O line.
+ */
+typedef uint32_t ioline_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef GPIO_TypeDef *ioportid_t;
+
+/**
+ * @brief Port Configuration.
+ * @details This structure stores the configuration parameters of all pads
+ * belonging to a port.
+ */
+typedef struct {
+ ioportid_t port;
+ iomode_t pads[PADS_PER_PORT];
+} PortConfig;
+
+/**
+ * @brief Generic I/O ports static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialized the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ PortConfig ports[TOTAL_PORTS];
+} PALConfig;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @brief GPIO port A identifier.
+ */
+#define IOPORT1 GPIOA
+
+/**
+ * @brief GPIO port B identifier.
+ */
+#define IOPORT2 GPIOB
+
+/**
+ * @brief GPIO port C identifier.
+ */
+#define IOPORT3 GPIOC
+
+/**
+ * @brief GPIO port D identifier.
+ */
+#define IOPORT4 GPIOD
+
+/**
+ * @brief GPIO port E identifier.
+ */
+#define IOPORT5 GPIOE
+
+/**
+ * @name Line handling macros
+ * @{
+ */
+/**
+ * @brief Forms a line identifier.
+ * @details A port/pad pair are encoded into an @p ioline_t type. The encoding
+ * of this type is platform-dependent.
+ * @note In this driver the pad number is encoded in the byte of the GPIO
+ * address that's zero on all Kinetis devices.
+ */
+#define PAL_LINE(port, pad) \
+ ((ioline_t)((uint32_t)(port) | ((uint32_t)(pad)<<20)))
+
+/**
+ * @brief Decodes a port identifier from a line identifier.
+ */
+#define PAL_PORT(line) \
+ ((GPIO_TypeDef *)(((uint32_t)(line)) & 0xF00FFFFFU))
+
+/**
+ * @brief Decodes a pad identifier from a line identifier.
+ */
+#define PAL_PAD(line) \
+ ((uint32_t)((uint32_t)(line) & 0x0FF00000U)>>20)
+
+/**
+ * @brief Value identifying an invalid line.
+ */
+#define PAL_NOLINE 0U
+/** @} */
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ *
+ * @param[in] config architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief Reads the physical I/O port states.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) \
+ (port)->PDIR
+
+/**
+ * @brief Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ * value.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) \
+ (port)->PDOR
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) \
+ (port)->PDOR = (bits)
+
+/**
+ * @brief Sets a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be ORed on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_setport(port, bits) \
+ (port)->PSOR = (bits)
+
+/**
+ * @brief Clears a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be cleared on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_clearport(port, bits) \
+ (port)->PCOR = (bits)
+
+/**
+ * @brief Toggles a bits mask on a I/O port.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be toggled on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_toggleport(port, bits) \
+ (port)->PTOR = (bits)
+
+/**
+ * @brief Reads a group of bits.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset) 0
+
+/**
+ * @brief Writes a group of bits.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] mode group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode) \
+ _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+#define pal_lld_readpad(port, pad) _pal_lld_readpad(port, pad)
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit) _pal_lld_writepad(port, pad, bit)
+
+/**
+ * @brief Sets a pad logical state to @p PAL_HIGH.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad) (port)->PSOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Clears a pad logical state to @p PAL_LOW.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) (port)->PCOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Toggles a pad logical state.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_togglepad(port, pad) (port)->PTOR = ((uint32_t) 1 << (pad))
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+#define pal_lld_setpadmode(port, pad, mode) \
+ _pal_lld_setpadmode(port, pad, mode)
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode);
+ void _pal_lld_setpadmode(ioportid_t port,
+ uint8_t pad,
+ iomode_t mode);
+ uint8_t _pal_lld_readpad(ioportid_t port,
+ uint8_t pad);
+ void _pal_lld_writepad(ioportid_t port,
+ uint8_t pad,
+ uint8_t bit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* HAL_PAL_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.c new file mode 100644 index 0000000..c80cf22 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.c @@ -0,0 +1,583 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/serial_lld.c
+ * @brief Kinetis KL2x Serial Driver subsystem low level driver source.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "osal.h"
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SD1 driver identifier.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ 38400
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+/**
+ * @brief Error handling routine.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] isr UART s1 register value
+ */
+static void set_error(SerialDriver *sdp, uint8_t s1) {
+ eventflags_t sts = 0;
+
+ if (s1 & UARTx_S1_OR)
+ sts |= SD_OVERRUN_ERROR;
+ if (s1 & UARTx_S1_PF)
+ sts |= SD_PARITY_ERROR;
+ if (s1 & UARTx_S1_FE)
+ sts |= SD_FRAMING_ERROR;
+ if (s1 & UARTx_S1_NF)
+ sts |= SD_NOISE_ERROR;
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, sts);
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Common error IRQ handler.
+ *
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_error_interrupt(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ /* S1 bits are write-1-to-clear for UART0 on KL2x. */
+ /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and
+ * then reading D.*/
+
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+ if(sdp == &SD1) {
+ if(s1 & UARTx_S1_IDLE) {
+ *(u->s1_p) |= UARTx_S1_IDLE;
+ }
+
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
+ }
+ return;
+ }
+#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
+
+ if(s1 & UARTx_S1_IDLE) {
+ (void)*(u->d_p);
+ }
+
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ (void)*(u->d_p);
+ }
+}
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ if (s1 & UARTx_S1_RDRF) {
+ osalSysLockFromISR();
+ if (iqIsEmptyI(&sdp->iqueue))
+ chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE);
+ if (iqPutI(&sdp->iqueue, *(u->d_p)) < Q_OK)
+ chnAddFlagsI(sdp, SD_OVERRUN_ERROR);
+ osalSysUnlockFromISR();
+ }
+
+ if (s1 & UARTx_S1_TDRE) {
+ msg_t b;
+
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ osalSysUnlockFromISR();
+
+ if (b < Q_OK) {
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ osalSysUnlockFromISR();
+ *(u->c2_p) &= ~UARTx_C2_TIE;
+ } else {
+ *(u->d_p) = b;
+ }
+ }
+
+ serve_error_interrupt(sdp);
+}
+
+/**
+ * @brief Attempts a TX preload
+ */
+static void preload(SerialDriver *sdp) {
+ UART_w_TypeDef *u = &(sdp->uart);
+
+ if (*(u->s1_p) & UARTx_S1_TDRE) {
+ msg_t b = oqGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ return;
+ }
+ *(u->d_p) = b;
+ *(u->c2_p) |= UARTx_C2_TIE;
+ }
+}
+
+/**
+ * @brief Driver output notification.
+ */
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD1);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD2);
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp)
+{
+ (void)qp;
+ preload(&SD3);
+}
+#endif
+
+/**
+ * @brief Common UART configuration.
+ *
+ */
+static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
+
+ UART_w_TypeDef *uart = &(sdp->uart);
+ uint32_t divisor;
+
+ /* Discard any incoming data. */
+ while (*(uart->s1_p) & UARTx_S1_RDRF) {
+ (void)*(uart->d_p);
+ }
+
+ /* Disable UART while configuring */
+ *(uart->c2_p) &= ~(UARTx_C2_RE | UARTx_C2_TE);
+
+ /* The clock sources for various UARTs can be different. */
+ divisor=KINETIS_BUSCLK_FREQUENCY;
+
+#if defined(KL2x)
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ /* UART0 can be clocked from several sources on KL2x. */
+ divisor = KINETIS_UART0_CLOCK_FREQ;
+ /* FIXME: change fixed OSR = 16 to dynamic value based on baud */
+ /* Note: OSR only works on KL2x/UART0; further UARTs have fixed 16. */
+ *(uart->c4_p) = UARTx_C4_OSR(16 - 1);
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#elif defined(K20x) /* KL2x */
+
+ /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */
+#if KINETIS_SERIAL_USE_UART0
+ if(sdp == &SD1)
+ divisor = KINETIS_SYSCLK_FREQUENCY;
+#endif /* KINETIS_SERIAL_USE_UART0 */
+#if KINETIS_SERIAL_USE_UART1
+ if(sdp == &SD2)
+ divisor = KINETIS_SYSCLK_FREQUENCY;
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#else /* K20x */
+#error Baud rate selection not implemented for this MCU type
+#endif /* K20x */
+
+ divisor = (divisor * 2 + 1) / config->sc_speed;
+
+ *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);
+ *(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);
+#if defined(K20x)
+ *(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);
+#endif /* K20x */
+
+ /* Line settings. */
+ *(uart->c1_p) = 0;
+ /* Enable error event interrupts (overrun, noise, framing, parity) */
+ *(uart->c3_p) = UARTx_C3_ORIE | UARTx_C3_NEIE | UARTx_C3_FEIE | UARTx_C3_PEIE;
+ /* Enable the peripheral; including receive interrupts. */
+ *(uart->c2_p) |= UARTx_C2_RE | UARTx_C2_RIE | UARTx_C2_TE;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL0_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL1_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+
+#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD1);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL1_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD2);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD3);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if KINETIS_SERIAL_USE_UART0
+ /* Driver initialization.*/
+ sdObjectInit(&SD1, NULL, notify1);
+#if ! KINETIS_SERIAL0_IS_LPUART
+ SD1.uart.bdh_p = &(UART0->BDH);
+ SD1.uart.bdl_p = &(UART0->BDL);
+ SD1.uart.c1_p = &(UART0->C1);
+ SD1.uart.c2_p = &(UART0->C2);
+ SD1.uart.c3_p = &(UART0->C3);
+ SD1.uart.c4_p = &(UART0->C4);
+ SD1.uart.s1_p = (volatile uint8_t *)&(UART0->S1);
+ SD1.uart.s2_p = &(UART0->S2);
+ SD1.uart.d_p = &(UART0->D);
+#else /* ! KINETIS_SERIAL0_IS_LPUART */
+ /* little endian! */
+ SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */
+ SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */
+ SD1.uart.c1_p = ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */
+ SD1.uart.c2_p = ((uint8_t *)&(LPUART0->CTRL)) + 2; /* C2: CTRL, byte 2 */
+ SD1.uart.c3_p = ((uint8_t *)&(LPUART0->CTRL)) + 3; /* C3: CTRL, byte 1 */
+ SD1.uart.c4_p = ((uint8_t *)&(LPUART0->BAUD)) + 3; /* C4: BAUD, byte 1 */
+ SD1.uart.s1_p = ((uint8_t *)&(LPUART0->STAT)) + 2; /* S1: STAT, byte 2 */
+ SD1.uart.s2_p = ((uint8_t *)&(LPUART0->STAT)) + 3; /* S2: STAT, byte 1 */
+ SD1.uart.d_p = ((uint8_t *)&(LPUART0->DATA)) + 0; /* D: DATA, byte 4 */
+#endif /* ! KINETIS_SERIAL0_IS_LPUART */
+#if KINETIS_SERIAL0_IS_UARTLP
+ SD1.uart.uartlp_p = UART0;
+ SD1.uart.uart_p = NULL;
+#elif KINETIS_SERIAL0_IS_LPUART
+ SD1.uart.lpuart_p = LPUART0;
+ SD1.uart.uart_p = NULL;
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SD1.uart.uart_p = UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ /* Driver initialization.*/
+ sdObjectInit(&SD2, NULL, notify2);
+#if ! KINETIS_SERIAL1_IS_LPUART
+ SD2.uart.bdh_p = &(UART1->BDH);
+ SD2.uart.bdl_p = &(UART1->BDL);
+ SD2.uart.c1_p = &(UART1->C1);
+ SD2.uart.c2_p = &(UART1->C2);
+ SD2.uart.c3_p = &(UART1->C3);
+ SD2.uart.c4_p = &(UART1->C4);
+ SD2.uart.s1_p = (volatile uint8_t *)&(UART1->S1);
+ SD2.uart.s2_p = &(UART1->S2);
+ SD2.uart.d_p = &(UART1->D);
+ SD2.uart.uart_p = UART1;
+#else /* ! KINETIS_SERIAL1_IS_LPUART */
+ /* little endian! */
+ SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */
+ SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */
+ SD2.uart.c1_p = ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */
+ SD2.uart.c2_p = ((uint8_t *)&(LPUART1->CTRL)) + 2; /* C2: CTRL, byte 2 */
+ SD2.uart.c3_p = ((uint8_t *)&(LPUART1->CTRL)) + 3; /* C3: CTRL, byte 1 */
+ SD2.uart.c4_p = ((uint8_t *)&(LPUART1->BAUD)) + 3; /* C4: BAUD, byte 1 */
+ SD2.uart.s1_p = ((uint8_t *)&(LPUART1->STAT)) + 2; /* S1: STAT, byte 2 */
+ SD2.uart.s2_p = ((uint8_t *)&(LPUART1->STAT)) + 3; /* S2: STAT, byte 1 */
+ SD2.uart.d_p = ((uint8_t *)&(LPUART1->DATA)) + 0; /* D: DATA, byte 4 */
+ SD2.uart.lpuart_p = LPUART1;
+ SD2.uart.uart_p = NULL;
+#endif /* ! KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ /* Driver initialization.*/
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.uart.bdh_p = &(UART2->BDH);
+ SD3.uart.bdl_p = &(UART2->BDL);
+ SD3.uart.c1_p = &(UART2->C1);
+ SD3.uart.c2_p = &(UART2->C2);
+ SD3.uart.c3_p = &(UART2->C3);
+ SD3.uart.c4_p = &(UART2->C4);
+ SD3.uart.s1_p = (volatile uint8_t *)&(UART2->S1);
+ SD3.uart.s2_p = &(UART2->S2);
+ SD3.uart.d_p = &(UART2->D);
+ SD3.uart.uart_p = UART2;
+#endif /* KINETIS_SERIAL_USE_UART2 */
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+ /* Enables the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+#if KINETIS_SERIAL0_IS_LPUART
+ SIM->SCGC5 |= SIM_SCGC5_LPUART0;
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) |
+ SIM_SOPT2_LPUART0SRC(KINETIS_UART0_CLOCK_SRC);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SIM->SCGC4 |= SIM_SCGC4_UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#if KINETIS_SERIAL0_IS_UARTLP
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_UART0SRC_MASK) |
+ SIM_SOPT2_UART0SRC(KINETIS_UART0_CLOCK_SRC);
+#endif /* KINETIS_SERIAL0_IS_UARTLP */
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART0Status_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+ nvicEnableVector(UART0Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ nvicEnableVector(LPUART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ nvicEnableVector(UART0_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART0 */
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+#if KINETIS_SERIAL1_IS_LPUART
+ SIM->SCGC5 |= SIM_SCGC5_LPUART1;
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) |
+ SIM_SOPT2_LPUART1SRC(KINETIS_UART1_CLOCK_SRC);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ SIM->SCGC4 |= SIM_SCGC4_UART1;
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART1Status_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+ nvicEnableVector(UART1Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ nvicEnableVector(LPUART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ nvicEnableVector(UART1_IRQn, KINETIS_SERIAL_UART1_PRIORITY);
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART1 */
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+ SIM->SCGC4 |= SIM_SCGC4_UART2;
+ configure_uart(sdp, config);
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicEnableVector(UART2Status_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+ nvicEnableVector(UART2Error_IRQn, KINETIS_SERIAL_UART0_PRIORITY);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ nvicEnableVector(UART2_IRQn, KINETIS_SERIAL_UART2_PRIORITY);
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ }
+#endif /* KINETIS_SERIAL_USE_UART2 */
+
+ }
+ /* Configures the peripheral.*/
+
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ /* TODO: Resets the peripheral.*/
+
+#if KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART0Status_IRQn);
+ nvicDisableVector(UART0Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ nvicDisableVector(LPUART0_IRQn);
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ nvicDisableVector(UART0_IRQn);
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL0_IS_LPUART
+ SIM->SCGC5 &= ~SIM_SCGC5_LPUART0;
+#else /* KINETIS_SERIAL0_IS_LPUART */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART0;
+#endif /* KINETIS_SERIAL0_IS_LPUART */
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART1
+ if (sdp == &SD2) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART1Status_IRQn);
+ nvicDisableVector(UART1Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ nvicDisableVector(LPUART1_IRQn);
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ nvicDisableVector(UART1_IRQn);
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+#if KINETIS_SERIAL1_IS_LPUART
+ SIM->SCGC5 &= ~SIM_SCGC5_LPUART1;
+#else /* KINETIS_SERIAL1_IS_LPUART */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART1;
+#endif /* KINETIS_SERIAL1_IS_LPUART */
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART2
+ if (sdp == &SD3) {
+#if KINETIS_HAS_SERIAL_ERROR_IRQ
+ nvicDisableVector(UART2Status_IRQn);
+ nvicDisableVector(UART2Error_IRQn);
+#else /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ nvicDisableVector(UART2_IRQn);
+#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
+ SIM->SCGC4 &= ~SIM_SCGC4_UART2;
+ }
+#endif
+ }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.h new file mode 100644 index 0000000..f11c063 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_serial_lld.h @@ -0,0 +1,220 @@ +/*
+ ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KL2x/serial_lld.h
+ * @brief Kinetis KL2x Serial Driver subsystem low level driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef HAL_SERIAL_LLD_H_
+#define HAL_SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SD1 driver enable switch.
+ * @details If set to @p TRUE the support for SD1 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART0) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART0 FALSE
+#endif
+/**
+ * @brief SD2 driver enable switch.
+ * @details If set to @p TRUE the support for SD2 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART1) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART1 FALSE
+#endif
+/**
+ * @brief SD3 driver enable switch.
+ * @details If set to @p TRUE the support for SD3 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART2 FALSE
+#endif
+
+/**
+ * @brief UART0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART0_PRIORITY 12
+#endif
+
+/**
+ * @brief UART1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART1_PRIORITY 12
+#endif
+
+/**
+ * @brief UART2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART2_PRIORITY 12
+#endif
+
+/**
+ * @brief UART0 clock source.
+ */
+#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART0_CLOCK_SRC 1 /* MCGFLLCLK clock, or MCGPLLCLK/2; or IRC48M */
+#endif
+
+/**
+ * @brief UART1 clock source.
+ */
+#if !defined(KINETIS_UART1_CLOCK_SRC) || defined(__DOXYGEN__)
+#define KINETIS_UART1_CLOCK_SRC 1 /* IRC48M */
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/** @brief error checks */
+#if KINETIS_SERIAL_USE_UART0 && !KINETIS_HAS_SERIAL0
+#error "UART0 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 && !KINETIS_HAS_SERIAL1
+#error "UART1 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 && !KINETIS_HAS_SERIAL2
+#error "UART2 not present in the selected device"
+#endif
+
+#if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
+ KINETIS_SERIAL_USE_UART2)
+#error "Serial driver activated but no UART peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Generic Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ * in order to configure and start a serial driver operations.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t sc_speed;
+ /* End of the mandatory fields.*/
+} SerialConfig;
+
+/**
+ * @brief Generic UART register structure.
+ * @note Individual UART register blocks (even within the same chip) can differ.
+ */
+
+typedef struct {
+ volatile uint8_t* bdh_p;
+ volatile uint8_t* bdl_p;
+ volatile uint8_t* c1_p;
+ volatile uint8_t* c2_p;
+ volatile uint8_t* c3_p;
+ volatile uint8_t* c4_p;
+ volatile uint8_t* s1_p;
+ volatile uint8_t* s2_p;
+ volatile uint8_t* d_p;
+ UART_TypeDef *uart_p;
+#if KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_UARTLP
+ UARTLP_TypeDef *uartlp_p;
+#endif /* KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_UARTLP */
+#if (KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_LPUART) \
+ || (KINETIS_SERIAL_USE_UART1 && KINETIS_SERIAL1_IS_LPUART)
+ LPUART_TypeDef *lpuart_p;
+#endif /* KINETIS_SERIAL_USE_UART0 && KINETIS_SERIAL0_IS_LPUART */
+} UART_w_TypeDef;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data \
+ _base_asynchronous_channel_data \
+ /* Driver state.*/ \
+ sdstate_t state; \
+ /* Input queue.*/ \
+ input_queue_t iqueue; \
+ /* Output queue.*/ \
+ output_queue_t oqueue; \
+ /* Input circular buffer.*/ \
+ uint8_t ib[SERIAL_BUFFERS_SIZE]; \
+ /* Output circular buffer.*/ \
+ uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ /* End of the mandatory fields.*/ \
+ /* Pointer to the UART registers block.*/ \
+ UART_w_TypeDef uart;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_SERIAL_USE_UART0 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+
+#if KINETIS_SERIAL_USE_UART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+
+#if KINETIS_SERIAL_USE_UART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sd_lld_init(void);
+ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+ void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* HAL_SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.c new file mode 100644 index 0000000..e6ed9e5 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.c @@ -0,0 +1,98 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/st_lld.c
+ * @brief ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__)
+/**
+ * @brief System Timer vector.
+ * @details This interrupt is used for system tick in periodic mode.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SysTick_Handler) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC
+ /* Periodic systick mode, the Cortex-Mx internal systick timer is used
+ in this mode.*/
+ SysTick->LOAD = (KINETIS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk |
+ SysTick_CTRL_TICKINT_Msk;
+
+ /* IRQ enabled.*/
+ nvicSetSystemHandlerPriority(HANDLER_SYSTICK, KINETIS_ST_IRQ_PRIORITY);
+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.h new file mode 100644 index 0000000..29c7035 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_st_lld.h @@ -0,0 +1,156 @@ +/*
+ ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/st_lld.h
+ * @brief ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef HAL_ST_LLD_H_
+#define HAL_ST_LLD_H_
+
+#include "mcuconf.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SysTick timer IRQ priority.
+ */
+#if !defined(KINETIS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_ST_IRQ_PRIORITY 8
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the time counter value.
+ *
+ * @return The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+ return false;
+}
+
+#endif /* HAL_ST_LLD_H_ */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.c new file mode 100644 index 0000000..e8d9778 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.c @@ -0,0 +1,832 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde/
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/usb_lld.c
+ * @brief KINETIS USB subsystem low level driver source.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief USB0 driver identifier.*/
+#if KINETIS_USB_USE_USB0 || defined(__DOXYGEN__)
+USBDriver USBD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief IN EP0 state.
+ */
+USBInEndpointState ep0in;
+
+/**
+ * @brief OUT EP0 state.
+ */
+USBOutEndpointState ep0out;
+
+/**
+ * @brief Buffer for the EP0 setup packets.
+ */
+static uint8_t ep0setup_buffer[8];
+
+/**
+ * @brief EP0 initialization structure.
+ */
+static const USBEndpointConfig ep0config = {
+ USB_EP_MODE_TYPE_CTRL,
+ _usb_ep0setup,
+ _usb_ep0in,
+ _usb_ep0out,
+ 64,
+ 64,
+ &ep0in,
+ &ep0out,
+ 1,
+ ep0setup_buffer
+};
+
+/*
+ * Buffer Descriptor Table (BDT)
+ */
+
+/*
+ * Buffer Descriptor (BD)
+ * */
+typedef struct {
+ uint32_t desc;
+ uint8_t* addr;
+} bd_t;
+
+/*
+ * Buffer Descriptor fields - p.889
+ */
+#define BDT_OWN 0x80
+#define BDT_DATA 0x40
+#define BDT_KEEP 0x20
+#define BDT_NINC 0x10
+#define BDT_DTS 0x08
+#define BDT_STALL 0x04
+
+#define BDT_DESC(bc, data) (BDT_OWN | BDT_DTS | ((data&0x1)<<6) | ((bc) << 16))
+
+/*
+ * BDT PID - p.891
+ */
+#define BDT_PID_OUT 0x01
+#define BDT_PID_IN 0x09
+#define BDT_PID_SETUP 0x0D
+#define BDT_TOK_PID(n) (((n)>>2)&0xF)
+
+/*
+ * BDT index fields
+ */
+#define DATA0 0
+#define DATA1 1
+
+#define RX 0
+#define TX 1
+
+#define EVEN 0
+#define ODD 1
+
+#define BDT_INDEX(endpoint, tx, odd) (((endpoint)<<2) | ((tx)<<1) | (odd))
+/*
+ * Get RX-ed/TX-ed bytes count from BDT entry
+ */
+#define BDT_BC(n) (((n)>>16)&0x3FF)
+
+/* The USB-FS needs 2 BDT entry per endpoint direction
+ * that adds to: 2*2*16 BDT entries for 16 bi-directional EP
+ */
+static volatile bd_t _bdt[(KINETIS_USB_ENDPOINTS)*2*2] __attribute__((aligned(512)));
+
+/* FIXME later with dyn alloc
+ * 16 EP
+ * 2 directions per EP
+ * 2 buffer per direction
+ * => 64 buffers
+ */
+static uint8_t _usbb[KINETIS_USB_ENDPOINTS*4][64] __attribute__((aligned(4)));
+static volatile uint8_t _usbbn=0;
+uint8_t* usb_alloc(uint8_t size)
+{
+ (void)size;
+ if(_usbbn < (KINETIS_USB_ENDPOINTS)*4)
+ return _usbb[_usbbn++];
+ while(1); /* Should not happen, ever */
+}
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/* Called from locked ISR. */
+void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n)
+{
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ USBInEndpointState *isp = epc->in_state;
+
+ bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];
+
+ if (n > (size_t)epc->in_maxsize)
+ n = (size_t)epc->in_maxsize;
+
+ /* Copy from buf to _usbb[] */
+ size_t i=0;
+ for(i=0;i<n;i++)
+ bd->addr[i] = isp->txbuf[i];
+
+ /* Update the Buffer status */
+ bd->desc = BDT_DESC(n, isp->data_bank);
+ /* Toggle the odd and data bits for next TX */
+ isp->data_bank ^= DATA1;
+ isp->odd_even ^= ODD;
+}
+
+/* Called from locked ISR. */
+void usb_packet_receive(USBDriver *usbp, usbep_t ep, size_t n)
+{
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ USBOutEndpointState *osp = epc->out_state;
+
+ bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, RX, osp->odd_even)];
+
+ if (n > (size_t)epc->out_maxsize)
+ n = (size_t)epc->out_maxsize;
+
+ /* Copy from _usbb[] to buf */
+ size_t i=0;
+ for(i=0;i<n;i++)
+ osp->rxbuf[i] = bd->addr[i];
+
+ /* Update the Buffer status
+ * Set current buffer to same DATA bank and then toggle.
+ * Since even/odd buffers are ping-pong and setup re-initialized them
+ * this should work correctly */
+ bd->desc = BDT_DESC(epc->out_maxsize, osp->data_bank);
+ osp->data_bank ^= DATA1;
+ usb_lld_start_out(usbp, ep);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*============================================================================*/
+
+#if KINETIS_USB_USE_USB0 || defined(__DOXYGEN__)
+/**
+ * @brief USB interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) {
+ USBDriver *usbp = &USBD1;
+ uint8_t istat = USB0->ISTAT;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* 04 - Bit2 - Start Of Frame token received */
+ if(istat & USBx_ISTAT_SOFTOK) {
+ _usb_isr_invoke_sof_cb(usbp);
+ USB0->ISTAT = USBx_ISTAT_SOFTOK;
+ }
+
+ /* 08 - Bit3 - Token processing completed */
+ while(istat & USBx_ISTAT_TOKDNE) {
+ uint8_t stat = USB0->STAT;
+ uint8_t ep = stat >> 4;
+ if(ep > KINETIS_USB_ENDPOINTS) {
+ OSAL_IRQ_EPILOGUE();
+ return;
+ }
+ const USBEndpointConfig *epc = usbp->epc[ep];
+
+ /* Get the correct BDT entry */
+ uint8_t odd_even = (stat & USBx_STAT_ODD_MASK) >> USBx_STAT_ODD_SHIFT;
+ uint8_t tx_rx = (stat & USBx_STAT_TX_MASK) >> USBx_STAT_TX_SHIFT;
+ bd_t *bd = (bd_t*)&_bdt[BDT_INDEX(ep,tx_rx,odd_even)];
+
+ /* Update the ODD/EVEN state for RX */
+ if(tx_rx == RX && epc->out_state != NULL)
+ epc->out_state->odd_even = odd_even;
+
+ switch(BDT_TOK_PID(bd->desc))
+ {
+ case BDT_PID_SETUP: // SETUP
+ {
+ /* Clear any pending IN stuff */
+ _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
+ /* Also in the chibios state machine */
+ (usbp)->receiving &= ~1;
+ /* After a SETUP, IN is always DATA1 */
+ usbp->epc[ep]->in_state->data_bank = DATA1;
+
+ /* Call SETUP function (ChibiOS core), which sends back stuff */
+ _usb_isr_invoke_setup_cb(usbp, ep);
+ /* Buffer is released by the above callback. */
+ /* from Paul: "unfreeze the USB, now that we're ready" */
+ USB0->CTL = USBx_CTL_USBENSOFEN;
+ } break;
+ case BDT_PID_IN: // IN
+ {
+ if(epc->in_state == NULL)
+ break;
+ /* Special case for SetAddress for EP0 */
+ if(ep == 0 && (((uint16_t)usbp->setup[0]<<8)|usbp->setup[1]) == 0x0500)
+ {
+ usbp->address = usbp->setup[2];
+ usb_lld_set_address(usbp);
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_ADDRESS);
+ usbp->state = USB_SELECTED;
+ }
+ uint16_t txed = BDT_BC(bd->desc);
+ epc->in_state->txcnt += txed;
+ if(epc->in_state->txcnt < epc->in_state->txsize)
+ {
+ epc->in_state->txbuf += txed;
+ osalSysLockFromISR();
+ usb_packet_transmit(usbp,ep,epc->in_state->txsize - epc->in_state->txcnt);
+ osalSysUnlockFromISR();
+ }
+ else
+ {
+ if(epc->in_cb != NULL)
+ _usb_isr_invoke_in_cb(usbp,ep);
+ }
+ } break;
+ case BDT_PID_OUT: // OUT
+ {
+ if(epc->out_state == NULL)
+ break;
+ uint16_t rxed = BDT_BC(bd->desc);
+
+ osalSysLockFromISR();
+ usb_packet_receive(usbp,ep,rxed);
+ osalSysUnlockFromISR();
+ if(rxed)
+ {
+ epc->out_state->rxbuf += rxed;
+
+ /* Update transaction data */
+ epc->out_state->rxcnt += rxed;
+ epc->out_state->rxsize -= rxed;
+ epc->out_state->rxpkts -= 1;
+
+ /* The transaction is completed if the specified number of packets
+ has been received or the current packet is a short packet.*/
+ if ((rxed < epc->out_maxsize) || (epc->out_state->rxpkts == 0))
+ {
+ if(epc->out_cb != NULL)
+ _usb_isr_invoke_out_cb(usbp, ep);
+ }
+ }
+ } break;
+ default:
+ break;
+ }
+ USB0->ISTAT = USBx_ISTAT_TOKDNE;
+ istat = USB0->ISTAT;
+ }
+
+ /* 01 - Bit0 - Valid USB Reset received */
+ if(istat & USBx_ISTAT_USBRST) {
+ _usb_reset(usbp);
+ USB0->ISTAT = USBx_ISTAT_USBRST;
+ OSAL_IRQ_EPILOGUE();
+ return;
+ }
+
+ /* 80 - Bit7 - STALL handshake received */
+ if(istat & USBx_ISTAT_STALL) {
+ USB0->ISTAT = USBx_ISTAT_STALL;
+ }
+
+ /* 02 - Bit1 - ERRSTAT condition triggered */
+ if(istat & USBx_ISTAT_ERROR) {
+ uint8_t err = USB0->ERRSTAT;
+ USB0->ERRSTAT = err;
+ USB0->ISTAT = USBx_ISTAT_ERROR;
+ }
+
+ /* 10 - Bit4 - Constant IDLE on USB bus detected */
+ if(istat & USBx_ISTAT_SLEEP) {
+ /* This seems to fire a few times before the device is
+ * configured - need to ignore those occurences somehow. */
+ /* The other option would be to only activate INTEN_SLEEPEN
+ * on CONFIGURED event, but that would need to be done in
+ * user firmware. */
+ if(usbp->state == USB_ACTIVE) {
+ _usb_suspend(usbp);
+ /* Enable interrupt on resume */
+ USB0->INTEN |= USBx_INTEN_RESUMEEN;
+ }
+
+ // low-power version (check!):
+ // enable wakeup interrupt on resume USB signaling
+ // (check that it was a wakeup int with USBx_USBTRC0_USB_RESUME_INT)
+ //? USB0->USBTRC0 |= USBx_USBTRC0_USBRESMEN
+ // suspend the USB module
+ //? USB0->USBCTRL |= USBx_USBCTRL_SUSP;
+
+ USB0->ISTAT = USBx_ISTAT_SLEEP;
+ }
+
+ /* 20 - Bit5 - Resume - Only allowed in sleep=suspend mode */
+ if(istat & USBx_ISTAT_RESUME) {
+ /* Disable interrupt on resume (should be disabled
+ * during normal operation according to datasheet). */
+ USB0->INTEN &= ~USBx_INTEN_RESUMEEN;
+
+ // low power version (check!):
+ // desuspend the USB module
+ //? USB0->USBCTRL &= ~USBx_USBCTRL_SUSP;
+ // maybe also
+ //? USB0->CTL = USBx_CTL_USBENSOFEN;
+ _usb_wakeup(usbp);
+ USB0->ISTAT = USBx_ISTAT_RESUME;
+ }
+
+ /* 40 - Bit6 - ATTACH - used */
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_USB_USE_USB0 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level USB driver initialization.
+ *
+ * @notapi
+ */
+void usb_lld_init(void) {
+ /* Driver initialization.*/
+ usbObjectInit(&USBD1);
+
+#if KINETIS_USB_USE_USB0
+
+ SIM->SOPT2 |= SIM_SOPT2_USBSRC;
+
+#if defined(K20x5) || defined(K20x7)
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+
+ /* MCGOUTCLK is the SYSCLK frequency, so don't divide for USB clock */
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+ #define KINETIS_USBCLK_FREQUENCY 48000000UL
+ uint32_t i,j;
+ for(i=0; i < 2; i++) {
+ for(j=0; j < 8; j++) {
+ if((KINETIS_PLLCLK_FREQUENCY * (i+1)) == (KINETIS_USBCLK_FREQUENCY*(j+1))) {
+ SIM->CLKDIV2 = i | SIM_CLKDIV2_USBDIV(j);
+ goto usbfrac_match_found;
+ }
+ }
+ }
+ usbfrac_match_found:
+ osalDbgAssert(i<2 && j <8,"USB Init error");
+
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error USB clock setting not implemented for this KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
+
+#elif defined(KL25) || defined (KL26) || defined(KL27)
+
+ /* No extra clock dividers for USB clock */
+
+#else /* defined(KL25) || defined (KL26) || defined(KL27) */
+#error USB driver not implemented for your MCU type
+#endif
+
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Configures and activates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_start(USBDriver *usbp) {
+ if (usbp->state == USB_STOP) {
+#if KINETIS_USB_USE_USB0
+ if (&USBD1 == usbp) {
+ /* Clear BDT */
+ uint8_t i;
+ for(i=0;i<KINETIS_USB_ENDPOINTS;i++) {
+ _bdt[i].desc=0;
+ _bdt[i].addr=0;
+ }
+
+ /* Enable Clock */
+#if KINETIS_USB0_IS_USBOTG
+ SIM->SCGC4 |= SIM_SCGC4_USBOTG;
+#else /* KINETIS_USB0_IS_USBOTG */
+ SIM->SCGC4 |= SIM_SCGC4_USBFS;
+#endif /* KINETIS_USB0_IS_USBOTG */
+
+#if KINETIS_HAS_USB_CLOCK_RECOVERY
+ USB0->CLK_RECOVER_IRC_EN |= USBx_CLK_RECOVER_IRC_EN_IRC_EN;
+ USB0->CLK_RECOVER_CTRL |= USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN;
+#endif /* KINETIS_HAS_USB_CLOCK_RECOVERY */
+
+ /* Reset USB module, wait for completion */
+ USB0->USBTRC0 |= USBx_USBTRC0_USBRESET;
+ while ((USB0->USBTRC0 & USBx_USBTRC0_USBRESET));
+
+ /* Set BDT Address */
+ USB0->BDTPAGE1 = ((uint32_t)_bdt) >> 8;
+ USB0->BDTPAGE2 = ((uint32_t)_bdt) >> 16;
+ USB0->BDTPAGE3 = ((uint32_t)_bdt) >> 24;
+
+ /* Clear all ISR flags */
+ USB0->ISTAT = 0xFF;
+ USB0->ERRSTAT = 0xFF;
+#if KINETIS_USB0_IS_USBOTG
+ USB0->OTGISTAT = 0xFF;
+#endif /* KINETIS_USB0_IS_USBOTG */
+ USB0->USBTRC0 |= 0x40; //a hint was given that this is an undocumented interrupt bit
+
+ /* Enable USB */
+ USB0->CTL = USBx_CTL_ODDRST | USBx_CTL_USBENSOFEN;
+ USB0->USBCTRL = 0;
+
+ /* Enable reset interrupt */
+ USB0->INTEN |= USBx_INTEN_USBRSTEN;
+
+ /* Enable interrupt in NVIC */
+#if KINETIS_USB0_IS_USBOTG
+ nvicEnableVector(USB_OTG_IRQn, KINETIS_USB_USB0_IRQ_PRIORITY);
+#else /* KINETIS_USB0_IS_USBOTG */
+ nvicEnableVector(USB_IRQn, KINETIS_USB_USB0_IRQ_PRIORITY);
+#endif /* KINETIS_USB0_IS_USBOTG */
+ }
+#endif /* KINETIS_USB_USE_USB0 */
+ }
+}
+
+/**
+ * @brief Deactivates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_stop(USBDriver *usbp) {
+ /* TODO: If in ready state then disables the USB clock.*/
+ if (usbp->state == USB_STOP) {
+#if KINETIS_USB_USE_USB0
+ if (&USBD1 == usbp) {
+#if KINETIS_USB0_IS_USBOTG
+ nvicDisableVector(USB_OTG_IRQn);
+#else /* KINETIS_USB0_IS_USBOTG */
+ nvicDisableVector(USB_IRQn);
+#endif /* KINETIS_USB0_IS_USBOTG */
+ }
+#endif /* KINETIS_USB_USE_USB0 */
+ }
+}
+
+/**
+ * @brief USB low level reset routine.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_reset(USBDriver *usbp) {
+ // FIXME, dyn alloc
+ _usbbn = 0;
+
+#if KINETIS_USB_USE_USB0
+
+ /* Reset BDT ODD/EVEN bits */
+ USB0->CTL = USBx_CTL_ODDRST;
+
+ /* EP0 initialization.*/
+ usbp->epc[0] = &ep0config;
+ usb_lld_init_endpoint(usbp, 0);
+
+ /* Clear all pending interrupts */
+ USB0->ERRSTAT = 0xFF;
+ USB0->ISTAT = 0xFF;
+
+ /* Set the address to zero during enumeration */
+ usbp->address = 0;
+ USB0->ADDR = 0;
+
+ /* Enable other interrupts */
+ USB0->ERREN = 0xFF;
+ USB0->INTEN = USBx_INTEN_TOKDNEEN |
+ USBx_INTEN_SOFTOKEN |
+ USBx_INTEN_STALLEN |
+ USBx_INTEN_ERROREN |
+ USBx_INTEN_USBRSTEN |
+ USBx_INTEN_SLEEPEN;
+
+ /* "is this necessary?", Paul from PJRC */
+ USB0->CTL = USBx_CTL_USBENSOFEN;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Sets the USB address.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_set_address(USBDriver *usbp) {
+
+#if KINETIS_USB_USE_USB0
+ USB0->ADDR = usbp->address&0x7F;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Enables an endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
+
+ if(ep > KINETIS_USB_ENDPOINTS)
+ return;
+
+ const USBEndpointConfig *epc = usbp->epc[ep];
+ uint8_t mask=0;
+
+ if(epc->out_state != NULL)
+ {
+ /* OUT Endpoint */
+ epc->out_state->odd_even = EVEN;
+ epc->out_state->data_bank = DATA0;
+ /* RXe */
+ _bdt[BDT_INDEX(ep, RX, EVEN)].desc = BDT_DESC(epc->out_maxsize, DATA0);
+ _bdt[BDT_INDEX(ep, RX, EVEN)].addr = usb_alloc(epc->out_maxsize);
+ /* RXo */
+ _bdt[BDT_INDEX(ep, RX, ODD)].desc = BDT_DESC(epc->out_maxsize, DATA1);
+ _bdt[BDT_INDEX(ep, RX, ODD)].addr = usb_alloc(epc->out_maxsize);
+ /* Enable OUT direction */
+ mask |= USBx_ENDPTn_EPRXEN;
+ }
+ if(epc->in_state != NULL)
+ {
+ /* IN Endpoint */
+ epc->in_state->odd_even = EVEN;
+ epc->in_state->data_bank = DATA0;
+ /* TXe, not used yet */
+ _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, EVEN)].addr = usb_alloc(epc->in_maxsize);
+ /* TXo, not used yet */
+ _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
+ _bdt[BDT_INDEX(ep, TX, ODD)].addr = usb_alloc(epc->in_maxsize);
+ /* Enable IN direction */
+ mask |= USBx_ENDPTn_EPTXEN;
+ }
+
+ /* EPHSHK should be set for CTRL, BULK, INTR not for ISOC*/
+ if((epc->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_ISOC)
+ mask |= USBx_ENDPTn_EPHSHK;
+ /* Endpoint is not a CTRL endpoint, disable SETUP transfers */
+ if((epc->ep_mode & USB_EP_MODE_TYPE) != USB_EP_MODE_TYPE_CTRL)
+ mask |= USBx_ENDPTn_EPCTLDIS;
+
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V = mask;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Disables all the active endpoints except the endpoint zero.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_disable_endpoints(USBDriver *usbp) {
+ (void)usbp;
+ uint8_t i;
+#if KINETIS_USB_USE_USB0
+ for(i=1;i<KINETIS_USB_ENDPOINTS;i++)
+ USB0->ENDPT[i].V = 0;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Returns the status of an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ if(ep > USB_MAX_ENDPOINTS)
+ return EP_STATUS_DISABLED;
+ if(!(USB0->ENDPT[ep].V & (USBx_ENDPTn_EPRXEN)))
+ return EP_STATUS_DISABLED;
+ else if(USB0->ENDPT[ep].V & USBx_ENDPTn_EPSTALL)
+ return EP_STATUS_STALLED;
+ return EP_STATUS_ACTIVE;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Returns the status of an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+ if(ep > USB_MAX_ENDPOINTS)
+ return EP_STATUS_DISABLED;
+#if KINETIS_USB_USE_USB0
+ if(!(USB0->ENDPT[ep].V & (USBx_ENDPTn_EPTXEN)))
+ return EP_STATUS_DISABLED;
+ else if(USB0->ENDPT[ep].V & USBx_ENDPTn_EPSTALL)
+ return EP_STATUS_STALLED;
+ return EP_STATUS_ACTIVE;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Reads a setup packet from the dedicated packet buffer.
+ * @details This function must be invoked in the context of the @p setup_cb
+ * callback in order to read the received setup packet.
+ * @pre In order to use this function the endpoint must have been
+ * initialized as a control endpoint.
+ * @post The endpoint is ready to accept another packet.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[out] buf buffer where to copy the packet data
+ *
+ * @notapi
+ */
+void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
+ /* Get the BDT entry */
+ USBOutEndpointState *os = usbp->epc[ep]->out_state;
+ bd_t *bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even)];
+ /* Copy the 8 bytes of data */
+ uint8_t n;
+ for (n = 0; n < 8; n++) {
+ buf[n] = bd->addr[n];
+ }
+ /* Release the buffer
+ * Setup packet is always DATA0
+ * Initialize buffers so current expects DATA0 & opposite DATA1 */
+ bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
+ _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ os->data_bank = DATA1;
+}
+
+/**
+ * @brief Starts a receive operation on an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
+ USBOutEndpointState *osp = usbp->epc[ep]->out_state;
+ /* Transfer initialization.*/
+ if (osp->rxsize == 0) /* Special case for zero sized packets.*/
+ osp->rxpkts = 1;
+ else
+ osp->rxpkts = (uint16_t)((osp->rxsize + usbp->epc[ep]->out_maxsize - 1) /
+ usbp->epc[ep]->out_maxsize);
+}
+
+/**
+ * @brief Starts a transmit operation on an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @note Called from ISR and locked zone.
+ * @notapi
+ */
+void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+ (void)ep;
+ usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);
+}
+
+/**
+ * @brief Brings an OUT endpoint in the stalled state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V |= USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an IN endpoint in the stalled state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V |= USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an OUT endpoint in the active state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V &= ~USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+/**
+ * @brief Brings an IN endpoint in the active state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
+ (void)usbp;
+#if KINETIS_USB_USE_USB0
+ USB0->ENDPT[ep].V &= ~USBx_ENDPTn_EPSTALL;
+#endif /* KINETIS_USB_USE_USB0 */
+}
+
+#endif /* HAL_USE_USB */
+
+/** @} */
diff --git a/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.h new file mode 100644 index 0000000..593ef16 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/ports/KINETIS/LLD/hal_usb_lld.h @@ -0,0 +1,428 @@ +/*
+ ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde/
+ (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file KINETIS/LLD/usb_lld.h
+ * @brief KINETIS USB subsystem low level driver header.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#ifndef HAL_USB_LLD_H_
+#define HAL_USB_LLD_H_
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum endpoint address.
+ */
+#define USB_MAX_ENDPOINTS 15
+
+/**
+ * @brief Status stage handling method.
+ */
+#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW
+
+/**
+ * @brief Address ack handling
+ */
+#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW
+
+/**
+ * @brief This device requires the address change after the status packet.
+ */
+#define USB_SET_ADDRESS_MODE USB_LATE_SET_ADDRESS
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief USB1 driver enable switch.
+ * @details If set to @p TRUE the support for USB1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(KINETIS_USB_USE_USB0) || defined(__DOXYGEN__)
+#define KINETIS_USB_USE_USB0 FALSE
+#endif
+
+/**
+ * @brief USB1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_USB_USB0_IRQ_PRIORITY)|| defined(__DOXYGEN__)
+#define KINETIS_USB_USB0_IRQ_PRIORITY 5
+#endif
+
+#if !defined(KINETIS_USB_ENDPOINTS) || defined(__DOXYGEN__)
+ #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if KINETIS_USB_USE_USB0 && !KINETIS_HAS_USB
+#error "USB not present in the selected device"
+#endif
+
+#if !KINETIS_USB_USE_USB0
+#error "USB driver activated but no USB peripheral assigned"
+#endif
+
+#if KINETIS_USB_USE_USB0 && \
+ !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_USB_USB0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to KINETIS_USB_USB0_IRQ_PRIORITY"
+#endif
+
+#if !defined(KINETIS_USB_IRQ_VECTOR)
+#error "KINETIS_USB_IRQ_VECTOR not defined"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of an IN endpoint state structure.
+ */
+typedef struct {
+ /**
+ * @brief Requested transmit transfer size.
+ */
+ size_t txsize;
+ /**
+ * @brief Transmitted bytes so far.
+ */
+ size_t txcnt;
+ /**
+ * @brief Pointer to the transmission linear buffer.
+ */
+ const uint8_t *txbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
+ /* */
+ bool odd_even; /* ODD / EVEN */
+ /* */
+ bool data_bank; /* DATA0 / DATA1 */
+} USBInEndpointState;
+
+/**
+ * @brief Type of an OUT endpoint state structure.
+ */
+typedef struct {
+ /**
+ * @brief Requested receive transfer size.
+ */
+ size_t rxsize;
+ /**
+ * @brief Received bytes so far.
+ */
+ size_t rxcnt;
+ /**
+ * @brief Pointer to the receive linear buffer.
+ */
+ uint8_t *rxbuf;
+#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Number of packets to receive.
+ */
+ uint16_t rxpkts;
+ /* */
+ bool odd_even; /* ODD / EVEN */
+ /* */
+ bool data_bank; /* DATA0 / DATA1 */
+} USBOutEndpointState;
+
+/**
+ * @brief Type of an USB endpoint configuration structure.
+ * @note Platform specific restrictions may apply to endpoints.
+ */
+typedef struct {
+ /**
+ * @brief Type and mode of the endpoint.
+ */
+ uint32_t ep_mode;
+ /**
+ * @brief Setup packet notification callback.
+ * @details This callback is invoked when a setup packet has been
+ * received.
+ * @post The application must immediately call @p usbReadPacket() in
+ * order to access the received packet.
+ * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL
+ * endpoints, it should be set to @p NULL for other endpoint
+ * types.
+ */
+ usbepcallback_t setup_cb;
+ /**
+ * @brief IN endpoint notification callback.
+ * @details This field must be set to @p NULL if callback is not required.
+ */
+ usbepcallback_t in_cb;
+ /**
+ * @brief OUT endpoint notification callback.
+ * @details This field must be set to @p NULL if callback is not required.
+ */
+ usbepcallback_t out_cb;
+ /**
+ * @brief IN endpoint maximum packet size.
+ * @details This field must be set to zero if the IN endpoint is not used.
+ */
+ uint16_t in_maxsize;
+ /**
+ * @brief OUT endpoint maximum packet size.
+ * @details This field must be set to zero if the OUT endpoint is not used.
+ */
+ uint16_t out_maxsize;
+ /**
+ * @brief @p USBEndpointState associated to the IN endpoint.
+ * @details This field must be set to @p NULL if the IN endpoint is not
+ * used.
+ */
+ USBInEndpointState *in_state;
+ /**
+ * @brief @p USBEndpointState associated to the OUT endpoint.
+ * @details This field must be set to @p NULL if the OUT endpoint is not
+ * used.
+ */
+ USBOutEndpointState *out_state;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Reserved field, not currently used.
+ * @note Initialize this field to 1 in order to be forward compatible.
+ */
+ uint16_t ep_buffers;
+ /**
+ * @brief Pointer to a buffer for setup packets.
+ * @details Setup packets require a dedicated 8-bytes buffer, set this
+ * field to @p NULL for non-control endpoints.
+ */
+ uint8_t *setup_buf;
+} USBEndpointConfig;
+
+/**
+ * @brief Type of an USB driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief USB events callback.
+ * @details This callback is invoked when an USB driver event is registered.
+ */
+ usbeventcb_t event_cb;
+ /**
+ * @brief Device GET_DESCRIPTOR request callback.
+ * @note This callback is mandatory and cannot be set to @p NULL.
+ */
+ usbgetdescriptor_t get_descriptor_cb;
+ /**
+ * @brief Requests hook callback.
+ * @details This hook allows to be notified of standard requests or to
+ * handle non standard requests.
+ */
+ usbreqhandler_t requests_hook_cb;
+ /**
+ * @brief Start Of Frame callback.
+ */
+ usbcallback_t sof_cb;
+ /* End of the mandatory fields.*/
+} USBConfig;
+
+/**
+ * @brief Structure representing an USB driver.
+ */
+struct USBDriver {
+ /**
+ * @brief Driver state.
+ */
+ usbstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const USBConfig *config;
+ /**
+ * @brief Bit map of the transmitting IN endpoints.
+ */
+ uint16_t transmitting;
+ /**
+ * @brief Bit map of the receiving OUT endpoints.
+ */
+ uint16_t receiving;
+ /**
+ * @brief Active endpoints configurations.
+ */
+ const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1];
+ /**
+ * @brief Fields available to user, it can be used to associate an
+ * application-defined handler to an IN endpoint.
+ * @note The base index is one, the endpoint zero does not have a
+ * reserved element in this array.
+ */
+ void *in_params[USB_MAX_ENDPOINTS];
+ /**
+ * @brief Fields available to user, it can be used to associate an
+ * application-defined handler to an OUT endpoint.
+ * @note The base index is one, the endpoint zero does not have a
+ * reserved element in this array.
+ */
+ void *out_params[USB_MAX_ENDPOINTS];
+ /**
+ * @brief Endpoint 0 state.
+ */
+ usbep0state_t ep0state;
+ /**
+ * @brief Next position in the buffer to be transferred through endpoint 0.
+ */
+ uint8_t *ep0next;
+ /**
+ * @brief Number of bytes yet to be transferred through endpoint 0.
+ */
+ size_t ep0n;
+ /**
+ * @brief Endpoint 0 end transaction callback.
+ */
+ usbcallback_t ep0endcb;
+ /**
+ * @brief Setup packet buffer.
+ */
+ uint8_t setup[8];
+ /**
+ * @brief Current USB device status.
+ */
+ uint16_t status;
+ /**
+ * @brief Assigned USB address.
+ */
+ uint8_t address;
+ /**
+ * @brief Current USB device configuration.
+ */
+ uint8_t configuration;
+#if defined(USB_DRIVER_EXT_FIELDS)
+ USB_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the next address in the packet memory.
+ */
+ uint32_t pmnext;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current frame number.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @return The current frame number.
+ *
+ * @notapi
+ */
+#define usb_lld_get_frame_number(usbp) ((USB0->FRMNUMH<<8)|USB0->FRMNUML)
+
+/**
+ * @brief Returns the exact size of a receive transaction.
+ * @details The received size can be different from the size specified in
+ * @p usbStartReceiveI() because the last packet could have a size
+ * different from the expected one.
+ * @pre The OUT endpoint must have been configured in transaction mode
+ * in order to use this function.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return Received data size.
+ *
+ * @notapi
+ */
+#define usb_lld_get_transaction_size(usbp, ep) \
+ ((usbp)->epc[ep]->out_state->rxcnt)
+
+/**
+ * @brief Connects the USB device.
+ *
+ * @api
+ */
+#if !defined(usb_lld_connect_bus)
+#define usb_lld_connect_bus(usbp) (USB0->CONTROL |= USBx_CONTROL_DPPULLUPNONOTG)
+#endif
+
+/**
+ * @brief Disconnect the USB device.
+ *
+ * @api
+ */
+#if !defined(usb_lld_disconnect_bus)
+/* Writing to USB0->CONTROL causes an unhandled exception when USB module is not clocked. */
+#if KINETIS_USB0_IS_USBOTG
+#define usb_lld_disconnect_bus(usbp) if(SIM->SCGC4 & SIM_SCGC4_USBOTG) {USB0->CONTROL &= ~USBx_CONTROL_DPPULLUPNONOTG;} else {}
+#else /* KINETIS_USB0_IS_USBOTG */
+#define usb_lld_disconnect_bus(usbp) if(SIM->SCGC4 & SIM_SCGC4_USBFS) {USB0->CONTROL &= ~USBx_CONTROL_DPPULLUPNONOTG;} else {}
+#endif /* KINETIS_USB0_IS_USBOTG */
+#endif
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if KINETIS_USB_USE_USB0 && !defined(__DOXYGEN__)
+extern USBDriver USBD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void usb_lld_init(void);
+ void usb_lld_start(USBDriver *usbp);
+ void usb_lld_stop(USBDriver *usbp);
+ void usb_lld_reset(USBDriver *usbp);
+ void usb_lld_set_address(USBDriver *usbp);
+ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
+ void usb_lld_disable_endpoints(USBDriver *usbp);
+ usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
+ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
+ void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_USB */
+
+#endif /* HAL_USB_LLD_H_ */
+
+/** @} */
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