diff options
Diffstat (limited to 'ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD')
3 files changed, 539 insertions, 0 deletions
diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c new file mode 100644 index 0000000..437dcf8 --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c @@ -0,0 +1,105 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOA_DATA, VAL_GPIOA_DIR, VAL_GPIOA_AFSEL, VAL_GPIOA_DR2R, + VAL_GPIOA_DR4R, VAL_GPIOA_DR8R, VAL_GPIOA_ODR, VAL_GPIOA_PUR, + VAL_GPIOA_PDR, VAL_GPIOA_SLR, VAL_GPIOA_DEN, VAL_GPIOA_AMSEL, + VAL_GPIOA_PCTL}, + {VAL_GPIOB_DATA, VAL_GPIOB_DIR, VAL_GPIOB_AFSEL, VAL_GPIOB_DR2R, + VAL_GPIOB_DR4R, VAL_GPIOB_DR8R, VAL_GPIOB_ODR, VAL_GPIOB_PUR, + VAL_GPIOB_PDR, VAL_GPIOB_SLR, VAL_GPIOB_DEN, VAL_GPIOB_AMSEL, + VAL_GPIOB_PCTL}, + {VAL_GPIOC_DATA, VAL_GPIOC_DIR, VAL_GPIOC_AFSEL, VAL_GPIOC_DR2R, + VAL_GPIOC_DR4R, VAL_GPIOC_DR8R, VAL_GPIOC_ODR, VAL_GPIOC_PUR, + VAL_GPIOC_PDR, VAL_GPIOC_SLR, VAL_GPIOC_DEN, VAL_GPIOC_AMSEL, + VAL_GPIOC_PCTL}, + {VAL_GPIOD_DATA, VAL_GPIOD_DIR, VAL_GPIOD_AFSEL, VAL_GPIOD_DR2R, + VAL_GPIOD_DR4R, VAL_GPIOD_DR8R, VAL_GPIOD_ODR, VAL_GPIOD_PUR, + VAL_GPIOD_PDR, VAL_GPIOD_SLR, VAL_GPIOD_DEN, VAL_GPIOD_AMSEL, + VAL_GPIOD_PCTL}, + {VAL_GPIOE_DATA, VAL_GPIOE_DIR, VAL_GPIOE_AFSEL, VAL_GPIOE_DR2R, + VAL_GPIOE_DR4R, VAL_GPIOE_DR8R, VAL_GPIOE_ODR, VAL_GPIOE_PUR, + VAL_GPIOE_PDR, VAL_GPIOE_SLR, VAL_GPIOE_DEN, VAL_GPIOE_AMSEL, + VAL_GPIOE_PCTL}, + {VAL_GPIOF_DATA, VAL_GPIOF_DIR, VAL_GPIOF_AFSEL, VAL_GPIOF_DR2R, + VAL_GPIOF_DR4R, VAL_GPIOF_DR8R, VAL_GPIOF_ODR, VAL_GPIOF_PUR, + VAL_GPIOF_PDR, VAL_GPIOF_SLR, VAL_GPIOF_DEN, VAL_GPIOF_AMSEL, + VAL_GPIOF_PCTL}, + {VAL_GPIOG_DATA, VAL_GPIOG_DIR, VAL_GPIOG_AFSEL, VAL_GPIOG_DR2R, + VAL_GPIOG_DR4R, VAL_GPIOG_DR8R, VAL_GPIOG_ODR, VAL_GPIOG_PUR, + VAL_GPIOG_PDR, VAL_GPIOG_SLR, VAL_GPIOG_DEN, VAL_GPIOG_AMSEL, + VAL_GPIOG_PCTL}, + {VAL_GPIOH_DATA, VAL_GPIOH_DIR, VAL_GPIOH_AFSEL, VAL_GPIOH_DR2R, + VAL_GPIOH_DR4R, VAL_GPIOH_DR8R, VAL_GPIOH_ODR, VAL_GPIOH_PUR, + VAL_GPIOH_PDR, VAL_GPIOH_SLR, VAL_GPIOH_DEN, VAL_GPIOH_AMSEL, + VAL_GPIOH_PCTL}, + {VAL_GPIOJ_DATA, VAL_GPIOJ_DIR, VAL_GPIOJ_AFSEL, VAL_GPIOJ_DR2R, + VAL_GPIOJ_DR4R, VAL_GPIOJ_DR8R, VAL_GPIOJ_ODR, VAL_GPIOJ_PUR, + VAL_GPIOJ_PDR, VAL_GPIOJ_SLR, VAL_GPIOJ_DEN, VAL_GPIOJ_AMSEL, + VAL_GPIOJ_PCTL}, + {VAL_GPIOK_DATA, VAL_GPIOK_DIR, VAL_GPIOK_AFSEL, VAL_GPIOK_DR2R, + VAL_GPIOK_DR4R, VAL_GPIOK_DR8R, VAL_GPIOK_ODR, VAL_GPIOK_PUR, + VAL_GPIOK_PDR, VAL_GPIOK_SLR, VAL_GPIOK_DEN, VAL_GPIOK_AMSEL, + VAL_GPIOK_PCTL}, + {VAL_GPIOL_DATA, VAL_GPIOL_DIR, VAL_GPIOL_AFSEL, VAL_GPIOL_DR2R, + VAL_GPIOL_DR4R, VAL_GPIOL_DR8R, VAL_GPIOL_ODR, VAL_GPIOL_PUR, + VAL_GPIOL_PDR, VAL_GPIOL_SLR, VAL_GPIOL_DEN, VAL_GPIOL_AMSEL, + VAL_GPIOL_PCTL}, + {VAL_GPIOM_DATA, VAL_GPIOM_DIR, VAL_GPIOM_AFSEL, VAL_GPIOM_DR2R, + VAL_GPIOM_DR4R, VAL_GPIOM_DR8R, VAL_GPIOM_ODR, VAL_GPIOM_PUR, + VAL_GPIOM_PDR, VAL_GPIOM_SLR, VAL_GPIOM_DEN, VAL_GPIOM_AMSEL, + VAL_GPIOM_PCTL}, + {VAL_GPION_DATA, VAL_GPION_DIR, VAL_GPION_AFSEL, VAL_GPION_DR2R, + VAL_GPION_DR4R, VAL_GPION_DR8R, VAL_GPION_ODR, VAL_GPION_PUR, + VAL_GPION_PDR, VAL_GPION_SLR, VAL_GPION_DEN, VAL_GPION_AMSEL, + VAL_GPION_PCTL}, + {VAL_GPIOP_DATA, VAL_GPIOP_DIR, VAL_GPIOP_AFSEL, VAL_GPIOP_DR2R, + VAL_GPIOP_DR4R, VAL_GPIOP_DR8R, VAL_GPIOP_ODR, VAL_GPIOP_PUR, + VAL_GPIOP_PDR, VAL_GPIOP_SLR, VAL_GPIOP_DEN, VAL_GPIOP_AMSEL, + VAL_GPIOP_PCTL}, + {VAL_GPIOQ_DATA, VAL_GPIOQ_DIR, VAL_GPIOQ_AFSEL, VAL_GPIOQ_DR2R, + VAL_GPIOQ_DR4R, VAL_GPIOQ_DR8R, VAL_GPIOQ_ODR, VAL_GPIOQ_PUR, + VAL_GPIOQ_PDR, VAL_GPIOQ_SLR, VAL_GPIOQ_DEN, VAL_GPIOQ_AMSEL, + VAL_GPIOQ_PCTL} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization is performed just after reset before BSS and + * DATA segments initialization. + */ +void __early_init(void) { + tiva_clock_init(); +} + +/** + * @brief Late initialization code. + * @note This initialization is performed after BSS and DATA segments + * initialization and before invoking the main() function. + */ +void boardInit(void) { +} diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h new file mode 100644 index 0000000..08bb36f --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h @@ -0,0 +1,429 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Texas Instruments TM4C1294 Launchpad Board. + */ + +/* + * Board identifier. + */ +#define BOARD_TI_TM4C1294_LAUNCHPAD +#define BOARD_NAME "Texas Instruments TM4C1294 Launchpad" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ADDR 0 /* 0 is internal PHY */ +#define BOARD_PHY_ID 0x2000A221 /* internal PHY ID */ +/* uncomment when using RMII */ +//#define BOARD_PHY_RMII + +/* + * MCU type + */ +//#define TM4C1290NCPDT +//#define TM4C1290NCZAD +//#define TM4C1292NCPDT +//#define TM4C1292NCZAD +//#define TM4C1294KCPDT +#define TM4C1294NCPDT +//#define TM4C1294NCZAD +//#define TM4C1297NCZAD +//#define TM4C1299KCZAD +//#define TM4C1299NCZAD +//#define TM4C129CNCPDT +//#define TM4C129CNCZAD +//#define TM4C129DNCPDT +//#define TM4C129DNCZAD +//#define TM4C129EKCPDT +//#define TM4C129ENCPDT +//#define TM4C129ENCZAD +//#define TM4C129LNCZAD +//#define TM4C129XKCZAD +//#define TM4C129XNCZAD + +/* + * Board oscillators-related settings. + */ +#define TIVA_XTAL_VALUE 25000000 + +/* + * IO pins assignments. + */ +#define GPIOA_UART0_RX 0 +#define GPIOA_UART0_TX 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_PIN4 4 +#define GPIOA_PIN5 5 +#define GPIOA_PIN6 6 +#define GPIOA_PIN7 7 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_PIN2 2 +#define GPIOB_PIN3 3 +#define GPIOB_PIN4 4 +#define GPIOB_PIN5 5 +#define GPIOB_PIN6 6 +#define GPIOB_PIN7 7 + +#define GPIOC_TCK_SWCLK 0 +#define GPIOC_TMS_SWDIO 1 +#define GPIOC_TDI 2 +#define GPIOC_TDO_SWO 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_PIN7 7 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_PIN2 2 +#define GPIOD_PIN3 3 +#define GPIOD_PIN4 4 +#define GPIOD_PIN5 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 + +#define GPIOE_PIN0 0 +#define GPIOE_PIN1 1 +#define GPIOE_PIN2 2 +#define GPIOE_PIN3 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 + +#define GPIOF_LED0 0 +#define GPIOF_PIN1 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_LED1 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 + +#define GPIOG_PIN0 0 +#define GPIOG_PIN1 1 +#define GPIOG_PIN2 2 +#define GPIOG_PIN3 3 +#define GPIOG_PIN4 4 +#define GPIOG_PIN5 5 +#define GPIOG_PIN6 6 +#define GPIOG_PIN7 7 + +#define GPIOH_PIN0 0 +#define GPIOH_PIN1 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 + +#define GPIOJ_SW1 0 +#define GPIOJ_PIN1 1 +#define GPIOJ_PIN2 2 +#define GPIOJ_PIN3 3 +#define GPIOJ_PIN4 4 +#define GPIOJ_PIN5 5 +#define GPIOJ_PIN6 6 +#define GPIOJ_PIN7 7 + +#define GPIOK_PIN0 0 +#define GPIOK_PIN1 1 +#define GPIOK_PIN2 2 +#define GPIOK_PIN3 3 +#define GPIOK_PIN4 4 +#define GPIOK_PIN5 5 +#define GPIOK_PIN6 6 +#define GPIOK_PIN7 7 + +#define GPIOL_PIN0 0 +#define GPIOL_PIN1 1 +#define GPIOL_PIN2 2 +#define GPIOL_PIN3 3 +#define GPIOL_PIN4 4 +#define GPIOL_PIN5 5 +#define GPIOL_PIN6 6 +#define GPIOL_PIN7 7 + +#define GPIOM_PIN0 0 +#define GPIOM_PIN1 1 +#define GPIOM_PIN2 2 +#define GPIOM_PIN3 3 +#define GPIOM_PIN4 4 +#define GPIOM_PIN5 5 +#define GPIOM_PIN6 6 +#define GPIOM_PIN7 7 + +#define GPION_LED2 0 +#define GPION_LED3 1 +#define GPION_PIN2 2 +#define GPION_PIN3 3 +#define GPION_PIN4 4 +#define GPION_PIN5 5 +#define GPION_PIN6 6 +#define GPION_PIN7 7 + +#define GPIOP_PIN0 0 +#define GPIOP_PIN1 1 +#define GPIOP_PIN2 2 +#define GPIOP_PIN3 3 +#define GPIOP_PIN4 4 +#define GPIOP_PIN5 5 +#define GPIOP_PIN6 6 +#define GPIOP_PIN7 7 + +#define GPIOQ_PIN0 0 +#define GPIOQ_PIN1 1 +#define GPIOQ_PIN2 2 +#define GPIOQ_PIN3 3 +#define GPIOQ_PIN4 4 +#define GPIOQ_PIN5 5 +#define GPIOQ_PIN6 6 +#define GPIOQ_PIN7 7 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + */ +#define VAL_GPIOA_DATA 0b00000000 +#define VAL_GPIOA_DIR 0b00000000 +#define VAL_GPIOA_AFSEL 0b00000000 +#define VAL_GPIOA_DR2R 0b11111111 +#define VAL_GPIOA_DR4R 0b00000000 +#define VAL_GPIOA_DR8R 0b00000000 +#define VAL_GPIOA_ODR 0b00000000 +#define VAL_GPIOA_PUR 0b00000000 +#define VAL_GPIOA_PDR 0b00000000 +#define VAL_GPIOA_SLR 0b00000000 +#define VAL_GPIOA_DEN 0b11111111 +#define VAL_GPIOA_AMSEL 0b0000 +#define VAL_GPIOA_PCTL 0x00000000 + +#define VAL_GPIOB_DATA 0b00000000 +#define VAL_GPIOB_DIR 0b00000000 +#define VAL_GPIOB_AFSEL 0b00000000 +#define VAL_GPIOB_DR2R 0b11111111 +#define VAL_GPIOB_DR4R 0b00000000 +#define VAL_GPIOB_DR8R 0b00000000 +#define VAL_GPIOB_ODR 0b00000000 +#define VAL_GPIOB_PUR 0b00000000 +#define VAL_GPIOB_PDR 0b00000000 +#define VAL_GPIOB_SLR 0b00000000 +#define VAL_GPIOB_DEN 0b11111111 +#define VAL_GPIOB_AMSEL 0b0000 +#define VAL_GPIOB_PCTL 0x00000000 + +#define VAL_GPIOC_DATA 0b00000000 +#define VAL_GPIOC_DIR 0b00001000 +#define VAL_GPIOC_AFSEL 0b00001111 +#define VAL_GPIOC_DR2R 0b11111111 +#define VAL_GPIOC_DR4R 0b00000000 +#define VAL_GPIOC_DR8R 0b00000000 +#define VAL_GPIOC_ODR 0b00000000 +#define VAL_GPIOC_PUR 0b00001111 +#define VAL_GPIOC_PDR 0b00000000 +#define VAL_GPIOC_SLR 0b00000000 +#define VAL_GPIOC_DEN 0b11111111 +#define VAL_GPIOC_AMSEL 0b0000 +#define VAL_GPIOC_PCTL 0x00001111 + +#define VAL_GPIOD_DATA 0b00000000 +#define VAL_GPIOD_DIR 0b00000000 +#define VAL_GPIOD_AFSEL 0b00000000 +#define VAL_GPIOD_DR2R 0b11111111 +#define VAL_GPIOD_DR4R 0b00000000 +#define VAL_GPIOD_DR8R 0b00000000 +#define VAL_GPIOD_ODR 0b00000000 +#define VAL_GPIOD_PUR 0b00000000 +#define VAL_GPIOD_PDR 0b00000000 +#define VAL_GPIOD_SLR 0b00000000 +#define VAL_GPIOD_DEN 0b11111111 +#define VAL_GPIOD_AMSEL 0b0000 +#define VAL_GPIOD_PCTL 0x00000000 + +#define VAL_GPIOE_DATA 0b00000000 +#define VAL_GPIOE_DIR 0b00000000 +#define VAL_GPIOE_AFSEL 0b00000000 +#define VAL_GPIOE_DR2R 0b11111111 +#define VAL_GPIOE_DR4R 0b00000000 +#define VAL_GPIOE_DR8R 0b00000000 +#define VAL_GPIOE_ODR 0b00000000 +#define VAL_GPIOE_PUR 0b00000000 +#define VAL_GPIOE_PDR 0b00000000 +#define VAL_GPIOE_SLR 0b00000000 +#define VAL_GPIOE_DEN 0b11111111 +#define VAL_GPIOE_AMSEL 0b0000 +#define VAL_GPIOE_PCTL 0x00000000 + +#define VAL_GPIOF_DATA 0b00000000 +#define VAL_GPIOF_DIR 0b00000000 +#define VAL_GPIOF_AFSEL 0b00000000 +#define VAL_GPIOF_DR2R 0b11111111 +#define VAL_GPIOF_DR4R 0b00000000 +#define VAL_GPIOF_DR8R 0b00000000 +#define VAL_GPIOF_ODR 0b00000000 +#define VAL_GPIOF_PUR 0b00000000 +#define VAL_GPIOF_PDR 0b00000000 +#define VAL_GPIOF_SLR 0b00000000 +#define VAL_GPIOF_DEN 0b11111111 +#define VAL_GPIOF_AMSEL 0b0000 +#define VAL_GPIOF_PCTL 0x00000000 + +#define VAL_GPIOG_DATA 0b00000000 +#define VAL_GPIOG_DIR 0b00000000 +#define VAL_GPIOG_AFSEL 0b00000000 +#define VAL_GPIOG_DR2R 0b11111111 +#define VAL_GPIOG_DR4R 0b00000000 +#define VAL_GPIOG_DR8R 0b00000000 +#define VAL_GPIOG_ODR 0b00000000 +#define VAL_GPIOG_PUR 0b00000000 +#define VAL_GPIOG_PDR 0b00000000 +#define VAL_GPIOG_SLR 0b00000000 +#define VAL_GPIOG_DEN 0b11111111 +#define VAL_GPIOG_AMSEL 0b0000 +#define VAL_GPIOG_PCTL 0x00000000 + +#define VAL_GPIOH_DATA 0b00000000 +#define VAL_GPIOH_DIR 0b00000000 +#define VAL_GPIOH_AFSEL 0b00000000 +#define VAL_GPIOH_DR2R 0b11111111 +#define VAL_GPIOH_DR4R 0b00000000 +#define VAL_GPIOH_DR8R 0b00000000 +#define VAL_GPIOH_ODR 0b00000000 +#define VAL_GPIOH_PUR 0b00000000 +#define VAL_GPIOH_PDR 0b00000000 +#define VAL_GPIOH_SLR 0b00000000 +#define VAL_GPIOH_DEN 0b11111111 +#define VAL_GPIOH_AMSEL 0b0000 +#define VAL_GPIOH_PCTL 0x00000000 + +#define VAL_GPIOJ_DATA 0b00000000 +#define VAL_GPIOJ_DIR 0b00000000 +#define VAL_GPIOJ_AFSEL 0b00000000 +#define VAL_GPIOJ_DR2R 0b11111111 +#define VAL_GPIOJ_DR4R 0b00000000 +#define VAL_GPIOJ_DR8R 0b00000000 +#define VAL_GPIOJ_ODR 0b00000000 +#define VAL_GPIOJ_PUR 0b00000001 +#define VAL_GPIOJ_PDR 0b00000000 +#define VAL_GPIOJ_SLR 0b00000000 +#define VAL_GPIOJ_DEN 0b11111111 +#define VAL_GPIOJ_AMSEL 0b0000 +#define VAL_GPIOJ_PCTL 0x00000000 + +#define VAL_GPIOK_DATA 0b00000000 +#define VAL_GPIOK_DIR 0b00000000 +#define VAL_GPIOK_AFSEL 0b00000000 +#define VAL_GPIOK_DR2R 0b11111111 +#define VAL_GPIOK_DR4R 0b00000000 +#define VAL_GPIOK_DR8R 0b00000000 +#define VAL_GPIOK_ODR 0b00000000 +#define VAL_GPIOK_PUR 0b00000000 +#define VAL_GPIOK_PDR 0b00000000 +#define VAL_GPIOK_SLR 0b00000000 +#define VAL_GPIOK_DEN 0b11111111 +#define VAL_GPIOK_AMSEL 0b0000 +#define VAL_GPIOK_PCTL 0x00000000 + +#define VAL_GPIOL_DATA 0b00000000 +#define VAL_GPIOL_DIR 0b00000000 +#define VAL_GPIOL_AFSEL 0b00000000 +#define VAL_GPIOL_DR2R 0b11111111 +#define VAL_GPIOL_DR4R 0b00000000 +#define VAL_GPIOL_DR8R 0b00000000 +#define VAL_GPIOL_ODR 0b00000000 +#define VAL_GPIOL_PUR 0b00000000 +#define VAL_GPIOL_PDR 0b00000000 +#define VAL_GPIOL_SLR 0b00000000 +#define VAL_GPIOL_DEN 0b11111111 +#define VAL_GPIOL_AMSEL 0b0000 +#define VAL_GPIOL_PCTL 0x00000000 + +#define VAL_GPIOM_DATA 0b00000000 +#define VAL_GPIOM_DIR 0b00000000 +#define VAL_GPIOM_AFSEL 0b00000000 +#define VAL_GPIOM_DR2R 0b11111111 +#define VAL_GPIOM_DR4R 0b00000000 +#define VAL_GPIOM_DR8R 0b00000000 +#define VAL_GPIOM_ODR 0b00000000 +#define VAL_GPIOM_PUR 0b00000000 +#define VAL_GPIOM_PDR 0b00000000 +#define VAL_GPIOM_SLR 0b00000000 +#define VAL_GPIOM_DEN 0b11111111 +#define VAL_GPIOM_AMSEL 0b0000 +#define VAL_GPIOM_PCTL 0x00000000 + +#define VAL_GPION_DATA 0b00000000 +#define VAL_GPION_DIR 0b00000000 +#define VAL_GPION_AFSEL 0b00000000 +#define VAL_GPION_DR2R 0b11111111 +#define VAL_GPION_DR4R 0b00000000 +#define VAL_GPION_DR8R 0b00000000 +#define VAL_GPION_ODR 0b00000000 +#define VAL_GPION_PUR 0b00000000 +#define VAL_GPION_PDR 0b00000000 +#define VAL_GPION_SLR 0b00000000 +#define VAL_GPION_DEN 0b11111111 +#define VAL_GPION_AMSEL 0b0000 +#define VAL_GPION_PCTL 0x00000000 + +#define VAL_GPIOP_DATA 0b00000000 +#define VAL_GPIOP_DIR 0b00000000 +#define VAL_GPIOP_AFSEL 0b00000000 +#define VAL_GPIOP_DR2R 0b11111111 +#define VAL_GPIOP_DR4R 0b00000000 +#define VAL_GPIOP_DR8R 0b00000000 +#define VAL_GPIOP_ODR 0b00000000 +#define VAL_GPIOP_PUR 0b00000000 +#define VAL_GPIOP_PDR 0b00000000 +#define VAL_GPIOP_SLR 0b00000000 +#define VAL_GPIOP_DEN 0b11111111 +#define VAL_GPIOP_AMSEL 0b0000 +#define VAL_GPIOP_PCTL 0x00000000 + +#define VAL_GPIOQ_DATA 0b00000000 +#define VAL_GPIOQ_DIR 0b00000000 +#define VAL_GPIOQ_AFSEL 0b00000000 +#define VAL_GPIOQ_DR2R 0b11111111 +#define VAL_GPIOQ_DR4R 0b00000000 +#define VAL_GPIOQ_DR8R 0b00000000 +#define VAL_GPIOQ_ODR 0b00000000 +#define VAL_GPIOQ_PUR 0b00000000 +#define VAL_GPIOQ_PDR 0b00000000 +#define VAL_GPIOQ_SLR 0b00000000 +#define VAL_GPIOQ_DEN 0b11111111 +#define VAL_GPIOQ_AMSEL 0b0000 +#define VAL_GPIOQ_PCTL 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk new file mode 100644 index 0000000..56298eb --- /dev/null +++ b/ChibiOS_16.1.5/community/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD |