interrupt driver

3 files changed, 52 insertions, 35 deletions

diff --git a/src/bootstrap.s b/src/bootstrap.s
index 5e71da0..fefa602 100644
--- a/src/bootstrap.s
+++ b/src/bootstrap.s
@@ -2,37 +2,10 @@
 .thumb
 
 .extern _start
-.extern fault_handler
+.extern _tstack
 
-.section .text
-
-fault1:
-    mov r0, 1
-    b fault_handler
-fault2:
-    mov r0, 2
-    b fault_handler
-fault3:
-    mov r0, 3
-    b fault_handler
-fault4:
-    mov r0, 4
-    b fault_handler
-fault5:
-    mov r0, 5
-    b fault_handler
-
-.section .bss
-.skip 2048
-stack_top:
-
-.section .isr_vector
-    .word stack_top
+.section .vector_table
+    .word _tstack
     .word _start
-    .word fault1
-    .word fault2
-    .word fault3
-    .word fault4
-    .word fault5
-    .skip 4 * 91
+    .skip 4 * 14
 
diff --git a/src/interrupt.zig b/src/interrupt.zig
new file mode 100644
index 0000000..60faec6
--- /dev/null
+++ b/src/interrupt.zig
@@ -0,0 +1,40 @@
+var vector_table: [256] *const fn () void = undefined;
+var vtor: *u32 = @ptrFromInt(0xE000ED08);
+
+pub const vector = enum(u8) {
+    NMI = 2,
+    HardFault,
+    MemManage,
+    BusFault,
+    UsageFault,
+    rsvd7,
+    rsvd8,
+    rsvd9,
+    rsvd10,
+    SVCall,
+    DebugMonitor,
+    rsvd13,
+    PendSV,
+    SysTick,
+};
+
+pub fn initialize() void {
+    register(.NMI, nmi);
+    register(.HardFault, hardfault);
+    register(.MemManage, memmanage);
+    register(.BusFault, busfault);
+    register(.UsageFault, usagefault);
+
+    vtor.* = @as(u32, @intFromPtr(&vector_table));
+}
+
+pub fn register(index: vector, handler: *const fn () void) void {
+    vector_table[@intFromEnum(index)] = handler;
+}
+
+fn nmi() void { while (true) {} }
+fn hardfault() void { while (true) {} }
+fn memmanage() void { while (true) {} }
+fn busfault() void { while (true) {} }
+fn usagefault() void { while (true) {} }
+
diff --git a/src/main.zig b/src/main.zig
index 3891e52..8857583 100644
--- a/src/main.zig
+++ b/src/main.zig
@@ -1,5 +1,6 @@
 const cpu = @import("cpu.zig");
 const gpio = @import("gpio.zig");
+const interrupt = @import("interrupt.zig");
 
 const rcc: *[39]u32 = @ptrFromInt(0x40021000);
 const gpioa = gpio.gpioa;
@@ -7,18 +8,21 @@ const gpioc = gpio.gpioc;
 
 export fn _start() callconv(.C) noreturn {
     cpu.interrupt_disable();
+    interrupt.initialize();
+    interrupt.register(.SVCall, svcall);
+    cpu.interrupt_enable();
 
     rcc[19] |= 5; // gpio a and c
     gpioa.set_mode(5, .output);
     gpioc.set_mode(13, .input);
 
     while (true) {
-        const state = gpioc.read(13);
-        gpioa.write(5, state);
+        asm volatile("svc 0");
     }
 }
 
-export fn fault_handler() callconv(.C) void {
-    while (true) {}
+fn svcall() void {
+    const state = gpioc.read(13);
+    gpioa.write(5, state);
 }