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msp430: lpm support; . uses base; expand dict size

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master
Clyne 1 year ago
parent 4bf01807b2
commit 494bd41b64
Signed by: clyne
GPG Key ID: 3267C8EBF3F9AFC7
3 changed files with 62 additions and 57 deletions
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17
forth/msp430.fth
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@ -1,18 +1,19 @@
: vector! 10 sys ;
: reg! 11 sys ;
: reg@ 12 sys ;
: 2reg! 13 sys ;
: 2reg@ 14 sys ;
: byte! 11 sys ;
: byte@ 12 sys ;
: reg! 13 sys ;
: reg@ 14 sys ;
: sr+ 15 sys ;
: sr- 16 sys ;
: lpm-exit 17 sys ;
: reg [ ' reg@ ' reg! ] literal literal ;
: 2reg [ ' 2reg@ ' 2reg! ] literal literal ;
: byte [ ' byte@ ' byte! ] literal literal ;
: set ( b r reg/wreg -- )
: set ( b r reg/byte -- )
>r over r> execute >r rot r> | -rot execute ;
: clear ( b r reg/wreg -- )
: clear ( b r reg/byte -- )
>r over r> execute >r rot invert r> & -rot execute ;
: toggle ( b r reg/wreg -- )
: toggle ( b r reg/byte -- )
>r over r> execute >r rot r> ^ -rot execute ;

40
msp430/alee-msp430.cpp
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@ -36,7 +36,8 @@ static char strbuf[80];
static void readchar(State& state);
static void serput(int c);
static void serputs(const char *s);
static void printint(DoubleCell n, char *buf);
static void printint(DoubleCell n, char *buf, int base);
static Error findword(State&, Word);
static void initGPIO();
@ -46,11 +47,11 @@ static void Software_Trim();
#define MCLK_FREQ_MHZ (8) // MCLK = 8MHz
//__attribute__((section(".hidict")))
//static uint8_t hidict[16384];
//static uint8_t hidict[32767];
static bool inISR = false;
static bool exitLpm;
static Addr isr_list[24] = {};
static SplitMemDictRW<sizeof(alee_dat), 16384> dict (alee_dat, 0x10000);
static SplitMemDictRW<sizeof(alee_dat), 32767> dict (alee_dat, 0x10000);
int main()
{
@ -129,8 +130,10 @@ void serputs(const char *s)
serput(*s++);
}
void printint(DoubleCell n, char *buf)
void printint(DoubleCell n, char *buf, int base)
{
static const char digit[] = "0123456789ABCDEF";
char *ptr = buf;
bool neg = n < 0;
@ -138,8 +141,8 @@ void printint(DoubleCell n, char *buf)
n = -n;
do {
*ptr++ = static_cast<char>((n % 10) + '0');
} while ((n /= 10));
*ptr++ = digit[n % base];
} while ((n /= base));
if (neg)
serput('-');
@ -154,7 +157,7 @@ void user_sys(State& state)
{
switch (state.pop()) {
case 0: // .
printint(state.pop(), strbuf);
printint(state.pop(), strbuf, state.dict.read(Dictionary::Base));
break;
case 1: // unused
state.push(static_cast<Addr>(state.dict.capacity() - state.dict.here()));
@ -181,16 +184,13 @@ void user_sys(State& state)
state.push(*reinterpret_cast<uint16_t *>(state.pop()));
break;
case 15:
if (!inISR)
_bis_SR_register(state.pop());
else
_bis_SR_register_on_exit(state.pop());
break;
case 16:
if (!inISR)
_bic_SR_register(state.pop());
else
_bic_SR_register_on_exit(state.pop());
break;
case 17:
exitLpm |= true;
break;
default:
break;
@ -369,21 +369,25 @@ void Software_Trim()
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
}
void alee_isr_handle(unsigned index)
bool alee_isr_handle(unsigned index)
{
const Addr isr = isr_list[index];
if (isr != 0) {
State isrstate (dict, readchar);
inISR = true;
exitLpm = false;
isrstate.execute(isr);
inISR = false;
return exitLpm;
}
return false;
}
#define DEFINE_ISR(VVV, III) \
__attribute__((interrupt(VVV))) \
void VVV##_ISR() { alee_isr_handle(III); }
void VVV##_ISR() { \
if (alee_isr_handle(III)) \
_low_power_mode_off_on_exit(); }
DEFINE_ISR(ECOMP0_VECTOR, 0)
DEFINE_ISR(PORT6_VECTOR, 1)

52
msp430/msp430fr2476.h
Unescape Escape View File

@ -4232,32 +4232,32 @@ sfr_b(UCB1IV_H);
* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
************************************************************/
#define ECOMP0_VECTOR (20) /* 0xFFCA */
#define PORT6_VECTOR (21) /* 0xFFCC */
#define PORT5_VECTOR (22) /* 0xFFCE */
#define PORT4_VECTOR (23) /* 0xFFD0 */
#define PORT3_VECTOR (24) /* 0xFFD2 */
#define PORT2_VECTOR (25) /* 0xFFD4 */
#define PORT1_VECTOR (26) /* 0xFFD6 */
#define ADC_VECTOR (27) /* 0xFFD8 */
#define EUSCI_B1_VECTOR (28) /* 0xFFDA */
#define EUSCI_B0_VECTOR (29) /* 0xFFDC */
#define EUSCI_A1_VECTOR (30) /* 0xFFDE */
#define EUSCI_A0_VECTOR (31) /* 0xFFE0 */
#define WDT_VECTOR (32) /* 0xFFE2 */
#define RTC_VECTOR (33) /* 0xFFE4 */
#define TIMER0_B1_VECTOR (34) /* 0xFFE6 */
#define TIMER0_B0_VECTOR (35) /* 0xFFE8 */
#define TIMER3_A1_VECTOR (36) /* 0xFFEA */
#define TIMER3_A0_VECTOR (37) /* 0xFFEC */
#define TIMER2_A1_VECTOR (38) /* 0xFFEE */
#define TIMER2_A0_VECTOR (39) /* 0xFFF0 */
#define TIMER1_A1_VECTOR (40) /* 0xFFF2 */
#define TIMER1_A0_VECTOR (41) /* 0xFFF4 */
#define TIMER0_A1_VECTOR (42) /* 0xFFF6 */
#define TIMER0_A0_VECTOR (43) /* 0xFFF8 */
#define UNMI_VECTOR (44) /* 0xFFFA */
#define SYSNMI_VECTOR (45) /* 0xFFFC */
#define ECOMP0_VECTOR (0x14) /* 0xFFCA */
#define PORT6_VECTOR (0x15) /* 0xFFCC */
#define PORT5_VECTOR (0x16) /* 0xFFCE */
#define PORT4_VECTOR (0x17) /* 0xFFD0 */
#define PORT3_VECTOR (0x18) /* 0xFFD2 */
#define PORT2_VECTOR (0x19) /* 0xFFD4 */
#define PORT1_VECTOR (0x1A) /* 0xFFD6 */
#define ADC_VECTOR (0x1B) /* 0xFFD8 */
#define EUSCI_B1_VECTOR (0x1C) /* 0xFFDA */
#define EUSCI_B0_VECTOR (0x1D) /* 0xFFDC */
#define EUSCI_A1_VECTOR (0x1E) /* 0xFFDE */
#define EUSCI_A0_VECTOR (0x1F) /* 0xFFE0 */
#define WDT_VECTOR (0x20) /* 0xFFE2 */
#define RTC_VECTOR (0x21) /* 0xFFE4 */
#define TIMER0_B1_VECTOR (0x22) /* 0xFFE6 */
#define TIMER0_B0_VECTOR (0x23) /* 0xFFE8 */
#define TIMER3_A1_VECTOR (0x24) /* 0xFFEA */
#define TIMER3_A0_VECTOR (0x25) /* 0xFFEC */
#define TIMER2_A1_VECTOR (0x26) /* 0xFFEE */
#define TIMER2_A0_VECTOR (0x27) /* 0xFFF0 */
#define TIMER1_A1_VECTOR (0x28) /* 0xFFF2 */
#define TIMER1_A0_VECTOR (0x29) /* 0xFFF4 */
#define TIMER0_A1_VECTOR (0x2A) /* 0xFFF6 */
#define TIMER0_A0_VECTOR (0x2B) /* 0xFFF8 */
#define UNMI_VECTOR (0x2C) /* 0xFFFA */
#define SYSNMI_VECTOR (0x2D) /* 0xFFFC */
#define RESET_VECTOR ("reset") /* 0xFFFE Reset (Highest Priority) */

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