finalize pcb design; add layout file

main
Clyne 1 year ago
parent f440728644
commit 5d91869649
Signed by: clyne
GPG Key ID: 3267C8EBF3F9AFC7

13
.gitignore vendored

@ -9,5 +9,18 @@ firmware/build
gui/imgui.ini
gui/stmdspgui
gui/stmdspgui.exe
hardware/fp-info-cache
hardware/*-backups
hardware/*.kicad_prl
hardware/*.csv
hardware/*.gbl
hardware/*.gbs
hardware/*.gbp
hardware/*.gbo
hardware/*.gm1
hardware/*.gtl
hardware/*.gts
hardware/*.gtp
hardware/*.gto
hardware/*.drl
hardware/*.zip

File diff suppressed because it is too large Load Diff

@ -3,26 +3,192 @@
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"board_outline_line_width": 0.09999999999999999,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.15,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 1.0,
"height": 8.0,
"width": 1.0
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
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}
},
"diff_pair_dimensions": [
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"via_gap": 0.0,
"width": 0.0
}
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"drc_exclusions": [
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"meta": {
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},
"rule_severities": {
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"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "warning",
"padstack": "warning",
"pth_inside_courtyard": "warning",
"shorting_items": "error",
"silk_edge_clearance": "ignore",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
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"solder_mask_min_width": 0.0,
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"td_curve_segcount": 5,
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@ -6,7 +6,7 @@
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@ -6,7 +6,7 @@
(title_block
(title "Power regulation")
(date "2023-08-08")
(date "2023-08-15")
(company "bitgloo")
(comment 1 "Released under the CERN Open Hardware Licence Version 2 - Strongly Reciprocal")
)
@ -395,6 +395,58 @@
)
)
)
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(effects (font (size 1.27 1.27)) hide)
)
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)
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)
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(effects (font (size 1.27 1.27)) hide)
)
(property "ki_description" "Power symbol creates a global label with name \"+5VD\"" (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
(symbol "+5VD_0_1"
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)
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)
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(effects (font (size 1.27 1.27)) hide)
@ -475,58 +527,6 @@
)
)
)
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(effects (font (size 1.27 1.27)) hide)
)
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(property "ki_keywords" "global power" (at 0 0 0)
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)
(property "ki_description" "Power symbol creates a global label with name \"VBUS\"" (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
)
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(pin power_in line (at 0 0 90) (length 0) hide
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@ -1109,34 +1109,6 @@
)
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(property "Value" "VBUS" (at 96.52 62.23 0)
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(pin "1" (uuid 2af5903d-2193-42bc-bea6-926b80d80d0b))
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(property "Value" "VBUS" (at 59.69 66.04 0)
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)
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(symbol (lib_id "power:+5VD") (at 59.69 71.12 0) (unit 1)
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(property "Value" "+5VD" (at 59.69 67.31 0)
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@ -6,7 +6,7 @@
(title_block
(title "User I/O")
(date "2023-08-08")
(date "2023-08-15")
(company "bitgloo")
(comment 1 "Released under the CERN Open Hardware Licence Version 2 - Strongly Reciprocal")
)

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