uploaded code
Clyne Sullivan
7 years ago
parent
8217c76e22
commit
f0f7ae0abc
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out/*
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main.hex
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MCUFLAGS = -mthumb -mcpu=cortex-m4
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CFLAGS = -Iinclude $(MCUFLAGS)
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all:
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arm-none-eabi-as $(MCUFLAGS) startup_stm32l476xx.s -c -o out/startup_stm32l476xx.o
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arm-none-eabi-gcc $(CFLAGS) system_stm32l4xx.c -c -o out/system_stm32l4xx.o
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arm-none-eabi-gcc $(CFLAGS) stm32l4xx_it.c -c -o out/stm32l4xx_it.o
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arm-none-eabi-gcc $(CFLAGS) main.c -c -o out/main.o
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arm-none-eabi-gcc $(CFLAGS) -T link.ld out/*.o -o out/main.elf
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arm-none-eabi-objcopy -O ihex out/main.elf main.hex
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clean:
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rm -rf out/*
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Load Diff
File diff suppressed because it is too large
Load Diff
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/**************************************************************************//**
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* @file core_cmFunc.h
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* @brief CMSIS Cortex-M Core Function Access Header File
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* @version V4.30
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* @date 20. October 2015
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******************************************************************************/
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/* Copyright (c) 2009 - 2015 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
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||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
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||||||
|
*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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|
POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef __CORE_CMFUNC_H
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#define __CORE_CMFUNC_H
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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/*------------------ RealView Compiler -----------------*/
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#if defined ( __CC_ARM )
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#include "cmsis_armcc.h"
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/*------------------ ARM Compiler V6 -------------------*/
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#include "cmsis_armcc_V6.h"
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/*------------------ GNU Compiler ----------------------*/
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#elif defined ( __GNUC__ )
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#include "cmsis_gcc.h"
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/*------------------ ICC Compiler ----------------------*/
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#elif defined ( __ICCARM__ )
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#include <cmsis_iar.h>
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/*------------------ TI CCS Compiler -------------------*/
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#elif defined ( __TMS470__ )
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#include <cmsis_ccs.h>
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/*------------------ TASKING Compiler ------------------*/
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#elif defined ( __TASKING__ )
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/*
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* The CMSIS functions have been implemented as intrinsics in the compiler.
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* Please use "carm -?i" to get an up to date list of all intrinsics,
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* Including the CMSIS ones.
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*/
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/*------------------ COSMIC Compiler -------------------*/
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#elif defined ( __CSMC__ )
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#include <cmsis_csm.h>
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#endif
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/*@} end of CMSIS_Core_RegAccFunctions */
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#endif /* __CORE_CMFUNC_H */
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/**************************************************************************//**
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* @file core_cmInstr.h
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* @brief CMSIS Cortex-M Core Instruction Access Header File
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* @version V4.30
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* @date 20. October 2015
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******************************************************************************/
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/* Copyright (c) 2009 - 2015 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
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||||||
|
- Neither the name of ARM nor the names of its contributors may be used
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|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
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||||||
|
*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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|
POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef __CORE_CMINSTR_H
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#define __CORE_CMINSTR_H
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/* ########################## Core Instruction Access ######################### */
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/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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Access to dedicated instructions
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@{
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*/
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/* CHIBIOS FIX */
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#if !defined(__CORTEX_SC)
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#define __CORTEX_SC 0
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#endif
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/*------------------ RealView Compiler -----------------*/
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#if defined ( __CC_ARM )
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#include "cmsis_armcc.h"
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/*------------------ ARM Compiler V6 -------------------*/
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#include "cmsis_armcc_V6.h"
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/*------------------ GNU Compiler ----------------------*/
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#elif defined ( __GNUC__ )
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#include "cmsis_gcc.h"
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/*------------------ ICC Compiler ----------------------*/
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#elif defined ( __ICCARM__ )
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#include <cmsis_iar.h>
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/*------------------ TI CCS Compiler -------------------*/
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#elif defined ( __TMS470__ )
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#include <cmsis_ccs.h>
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/*------------------ TASKING Compiler ------------------*/
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#elif defined ( __TASKING__ )
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/*
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* The CMSIS functions have been implemented as intrinsics in the compiler.
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* Please use "carm -?i" to get an up to date list of all intrinsics,
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* Including the CMSIS ones.
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*/
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/*------------------ COSMIC Compiler -------------------*/
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#elif defined ( __CSMC__ )
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#include <cmsis_csm.h>
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#endif
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/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
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#endif /* __CORE_CMINSTR_H */
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/**************************************************************************//**
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* @file core_cmSimd.h
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* @brief CMSIS Cortex-M SIMD Header File
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* @version V4.30
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* @date 20. October 2015
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******************************************************************************/
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/* Copyright (c) 2009 - 2015 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
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|
to endorse or promote products derived from this software without
|
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|
specific prior written permission.
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|
*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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|
POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef __CORE_CMSIMD_H
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#define __CORE_CMSIMD_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ################### Compiler specific Intrinsics ########################### */
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/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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Access to dedicated SIMD instructions
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@{
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*/
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/*------------------ RealView Compiler -----------------*/
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#if defined ( __CC_ARM )
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#include "cmsis_armcc.h"
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/*------------------ ARM Compiler V6 -------------------*/
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#include "cmsis_armcc_V6.h"
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/*------------------ GNU Compiler ----------------------*/
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#elif defined ( __GNUC__ )
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#include "cmsis_gcc.h"
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/*------------------ ICC Compiler ----------------------*/
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#elif defined ( __ICCARM__ )
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#include <cmsis_iar.h>
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/*------------------ TI CCS Compiler -------------------*/
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#elif defined ( __TMS470__ )
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#include <cmsis_ccs.h>
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/*------------------ TASKING Compiler ------------------*/
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#elif defined ( __TASKING__ )
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/*
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* The CMSIS functions have been implemented as intrinsics in the compiler.
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* Please use "carm -?i" to get an up to date list of all intrinsics,
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|
* Including the CMSIS ones.
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*/
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/*------------------ COSMIC Compiler -------------------*/
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#elif defined ( __CSMC__ )
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#include <cmsis_csm.h>
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#endif
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/*@} end of group CMSIS_SIMD_intrinsics */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CORE_CMSIMD_H */
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File diff suppressed because it is too large
Load Diff
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/**
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******************************************************************************
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* @file system_stm32l4xx.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 29-April-2016
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* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
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||||||
|
******************************************************************************
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||||||
|
*/
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||||||
|
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l4xx_system
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* @{
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*/
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/**
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* @brief Define to prevent recursive inclusion
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*/
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#ifndef __SYSTEM_STM32L4XX_H
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#define __SYSTEM_STM32L4XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup STM32L4xx_System_Includes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L4xx_System_Exported_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetSysClockFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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|
Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
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extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
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extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */
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||||||
|
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|
/**
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|
* @}
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|
*/
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|
/** @addtogroup STM32L4xx_System_Exported_Constants
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|
* @{
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|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32L4xx_System_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32L4xx_System_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern void SystemInit(void);
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__SYSTEM_STM32L4XX_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,169 @@
|
|||||||
|
/*
|
||||||
|
*****************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32L476RGTx Device with
|
||||||
|
** 1024KByte FLASH, 96KByte RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed as is, without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
** (c)Copyright Ac6.
|
||||||
|
** You may use this file as-is or modify it according to the needs of your
|
||||||
|
** project. Distribution of this file (unmodified or modified) is not
|
||||||
|
** permitted. Ac6 permit registered System Workbench for MCU users the
|
||||||
|
** rights to distribute the assembled, compiled & linked contents of this
|
||||||
|
** file as part of an application binary file, provided that it is built
|
||||||
|
** using the System Workbench for MCU toolchain.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = 0x20018000; /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200;; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400;; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||||
|
.ARM : {
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >RAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@ -0,0 +1,63 @@
|
|||||||
|
#include "stm32l476xx.h"
|
||||||
|
|
||||||
|
#define STK_CTRL *((uint32_t *)0xE000E010)
|
||||||
|
#define STK_LOAD *((uint32_t *)0xE000E014)
|
||||||
|
#define STK_VAL *((uint32_t *)0xE000E018)
|
||||||
|
#define STK_CALIB *((uint32_t *)0xE000E01C)
|
||||||
|
|
||||||
|
extern void delay(uint32_t count);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Accomplishments:
|
||||||
|
* - GPIO in/out
|
||||||
|
* - got to 40MHz clock
|
||||||
|
*/
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
// turn on HSI
|
||||||
|
RCC->CR |= RCC_CR_HSION;
|
||||||
|
while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY);
|
||||||
|
|
||||||
|
// get PLLR to 80MHz (max)
|
||||||
|
// VCO = C * (N/M) -> 16 * (10/1) = 160
|
||||||
|
// SCLK = VCO / R = 160 / 4 = 40 MHz
|
||||||
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC); // source HSI, 16MHz
|
||||||
|
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSI;
|
||||||
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM);
|
||||||
|
RCC->PLLCFGR |= 10 << RCC_PLLCFGR_PLLN_Pos;
|
||||||
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR); // /4
|
||||||
|
RCC->PLLCFGR |= 1 << RCC_PLLCFGR_PLLR_Pos;
|
||||||
|
RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN; // PLLR on
|
||||||
|
|
||||||
|
// start PLL
|
||||||
|
RCC->CR |= RCC_CR_PLLON;
|
||||||
|
while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
|
||||||
|
|
||||||
|
// set system clock to PLL
|
||||||
|
RCC->CFGR &= ~(RCC_CFGR_SW);
|
||||||
|
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||||
|
while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
|
||||||
|
|
||||||
|
// SysTick setup? Assume 4MHz reset clock
|
||||||
|
STK_LOAD = 40000;
|
||||||
|
STK_CTRL |= 0x07; // AHB, inten, enable
|
||||||
|
|
||||||
|
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // A clk enable
|
||||||
|
GPIOA->MODER &= ~(GPIO_MODER_MODE5 | GPIO_MODER_MODE0); // A5 -> output, A0 input
|
||||||
|
GPIOA->MODER |= GPIO_MODER_MODE5_0;
|
||||||
|
GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPD5 | GPIO_PUPDR_PUPD0);
|
||||||
|
GPIOA->PUPDR |= GPIO_PUPDR_PUPD5_0 | GPIO_PUPDR_PUPD0_1; // pd for button
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
delay(500);
|
||||||
|
//if (GPIOA->IDR & 0x01)
|
||||||
|
GPIOA->BSRR |= 1 << 5;
|
||||||
|
delay(500);
|
||||||
|
//else
|
||||||
|
GPIOA->BRR |= 1 << 5;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void _exit(int code)
|
||||||
|
{ for (;;); }
|
||||||
@ -0,0 +1,4 @@
|
|||||||
|
#!/bin/bash
|
||||||
|
|
||||||
|
openocd -f /usr/share/openocd/scripts/board/st_nucleo_l476rg.cfg \
|
||||||
|
-c "init; reset halt; flash write_image erase main.hex; reset run; exit"
|
||||||
@ -0,0 +1,524 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32l476xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32L476xx devices vector table GCC toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address,
|
||||||
|
* - Configure the clock system
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m4
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr sp, =_estack /* Atollic update: set stack pointer */
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
|
||||||
|
LoopForever:
|
||||||
|
b LoopForever
|
||||||
|
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler
|
||||||
|
.word PVD_PVM_IRQHandler
|
||||||
|
.word TAMP_STAMP_IRQHandler
|
||||||
|
.word RTC_WKUP_IRQHandler
|
||||||
|
.word FLASH_IRQHandler
|
||||||
|
.word RCC_IRQHandler
|
||||||
|
.word EXTI0_IRQHandler
|
||||||
|
.word EXTI1_IRQHandler
|
||||||
|
.word EXTI2_IRQHandler
|
||||||
|
.word EXTI3_IRQHandler
|
||||||
|
.word EXTI4_IRQHandler
|
||||||
|
.word DMA1_Channel1_IRQHandler
|
||||||
|
.word DMA1_Channel2_IRQHandler
|
||||||
|
.word DMA1_Channel3_IRQHandler
|
||||||
|
.word DMA1_Channel4_IRQHandler
|
||||||
|
.word DMA1_Channel5_IRQHandler
|
||||||
|
.word DMA1_Channel6_IRQHandler
|
||||||
|
.word DMA1_Channel7_IRQHandler
|
||||||
|
.word ADC1_2_IRQHandler
|
||||||
|
.word CAN1_TX_IRQHandler
|
||||||
|
.word CAN1_RX0_IRQHandler
|
||||||
|
.word CAN1_RX1_IRQHandler
|
||||||
|
.word CAN1_SCE_IRQHandler
|
||||||
|
.word EXTI9_5_IRQHandler
|
||||||
|
.word TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.word TIM1_UP_TIM16_IRQHandler
|
||||||
|
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.word TIM1_CC_IRQHandler
|
||||||
|
.word TIM2_IRQHandler
|
||||||
|
.word TIM3_IRQHandler
|
||||||
|
.word TIM4_IRQHandler
|
||||||
|
.word I2C1_EV_IRQHandler
|
||||||
|
.word I2C1_ER_IRQHandler
|
||||||
|
.word I2C2_EV_IRQHandler
|
||||||
|
.word I2C2_ER_IRQHandler
|
||||||
|
.word SPI1_IRQHandler
|
||||||
|
.word SPI2_IRQHandler
|
||||||
|
.word USART1_IRQHandler
|
||||||
|
.word USART2_IRQHandler
|
||||||
|
.word USART3_IRQHandler
|
||||||
|
.word EXTI15_10_IRQHandler
|
||||||
|
.word RTC_Alarm_IRQHandler
|
||||||
|
.word DFSDM1_FLT3_IRQHandler
|
||||||
|
.word TIM8_BRK_IRQHandler
|
||||||
|
.word TIM8_UP_IRQHandler
|
||||||
|
.word TIM8_TRG_COM_IRQHandler
|
||||||
|
.word TIM8_CC_IRQHandler
|
||||||
|
.word ADC3_IRQHandler
|
||||||
|
.word FMC_IRQHandler
|
||||||
|
.word SDMMC1_IRQHandler
|
||||||
|
.word TIM5_IRQHandler
|
||||||
|
.word SPI3_IRQHandler
|
||||||
|
.word UART4_IRQHandler
|
||||||
|
.word UART5_IRQHandler
|
||||||
|
.word TIM6_DAC_IRQHandler
|
||||||
|
.word TIM7_IRQHandler
|
||||||
|
.word DMA2_Channel1_IRQHandler
|
||||||
|
.word DMA2_Channel2_IRQHandler
|
||||||
|
.word DMA2_Channel3_IRQHandler
|
||||||
|
.word DMA2_Channel4_IRQHandler
|
||||||
|
.word DMA2_Channel5_IRQHandler
|
||||||
|
.word DFSDM1_FLT0_IRQHandler
|
||||||
|
.word DFSDM1_FLT1_IRQHandler
|
||||||
|
.word DFSDM1_FLT2_IRQHandler
|
||||||
|
.word COMP_IRQHandler
|
||||||
|
.word LPTIM1_IRQHandler
|
||||||
|
.word LPTIM2_IRQHandler
|
||||||
|
.word OTG_FS_IRQHandler
|
||||||
|
.word DMA2_Channel6_IRQHandler
|
||||||
|
.word DMA2_Channel7_IRQHandler
|
||||||
|
.word LPUART1_IRQHandler
|
||||||
|
.word QUADSPI_IRQHandler
|
||||||
|
.word I2C3_EV_IRQHandler
|
||||||
|
.word I2C3_ER_IRQHandler
|
||||||
|
.word SAI1_IRQHandler
|
||||||
|
.word SAI2_IRQHandler
|
||||||
|
.word SWPMI1_IRQHandler
|
||||||
|
.word TSC_IRQHandler
|
||||||
|
.word LCD_IRQHandler
|
||||||
|
.word 0
|
||||||
|
.word RNG_IRQHandler
|
||||||
|
.word FPU_IRQHandler
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_PVM_IRQHandler
|
||||||
|
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMP_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_2_IRQHandler
|
||||||
|
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_TX_IRQHandler
|
||||||
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_SCE_IRQHandler
|
||||||
|
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_TIM15_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_TIM16_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT3_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC3_IRQHandler
|
||||||
|
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC1_IRQHandler
|
||||||
|
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT0_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT1_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT2_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP_IRQHandler
|
||||||
|
.thumb_set COMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM1_IRQHandler
|
||||||
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM2_IRQHandler
|
||||||
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_FS_IRQHandler
|
||||||
|
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPUART1_IRQHandler
|
||||||
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak QUADSPI_IRQHandler
|
||||||
|
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI2_IRQHandler
|
||||||
|
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SWPMI1_IRQHandler
|
||||||
|
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TSC_IRQHandler
|
||||||
|
.thumb_set TSC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LCD_IRQHandler
|
||||||
|
.thumb_set LCD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RNG_IRQHandler
|
||||||
|
.thumb_set RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
@ -0,0 +1,43 @@
|
|||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
static uint32_t ticks = 0;
|
||||||
|
|
||||||
|
void delay(uint32_t count)
|
||||||
|
{
|
||||||
|
uint32_t target = ticks + count;
|
||||||
|
while (ticks < target);
|
||||||
|
}
|
||||||
|
|
||||||
|
void NMI_Handler(void) {}
|
||||||
|
|
||||||
|
void HardFault_Handler(void)
|
||||||
|
{
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void MemManage_Handler(void)
|
||||||
|
{
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void BusFault_Handler(void)
|
||||||
|
{
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void UsageFault_Handler(void)
|
||||||
|
{
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void SVC_Handler(void) {}
|
||||||
|
|
||||||
|
void DebugMon_Handler(void) {}
|
||||||
|
|
||||||
|
void PendSV_Handler(void) {}
|
||||||
|
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
ticks++;
|
||||||
|
}
|
||||||
|
|
||||||
@ -0,0 +1,44 @@
|
|||||||
|
#include "stm32l476xx.h"
|
||||||
|
|
||||||
|
/************************* Miscellaneous Configuration ************************/
|
||||||
|
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||||
|
Internal SRAM. */
|
||||||
|
/* #define VECT_TAB_SRAM */
|
||||||
|
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||||
|
This value must be a multiple of 0x200. */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
void SystemInit(void)
|
||||||
|
{
|
||||||
|
/* FPU settings ------------------------------------------------------------*/
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||||
|
/* Set MSION bit */
|
||||||
|
RCC->CR |= RCC_CR_MSION;
|
||||||
|
|
||||||
|
/* Reset CFGR register */
|
||||||
|
RCC->CFGR = 0x00000000U;
|
||||||
|
|
||||||
|
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||||
|
RCC->CR &= 0xEAF6FFFFU;
|
||||||
|
|
||||||
|
/* Reset PLLCFGR register */
|
||||||
|
RCC->PLLCFGR = 0x00001000U;
|
||||||
|
|
||||||
|
/* Reset HSEBYP bit */
|
||||||
|
RCC->CR &= 0xFFFBFFFFU;
|
||||||
|
|
||||||
|
/* Disable all interrupts */
|
||||||
|
RCC->CIER = 0x00000000U;
|
||||||
|
|
||||||
|
/* Configure the Vector Table location add offset address ------------------*/
|
||||||
|
#ifdef VECT_TAB_SRAM
|
||||||
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||||
|
#else
|
||||||
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
Loading…
Reference in New Issue