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/*
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* STM32G0xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 3...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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#define STM32G0xx_MCUCONF
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#define STM32G031_MCUCONF
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#define STM32G041_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT FALSE
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#define STM32_CLOCK_DYNAMIC FALSE
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#define STM32_VOS STM32_VOS_RANGE2
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#define STM32_PWR_CR2 (STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)
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#define STM32_PWR_CR3 (PWR_CR3_EIWUL)
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#define STM32_PWR_CR4 (0U)
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#define STM32_PWR_PUCRA (0U)
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#define STM32_PWR_PDCRA (0U)
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#define STM32_PWR_PUCRB (0U)
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#define STM32_PWR_PDCRB (0U)
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#define STM32_PWR_PUCRC (0U)
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#define STM32_PWR_PDCRC (0U)
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#define STM32_PWR_PUCRD (0U)
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#define STM32_PWR_PDCRD (0U)
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#define STM32_PWR_PUCRF (0U)
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#define STM32_PWR_PDCRF (0U)
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#define STM32_HSIDIV_VALUE 1
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#define STM32_HSI16_ENABLED TRUE
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSI_ENABLED FALSE
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#define STM32_LSE_ENABLED FALSE
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#define STM32_SW STM32_SW_HSISYS
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#define STM32_PLLSRC STM32_PLLSRC_NOCLOCK
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#define STM32_PLLM_VALUE 2
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#define STM32_PLLN_VALUE 8
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#define STM32_PLLP_VALUE 4
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#define STM32_PLLQ_VALUE 4
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#define STM32_PLLR_VALUE 4
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV4
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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#define STM32_MCOPRE STM32_MCOPRE_DIV1
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#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
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/*
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* Peripherals clocks and sources.
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*/
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#define STM32_USART1SEL STM32_USART1SEL_PCLK
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#define STM32_USART2SEL STM32_USART2SEL_PCLK
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#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
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#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
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#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK
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#define STM32_TIM1SEL STM32_TIM1SEL_TIMPCLK
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#define STM32_RNGSEL STM32_RNGSEL_HSI16
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#define STM32_RNGDIV_VALUE 1
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
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/*
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* Shared IRQ settings.
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*/
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#define STM32_IRQ_EXTI0_1_PRIORITY 3
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#define STM32_IRQ_EXTI2_3_PRIORITY 3
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#define STM32_IRQ_EXTI4_15_PRIORITY 3
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#define STM32_IRQ_EXTI1921_PRIORITY 3
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#define STM32_IRQ_USART1_PRIORITY 2
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#define STM32_IRQ_USART2_PRIORITY 2
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#define STM32_IRQ_LPUART1_PRIORITY 2
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#define STM32_IRQ_TIM1_UP_PRIORITY 1
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#define STM32_IRQ_TIM1_CC_PRIORITY 1
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#define STM32_IRQ_TIM2_PRIORITY 1
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#define STM32_IRQ_TIM3_PRIORITY 1
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#define STM32_IRQ_TIM14_PRIORITY 1
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#define STM32_IRQ_TIM16_PRIORITY 1
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#define STM32_IRQ_TIM17_PRIORITY 1
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/*
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* ADC driver system settings.
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*/
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#define STM32_ADC_USE_ADC1 FALSE
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#define STM32_ADC_ADC1_CFGR2 ADC_CFGR2_CKMODE_ADCCLK
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_ADC_PRESCALER_VALUE 2
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/*
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* GPT driver system settings.
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM14 FALSE
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#define STM32_GPT_USE_TIM16 FALSE
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#define STM32_GPT_USE_TIM17 FALSE
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/*
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* I2C driver system settings.
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2C_I2C1_IRQ_PRIORITY 3
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#define STM32_I2C_I2C2_IRQ_PRIORITY 3
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#define STM32_I2C_I2C1_DMA_PRIORITY 3
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#define STM32_I2C_I2C2_DMA_PRIORITY 3
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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/*
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* PWM driver system settings.
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*/
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#define STM32_PWM_USE_TIM1 FALSE
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#define STM32_PWM_USE_TIM2 FALSE
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#define STM32_PWM_USE_TIM3 FALSE
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#define STM32_PWM_USE_TIM14 FALSE
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#define STM32_PWM_USE_TIM16 FALSE
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#define STM32_PWM_USE_TIM17 FALSE
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/*
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* RTC driver system settings.
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*/
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#define STM32_RTC_PRESA_VALUE 32
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#define STM32_RTC_PRESS_VALUE 1024
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#define STM32_RTC_CR_INIT 0
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#define STM32_RTC_TAMPCR_INIT 0
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/*
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* SERIAL driver system settings.
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*/
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#define STM32_SERIAL_USE_USART1 FALSE
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#define STM32_SERIAL_USE_USART2 TRUE
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#define STM32_SERIAL_USE_LPUART1 FALSE
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/*
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* SIO driver system settings.
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*/
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#define STM32_SIO_USE_USART1 FALSE
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#define STM32_SIO_USE_USART2 FALSE
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#define STM32_SIO_USE_LPUART1 FALSE
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/*
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* SPI driver system settings.
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*/
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#define STM32_SPI_USE_SPI1 FALSE
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#define STM32_SPI_USE_SPI2 FALSE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 2
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#define STM32_SPI_SPI2_IRQ_PRIORITY 2
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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#define STM32_I2S_USE_SPI1 TRUE
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#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_I2S_SPI1_IRQ_PRIORITY 2
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/*
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* ST driver system settings.
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*/
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#define STM32_ST_IRQ_PRIORITY 2
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#define STM32_ST_USE_TIMER 2
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/*
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* TRNG driver system settings.
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* NOTE: STM32G041 only.
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*/
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#define STM32_TRNG_USE_RNG1 FALSE
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/*
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* UART driver system settings.
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*/
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#define STM32_UART_USE_USART1 FALSE
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#define STM32_UART_USE_USART2 FALSE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* WDG driver system settings.
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*/
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#define STM32_WDG_USE_IWDG FALSE
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#endif /* MCUCONF_H */
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