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AgeCommit message (Expand)Author
2021-01-27sandboxed user algorithmClyne Sullivan
2021-01-23increase signal buffers; fix oversampleClyne Sullivan
2021-01-23untested port cleanup; add sclock; up cpu to 480MClyne Sullivan
2021-01-22upload initial portClyne Sullivan
2020-11-08fixed sample rate settingClyne Sullivan
2020-10-30keep target as L476; minimize RAM usageClyne Sullivan
2020-10-22set sampling rateClyne Sullivan
2020-10-20firmware can port to L432KC; gui: edit buffer sizeClyne Sullivan
2020-10-20signal gen with dac channel 2Clyne Sullivan
2020-10-17Sampling rate done. 96kS/sClyne Sullivan
2020-10-16fixed sample rate issues; up to 88kS/sClyne Sullivan
2020-08-29improved elf loadingClyne Sullivan
2020-08-22adc/dac passthroughClyne Sullivan
2020-08-04reorganized code; added dac supportClyne Sullivan
2020-05-30added project files; need to organize codeClyne Sullivan
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-04 03:17:42 +0000