initial commit

5 files changed, 654 insertions, 0 deletions

diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt
new file mode 100644
index 0000000..9d3f543
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2019-2021 Arm Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the License); you may
+# not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an AS IS BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+file(GLOB SRC "./*_*.c")
+target_sources(cmsis-nn PRIVATE ${SRC})
diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c
new file mode 100644
index 0000000..6b1366d
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2022 Arm Limited or its affiliates.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_elementwise_add_s16
+ * Description:  Elementwise add
+ *
+ * $Date:        14 Februari 2022
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M CPUs
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+#include "arm_nnsupportfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup BasicMath
+ * @{
+ */
+
+/*
+ * s16 elementwise add
+ *
+ * Refer header file for details.
+ *
+ */
+
+/* Note: __SHIFT is expected to be <=0 */
+
+arm_status arm_elementwise_add_s16(const int16_t *input_1_vect,
+                                   const int16_t *input_2_vect,
+                                   const int32_t input_1_offset,
+                                   const int32_t input_1_mult,
+                                   const int32_t input_1_shift,
+                                   const int32_t input_2_offset,
+                                   const int32_t input_2_mult,
+                                   const int32_t input_2_shift,
+                                   const int32_t left_shift,
+                                   int16_t *output,
+                                   const int32_t out_offset,
+                                   const int32_t out_mult,
+                                   const int32_t out_shift,
+                                   const int32_t out_activation_min,
+                                   const int32_t out_activation_max,
+                                   const int32_t block_size)
+{
+    (void)input_1_offset;
+    (void)input_2_offset;
+    (void)out_offset;
+    int32_t loop_count;
+    int32_t input_1;
+    int32_t input_2;
+    int32_t sum;
+
+    loop_count = block_size;
+
+    while (loop_count > 0)
+    {
+        /* C = A + B */
+        input_1 = *input_1_vect++ << left_shift;
+        input_2 = *input_2_vect++ << left_shift;
+
+        input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift);
+        input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift);
+
+        sum = input_1 + input_2;
+        sum = arm_nn_requantize(sum, out_mult, out_shift);
+
+        sum = MAX(sum, out_activation_min);
+        sum = MIN(sum, out_activation_max);
+
+        *output++ = (int16_t)sum;
+
+        /* Decrement loop counter */
+        loop_count--;
+    }
+
+    return (ARM_MATH_SUCCESS);
+}
+
+/**
+ * @} end of BasicMath group
+ */
diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c
new file mode 100644
index 0000000..13b6bb3
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2010-2022 Arm Limited or its affiliates.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_elementwise_add_s8
+ * Description:  Elementwise add
+ *
+ * $Date:        3 Februari 2022
+ * $Revision:    V.2.6.0
+ *
+ * Target Processor:  Cortex-M CPUs
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+#include "arm_nnsupportfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup BasicMath
+ * @{
+ */
+
+/*
+ * s8 elementwise add
+ *
+ * Refer header file for details.
+ *
+ */
+
+/* Note: __SHIFT is expected to be <=0 */
+
+arm_status arm_elementwise_add_s8(const int8_t *input_1_vect,
+                                  const int8_t *input_2_vect,
+                                  const int32_t input_1_offset,
+                                  const int32_t input_1_mult,
+                                  const int32_t input_1_shift,
+                                  const int32_t input_2_offset,
+                                  const int32_t input_2_mult,
+                                  const int32_t input_2_shift,
+                                  const int32_t left_shift,
+                                  int8_t *output,
+                                  const int32_t out_offset,
+                                  const int32_t out_mult,
+                                  const int32_t out_shift,
+                                  const int32_t out_activation_min,
+                                  const int32_t out_activation_max,
+                                  const int32_t block_size)
+{
+#if defined(ARM_MATH_MVEI)
+    int32_t count = block_size;
+
+    while (count > 0)
+    {
+        int32x4_t vect_1;
+        int32x4_t vect_2;
+
+        mve_pred16_t p = vctp32q((uint32_t)count);
+
+        vect_1 = vldrbq_z_s32(input_1_vect, p);
+        vect_2 = vldrbq_z_s32(input_2_vect, p);
+
+        vect_1 = vaddq_s32(vect_1, vdupq_n_s32(input_1_offset));
+        vect_2 = vaddq_s32(vect_2, vdupq_n_s32(input_2_offset));
+
+        vect_1 = vshlq_r_s32(vect_1, left_shift);
+        vect_2 = vshlq_r_s32(vect_2, left_shift);
+
+        vect_1 = arm_requantize_mve(vect_1, input_1_mult, input_1_shift);
+        vect_2 = arm_requantize_mve(vect_2, input_2_mult, input_2_shift);
+
+        vect_1 = vaddq_s32(vect_1, vect_2);
+        vect_1 = arm_requantize_mve(vect_1, out_mult, out_shift);
+
+        vect_1 = vaddq_n_s32(vect_1, out_offset);
+
+        vect_1 = vmaxq_s32(vect_1, vdupq_n_s32(out_activation_min));
+        vect_1 = vminq_s32(vect_1, vdupq_n_s32(out_activation_max));
+
+        input_1_vect += 4;
+        input_2_vect += 4;
+        vstrbq_p_s32(output, vect_1, p);
+
+        output += 4;
+        count -= 4;
+    }
+#else
+    int32_t loop_count;
+    int32_t input_1;
+    int32_t input_2;
+    int32_t sum;
+
+#if defined(ARM_MATH_DSP)
+    int32_t a_1, b_1, a_2, b_2;
+
+    int32_t offset_1_packed, offset_2_packed;
+
+    int8_t r1, r2, r3, r4;
+
+    offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL);
+    offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL);
+
+    loop_count = block_size >> 2;
+
+    while (loop_count > 0)
+    {
+        /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension
+           intrinsic */
+        input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1);
+        input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2);
+
+        a_1 = __SADD16(a_1, offset_1_packed);
+        b_1 = __SADD16(b_1, offset_1_packed);
+
+        a_2 = __SADD16(a_2, offset_2_packed);
+        b_2 = __SADD16(b_2, offset_2_packed);
+
+        /* Sum 1 */
+        input_1 = (b_1 & 0x0FFFF) << left_shift;
+
+        input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift);
+
+        input_2 = (b_2 & 0x0FFFF) << left_shift;
+        input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift);
+
+        sum = input_1 + input_2;
+        sum = arm_nn_requantize(sum, out_mult, out_shift);
+        sum += out_offset;
+        sum = MAX(sum, out_activation_min);
+        sum = MIN(sum, out_activation_max);
+        r1 = (q7_t)sum;
+
+        /* Sum 3 */
+        input_1 = ((b_1 >> 16) & 0x0FFFF) << left_shift;
+        input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift);
+
+        input_2 = ((b_2 >> 16) & 0x0FFFF) << left_shift;
+        input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift);
+
+        sum = input_1 + input_2;
+        sum = arm_nn_requantize(sum, out_mult, out_shift);
+        sum += out_offset;
+        sum = MAX(sum, out_activation_min);
+        sum = MIN(sum, out_activation_max);
+        r3 = (q7_t)sum;
+
+        /* Sum 2 */
+        input_1 = (a_1 & 0x0FFFF) << left_shift;
+        input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift);
+
+        input_2 = (a_2 & 0x0FFFF) << left_shift;
+        input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift);
+
+        sum = input_1 + input_2;
+        sum = arm_nn_requantize(sum, out_mult, out_shift);
+        sum += out_offset;
+        sum = MAX(sum, out_activation_min);
+        sum = MIN(sum, out_activation_max);
+        r2 = (q7_t)sum;
+
+        /* Sum 4 */
+        input_1 = ((a_1 >> 16) & 0x0FFFF) << left_shift;
+        input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift);
+
+        input_2 = ((a_2 >> 16) & 0x0FFFF) << left_shift;
+        input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift);
+
+        sum = input_1 + input_2;
+        sum = arm_nn_requantize(sum, out_mult, out_shift);
+        sum += out_offset;
+        sum = MAX(sum, out_activation_min);
+        sum = MIN(sum, out_activation_max);
+        r4 = (q7_t)sum;
+
+        arm_nn_write_q7x4_ia(&output, PACK_Q7x4_32x1(r1, r2, r3, r4));
+
+        loop_count--;
+    }
+
+    loop_count = block_size & 0x3;
+#else
+    loop_count = block_size;
+#endif
+
+    while (loop_count > 0)
+    {
+        /* C = A + B */
+
+        input_1 = (*input_1_vect++ + input_1_offset) << left_shift;
+        input_2 = (*input_2_vect++ + input_2_offset) << left_shift;
+
+        input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift);
+        input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift);
+
+        sum = input_1 + input_2;
+        sum = arm_nn_requantize(sum, out_mult, out_shift);
+        sum += out_offset;
+
+        sum = MAX(sum, out_activation_min);
+        sum = MIN(sum, out_activation_max);
+
+        *output++ = (q7_t)sum;
+
+        /* Decrement loop counter */
+        loop_count--;
+    }
+
+#endif /* ARM_MATH_MVEI */
+
+    return (ARM_MATH_SUCCESS);
+}
+
+/**
+ * @} end of BasicMath group
+ */
diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c
new file mode 100644
index 0000000..4e25574
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2022 Arm Limited or its affiliates.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_elementwise_mul_s16
+ * Description:  Element wise multiplication
+ *
+ * $Date:        14 Februari 2022
+ * $Revision:    V.1.0.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+#include "arm_nnsupportfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup BasicMath
+ * @{
+ */
+
+/**
+ * @brief s16 element wise multiplication of two vectors
+ *
+ * @note   Refer header file for details.
+ *
+ */
+arm_status arm_elementwise_mul_s16(const int16_t *input_1_vect,
+                                   const int16_t *input_2_vect,
+                                   const int32_t input_1_offset,
+                                   const int32_t input_2_offset,
+                                   int16_t *output,
+                                   const int32_t out_offset,
+                                   const int32_t out_mult,
+                                   const int32_t out_shift,
+                                   const int32_t out_activation_min,
+                                   const int32_t out_activation_max,
+                                   const int32_t block_size)
+{
+    (void)input_1_offset;
+    (void)input_2_offset;
+    (void)out_offset;
+    int32_t loop_count;
+    int32_t input_1;
+    int32_t input_2;
+    int32_t mul_res;
+
+    loop_count = block_size;
+
+    while (loop_count > 0)
+    {
+        /* C = A * B */
+
+        input_1 = *input_1_vect++;
+        input_2 = *input_2_vect++;
+
+        mul_res = input_1 * input_2;
+        mul_res = arm_nn_requantize(mul_res, out_mult, out_shift);
+
+        mul_res = MAX(mul_res, out_activation_min);
+        mul_res = MIN(mul_res, out_activation_max);
+
+        *output++ = (int16_t)mul_res;
+
+        /* Decrement loop counter */
+        loop_count--;
+    }
+
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of BasicMath group
+ */
diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c
new file mode 100644
index 0000000..ff04cbf
--- /dev/null
+++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2010-2022 Arm Limited or its affiliates.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS NN Library
+ * Title:        arm_elementwise_mul_s8
+ * Description:  Element wise multiplication
+ *
+ * $Date:        3 Februari 2022
+ * $Revision:    V.1.1.0
+ *
+ * Target Processor:  Cortex-M cores
+ *
+ * -------------------------------------------------------------------- */
+
+#include "arm_nnfunctions.h"
+#include "arm_nnsupportfunctions.h"
+
+/**
+ *  @ingroup groupNN
+ */
+
+/**
+ * @addtogroup BasicMath
+ * @{
+ */
+
+/**
+ * @brief s8 element wise multiplication of two vectors
+ *
+ * @note   Refer header file for details.
+ *
+ */
+
+arm_status arm_elementwise_mul_s8(const int8_t *input_1_vect,
+                                  const int8_t *input_2_vect,
+                                  const int32_t input_1_offset,
+                                  const int32_t input_2_offset,
+                                  int8_t *output,
+                                  const int32_t out_offset,
+                                  const int32_t out_mult,
+                                  const int32_t out_shift,
+                                  const int32_t out_activation_min,
+                                  const int32_t out_activation_max,
+                                  const int32_t block_size)
+{
+
+    int32_t loop_count;
+#if defined(ARM_MATH_MVEI)
+
+    loop_count = (block_size + 3) / 4;
+    uint32_t num_elements = block_size;
+
+    for (int i = 0; i < loop_count; i++)
+    {
+        mve_pred16_t p = vctp32q(num_elements);
+
+        int32x4_t input_1 = vldrbq_z_s32(input_1_vect, p);
+        input_1 = vaddq_n_s32(input_1, input_1_offset);
+
+        int32x4_t input_2 = vldrbq_z_s32(input_2_vect, p);
+        input_2 = vaddq_n_s32(input_2, input_2_offset);
+
+        int32x4_t res_0 = vmulq_s32(input_1, input_2);
+
+        res_0 = arm_requantize_mve_32x4(res_0, vdupq_n_s32(out_mult), vdupq_n_s32(out_shift));
+
+        res_0 += vdupq_n_s32(out_offset);
+
+        res_0 = vmaxq_s32(res_0, vdupq_n_s32(out_activation_min));
+        res_0 = vminq_s32(res_0, vdupq_n_s32(out_activation_max));
+
+        vstrbq_p_s32(output, res_0, p);
+        input_1_vect += 4;
+        input_2_vect += 4;
+        output += 4;
+        num_elements -= 4;
+    }
+
+#else
+    int32_t input_1;
+    int32_t input_2;
+    int32_t mul_res;
+
+#if defined(ARM_MATH_DSP)
+    int32_t a_1, b_1, a_2, b_2;
+
+    int32_t offset_1_packed, offset_2_packed;
+
+    int8_t r1, r2, r3, r4;
+
+    offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL);
+    offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL);
+
+    loop_count = block_size >> 2;
+
+    while (loop_count > 0)
+    {
+        /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension
+           intrinsic */
+        input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1);
+        input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2);
+
+        a_1 = __SADD16(a_1, offset_1_packed);
+        b_1 = __SADD16(b_1, offset_1_packed);
+
+        a_2 = __SADD16(a_2, offset_2_packed);
+        b_2 = __SADD16(b_2, offset_2_packed);
+
+        /* Mul 1 */
+        input_1 = (int16_t)(b_1 & 0x0FFFFL);
+        input_2 = (int16_t)(b_2 & 0x0FFFFL);
+
+        mul_res = input_1 * input_2;
+        mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
+
+        mul_res = MAX(mul_res, out_activation_min);
+        mul_res = MIN(mul_res, out_activation_max);
+        r1 = (q7_t)mul_res;
+
+        /* Mul 3 */
+        input_1 = (int16_t)((b_1 >> 16U) & 0x0FFFFL);
+        input_2 = (int16_t)((b_2 >> 16U) & 0x0FFFFL);
+
+        mul_res = input_1 * input_2;
+        mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
+        mul_res = MAX(mul_res, out_activation_min);
+        mul_res = MIN(mul_res, out_activation_max);
+        r3 = (q7_t)mul_res;
+
+        /* Mul 2 */
+        input_1 = (int16_t)(a_1 & 0x0FFFFL);
+        input_2 = (int16_t)(a_2 & 0x0FFFFL);
+
+        mul_res = input_1 * input_2;
+        mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
+        mul_res = MAX(mul_res, out_activation_min);
+        mul_res = MIN(mul_res, out_activation_max);
+        r2 = (q7_t)mul_res;
+
+        /* Mul 4 */
+        input_1 = (int16_t)((a_1 >> 16U) & 0x0FFFFL);
+        input_2 = (int16_t)((a_2 >> 16U) & 0x0FFFFL);
+
+        mul_res = input_1 * input_2;
+        mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
+        mul_res = MAX(mul_res, out_activation_min);
+        mul_res = MIN(mul_res, out_activation_max);
+        r4 = (q7_t)mul_res;
+
+        arm_nn_write_q7x4_ia(&output, PACK_Q7x4_32x1(r1, r2, r3, r4));
+
+        loop_count--;
+    }
+
+    loop_count = block_size & 0x3;
+#else
+    loop_count = block_size;
+#endif
+
+    while (loop_count > 0)
+    {
+        /* C = A * B */
+
+        input_1 = *input_1_vect++ + input_1_offset;
+        input_2 = *input_2_vect++ + input_2_offset;
+
+        mul_res = input_1 * input_2;
+        mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
+
+        mul_res = MAX(mul_res, out_activation_min);
+        mul_res = MIN(mul_res, out_activation_max);
+
+        *output++ = (q7_t)mul_res;
+
+        /* Decrement loop counter */
+        loop_count--;
+    }
+#endif
+    return ARM_MATH_SUCCESS;
+}
+
+/**
+ * @} end of BasicMath group
+ */