update openocd script

fyi: use latest openocd for u0 support

openocd.cfg

@@ -0,0 +1,6 @@
+source [find interface/stlink.cfg]
+transport select dapdirect_swd
+source [find target/stm32u0x.cfg]
+
+# Comment below to debug w/ gdb
+program build/microphone.hex verify reset exit

stm32u0x.cfg

@@ -1,60 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-
-# Configuration file for STM32U0x series.
-#
-# STM32U0 devices support only SWD transport.
-#
-
-source [find interface/stlink.cfg]
-transport select dapdirect_swd
-
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME stm32u0x
-}
-
-# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
-if { [info exists WORKAREASIZE] } {
-   set _WORKAREASIZE $WORKAREASIZE
-} else {
-   set _WORKAREASIZE 0x1000
-}
-
-if { [info exists CPUTAPID] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x6ba02477
-}
-
-swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp   stm32l4x 0x1FFF6800 0 0 0 $_TARGETNAME
-
-adapter speed 2000
-
-if {![using_hla]} {
-	# Use SYSRESETREQ to perform a soft reset if SRST is not fitted.
-	cortex_m reset_config sysresetreq
-}
-
-$_TARGETNAME configure -event examine-end {
-	# Enable debug during low power modes (uses more power).
-	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
-	mmw 0x40015804 0x00000006 0
-
-	# Stop watchdog counters when core is halted.
-	# DBGMCU_APB1_FZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
-	mmw 0x40015808 0x00001800 0
-}
-
-program build/microphone.hex verify reset exit