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authorClyne Sullivan <clyne@bitgloo.com>2024-10-06 08:48:02 -0400
committerClyne Sullivan <clyne@bitgloo.com>2024-10-06 08:48:02 -0400
commitc539462ef74b2d385c348cf84f0117c4f6fa2945 (patch)
tree2d688637d160efde1d8684b8b112358cfa8cc9fd /src/main.zig
parent69c9c4a84d9c40ced2826ba450f85916f43721db (diff)
interrupt driver
Diffstat (limited to 'src/main.zig')
-rw-r--r--src/main.zig12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/main.zig b/src/main.zig
index 3891e52..8857583 100644
--- a/src/main.zig
+++ b/src/main.zig
@@ -1,5 +1,6 @@
const cpu = @import("cpu.zig");
const gpio = @import("gpio.zig");
+const interrupt = @import("interrupt.zig");
const rcc: *[39]u32 = @ptrFromInt(0x40021000);
const gpioa = gpio.gpioa;
@@ -7,18 +8,21 @@ const gpioc = gpio.gpioc;
export fn _start() callconv(.C) noreturn {
cpu.interrupt_disable();
+ interrupt.initialize();
+ interrupt.register(.SVCall, svcall);
+ cpu.interrupt_enable();
rcc[19] |= 5; // gpio a and c
gpioa.set_mode(5, .output);
gpioc.set_mode(13, .input);
while (true) {
- const state = gpioc.read(13);
- gpioa.write(5, state);
+ asm volatile("svc 0");
}
}
-export fn fault_handler() callconv(.C) void {
- while (true) {}
+fn svcall() void {
+ const state = gpioc.read(13);
+ gpioa.write(5, state);
}