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pendsv, clock lib

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master
Clyne Sullivan 7 years ago
parent 5f137a4fd6
commit de7c4fb07d
6 changed files with 115 additions and 63 deletions
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1
Makefile
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@ -5,6 +5,7 @@ all:
arm-none-eabi-as $(MCUFLAGS) startup_stm32l476xx.s -c -o out/startup_stm32l476xx.o
arm-none-eabi-gcc $(CFLAGS) system_stm32l4xx.c -c -o out/system_stm32l4xx.o
arm-none-eabi-gcc $(CFLAGS) stm32l4xx_it.c -c -o out/stm32l4xx_it.o
arm-none-eabi-gcc $(CFLAGS) clock.c -c -o out/clock.o
arm-none-eabi-gcc $(CFLAGS) main.c -c -o out/main.o
arm-none-eabi-gcc $(CFLAGS) -T link.ld out/*.o -o out/main.elf
arm-none-eabi-objcopy -O ihex out/main.elf main.hex

59
clock.c
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@ -0,0 +1,59 @@
#include <clock.h>
#include <stm32l476xx.h>
#define STK_CTRL *((uint32_t *)0xE000E010)
#define STK_LOAD *((uint32_t *)0xE000E014)
#define STK_VAL *((uint32_t *)0xE000E018)
#define STK_CALIB *((uint32_t *)0xE000E01C)
// ticks since init
static uint32_t ticks = 0;
void clock_init(void)
{
// turn on HSI (16MHz)
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY);
// get PLLR to 80MHz (max)
// VCO = C * (N/M) -> 16 * (10/1) = 160
// SCLK = VCO / R = 160 / 2 = 80 MHz
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC);
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSI;
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM);
RCC->PLLCFGR |= 10 << RCC_PLLCFGR_PLLN_Pos;
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR); // /2
RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN; // PLLR on
// start PLL
RCC->CR |= RCC_CR_PLLON;
while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
// set system clock to PLL
RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
// SysTick init. 80MHz / 80000 = 1kHz, ms precision
STK_LOAD = 80000;
STK_CTRL |= 0x07; // no div, interrupt, enable
}
void delay(uint32_t count)
{
uint32_t target = ticks + count;
while (ticks < target);
}
void PendSV_Handler(void) {
}
void SysTick_Handler(void)
{
// just keep counting
ticks++;
if (!(ticks % 500))
SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
}

16
include/clock.h
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@ -0,0 +1,16 @@
#ifndef CLOCK_H_
#define CLOCK_H_
#include <stdint.h>
/**
* Sets HCLK (system clock) to 80MHz, the maximum.
*/
extern void clock_init(void);
/**
* Sleeps for given milliseconds.
*/
void delay(uint32_t ms);
#endif // CLOCK_H_

24
include/stm32l476xx.h
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@ -18497,6 +18497,30 @@ typedef struct
#define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
#define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
/*typedef struct {
uint32_t CPUID;
uint32_t ICSR;
uint32_t VTOR;
uint32_t AIRCR;
uint32_t SCR;
uint32_t CCR;
uint32_t SHPR1;
uint32_t SHPR2;
uint32_t SHPR3;
uint32_t SHCRS;
uint32_t CFSR;
uint32_t HFSR;
uint32_t rsvd;
uint32_t MMAR;
uint32_t BFAR;
uint32_t AFSR;
} __attribute__ ((packed)) SCB_TypeDef;
#define SCB_ADDR (0xE000ED00)
#define SCB *((SCB_TypeDef *)SCB_ADDR)
#define SCB_ICSR_PENDSVSET (1 << 28)*/
#ifdef __cplusplus
}
#endif /* __cplusplus */

59
main.c
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@ -1,16 +1,10 @@
#include "stm32l476xx.h"
#define STK_CTRL *((uint32_t *)0xE000E010)
#define STK_LOAD *((uint32_t *)0xE000E014)
#define STK_VAL *((uint32_t *)0xE000E018)
#define STK_CALIB *((uint32_t *)0xE000E01C)
extern void delay(uint32_t count);
#include <stm32l476xx.h>
#include <clock.h>
/**
* Accomplishments:
* - GPIO in/out
* - got to 40MHz clock
* - got to 80MHz clock
*/
void pulse(uint8_t byte);
@ -21,50 +15,23 @@ int main(void)
FLASH->ACR &= ~(FLASH_ACR_LATENCY);
FLASH->ACR |= FLASH_ACR_LATENCY_2WS;
// turn on HSI
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) != RCC_CR_HSIRDY);
// get PLLR to 80MHz (max)
// VCO = C * (N/M) -> 16 * (10/1) = 160
// SCLK = VCO / R = 160 / 4 = 40 MHz
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC); // source HSI, 16MHz
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSI;
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM);
RCC->PLLCFGR |= 10 << RCC_PLLCFGR_PLLN_Pos;
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR); // /4
RCC->PLLCFGR |= 1 << RCC_PLLCFGR_PLLR_Pos;
RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN; // PLLR on
// start PLL
RCC->CR |= RCC_CR_PLLON;
while ((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY);
// set system clock to PLL
RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL);
// SysTick setup? Assume 4MHz reset clock
STK_LOAD = 40000;
STK_CTRL |= 0x07; // AHB, inten, enable
clock_init();
RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN; // A clk enable
GPIOA->MODER &= ~(GPIO_MODER_MODE5 | GPIO_MODER_MODE0); // A5 -> output, A0 input
GPIOA->MODER |= GPIO_MODER_MODE5_0;
GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPD5 | GPIO_PUPDR_PUPD0);
GPIOA->PUPDR |= GPIO_PUPDR_PUPD5_0 | GPIO_PUPDR_PUPD0_1; // pd for button
pulse(*((uint8_t *)0x08080000)); // 0b00100101
GPIOA->MODER &= ~(GPIO_MODER_MODE5 | GPIO_MODER_MODE6); // A5 -> output, A0 input
GPIOA->MODER |= GPIO_MODER_MODE5_0 | GPIO_MODER_MODE6_0;
GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPD5 | GPIO_PUPDR_PUPD6);
GPIOA->PUPDR |= GPIO_PUPDR_PUPD5_0 | GPIO_PUPDR_PUPD6_0; // pulldown for button (1)
//if (GPIOA->IDR & 0x01)
while (1);/* {
while (1) {
delay(500);
//if (GPIOA->IDR & 0x01)
GPIOA->BSRR |= 1 << 5;
GPIOA->BRR |= 1 << 6;
delay(500);
//else
GPIOA->BSRR |= 1 << 6;
GPIOA->BRR |= 1 << 5;
}*/
}
}
void _exit(int code)

15
stm32l4xx_it.c
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@ -1,13 +1,5 @@
#include <stdint.h>
static uint32_t ticks = 0;
void delay(uint32_t count)
{
uint32_t target = ticks + count;
while (ticks < target);
}
void NMI_Handler(void) {}
void HardFault_Handler(void)
@ -34,10 +26,3 @@ void SVC_Handler(void) {}
void DebugMon_Handler(void) {}
void PendSV_Handler(void) {}
void SysTick_Handler(void)
{
ticks++;
}

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