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boot at 32Ksps; fix 96Ksps

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pull/3/head
Clyne 3 years ago
parent 564e20975b
commit 716be4fc87
4 changed files with 12 additions and 6 deletions
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3
ChibiOS_20.3.2/os/hal/ports/STM32/STM32H7xx/hal_lld.h
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@ -377,6 +377,7 @@
#define STM32_ODEN_DISABLED 0U #define STM32_ODEN_DISABLED 0U
#define STM32_ODEN_ENABLED (SYSCFG_PWRCR_ODEN) #define STM32_ODEN_ENABLED (SYSCFG_PWRCR_ODEN)
#define STM32_VOS_SCALE0 0U
#define STM32_VOS_SCALE3 (PWR_D3CR_VOS_0) #define STM32_VOS_SCALE3 (PWR_D3CR_VOS_0)
#define STM32_VOS_SCALE2 (PWR_D3CR_VOS_1) #define STM32_VOS_SCALE2 (PWR_D3CR_VOS_1)
#define STM32_VOS_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) #define STM32_VOS_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
@ -1404,7 +1405,7 @@
* @name Constants depending on VOS and ODEN setting * @name Constants depending on VOS and ODEN setting
* @{ * @{
*/ */
#if STM32_VOS == STM32_VOS_SCALE1 #if STM32_VOS == STM32_VOS_SCALE1 || STM32_VOS == STM32_VOS_SCALE0
#define STM32_0WS_THRESHOLD 70000000U #define STM32_0WS_THRESHOLD 70000000U
#define STM32_1WS_THRESHOLD 140000000U #define STM32_1WS_THRESHOLD 140000000U
#define STM32_2WS_THRESHOLD 210000000U #define STM32_2WS_THRESHOLD 210000000U

9
source/adc.cpp
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@ -18,7 +18,7 @@ const ADCConfig ADC::m_config = {
.calibration = 0, .calibration = 0,
}; };
const ADCConversionGroup ADC::m_group_config = { ADCConversionGroup ADC::m_group_config = {
.circular = true, .circular = true,
.num_channels = 1, .num_channels = 1,
.end_cb = ADC::conversionCallback, .end_cb = ADC::conversionCallback,
@ -46,7 +46,7 @@ std::array<std::array<uint32_t, 2>, 6> ADC::m_rate_presets = {{
{/* 20k */ 80, 8}, {/* 20k */ 80, 8},
{/* 32k */ 80, 5}, {/* 32k */ 80, 5},
{/* 48k */ 96, 4}, {/* 48k */ 96, 4},
{/* 96k */ 96, 2} {/* 96k */ 288, 10}
}}; }};
adcsample_t *ADC::m_current_buffer = nullptr; adcsample_t *ADC::m_current_buffer = nullptr;
@ -59,8 +59,6 @@ void ADC::begin()
adcStart(m_driver, &m_config); adcStart(m_driver, &m_config);
adcSTM32EnableVREF(m_driver); adcSTM32EnableVREF(m_driver);
setRate(SClock::Rate::R32K);
} }
void ADC::start(adcsample_t *buffer, size_t count, Operation operation) void ADC::start(adcsample_t *buffer, size_t count, Operation operation)
@ -101,6 +99,9 @@ void ADC::setRate(SClock::Rate rate)
RCC->CR |= RCC_CR_PLL2ON; RCC->CR |= RCC_CR_PLL2ON;
while ((RCC->CR & RCC_CR_PLL2RDY) != RCC_CR_PLL2RDY); while ((RCC->CR & RCC_CR_PLL2RDY) != RCC_CR_PLL2RDY);
m_group_config.smpr[0] = rate != SClock::Rate::R96K ? ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_12P5)
: ADC_SMPR1_SMP_AN5(ADC_SMPR_SMP_2P5);
adcStart(m_driver, &m_config); adcStart(m_driver, &m_config);
} }

2
source/adc.hpp
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@ -34,7 +34,7 @@ private:
static ADCDriver *m_driver; static ADCDriver *m_driver;
static const ADCConfig m_config; static const ADCConfig m_config;
static const ADCConversionGroup m_group_config; static ADCConversionGroup m_group_config;
static std::array<std::array<uint32_t, 2>, 6> m_rate_presets; static std::array<std::array<uint32_t, 2>, 6> m_rate_presets;

4
source/main.cpp
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@ -82,8 +82,12 @@ int main()
ADC::begin(); ADC::begin();
DAC::begin(); DAC::begin();
SClock::begin();
USBSerial::begin(); USBSerial::begin();
SClock::setRate(SClock::Rate::R32K);
ADC::setRate(SClock::Rate::R32K);
// Start the conversion manager thread // Start the conversion manager thread
chTMObjectInit(&conversion_time_measurement); chTMObjectInit(&conversion_time_measurement);
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1,

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