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@ -18,30 +18,31 @@
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* STM32H743xI generic setup.
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*
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* AXI SRAM - BSS, Data, Heap.
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* SRAM1+SRAM2 - None.
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* SRAM4 - NOCACHE.
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* SRAM1 - SIGGEN.
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* SRAM2 - DAC.
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* SRAM4 - ADC.
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* DTCM-RAM - Main Stack, Process Stack.
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* ITCM-RAM - STMDSP Algorithm.
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* BCKP SRAM - None.
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*/
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MEMORY
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{
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flash0 (rx) : org = 0x08000000, len = 1M /* Flash bank1+bank2 */
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flash1 (rx) : org = 0x08000000, len = 512K /* Flash bank 1 */
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flash2 (rx) : org = 0x08080000, len = 512K /* Flash bank 2 */
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flash0 (rx) : org = 0x08000000, len = 1M /* Flash bank1+bank2 */
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flash1 (rx) : org = 0x08000000, len = 512K /* Flash bank 1 */
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flash2 (rx) : org = 0x08080000, len = 512K /* Flash bank 2 */
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flash3 (rx) : org = 0x00000000, len = 0
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flash4 (rx) : org = 0x00000000, len = 0
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flash5 (rx) : org = 0x00000000, len = 0
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flash6 (rx) : org = 0x00000000, len = 0
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flash7 (rx) : org = 0x00000000, len = 0
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ram0 (wx) : org = 0x24000000, len = 320k /* AXI SRAM */
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ram1 (wx) : org = 0x30000000, len = 32k /* AHB SRAM1+SRAM2 */
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ram1 (wx) : org = 0x30000000, len = 16k /* AHB SRAM1 */
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ram2 (wx) : org = 0x30004000, len = 16k /* AHB SRAM2 */
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ram3 (wx) : org = 0x38000000, len = 16k /* AHB SRAM4 */
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ram4 (wx) : org = 0x00000000, len = 0
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ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
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ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
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ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
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ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
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ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
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ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
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}
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/* For each data/text section two region are defined, a virtual region
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@ -97,7 +98,7 @@ INCLUDE rules_stacks.ld
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/*===========================================================================*/
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/* RAM region to be used for nocache segment.*/
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REGION_ALIAS("NOCACHE_RAM", ram3);
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/*REGION_ALIAS("NOCACHE_RAM", ram3);*/
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/* RAM region to be used for eth segment.*/
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/*REGION_ALIAS("ETH_RAM", ram3);*/
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@ -105,7 +106,7 @@ REGION_ALIAS("NOCACHE_RAM", ram3);
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SECTIONS
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{
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/* Special section for non cache-able areas.*/
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.nocache (NOLOAD) : ALIGN(4)
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/*.nocache (NOLOAD) : ALIGN(4)
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{
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__nocache_base__ = .;
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*(.nocache)
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@ -113,7 +114,7 @@ SECTIONS
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*(.bss.__nocache_*)
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. = ALIGN(4);
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__nocache_end__ = .;
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} > NOCACHE_RAM
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} > NOCACHE_RAM*/
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/* Special section for Ethernet DMA non cache-able areas.*/
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/*.eth (NOLOAD) : ALIGN(4)
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